1/*
2 -
3 * Copyright (c) 2010 Isilon Systems, Inc.
4 * Copyright (c) 2010 iX Systems, Inc.
5 * Copyright (c) 2010 Panasas, Inc.
6 * Copyright (c) 2013, 2014 Mellanox Technologies, Ltd.
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 *    notice unmodified, this list of conditions, and the following
14 *    disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29
30 */
31#ifndef	_LINUX_IO_H_
32#define	_LINUX_IO_H_
33/*
34 #include <machine/vm.h>
35 #include <sys/endian.h>
36 */
37static inline uint32_t __raw_readl(const volatile void *addr) {
38	return *(const volatile uint32_t *) addr;
39}
40
41static inline void __raw_writel(uint32_t b, volatile void *addr) {
42	*(volatile uint32_t *) addr = b;
43}
44/*
45 static inline uint64_t
46 __raw_readq(const volatile void *addr)
47 {
48 return *(const volatile uint64_t *)addr;
49 }
50 */
51static inline void __raw_writeq(uint64_t b, volatile void *addr) {
52	*(volatile uint64_t *) addr = b;
53}
54/*
55
56 * XXX This is all x86 specific.  It should be bus space access.
57 */
58#define mmiowb()
59
60#undef writel
61static inline void writel(uint32_t b, void *addr) {
62	*(volatile uint32_t *) addr = b;
63}
64/*
65 #undef writeq
66 static inline void
67 writeq(uint64_t b, void *addr)
68 {
69 *(volatile uint64_t *)addr = b;
70 }
71
72 #undef writeb
73 static inline void
74 writeb(uint8_t b, void *addr)
75 {
76 *(volatile uint8_t *)addr = b;
77 }
78
79 #undef writew
80 static inline void
81 writew(uint16_t b, void *addr)
82 {
83 *(volatile uint16_t *)addr = b;
84 }
85
86 #undef ioread32be
87 static inline uint32_t
88 ioread32be(const volatile void *addr)
89 {
90 return be32toh(*(const volatile uint32_t *)addr);
91 }
92
93 #undef iowrite32be
94 static inline void
95 iowrite32be(uint32_t v, volatile void *addr)
96 {
97 *(volatile uint32_t *)addr = htobe32(v);
98 }
99
100 void *_ioremap_attr(vm_paddr_t phys_addr, unsigned long size, int attr);
101 #define	ioremap_nocache(addr, size)					\
102    _ioremap_attr((addr), (size), VM_MEMATTR_UNCACHEABLE)
103 #define	ioremap_wc(addr, size)						\
104    _ioremap_attr((addr), (size), VM_MEMATTR_WRITE_COMBINING)
105 #define	ioremap	ioremap_nocache
106 void iounmap(void *addr);
107
108 #define	memset_io(a, b, c)	memset((a), (b), (c))
109 #define	memcpy_fromio(a, b, c)	memcpy((a), (b), (c))
110 #define	memcpy_toio(a, b, c)	memcpy((a), (b), (c))
111 */
112static inline void __iowrite64_copy(void *to, void *from, size_t count) {
113#ifdef __LP64__
114	uint64_t *src;
115	uint64_t *dst;
116	int i;
117
118	for (i = 0, src = from, dst = to; i < count; i++, src++, dst++)
119		__raw_writeq(*src, dst);
120#else
121	uint32_t *src;
122	uint32_t *dst;
123	int i;
124
125	count *= 2;
126	for (i = 0, src = from, dst = to; i < count; i++, src++, dst++)
127	__raw_writel(*src, dst);
128#endif
129}
130
131#endif	 /*_LINUX_IO_H_*/
132
133