1/*
2 * Copyright (c) 2017 ETH Zurich.
3 * All rights reserved.
4 *
5 * This file is distributed under the terms in the attached LICENSE file.
6 * If you do not find this file, copies can be found by writing to:
7 * ETH Zurich D-INFK, Universitaetstr. 6, CH-8092 Zurich. Attn: Systems Group.
8 */
9
10#ifndef MLX4_DEVIF_QUEUE_H
11#define MLX4_DEVIF_QUEUE_H
12
13#include <devif/queue_interface_backend.h>
14
15struct mlx4_en_priv;
16
17typedef struct mlx4_queue {
18    struct devq q;
19    // struct mlx4_dev *dev;
20    struct mlx4_en_priv *priv;
21
22    uint32_t pci_vendor, pci_deviceid, pci_bus, pci_device, pci_function;
23    char *name;
24    uint64_t mac_address;
25
26    regionid_t region_id;
27    genpaddr_t region_base;
28    gensize_t  region_size;
29    void *region_mapped;
30
31    unsigned interrupt_mode;
32    void (*isr)(void *);
33} mlx4_queue_t;
34
35int mlx4_en_xmit(struct mlx4_en_priv *priv, int tx_ind, genpaddr_t buffer_data, size_t length);
36void mlx4_en_xmit_poll(struct mlx4_en_priv *priv, int tx_ind);
37
38errval_t mlx4_en_enqueue_rx(mlx4_queue_t *queue, regionid_t rid,
39                            genoffset_t offset, genoffset_t length,
40                            genoffset_t valid_data, genoffset_t valid_length,
41                            uint64_t flags);
42errval_t mlx4_en_dequeue_rx(mlx4_queue_t *queue, regionid_t* rid, genoffset_t* offset,
43                            genoffset_t* length, genoffset_t* valid_data,
44                            genoffset_t* valid_length, uint64_t* flags);
45errval_t mlx4_en_enqueue_tx(mlx4_queue_t *queue, regionid_t rid,
46                            genoffset_t offset, genoffset_t length,
47                            genoffset_t valid_data, genoffset_t valid_length,
48                            uint64_t flags);
49errval_t mlx4_en_dequeue_tx(mlx4_queue_t *queue, regionid_t* rid, genoffset_t* offset,
50                            genoffset_t* length, genoffset_t* valid_data,
51                            genoffset_t* valid_length, uint64_t* flags);
52
53#endif
54