1/** 2 * \file 3 * \brief IA32 performance monitoring 4 */ 5 6/* 7 * Copyright (c) 2007, 2008, 2009, 2010, ETH Zurich. 8 * All rights reserved. 9 * 10 * This file is distributed under the terms in the attached LICENSE file. 11 * If you do not find this file, copies can be found by writing to: 12 * ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group. 13 */ 14 15#include <stdint.h> 16#include <stdbool.h> 17#include <barrelfish/barrelfish.h> 18#include <barrelfish/cspace.h> 19#include <barrelfish/caddr.h> 20#include <barrelfish/lmp_endpoints.h> 21#include <arch/x86/barrelfish/perfmon.h> 22#include <arch/x86/barrelfish_kpi/perfmon_amd.h> 23#include <barrelfish/dispatcher_arch.h> 24 25/** 26 * \brief Setup use of performance counter 27 * 28 * \param handle The handle to the dispatcher 29 * \param counter Which counter to use. 30 * \param evt The event to use 31 * \param umask The mask on the event 32 * \param kernel Is it kernel or user readable 33 * 34 * Currently this only works for AMD machines and it has 4 counters 35 * (0-3). 36 */ 37errval_t perfmon_setup(dispatcher_handle_t handle, perfmon_counter_t counter, 38 perfmon_event_t evt, perfmon_mask_t umask, bool kernel) 39{ 40 errval_t err; 41 42 // Setup the counter 43 err = invoke_perfmon_activate(cap_perfmon, evt, umask, kernel, counter, 0, 0); 44 if(err_is_fail(err)) { 45 err_push(err, LIB_ERR_INVOKE_PERFMON_SETUP); 46 } 47 48 // Initialize it to 0 49 err = invoke_perfmon_write(cap_perfmon, counter, 0); 50 if(err_is_fail(err)) { 51 err_push(err, LIB_ERR_INVOKE_PERFMON_WRITE); 52 } 53 54 return SYS_ERR_OK; 55} 56 57const char *perfmon_str(uint64_t event) 58{ 59 const char *str = NULL; 60 61 switch(event) { 62 case EVENT_AMD_L3_CACHE_MISSES: 63 str = "L3 cache misses"; 64 break; 65 66 case EVENT_AMD_L3_EVICTIONS: 67 str = "L3 evictions"; 68 break; 69 70 case EVENT_AMD_DATA_CACHE_MISSES: 71 str = "Data Cache Misses"; 72 break; 73 case EVENT_AMD_DATA_CACHE_REFILLS_L2_NB: 74 str = "Data Cache Refills from L2 or Northbridge"; 75 break; 76 case EVENT_AMD_DATA_CACHE_REFILLS_NB: 77 str = "Data Cache Refills from the Northbridge"; 78 break; 79 case EVENT_AMD_DATA_CACHE_LINES_EVICTED: 80 str = "Data Cache Lines Evicted"; 81 break; 82 83 case EVENT_AMD_MEM_REQ_TYPES: 84 str = "Memory Requests by Type"; 85 break; 86 87 case EVENT_AMD_OCTWORDS_TO_SYSTEM: 88 str = "Octwords written to System"; 89 break; 90 91 case EVENT_AMD_L2_CACHE_MISSES: 92 str = "L2 Cache Misses"; 93 break; 94 95 case EVENT_AMD_INSTRUCTION_CACHE_MISSES: 96 str = "Instruction Cache Misses"; 97 break; 98 99 case EVENT_AMD_L2_FILL_WRITEBACK: 100 str = "L2 Cache Fill Writeback"; 101 break; 102 103 case EVENT_AMD_HYPERTRANSPORT_LINK0_BANDWIDTH: 104 str = "HyperTransport Link 0 Bandwidth"; 105 break; 106 107 case EVENT_AMD_HYPERTRANSPORT_LINK1_BANDWIDTH: 108 str = "HyperTransport Link 1 Bandwidth"; 109 break; 110 111 case EVENT_AMD_HYPERTRANSPORT_LINK2_BANDWIDTH: 112 str = "HyperTransport Link 2 Bandwidth"; 113 break; 114 115 default: 116 assert(!"Unknown performance event!"); 117 break; 118 } 119 120 return str; 121} 122