1/* 2 * Some or all of this work - Copyright (c) 2006 - 2016, Intel Corp. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without modification, 6 * are permitted provided that the following conditions are met: 7 * 8 * Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * Neither the name of Intel Corporation nor the names of its contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 30if (STTT("Integer arithmetic", TCLF, 0, W000)) { 31 SRMT("ADD0") 32 ADD0() 33 SRMT("SUB0") 34 SUB0() 35 SRMT("MTP0") 36 MTP0() 37 SRMT("DVD0") 38 DVD0() 39 SRMT("ICR0") 40 ICR0() 41 SRMT("DCR0") 42 DCR0() 43 SRMT("AND0") 44 AND0() 45 SRMT("NAN0") 46 NAN0() 47 SRMT("NOR0") 48 NOR0() 49 SRMT("NOT0") 50 NOT0() 51 SRMT("OR00") 52 OR00() 53 SRMT("XOR0") 54 XOR0() 55 SRMT("MOD0") 56 MOD0() 57 SRMT("SHL0") 58 SHL0() 59 SRMT("SHR0") 60 SHR0() 61 SRMT("FSL0") 62 FSL0() 63 SRMT("FSR0") 64 FSR0() 65} 66FTTT() 67