1/** 2 * \file plat_arm_vm.c 3 * \brief 4 */ 5 6 7/* 8 * Copyright (c) 2016 ETH Zurich. 9 * All rights reserved. 10 * 11 * This file is distributed under the terms in the attached LICENSE file. 12 * If you do not find this file, copies can be found by writing to: 13 * ETH Zurich D-INFK, Universitaetsstrasse 6, CH-8092 Zurich. Attn: Systems Group. 14 */ 15 16#include <kernel.h> 17#include <offsets.h> 18#include <platform.h> 19#include <serial.h> 20#include <arch/arm/pl011.h> 21#include <arch/armv8/gic_v3.h> 22 23// #include <dev/apm88xxxx/apm88xxxx_pc16550_dev.h> 24// #include <arch/arm/gic.h> 25#include <sysreg.h> 26#include <dev/armv8_dev.h> 27#include <barrelfish_kpi/arm_core_data.h> 28#include <psci.h> 29#include <arch/armv8/global.h> 30// #include <arch/armv8/gic_v3.h> 31// #include <paging_kernel_arch.h> 32 33/* RAM starts at 0, provided by the MMAP */ 34lpaddr_t phys_memory_start= 0; 35 36/* 37 * ---------------------------------------------------------------------------- 38 * GIC 39 * ---------------------------------------------------------------------------- 40 */ 41 42lpaddr_t platform_gic_dist_base = 0x8000000; 43lpaddr_t platform_gic_redist_base = 0x80a0000; 44 45/* 46 * ---------------------------------------------------------------------------- 47 * UART 48 * ---------------------------------------------------------------------------- 49 */ 50 51/* the maximum number of UARTS supported */ 52#define MAX_NUM_UARTS 1 53 54/* the serial console port */ 55unsigned int serial_console_port = 0; 56 57/* the debug console port */ 58unsigned int serial_debug_port = 0; 59 60/* the number of physical ports */ 61unsigned serial_num_physical_ports = 1; 62 63/* uart bases */ 64lpaddr_t uart_base[MAX_NUM_UARTS] = 65{ 66 0x9000000 67}; 68 69/* uart sizes */ 70size_t uart_size[MAX_NUM_UARTS] = 71{ 72 4096 73}; 74 75errval_t serial_init(unsigned port, bool initialize_hw) 76{ 77 lvaddr_t base = local_phys_to_mem(uart_base[port]); 78 pl011_init(port, base, initialize_hw); 79 return SYS_ERR_OK; 80}; 81 82/* 83 * Return the address of the UART device. 84 */ 85lpaddr_t platform_get_uart_address(unsigned port) 86{ 87 return local_phys_to_mem(uart_base[port]); 88} 89 90/* 91 * Do any extra initialisation for this particular CPU (e.g. A9/A15). 92 */ 93void platform_revision_init(void) 94{ 95 96} 97 98/* 99 * Figure out how much RAM we have 100 */ 101size_t platform_get_ram_size(void) 102{ 103 return 0; 104} 105 106/* 107 * Boot secondary processors 108 */ 109errval_t platform_boot_core(hwid_t target, genpaddr_t gen_entry, genpaddr_t context) 110{ 111 printf("Invoking PSCI on: cpu=0x%lx, entry=0x%lx, context=0x%lx\n", target, gen_entry, context); 112 struct armv8_core_data *cd = (struct armv8_core_data *)local_phys_to_mem(context); 113 cd->page_table_root = armv8_TTBR1_EL1_rd(NULL); 114 cd->cpu_driver_globals_pointer = (uintptr_t)global; 115 __asm volatile("dsb sy\n" 116 "dmb sy\n" 117 "isb \n"); 118 return psci_cpu_on(target, gen_entry, context); 119} 120 121void platform_notify_bsp(lpaddr_t *mailbox) 122{ 123 124} 125 126 127/* 128 * Return the core count 129 */ 130size_t platform_get_core_count(void) 131{ 132 return 0; 133} 134 135/* 136 * Print system identification. MMU is NOT yet enabled. 137 */ 138void platform_print_id(void) 139{ 140 141} 142 143/* 144 * Fill out provided `struct platform_info` 145 */ 146void platform_get_info(struct platform_info *pi) 147{ 148 pi->arch = PI_ARCH_ARMV8A; 149 pi->platform = PI_PLATFORM_QEMU; 150} 151 152void armv8_get_info(struct arch_info_armv8 *ai) 153{ 154 155} 156