1/** 2 * \file 3 * \brief Arch specific definitions, can be included by others. 4 */ 5 6/* 7 * Copyright (c) 2010-2013 ETH Zurich. 8 * Copyright (c) 2014, HP Labs. 9 * All rights reserved. 10 * 11 * This file is distributed under the terms in the attached LICENSE file. 12 * If you do not find this file, copies can be found by writing to: 13 * ETH Zurich D-INFK, Universitaetstr. 6, CH-8092 Zurich. Attn: Systems Group. 14 */ 15 16#ifndef TARGET_X86_64_BARRELFISH_KPI_PAGING_H 17#define TARGET_X86_64_BARRELFISH_KPI_PAGING_H 18 19#ifndef __ASSEMBLER__ 20typedef uint64_t paging_x86_64_flags_t; 21#endif 22 23/** The system's base page size is 4kB */ 24#define X86_64_BASE_PAGE_BITS 12 25#define X86_64_BASE_PAGE_SIZE (1<<X86_64_BASE_PAGE_BITS) 26#define X86_64_BASE_PAGE_MASK (X86_64_BASE_PAGE_SIZE - 1) 27#define X86_64_BASE_PAGE_OFFSET(a) ((a) & X86_64_BASE_PAGE_MASK) 28 29/** The system's large page size is 2MB */ 30#define X86_64_LARGE_PAGE_BITS 21 31#define X86_64_LARGE_PAGE_SIZE (1<<X86_64_LARGE_PAGE_BITS) 32#define X86_64_LARGE_PAGE_MASK (X86_64_LARGE_PAGE_SIZE - 1) 33#define X86_64_LARGE_PAGE_OFFSET(a) ((a) & X86_64_LARGE_PAGE_MASK) 34 35/** The system's huge page size is 1GB */ 36#define X86_64_HUGE_PAGE_BITS 30 37#define X86_64_HUGE_PAGE_SIZE (1<<X86_64_HUGE_PAGE_BITS) 38#define X86_64_HUGE_PAGE_MASK (X86_64_HUGE_PAGE_SIZE - 1) 39#define X86_64_HUGE_PAGE_OFFSET(a) ((a) & X86_64_HUGE_PAGE_MASK) 40 41/** 42 * Bits within the various page directories and tables. 43 */ 44#define X86_64_PTABLE_EXECUTE_DISABLE (((paging_x86_64_flags_t)1) << 63) 45#define X86_64_VTD_PAGE_SNOOP (((paging_x86_64_flags_t)1) << 11) 46#define X86_64_PTABLE_GLOBAL_PAGE (((paging_x86_64_flags_t)1) << 8) 47#define X86_64_PTABLE_ATTR_INDEX (((paging_x86_64_flags_t)1) << 7) 48#define X86_64_PTABLE_DIRTY (((paging_x86_64_flags_t)1) << 6) 49#define X86_64_PTABLE_ACCESSED (((paging_x86_64_flags_t)1) << 5) 50#define X86_64_PTABLE_CACHE_DISABLED (((paging_x86_64_flags_t)1) << 4) 51#define X86_64_PTABLE_WRITE_THROUGH (((paging_x86_64_flags_t)1) << 3) 52#define X86_64_PTABLE_USER_SUPERVISOR (((paging_x86_64_flags_t)1) << 2) 53#define X86_64_PTABLE_READ_WRITE (((paging_x86_64_flags_t)1) << 1) 54#define X86_64_PTABLE_PRESENT (((paging_x86_64_flags_t)1) << 0) 55 56#define X86_64_PTABLE_BITS 9 /**< Page directory/table size in bits */ 57/** Page directory/table size */ 58#define X86_64_PTABLE_SIZE (1UL<<X86_64_PTABLE_BITS) 59#define X86_64_PTABLE_MASK 0x1ff /**< Page dir/table address mask */ 60#define X86_64_PTABLE_CLEAR 0 /**< Bitmap of a clear table entry */ 61 62#define X86_64_PTABLE_ENTRY_SIZE sizeof(union x86_64_pdir_entry) 63 64/// Default access is read/write, but not execute 65#define X86_64_PTABLE_ACCESS_DEFAULT \ 66 (X86_64_PTABLE_EXECUTE_DISABLE | X86_64_PTABLE_USER_SUPERVISOR | \ 67 X86_64_PTABLE_READ_WRITE) 68#define X86_64_PTABLE_ACCESS_READONLY \ 69 (X86_64_PTABLE_EXECUTE_DISABLE | X86_64_PTABLE_USER_SUPERVISOR) 70 71/* Macros to compute the corresponding portions of the vaddr */ 72#define X86_64_PML4_BASE(base) (((uint64_t)(base) >> 39) & X86_64_PTABLE_MASK) 73#define X86_64_PDPT_BASE(base) (((uint64_t)(base) >> 30) & X86_64_PTABLE_MASK) 74#define X86_64_PDIR_BASE(base) (((uint64_t)(base) >> 21) & X86_64_PTABLE_MASK) 75#define X86_64_PTABLE_BASE(base) (((uint64_t)(base) >> 12) & X86_64_PTABLE_MASK) 76 77#endif // TARGET_X86_64_BARRELFISH_KPI_PAGING_H 78