1/** 2 * \file 3 * \brief Paging definitions for arm_v5. 4 */ 5 6/* 7 * Copyright (c) 2010, ETH Zurich. 8 * All rights reserved. 9 * 10 * This file is distributed under the terms in the attached LICENSE file. 11 * If you do not find this file, copies can be found by writing to: 12 * ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group. 13 */ 14 15#ifndef TARGET_ARM_BARRELFISH_KPI_PAGING_ARM_V5_H 16#define TARGET_ARM_BARRELFISH_KPI_PAGING_ARM_V5_H 17 18/* Default page size is 4K */ 19#define BASE_PAGE_BITS 12 20#define BASE_PAGE_SIZE (1u << BASE_PAGE_BITS) 21#define BASE_PAGE_MASK (BASE_PAGE_SIZE - 1) 22#define BASE_PAGE_OFFSET(a) ((a) & BASE_PAGE_MASK) 23 24/* 1MB large pages */ 25#define LARGE_PAGE_BITS 20 26#define LARGE_PAGE_SIZE (1u << LARGE_PAGE_BITS) 27#define LARGE_PAGE_MASK (LARGE_PAGE_SIZE - 1) 28#define LARGE_PAGE_OFFSET(a) ((a) & LARGE_PAGE_MASK) 29 30#define ARM_L1_OFFSET(addr) ((((uintptr_t)addr) >> 20) & 0xfff) // 12 bits 31#define ARM_L2_OFFSET(addr) ((((uintptr_t)addr) >> 12) & 0xff) // 8 bits 32#define ARM_PAGE_OFFSET(addr) ((uintptr_t)addr & 0xfff) // 12 bits 33 34// L1 Alignment determined by TTBR register (bits 13:0 ignored by hardware) 35#define ARM_L1_ALIGN 16384u 36 37#define ARM_L1_MAX_ENTRIES 4096u 38#define ARM_L1_BYTES_PER_ENTRY 4u 39#define ARM_L1_SECTION_BYTES (1024u * 1024u) 40#define ARM_L1_TABLE_BYTES (ARM_L1_MAX_ENTRIES * ARM_L1_BYTES_PER_ENTRY) 41 42#define ARM_L2_ALIGN 1024u 43#define ARM_L2_MAX_ENTRIES 256u 44#define ARM_L2_BYTES_PER_ENTRY 4u 45#define ARM_L2_TABLE_BYTES ARM_L2_ALIGN 46 47/* Page type independent page options */ 48#define KPI_PAGING_FLAGS_READ 0x01 49#define KPI_PAGING_FLAGS_WRITE 0x02 50#define KPI_PAGING_FLAGS_EXECUTE 0x04 51#define KPI_PAGING_FLAGS_NOCACHE 0x08 52#define KPI_PAGING_FLAGS_MASK 0x0f 53 54#endif // TARGET_ARM_BARRELFISH_KPI_PAGING_ARM_V5_H 55