1/** 2 * \file 3 * \brief PCI configuration space access. 4 */ 5 6/* 7 * Copyright (c) 2007, 2008, 2009, ETH Zurich. 8 * All rights reserved. 9 * 10 * This file is distributed under the terms in the attached LICENSE file. 11 * If you do not find this file, copies can be found by writing to: 12 * ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group. 13 */ 14 15#ifndef PCI_CONFSPACE_H 16#define PCI_CONFSPACE_H 17 18#define PCI_NBUSES 256 ///< Maximum number of PCI buses 19#define PCI_NDEVICES 32 ///< Maximum number of PCI devices on a bus 20#define PCI_NFUNCTIONS 8 ///< Maximum number of PCI functions on a device 21#define PCI_NBARS 6 ///< Maximum number of BARs per function 22#define PCI_NINTPINS 4 ///< Number of PCI wired interrupt pins (INTA-INTD) 23 24// XXX: this enum defines region types that must not overlap 25// with the KPI-defined enum region_type. 26enum user_region_type { 27 /* X86 */ 28 RegionType_LocalAPIC = RegionType_Max, ///< local APIC start address 29 RegionType_IOAPIC, ///< I/O APIC start address 30 /* ARMv8 */ 31 RegionType_GIC, ///< GIC Start Address 32 RegionType_GIC_DIST 33}; 34 35struct pci_address { 36 uint8_t bus; 37 uint8_t device; 38 uint8_t function; 39}; 40 41uint32_t pci_read_conf_header(struct pci_address *address, uint64_t dword); 42void pci_write_conf_header(struct pci_address *address, uint64_t dword, 43 uint32_t data); 44 45int pcie_confspace_init(struct capref, lpaddr_t pbase, uint16_t segment, uint8_t startbus, 46 uint8_t endbus); 47lvaddr_t pcie_confspace_access(struct pci_address addr); 48 49uint8_t pcie_get_endbus(void); 50void pcie_enable(void); 51void pcie_disable(void); 52 53struct pci_device_info *pci_get_device(uint64_t class_code, 54 uint64_t sub_class, uint64_t prog_if, uint64_t vendor_id, uint64_t device_id, 55 uint64_t bus, uint64_t device, uint64_t function); 56 57#endif 58