1/*
2 * Copyright (c) 2014 ETH Zurich.
3 * All rights reserved.
4 *
5 * This file is distributed under the terms in the attached LICENSE file.
6 * If you do not find this file, copies can be found by writing to:
7 * ETH Zurich D-INFK, Universitaetsstrasse 6, CH-8092 Zurich. Attn: Systems Group.
8 */
9
10#ifndef LIB_DMA_H
11#define LIB_DMA_H
12
13/* forward declarations */
14struct dma_device;
15struct dma_channel;
16struct dma_request;
17
18/* service name for the driver services */
19
20/// the service name for the exported devices
21#define IOAT_DMA_SERVICE_NAME "ioat_dma_svc"
22
23/// the service name for the exported devices
24#define XEON_PHI_DMA_SERVICE_NAME "xeon_phi_dma_svc"
25
26/* type declarations for the IDs */
27
28/// IOAT DMA device id
29typedef uint8_t dma_dev_id_t;
30
31/// DMA channel id
32typedef uint16_t dma_chan_id_t;
33
34/// IOAT DMA request ID
35typedef uint64_t dma_req_id_t;
36
37/**
38 * Enumeration of possible interrupt types supported by the hardware
39 */
40typedef enum dma_irq {
41    DMA_IRQ_DISABLED,     ///< interrupts are disabled
42    DMA_IRQ_MSIX,         ///< use MSI-X interrupts
43    DMA_IRQ_MSI,          ///< use MSI interrupts
44    DMA_IRQ_INTX,         ///< use normal INTx interrupts
45} dma_irq_t;
46
47/**
48 * Device types. Which DMA engine we have.
49 */
50typedef enum dma_dev_type {
51    DMA_DEV_TYPE_INVALID=0,
52    DMA_DEV_TYPE_IOAT=1,
53    DMA_DEV_TYPE_XEON_PHI=2,
54    DMA_DEV_TYPE_CLIENT=3
55} dma_dev_type_t;
56
57
58/// interrupt handler function type definition
59typedef void (*dma_irq_fn_t)(errval_t err, struct dma_channel *dev, void *arg);
60
61/**
62 * represents a mapped piece of memory for DMA management purposes
63 */
64struct dma_mem
65{
66    lvaddr_t vaddr;         ///< virtual address of the mapped region
67    lpaddr_t paddr;         ///< physical address of the underlying frame
68    uint64_t bytes;         ///< size of the region in bytes
69    struct capref frame;    ///< frame capability backing this region
70};
71
72/*
73 * service name defines
74 */
75#define DMA_SVC_NAME_IOAT       "ioat_dma_svc"
76#define DMA_SVC_NAME_XEON_PHI   "xeon_phi_dma_svc"
77
78
79#endif  /* LIB_DMA_H */
80