1/**
2 * \file
3 * \brief
4 */
5
6/*
7 * Copyright (c) 2007, 2008, 2009, 2010, 2011, ETH Zurich.
8 * All rights reserved.
9 *
10 * This file is distributed under the terms in the attached LICENSE file.
11 * If you do not find this file, copies can be found by writing to:
12 * ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group.
13 */
14
15#ifndef ARCH_X86_64_BARRELFISH_KPI_ASM_INLINES_H
16#define ARCH_X86_64_BARRELFISH_KPI_ASM_INLINES_H
17
18#ifndef __ASSEMBLER__
19
20#include <target/x86_64/barrelfish_kpi/registers_target.h>
21
22static inline void cpuid(uint32_t function, uint32_t *eax, uint32_t *ebx,
23                         uint32_t *ecx, uint32_t *edx)
24{
25    // make it possible to omit certain return registers
26    uint32_t a, b, c, d;
27    if (eax == NULL) {
28        eax = &a;
29    }
30    if (ebx == NULL) {
31        ebx = &b;
32    }
33    if (ecx == NULL) {
34        ecx = &c;
35    }
36    if (edx == NULL) {
37        edx = &d;
38    }
39    __asm volatile("cpuid"
40                   : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx)
41                   : "a" (function)
42                   );
43}
44
45
46/** \brief Atomic compare-and-swap on 128 bits
47 *
48 * If *dst == old then *dst = new, returns 0 on failure
49 *
50 * Note, dest should point to a 128bit structure that is to be overwritten
51 */
52static inline int cmpxchg128(volatile uint64_t dest[2], uint64_t old_top, uint64_t old_bot, uint64_t new_top, uint64_t new_bot)
53{
54    uint8_t ret;
55
56    __asm volatile (
57        "lock cmpxchg16b %1\n\t"
58        "setz %0\n\t"
59        : "=a"(ret), "=m"(*dest)//, "=d"(old_top), "=a"(old_bot)
60        : "a"(old_top), "d"(old_bot), "b"(new_top), "c"(new_bot), "m"(*dest)
61        : "memory");
62
63    return ret;
64}
65
66static inline void fpu_init(void)
67{
68    __asm volatile ("fninit");
69}
70
71#endif // __ASSEMBLER__
72
73#endif // ARCH_X86_64_BARRELFISH_KPI_ASM_INLINES_H
74