1/**
2 * \file
3 * \brief Some arch specific asm inlines
4 */
5
6/*
7 * Copyright (c) 2007, 2008, 2009, 2010, 2012, ETH Zurich.
8 * All rights reserved.
9 *
10 * This file is distributed under the terms in the attached LICENSE file.
11 * If you do not find this file, copies can be found by writing to:
12 * ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group.
13 */
14
15#ifndef ARCH_ARM_BARRELFISH_KPI_ARM_H
16#define ARCH_ARM_BARRELFISH_KPI_ARM_H
17
18#ifndef __ASSEMBLER__
19
20#if defined (__ARM_ARCH_7A__) || defined(__ARM_ARCH_7M__)
21
22static inline void dmb(void)
23{
24	__asm volatile ("dmb" : : : "memory");
25}
26
27#else
28
29static inline void dmb(void)
30{
31	__asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0) : "memory");
32}
33
34#endif
35
36static inline uint8_t is_cycle_counter_overflow(void)
37{
38	uint32_t regval;
39	__asm volatile ("mrc p15, 0, %0, c9, c12, 3\t\n" : "=r"(regval));
40
41	return (regval & 0x80000000);
42}
43
44static inline uint32_t get_cycle_count(void)
45{
46
47	uint32_t val;
48	__asm volatile ("mrc p15, 0, %0, c9, c13, 0\t\n": "=r"(val));
49
50	return  val;
51}
52
53
54static inline void reset_cycle_counter(void)
55{
56	uint32_t val = 1; //in general enable all counters
57	val |= 4;		  //reset cycle counter
58
59	// program the performance-counter control-register:
60	__asm volatile ("mcr p15, 0, %0, c9, c12, 0\t\n" :: "r"(val));
61
62	 // enable cycle counter:
63	__asm volatile ("mcr p15, 0, %0, c9, c12, 1\t\n" :: "r"(0x80000000));
64
65	// clear overflow:
66	__asm volatile ("MCR p15, 0, %0, c9, c12, 3\t\n" :: "r"(0x80000000));
67}
68
69#endif // __ASSEMBLER__
70
71#endif //  ARCH_ARM_BARRELFISH_KPI_ARM_H
72