1/** 2 * \file 3 * \brief Some arch specific asm inlines 4 */ 5 6/* 7 * Copyright (c) 2015, ETH Zurich. 8 * All rights reserved. 9 * 10 * This file is distributed under the terms in the attached LICENSE file. 11 * If you do not find this file, copies can be found by writing to: 12 * ETH Zurich D-INFK, Universitaetstr 6, CH-8092 Zurich. Attn: Systems Group. 13 */ 14 15#ifndef ARCH_AARCH64_BARRELFISH_KPI_ASM_INLINES_H 16#define ARCH_AARCH64_BARRELFISH_KPI_ASM_INLINES_H 17 18#ifndef __ASSEMBLER__ 19 20#include <stdint.h> 21 22static inline uint64_t rdtsc(void) 23{ 24 uint64_t ccnt; 25 __asm__ volatile("mrs %[ccnt], CNTVCT_EL0;" : [ccnt] "=r" (ccnt)); 26 return ccnt; 27} 28 29static inline uint64_t rdtscp(void) 30{ 31 uint64_t ccnt; 32 /* An ISB flushes the pipeline, and re-fetches the instructions from the 33 * cache or memory and ensures that the effects of any completed 34 * context-changing operation before the ISB are visible to any instruction 35 * after the ISB 36 */ 37 __asm__ volatile("isb" : : : "memory"); 38 __asm__ volatile("mrs %[ccnt], CNTVCT_EL0;" : [ccnt] "=r" (ccnt)); 39 return ccnt; 40} 41 42 43static inline void dmb(void) 44{ 45 __asm volatile ("dmb sy" : : : "memory"); 46} 47 48static inline uint8_t is_cycle_counter_overflow(void) 49{ 50 //NYI 51 return 0; 52} 53 54static inline uint32_t get_cycle_count(void) 55{ 56 //NYI 57 return 0; 58} 59 60 61static inline void reset_cycle_counter(void) 62{ 63 //NYI 64} 65 66#endif // __ASSEMBLER__ 67 68#endif // ARCH_AARCH64_BARRELFISH_KPI_ASM_INLINES_H 69