1/*
2 * Copyright (c) 2007, 2008, 2009, 2010, 2011 ETH Zurich.
3 * All rights reserved.
4 *
5 * This file is distributed under the terms in the attached LICENSE file.
6 * If you do not find this file, copies can be found by writing to:
7 * ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group.
8 */
9
10interface pci "The PCI Interface" {
11    typedef uint32 caps_per_bar[6]; // 6 == PCI_NBARS
12
13    /* Init PCI device */
14    rpc init_pci_device(in uint32 class_code,
15                        in uint32 sub_class,
16                        in uint32 prog_if,
17                        in uint32 vendor_id,
18                        in uint32 device_id,
19                        in uint32 bus,
20                        in uint32 dev,
21                        in uint32 fun,
22                        out errval err,
23                        out uint8 nr_allocated_bars // Number of bars supported
24                        );
25
26    /* Init legacy IO device */
27    rpc init_legacy_device(in uint16 iomin,
28                           in uint16 iomax,
29                           in uint8 irq,
30                           in uint8 coreid, // core ID for interrupt handler
31                           in uint32 vector,// interrupt vector (0 == no interrupt)
32                           out errval err,
33                           out cap iocap);
34
35    /* request a bar cap for a previously-initialised device */
36    rpc get_bar_cap(in uint32 idx,
37                    out errval err,
38                    out cap cap,
39                    out uint8 type,
40                    out uint8 bar_nr);
41
42    /* request an irq cap for a previously-initialised device */
43    rpc get_irq_cap(in uint16 idx, out errval err, out cap cap);
44
45    /* reregister interrupt for a previously-initialized device */
46    rpc reregister_interrupt(in uint32 class_code,
47                        in uint32 sub_class,
48                        in uint32 prog_if,
49                        in uint32 vendor_id,
50                        in uint32 device_id,
51                        in uint32 bus,
52                        in uint32 dev,
53                        in uint32 fun,
54                        in uint8 coreid,  // core ID for interrupt handler
55                        in uint32 vector, // interrupt vector (0 == no interrupt)
56                        out errval err);
57
58    /* Kludge: retrieve frame cap to VBE BIOS
59    rpc get_vbe_bios_cap(out errval err, out cap cap, out uint32 size);
60    rpc reset(out errval err);
61    rpc sleep(in int state, out errval err);  */
62
63    /* read PCI conf header */
64    rpc read_conf_header(in uint32 dword, out errval err, out uint32 val);
65
66    /* write PCI conf header */
67    rpc write_conf_header(in uint32 dword, in uint32 val, out errval err);
68    
69    /* Enable (legacy) interrupt */
70    rpc irq_enable(out errval err);
71
72    /* Enable MSI-X for the specified PCI device. */
73    rpc msix_enable_addr(in uint8 bus, in uint8 dev, in uint8 fn,
74                         out errval err,
75                         out uint16 vec_count);
76    rpc msix_enable(out errval err,
77                    out uint16 vec_count);
78
79    /* Configure specified MSI-X vector */
80    rpc msix_vector_init_addr(in uint8 bus, in uint8 dev, in uint8 fn,
81                              in uint16 idx,        /* Index of MSI-X vector */
82                              in uint8 destination, /* Interrupt Destination */
83                              in uint8 vector,      /* Interrupt Vector */
84                              out errval err);
85    rpc msix_vector_init(in uint16 idx,        /* Index of MSI-X vector */
86                         in uint8 destination, /* Interrupt Destination */
87                         in uint8 vector,      /* Interrupt Vector */
88                         out errval err);
89};
90