1/*
2 * Copyright (c) 2014 ETH Zurich. All rights reserved.
3 *
4 * This file is distributed under the terms in the attached LICENSE file.
5 * If you do not find this file, copies can be found by writing to:
6 * ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group.
7 */
8
9/*
10 * xeon_phi_i2c_oc.dev
11 *
12 * description: register definitions for the I2C Bus Overclocking Interface
13 * 
14 * Protection Level: Ring0
15 * Visibility: Host / Coprocessor
16 * Reset Domain: CSR_RESET, HOT_RESET
17 * Register Access: TRM, I2C
18 */
19
20device xeon_phi_i2c_oc lsbfirst ( addr base ) "Intel Xeon Phi I2C Bus Overclocking Unit" {
21	
22	/*
23	 *
24	 */
25	register icr rw addr(base, 0x1000) "I2C Control Register for LRB Over-clocking Unit" { 
26		value 32 "Value";
27	};
28	
29	/*
30	 * 
31	 */
32	register isr rw addr(base, 0x1004) "I2C Status Register for LRB Over-clocking Unit" { 
33		value 32 "Value";
34	};
35	
36	/*
37	 * 
38	 */
39	register isar rw addr(base, 0x1008) "I2C Slave Address Register for LRB Over-clocking Unit" { 
40		value 32 "Value";
41	};
42	
43	/*
44	 * 
45	 */
46	register idbr rw addr(base, 0x100C) "I2C Data Buffer Register for LRB Over-clocking Unit" { 
47		value 32 "Value";
48	};
49	
50	/*
51	 * 
52	 */
53	register idmr rw addr(base, 0x1010) "2C Bus Monitor Register for LRB Over-clocking Unit" { 
54		value 32 "Value";
55	};
56
57};
58
59