1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstr. 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_iss_isif.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_iss_isif msbfirst ( addr base ) "" { 29 30 31 constants dwen_status width(1) "" { 32 DWEN_0 = 0 "Disable"; 33 DWEN_1 = 1 "Enable"; 34 }; 35 36 register isif_syncen addr(base, 0x0) "" { 37 _ 16 mbz; 38 _ 14 mbz; 39 dwen 1 rw type(dwen_status) "Controls the storage of image sensor RAW data in memory. This bit is loaded with the timing of the internal VD signal: it becomes active starting at the lead of the VD signal that comes after 1 is written in this bit."; 40 syen 1 rw type(dwen_status) "Controls ON/OFF of VD/HD output. Internal timing generator becomes active and VD/HD output starts when 1 is written in this bit. In case of input, VD/HD loading begins."; 41 }; 42 43 constants mdfs_status width(1) "" { 44 MDFS_1_r = 1 "Even field"; 45 MDFS_0_r = 0 "Odd field"; 46 }; 47 48 constants inpmod_status width(2) "" { 49 INPMOD_0 = 0 "RAW data"; 50 INPMOD_1 = 1 "YCbCr 16bit"; 51 INPMOD_3 = 3 "Reserved"; 52 INPMOD_2 = 2 "YCbCr 8bit"; 53 }; 54 55 constants ovf_status width(1) "" { 56 OVF_0 = 0 "No overflow pending (r) No action (w)"; 57 OVF_1 = 1 "Overflow pending (r) Clear overflow (w)"; 58 }; 59 60 constants ccdw_status width(3) "" { 61 CCDW_6 = 6 "Reserved"; 62 CCDW_1 = 1 "1-bit right shift out[15:0] = 00000 & data[11:1]"; 63 CCDW_7 = 7 "Reserved"; 64 CCDW_0 = 0 "No shift out[15:0] = 0000 & data[11:0]"; 65 CCDW_2 = 2 "2-bit right shift out[15:0] = 000000 & data[11:2]"; 66 CCDW_4 = 4 "4-bit right shift out[15:0] = 00000000 & data[11:4]"; 67 CCDW_5 = 5 "Reserved"; 68 CCDW_3 = 3 "3-bit right shift out[15:0] = 0000000 & data[11:3]"; 69 }; 70 71 constants ccdmd_status width(1) "" { 72 CCDMD_0 = 0 "Progressive image sensor"; 73 CCDMD_1 = 1 "Interlaced image sensor"; 74 }; 75 76 constants dpol_status width(1) "" { 77 DPOL_0 = 0 "No change"; 78 DPOL_1 = 1 "One's complement"; 79 }; 80 81 constants swen_status width(1) "" { 82 SWEN_0 = 0 "WEN not used"; 83 SWEN_1 = 1 "Use external WEN"; 84 }; 85 86 constants fipol_status width(1) "" { 87 FIPOL_0 = 0 "Positive"; 88 FIPOL_1 = 1 "Negative"; 89 }; 90 91 constants fidd_status width(1) "" { 92 FIDD_0 = 0 "Input"; 93 FIDD_1 = 1 "Output"; 94 }; 95 96 register isif_modeset addr(base, 0x4) "" { 97 _ 16 mbz; 98 mdfs 1 ro type(mdfs_status) "Field Status This bit indicates the status of the current FLD signal when the ISIF module is in interlaced mode."; 99 hlpf 1 rw type(dwen_status) "Low pass filter enable. When this bit is enabled, a 3-tap (1/4 + 1/2 Z + 1/4 Z) filtering process is performed on the sensor data."; 100 inpmod 2 rw type(inpmod_status) "Data input mode:"; 101 ovf 1 rw type(ovf_status) "ISIF module write port overflow status bit If the write port of the ISIF module overflows when writing data to SDRAM, this bit will toggle."; 102 ccdw 3 rw type(ccdw_status) "This bit enables to shift right (divide) the up-to-12-bit RAW data value when writing out to SDRAM. The effect is that the dynamic of the output signal is decreased. The ISIF_MODESET.CCDW, ISIF_HSIZE.ADCR, ISIF_HSIZE.HSIZE, ISIF_CCDCFG.BSWD, ISIF_CCDCFG.MSBINV, ISIF_CCDCFG.SDRPACK bit fields control how pixel data are stored to SDRAM."; 103 ccdmd 1 rw type(ccdmd_status) "Field mode: This bit selects the type of image sensor: interlaced or progressive"; 104 dpol 1 rw type(dpol_status) "Image sensor input data polarity"; 105 swen 1 rw type(swen_status) "External WEN selection In case this bit and SYNCEN.DWEN are set to 1, the external WEN signal is used to store image sensor data to memory."; 106 fipol 1 rw type(fipol_status) "FLD Signal Polarity"; 107 hdpol 1 rw type(fipol_status) "HD Sync Signal Polarity"; 108 vdpol 1 rw type(fipol_status) "VD Sync Signal Polarity"; 109 fidd 1 rw type(fidd_status) "FLD Signal Direction. There must be at least three clock cycles between the time this bit is modified and the HD/VD pulse for the start of frame comes."; 110 hdvdd 1 rw type(fidd_status) "VD,HD Sync Signal Direction. There must be at least three clock cycles between the time this bit is modified and the HD/VD pulse for the start of frame comes."; 111 }; 112 113 register isif_hdw addr(base, 0x8) "" { 114 _ 16 mbz; 115 _ 4 mbz; 116 hdw 12 rw "HD width: Sets width of HD. HD width = HDW + 1 clock"; 117 }; 118 119 register isif_vdw addr(base, 0xC) "" { 120 _ 16 mbz; 121 _ 4 mbz; 122 vdw 12 rw "VD width : Sets width of VD. VD width = VDW + 1 line"; 123 }; 124 125 register isif_ppln addr(base, 0x10) "" { 126 _ 16 mbz; 127 ppln 16 rw "Pixels per line Number of pixel clock periods in one line HD period = PPLN+1 pixel clocks. PPLN is not used when HD and VD are inputs, that is, when VDHDOUT in MODESET is cleared to 0. *This bit field is latched by VD."; 128 }; 129 130 register isif_lpfr addr(base, 0x14) "Line per Frame/Field" { 131 _ 16 mbz; 132 lpfr 16 rw "Half lines per filed or frame Sets number of half lines per frame or field. VD period = (LPFR+1)/2 lines. LPFR is not used when HD and are inputs, that is, when VDHDOUT in MODESET is cleared to 0. *This bit field is latched by VD."; 133 }; 134 135 register isif_sph addr(base, 0x18) "Start Pixel Horizontal" { 136 _ 16 mbz; 137 _ 1 mbz; 138 sph 15 rw "The first pixel in a line to be stored to memory."; 139 }; 140 141 register isif_lnh addr(base, 0x1C) "" { 142 _ 16 mbz; 143 _ 1 mbz; 144 lnh 15 rw "Number of pixels in an line to be stored to memory. Number of pixels = LNH + 1."; 145 }; 146 147 register isif_slv0 addr(base, 0x20) "SDRAM output vertical field 0 start line control" { 148 _ 17 mbz; 149 slv0 15 rw "Start Line, Vertical (Field 0)Sets line at which data output to SDRAM will begin, measured from the start of VD *This bit field is latched by VD. ."; 150 }; 151 152 register isif_slv1 addr(base, 0x24) "SDRAM output vertical field 1 start line control" { 153 _ 17 mbz; 154 slv1 15 rw "Start Line, Vertical (Field 1)Sets line at which data output to SDRAM will begin, measured from the start of VD *This bit field is latched by VD. ."; 155 }; 156 157 register isif_lnv addr(base, 0x28) "" { 158 _ 16 mbz; 159 _ 1 mbz; 160 lnv 15 rw "The number of lines to be stored to memory. Number of lines = LNV + 1"; 161 }; 162 163 constants clho_status width(8) "" { 164 CLHO_0 = 0 "Pixel invalid"; 165 CLHO_1 = 1 "Pixel valid"; 166 }; 167 168 register isif_culh addr(base, 0x2C) "" { 169 _ 16 mbz; 170 clho 8 rw type(clho_status) "Culling Pattern in ODD Line: Sets culling pattern when data is loaded into memory (odd lines). Example: 0xAA: 1 / 2 horizontal direction culling. LSB becomes left side on screen."; 171 clhe 8 rw type(clho_status) "Culling Pattern in Even Line: Sets culling pattern when data is loaded into memory (even lines)."; 172 }; 173 174 register isif_culv addr(base, 0x30) "" { 175 _ 16 mbz; 176 _ 8 mbz; 177 culv 8 rw type(clho_status) "Culling Pattern in Vertical Line Example: 0x88: 1/4 vertical direction culling. LSB becomes top side on screen."; 178 }; 179 180 constants adcr_status width(1) "" { 181 ADCR_0 = 0 "Address increment."; 182 ADCR_1 = 1 "Address decrement."; 183 }; 184 185 register isif_hsize addr(base, 0x34) "SDRAM output control register" { 186 _ 16 mbz; 187 _ 3 mbz; 188 adcr 1 rw type(adcr_status) "SDRAM address decrement. By setting this bit, memory address in a line is automatically decreased so that a line can be Horizontally flipped in memory. The ISIF_MODESET.CCDW, ISIF_HSIZE.ADCR, ISIF_HSIZE.HSIZE, ISIF_CCDCFG.BSWD, ISIF_CCDCFG.MSBINV, ISIF_CCDCFG.SDRPACK bit fields control how pixel data are stored to SDRAM."; 189 hsize 12 rw "Memory address offset between the lines. Specify the offset in 32-byte units."; 190 }; 191 192 constants fiinv_status width(1) "" { 193 FIINV_0 = 0 "No change."; 194 FIINV_1 = 1 "Inverse FID"; 195 }; 196 197 constants fofst_status width(2) "" { 198 FOFST_0 = 0 "+1 line"; 199 FOFST_1 = 1 "+2 lines"; 200 FOFST_3 = 3 "+4 lines"; 201 FOFST_2 = 2 "+3 lines"; 202 }; 203 204 constants lofstee_status width(3) "" { 205 LOFSTEE_0 = 0 "+1 line"; 206 LOFSTEE_1 = 1 "+2 lines"; 207 LOFSTEE_2 = 2 "+3 lines"; 208 LOFSTEE_3 = 3 "+4 lines"; 209 LOFSTEE_4 = 4 "- 1 line"; 210 LOFSTEE_5 = 5 "- 2 lines"; 211 LOFSTEE_6 = 6 "- 3 lines"; 212 LOFSTEE_7 = 7 "- 4 lines"; 213 }; 214 215 register isif_sdofst addr(base, 0x38) "SDRAM output control register" { 216 _ 17 mbz; 217 fiinv 1 rw type(fiinv_status) "FID polarity: This bit inverse a FID polarity."; 218 fofst 2 rw type(fofst_status) "Field line offset value in odd (FID = 1) field"; 219 lofstee 3 rw type(lofstee_status) "Field line offset value in even line, even field"; 220 lofstoe 3 rw type(lofstee_status) "Field line offset value in odd line, even field"; 221 lofsteo 3 rw type(lofstee_status) "Field line offset value in even line, odd field"; 222 lofstoo 3 rw type(lofstee_status) "Field line offset value in odd line, odd field"; 223 }; 224 225 register isif_cadu addr(base, 0x3C) "SDRAM output control register" { 226 _ 16 mbz; 227 _ 5 mbz; 228 cadu 11 rw "Memory Address (Upper 11-bits): Specifies the memory destination address. The actual address is the value set here multiplied by 32bytes."; 229 }; 230 231 register isif_cadl addr(base, 0x40) "SDRAM output control register" { 232 _ 16 mbz; 233 cadl 16 rw "Memory Address (Lower 16-bits): Specifies the memory destination address. The actual address is the value set here multiplied by 32bytes."; 234 }; 235 236 constants corrsft_status width(3) "" { 237 CORRSFT_6 = 6 "6-bit left shift"; 238 CORRSFT_1 = 1 "1-bit left shift"; 239 CORRSFT_7 = 7 "Reserved"; 240 CORRSFT_0 = 0 "No shift"; 241 CORRSFT_2 = 2 "2-bit left shift"; 242 CORRSFT_4 = 4 "4-bit left shift"; 243 CORRSFT_5 = 5 "5-bit left shift"; 244 CORRSFT_3 = 3 "3-bit left shift"; 245 }; 246 247 constants linmd_status width(1) "" { 248 LINMD_0 = 0 "Uniform sampling"; 249 LINMD_1 = 1 "Non-uniform sampling"; 250 }; 251 252 register isif_lincfg0 addr(base, 0x44) "INPUT LINEARIZATION CTRL REGISTER" { 253 _ 16 mbz; 254 _ 9 mbz; 255 corrsft 3 rw type(corrsft_status) "Shift up value for the correction value (S10)."; 256 _ 2 mbz; 257 linmd 1 rw type(linmd_status) "Linearization Mode:"; 258 linen 1 rw type(dwen_status) "Linearization Enable:"; 259 }; 260 261 register isif_lincfg1 addr(base, 0x48) "INPUT LINEARIZATION CTRL REGISTER" { 262 _ 16 mbz; 263 _ 5 mbz; 264 lutscl 11 rw "Scale factor (U11Q10) for LUT input. Range: 0 - 1+1023/1024 It is applied to the Input Data before looking up the correction factor. The scale factor is only applied to the table input. It is not applied when using the input value to compute the output."; 265 }; 266 267 constants cp0_f1_status width(2) "" { 268 CP0_F1_0 = 0 "R / Ye"; 269 CP0_F1_1 = 1 "Gr / Cy"; 270 CP0_F1_3 = 3 "B / Mg"; 271 CP0_F1_2 = 2 "Gb / G"; 272 }; 273 274 register isif_ccolp addr(base, 0x4C) "" { 275 _ 16 mbz; 276 cp0_f1 2 rw type(cp0_f1_status) "Specifies color pattern for pixel position 0 (Field 1) Pixel position 0 corresponds to pixel count=0 at even line in case of CFAP= 0, and to pixel count=0 in case of CFAP= 1."; 277 cp1_f1 2 rw type(cp0_f1_status) "Specifies color pattern for pixel position 1 (Field 1) Pixel position 1 corresponds to pixel count=1 at even line in case of CFAP= 0, and to pixel count=1 in case of CFAP= 1."; 278 cp2_f1 2 rw type(cp0_f1_status) "Specifies color pattern for pixel position 2 (Field 1) Pixel position 2 corresponds to pixel count=0 at odd line in case of CFAP= 0, and to pixel count=2 in case of CFAP= 1."; 279 cp3_f1 2 rw type(cp0_f1_status) "Specifies color pattern for pixel position 3 (Field 1) Pixel position 3 corresponds to pixel count=1 at odd line in case of CFAP= 0. Not applicable for CFAP= 1."; 280 cp0_f0 2 rw type(cp0_f1_status) "Specifies color pattern for pixel position 0 (Field 0) Pixel position 0 corresponds to pixel count=0 at even line in case of CFAP= 0, and to pixel count=0 in case of CFAP= 1."; 281 cp1_f0 2 rw type(cp0_f1_status) "Specifies color pattern for pixel position 1 (Field 0) Pixel position 1 corresponds to pixel count=1 at even line in case of CFAP= 0, and to pixel count=1 in case of CFAP= 1."; 282 cp2_f0 2 rw type(cp0_f1_status) "Specifies color pattern for pixel position 2 (Field 0) Pixel position 2 corresponds to pixel count=0 at odd line in case of CFAP= 0, and to pixel count=2 in case of CFAP= 1."; 283 cp3_f0 2 rw type(cp0_f1_status) "Specifies color pattern for pixel position 3 (Field 0) Pixel position 3 corresponds to pixel count=1 at odd line in case of CFAP= 0. Not applicable for CFAP= 1."; 284 }; 285 286 register isif_crgain addr(base, 0x50) "" { 287 _ 16 mbz; 288 _ 4 mbz; 289 cgr 12 rw "R/Ye gain: Performs gain adjustment on image sensor data. U12Q9. Range: 0 - 7+511/512"; 290 }; 291 292 register isif_cgrgain addr(base, 0x54) "" { 293 _ 16 mbz; 294 _ 4 mbz; 295 cggr 12 rw "Gr/Cy gain: Performs gain adjustment on image sensor data. U12Q9. Range: 0 - 7+511/512"; 296 }; 297 298 register isif_cgbgain addr(base, 0x58) "" { 299 _ 16 mbz; 300 _ 4 mbz; 301 cggb 12 rw "Gb/Cy gain: Performs gain adjustment on image sensor data. U12Q9. Range: 0 - 7+511/512"; 302 }; 303 304 register isif_cbgain addr(base, 0x5C) "" { 305 _ 16 mbz; 306 _ 4 mbz; 307 cgb 12 rw "B/Mg gain: Performs gain adjustment on image sensor data. U12Q9. Range: 0 - 7+511/512"; 308 }; 309 310 register isif_cofsta addr(base, 0x60) "" { 311 _ 16 mbz; 312 _ 4 mbz; 313 coft 12 rw "Image sensor offset: Performs offset value adjustment on image sensor data (0~4095)."; 314 }; 315 316 register isif_vdint0 addr(base, 0x70) "" { 317 _ 16 mbz; 318 _ 1 mbz; 319 cvd0 15 rw "VD0 Interrupt timing in a field (line number)."; 320 }; 321 322 register isif_vdint1 addr(base, 0x74) "" { 323 _ 16 mbz; 324 _ 1 mbz; 325 cvd1 15 rw "VD1 Interrupt timing in a field (line number)."; 326 }; 327 328 register isif_vdint2 addr(base, 0x78) "" { 329 _ 16 mbz; 330 _ 1 mbz; 331 cvd2 15 rw "VD2 Interrupt timing in a field (line number)."; 332 }; 333 334 constants dpcmpre_status width(1) "" { 335 DPCMPRE_0 = 0 "Predictor 1"; 336 DPCMPRE_1 = 1 "Predictor 2"; 337 }; 338 339 register isif_misc addr(base, 0x7C) "" { 340 _ 16 mbz; 341 _ 2 mbz; 342 dpcmpre 1 rw type(dpcmpre_status) "Selects Predictor for DPCM Encoder (12-8)"; 343 dpcmen 1 rw type(dwen_status) "Enables DPCM Encoding (12-8)"; 344 _ 11 mbz; 345 _ 1 mbz; 346 }; 347 348 constants cfap_status width(1) "" { 349 CFAP_0 = 0 "Mosaic color pattern. It should look like this. G R G R G R G R G R . . . B G B G B G B G B G . . . G R G R G R G R G R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ."; 350 CFAP_1 = 1 "Stripe color pattern. It should look like this. R G B R G B R G B . . . R G B R G B R G B . . . R G B R G B R G B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ."; 351 }; 352 353 constants gwdi_status width(4) "" { 354 GWDI_6 = 6 "bit 9"; 355 GWDI_1 = 1 "bit 14"; 356 GWDI_10 = 10 "Reserved"; 357 GWDI_7 = 7 "bit 8"; 358 GWDI_13 = 13 "Reserved"; 359 GWDI_0 = 0 "bit 15"; 360 GWDI_2 = 2 "bit 13"; 361 GWDI_8 = 8 "bit 7"; 362 GWDI_9 = 9 "Reserved"; 363 GWDI_11 = 11 "Reserved"; 364 GWDI_4 = 4 "bit 11"; 365 GWDI_5 = 5 "bit 10"; 366 GWDI_15 = 15 "Reserved"; 367 GWDI_12 = 12 "Reserved"; 368 GWDI_3 = 3 "bit 12"; 369 GWDI_14 = 14 "Reserved"; 370 }; 371 372 register isif_cgammawd addr(base, 0x80) "" { 373 _ 16 mbz; 374 _ 1 mbz; 375 wben2 1 rw type(dwen_status) "White Balance Enable for H3A"; 376 wben1 1 rw type(dwen_status) "White Balance Enable for IPIPE"; 377 wben0 1 rw type(dwen_status) "White Balance Enable for memory capture"; 378 _ 1 mbz; 379 ofsten2 1 rw type(dwen_status) "Offset control Enable for H3A"; 380 ofsten1 1 rw type(dwen_status) "Offset control Enable for IPIPE"; 381 ofsten0 1 rw type(dwen_status) "Offset control Enable for SDRAM capture"; 382 _ 2 mbz; 383 cfap 1 rw type(cfap_status) "Selects CFA pattern"; 384 gwdi 4 rw type(gwdi_status) "Selects MSB position of Input Data"; 385 ccdtbl 1 rw type(dwen_status) "On/Off control of A-law table for SDRAM capture"; 386 }; 387 388 register isif_rec656if addr(base, 0x84) "INPUT CONFIG REGISTER" { 389 _ 16 mbz; 390 _ 14 mbz; 391 r656on 1 rw type(dwen_status) "CCIR Rec.656 interface mode"; 392 eccfvh 1 rw type(dwen_status) "Error correction of FVH code"; 393 }; 394 395 constants vldc_status width(1) "" { 396 VLDC_0 = 0 "Enable"; 397 VLDC_1 = 1 "Disable"; 398 }; 399 400 constants bswd_status width(1) "" { 401 BSWD_0 = 0 "Disable"; 402 BSWD_1 = 1 "Enable (swap)"; 403 }; 404 405 constants y8pos_status width(1) "" { 406 Y8POS_0 = 0 "even pixel"; 407 Y8POS_1 = 1 "odd pixel"; 408 }; 409 410 constants trgsel_status width(1) "" { 411 TRGSEL_0 = 0 "DWEN register"; 412 TRGSEL_1 = 1 "FID input port"; 413 }; 414 415 constants wenlog_status width(1) "" { 416 WENLOG_0 = 0 "internal valid signal and WEN signal is ANDed logically."; 417 WENLOG_1 = 1 "internal valid signal and WEN signal is ORed logically."; 418 }; 419 420 constants fidmd_status width(2) "" { 421 FIDMD_0 = 0 "latch the FID at the VSYNC timing"; 422 FIDMD_1 = 1 "no latch the FID"; 423 FIDMD_3 = 3 "Reserved"; 424 FIDMD_2 = 2 "Reserved"; 425 }; 426 427 constants bt656_status width(1) "" { 428 BT656_0 = 0 "8 bits"; 429 BT656_1 = 1 "10 bits"; 430 }; 431 432 constants ycinswp_status width(1) "" { 433 YCINSWP_0 = 0 "YIN7-0 = Y signal / CIN7-0 = C signal"; 434 YCINSWP_1 = 1 "YIN7-0 = C signal / CIN7-0 = Y signal"; 435 }; 436 437 constants sdrpack_status width(2) "" { 438 SDRPACK_0 = 0 "16 bits / pixel"; 439 SDRPACK_1 = 1 "12 bits / pixel"; 440 SDRPACK_3 = 3 "Reserved"; 441 SDRPACK_2 = 2 "8 bits / pixel"; 442 }; 443 444 register isif_ccdcfg addr(base, 0x88) "" { 445 _ 16 mbz; 446 vldc 1 rw type(vldc_status) "On/off control of CPU registers resynchronize function by VSYNC. All the others are shadowed registers, where register values are updated at V-sync timing by default. If VDLC=1, ISIF register values are updated immediately after register write just like non-shadowed registers."; 447 _ 1 mbz; 448 msbinvi 1 rw type(dwen_status) "MSB inverse of CIN port when the data are captured to SDRAM. The ISIF_MODESET.CCDW, ISIF_HSIZE.ADCR, ISIF_HSIZE.HSIZE, ISIF_CCDCFG.BSWD, ISIF_CCDCFG.MSBINV, ISIF_CCDCFG.SDRPACK bit fields control how pixel data are stored to SDRAM."; 449 bswd 1 rw type(bswd_status) "On/off control of Byte SWAP function when SDRAM capturing. The ISIF_MODESET.CCDW, ISIF_HSIZE.ADCR, ISIF_HSIZE.HSIZE, ISIF_CCDCFG.BSWD, ISIF_CCDCFG.MSBINV, ISIF_CCDCFG.SDRPACK bit fields control how pixel data are stored to SDRAM."; 450 y8pos 1 rw type(y8pos_status) "Selects Y signal position when in 8bit input mode"; 451 extrg 1 rw "Setting 1 to this register, the SDRAM address is initialized at the rising edge of FID input signal or DWEN register."; 452 trgsel 1 rw type(trgsel_status) "Select trigger source signal of SDRAM address initializing in case EXTRG=1."; 453 wenlog 1 rw type(wenlog_status) "Specifies the CCD valid area."; 454 fidmd 2 rw type(fidmd_status) "Specifies FID detection mode"; 455 bt656 1 rw type(bt656_status) "Selects bit width of CCIR656. This bit applies only ifISIF_REC656IF.R656ON = 1."; 456 ycinswp 1 rw type(ycinswp_status) "The ISIF module has a 16-bit interface. When 16-bit YUV data are input, the luma data (YIN7-0) are expected to be on the 8 MS bits and the chroma (CIN7-0) data are expected to be on the LS bits. This bit enables to swap the 8 MS bits with the 8 LS bits of the interface in case the luma and chroma do not come in the correct order. See the top-level ISIF block diagram."; 457 _ 1 mbz; 458 _ 1 mbz; 459 sdrpack 2 rw type(sdrpack_status) "This bit field selects how the data are stored to SDRAM. There can be 8, 12 or 16 bits per pixel. The ISIF_MODESET.CCDW, ISIF_HSIZE.ADCR, ISIF_HSIZE.HSIZE, ISIF_CCDCFG.BSWD, ISIF_CCDCFG.MSBINV, ISIF_CCDCFG.SDRPACK bit fields control how pixel data are stored to SDRAM."; 460 }; 461 462 constants vdfcuda_status width(1) "" { 463 VDFCUDA_0 = 0 "The whole line is corrected."; 464 VDFCUDA_1 = 1 "Pixels upper than the defect are not corrected."; 465 }; 466 467 constants vdfcsl_status width(2) "" { 468 VDFCSL_0 = 0 "Defect level subtraction. Just fed through if data are saturating."; 469 VDFCSL_1 = 1 "Defect level subtraction. Horizontal interpolation ((i-2)+(i+2))/2 if data are saturating."; 470 VDFCSL_3 = 3 "Reserved"; 471 VDFCSL_2 = 2 "Horizontal interpolation ((i-2)+(i+2))/2."; 472 }; 473 474 register isif_dfcctl addr(base, 0x8C) "VERTICAL LINE DEFCT CTRL REGISTER" { 475 _ 16 mbz; 476 _ 5 mbz; 477 vdflsft 3 rw "Vertical line Defect level shift value Defect Level (value to be subtracted from the data) is 8bit width, but can be up-shifted up to 6bits by VDFLSFT. Left shift value = VDFLSFT (Range: 0-6) Setting 7 to VDFLSFT is not allowed."; 478 vdfcuda 1 rw type(vdfcuda_status) "Vertical line Defect Correction upper pixels disable."; 479 vdfcsl 2 rw type(vdfcsl_status) "Vertical line Defect Correction mode select."; 480 vdfcen 1 rw type(dwen_status) "Vertical line Defect Correction enable. This bit field is latched by VD."; 481 _ 4 mbz; 482 }; 483 484 register isif_vdfsatlv addr(base, 0x90) "VERTICAL LINE DEFCT CTRL REGISTER" { 485 _ 16 mbz; 486 _ 4 mbz; 487 vdfslv 12 rw "Vertical line Defect Correction saturation level. VDFSLV is U12 (Range: 0 - 4,095)."; 488 }; 489 490 constants dfcmarst_status width(1) "" { 491 DFCMARST_0 = 0 "Increment the memory address"; 492 DFCMARST_1 = 1 "Clear the memory address to offset 0"; 493 }; 494 495 register isif_dfcmemctl addr(base, 0x94) "VERTICAL LINE DEFCT CTRL REGISTER" { 496 _ 16 mbz; 497 _ 11 mbz; 498 dfcmclr 1 rw "Defect correction. Memory clear. Writing 1 to this bit clears the memory contents to all zero. It will be automatically cleared to `0` when the memory clear is completed."; 499 _ 1 mbz; 500 dfcmarst 1 rw type(dfcmarst_status) "Defect correction. Memory address reset. Setting DFCMWR or DFCMRD with LSCMARST set starts memory access to address offset 0. DFCMARST is automatically cleared if data transfer completes. Setting DFCMWR or DFCMRD with LSCMARST cleared starts memory access to the next address."; 501 dfcmrd 1 rw "Defect correction. Memory read [for debug purpose] Writing 1 to this bit starts reading from the memory. It will be automatically cleared when the data transfer is completed, and the data can be read from DFCMEM4-0."; 502 dfcmwr 1 rw "Defect correction. Memory write Writing 1 to this bit starts writing to the memory. It will be automatically cleared when the data transfer is completed. DFCMEM4-0 should be set prior to the memory access."; 503 }; 504 505 register isif_dfcmem0 addr(base, 0x98) "Defect correction memory" { 506 _ 16 mbz; 507 _ 3 mbz; 508 dfcmem0 13 rw "Defect correction memory 0 Sets V position of the defects."; 509 }; 510 511 register isif_dfcmem1 addr(base, 0x9C) "Defect correction memory" { 512 _ 16 mbz; 513 _ 3 mbz; 514 dfcmem1 13 rw "Defect correction memory 1 Sets H position of the defects."; 515 }; 516 517 register isif_dfcmem2 addr(base, 0xA0) "Defect correction memory" { 518 _ 16 mbz; 519 _ 8 mbz; 520 dfcmem2 8 rw "Defect correction Memory 2 Set SUB1: Defect level of the Vertical line defect position (V = Vdefect). DFCMEM2 can be up shifted according to VDFLSFT, and subtracted from the data for Vertical line defect correction."; 521 }; 522 523 register isif_dfcmem3 addr(base, 0xA4) "Defect correction memory" { 524 _ 16 mbz; 525 _ 8 mbz; 526 dfcmem3 8 rw "<Defect correction> Memory 3 Set SUB2: Defect level of the pixels upper than the Vertical line defect (V < Vdefect). DFCMEM3 can be up shifted according to VDFLSFT, and subtracted from the data for Vertical line defect correction."; 527 }; 528 529 register isif_dfcmem4 addr(base, 0xA8) "Defect correction memory" { 530 _ 16 mbz; 531 _ 8 mbz; 532 dfcmem4 8 rw "Memory 4 Set SUB3: Defect level of the pixels lower than the Vertical line defect (V > Vdefect). DFCMEM4 can be up shifted according to VDFLSFT, and subtracted from the data for Vertical line defect correction."; 533 }; 534 535 register isif_clampcfg addr(base, 0xAC) "BLACK CLAMP CTRL REGISTER" { 536 _ 16 mbz; 537 _ 11 mbz; 538 clmd 1 rw type(vdfcsl_status) "Black clamp mode Clamp value can be calculated regardless of the color or can be calculated separately for each 4 colors."; 539 _ 1 mbz; 540 clhmd 2 rw type(vdfcsl_status) "Horizontal Clamp mode"; 541 clen 1 rw type(dwen_status) "Black Clamp Enable Enables clamp value to be subtracted from Image data."; 542 }; 543 544 register isif_cldcofst addr(base, 0xB0) "BLACK CLAMP CTRL REGISTER" { 545 _ 16 mbz; 546 _ 3 mbz; 547 cldc 13 rw "DC offset for black clamp This value is added to the incoming pixels regardless whether optical black clamp is enabled (ISIF_CLAMPCFG.CLEN). This value is in S13Q0 format."; 548 }; 549 550 register isif_clsv addr(base, 0xB4) "BLACK CLAMP CTRL REGISTER" { 551 _ 16 mbz; 552 _ 3 mbz; 553 clsv 13 rw "Black Clamp Start position (V). Sets the line number where clamp value subtraction starts. Range: 0 - 8191"; 554 }; 555 556 constants clhwn_status width(2) "" { 557 CLHWN_0 = 0 "Window is 2 pixels tall (N=1)"; 558 CLHWN_1 = 1 "Window is 4 pixels tall (N=2)"; 559 CLHWN_3 = 3 "Window is 16 pixels tall (N=4)"; 560 CLHWN_2 = 2 "Window is 8 pixels tall (N=3)"; 561 }; 562 563 constants clhwm_status width(2) "" { 564 CLHWM_0 = 0 "Window is 32 pixels wide (M=5)"; 565 CLHWM_1 = 1 "Window is 64 pixels wide (M=6)"; 566 CLHWM_3 = 3 "Window is 256 pixels wide (M=8)"; 567 CLHWM_2 = 2 "Window is 128 pixels wide (M=7)"; 568 }; 569 570 constants clhlmt_status width(1) "" { 571 CLHLMT_0 = 0 "Limitation disabled"; 572 CLHLMT_1 = 1 "Limitation enabled"; 573 }; 574 575 constants clhwbs_status width(1) "" { 576 CLHWBS_0 = 0 "The most left window"; 577 CLHWBS_1 = 1 "The most right window"; 578 }; 579 580 register isif_clhwin0 addr(base, 0xB8) "BLACK CLAMP CTRL REGISTER" { 581 _ 16 mbz; 582 _ 2 mbz; 583 clhwn 2 rw type(clhwn_status) "Horizontal Black clamp - Vertical dimension of a Window (2)."; 584 _ 2 mbz; 585 clhwm 2 rw type(clhwm_status) "Horizontal Black clamp - Horizontal dimension of a Window (2)."; 586 _ 1 mbz; 587 clhlmt 1 rw type(clhlmt_status) "Horizontal Black clamp - Pixel value limitation for the Horizontal clamp value calculation. If this bit is set, the maximum pixel value to be used for the clamp value calculation would be limited to 1023. By setting this bit, the pixel value greater than 1023 will be replaced by the last pixel value which was equal to or less than 1023. In case ISIF_CLAMPCFG.CLMD=1 (4-color mode), the pixel value greater than 1023 will be replaced by the last pixel value of the same color which was equal to or less than 1023."; 588 clhwbs 1 rw type(clhwbs_status) "Horizontal Black clamp - Base Window select"; 589 clhwc 5 rw "Horizontal Black clamp - Window count per color Window count = CLHWC+1 Range: 1 - 32"; 590 }; 591 592 register isif_clhwin1 addr(base, 0xBC) "BLACK CLAMP CTRL REGISTER" { 593 _ 16 mbz; 594 _ 3 mbz; 595 clhsh 13 rw "Horizontal black clamp. Window Start position (H). Range: 0 - 8191"; 596 }; 597 598 register isif_clhwin2 addr(base, 0xC0) "BLACK CLAMP CTRL REGISTER" { 599 _ 16 mbz; 600 _ 3 mbz; 601 clhsv 13 rw "Horizontal black clamp. Window Start position (V). Range: 0 - 8191"; 602 }; 603 604 register isif_clvrv addr(base, 0xC4) "BLACK CLAMP CTRL REGISTER" { 605 _ 16 mbz; 606 _ 4 mbz; 607 clvrv 12 rw "Vertical black clamp reset value. (U12) Range: 0 to 4095"; 608 }; 609 610 constants clvrvsl_status width(2) "" { 611 CLVRVSL_0 = 0 "The base value calculated for Horizontal direction"; 612 CLVRVSL_1 = 1 "Value set via the configuration register"; 613 CLVRVSL_3 = 3 "Reserved"; 614 CLVRVSL_2 = 2 "No update (same as the previous image)"; 615 }; 616 617 constants clvobh_status width(3) "" { 618 CLVOBH_6 = 6 "Reserved"; 619 CLVOBH_1 = 1 "4 pixels wide (L=2)"; 620 CLVOBH_7 = 7 "Reserved"; 621 CLVOBH_0 = 0 "2 pixels wide (L=1)"; 622 CLVOBH_2 = 2 "8 pixels wide (L=3)"; 623 CLVOBH_4 = 4 "32 pixels wide (L=5)"; 624 CLVOBH_5 = 5 "64 pixels wide (L=6)"; 625 CLVOBH_3 = 3 "16 pixels wide (L=4)"; 626 }; 627 628 register isif_clvwin0 addr(base, 0xC8) "BLACK CLAMP CTRL REGISTER" { 629 _ 16 mbz; 630 clvcoef 8 rw "Vertical Black clamp - Line average coefficient (k). Set a coefficient which is applied to the line average for clamp value calculation. (1-k) is applied to the clamp value of the previous line. Value in the U8Q8 format, the range is 0 to 255/256."; 631 _ 2 mbz; 632 clvrvsl 2 rw type(clvrvsl_status) "Vertical Black clamp - reset value selection Select the reset value for the clamp value of the previous line"; 633 _ 1 mbz; 634 clvobh 3 rw type(clvobh_status) "Vertical Black clamp - Optical Black H valid (2)."; 635 }; 636 637 register isif_clvwin1 addr(base, 0xCC) "BLACK CLAMP CTRL REGISTER" { 638 _ 16 mbz; 639 _ 3 mbz; 640 clvsh 13 rw "Vertical black clamp. Window Start position (H). Range: 0 - 8191"; 641 }; 642 643 register isif_clvwin2 addr(base, 0xD0) "BLACK CLAMP CTRL REGISTER" { 644 _ 16 mbz; 645 _ 3 mbz; 646 clvsv 13 rw "Vertical black clamp. Window Start position (V). Range: 0 - 8191"; 647 }; 648 649 register isif_clvwin3 addr(base, 0xD4) "BLACK CLAMP CTRL REGISTER" { 650 _ 16 mbz; 651 _ 3 mbz; 652 clvobv 13 rw "Vertical black clamp. Optical black V valid (V). Range: 0 - 8191"; 653 }; 654 655 register isif_lschofst addr(base, 0xD8) "2D Lens Shading Correction Register" { 656 _ 16 mbz; 657 _ 2 mbz; 658 hofst 14 rw "H direction Data offset for Lens Shading Correction. Range: 0-16,383 Not valid if the Formatter is enabled."; 659 }; 660 661 register isif_lscvofst addr(base, 0xDC) "2D Lens Shading Correction Register" { 662 _ 16 mbz; 663 _ 2 mbz; 664 vofst 14 rw "V direction Data offset for Lens Shading Correction. Range: 0-16,383"; 665 }; 666 667 register isif_lschval addr(base, 0xE0) "2D Lens Shading Correction Register" { 668 _ 16 mbz; 669 _ 2 mbz; 670 hval 14 rw "Number of valid pixels in H direction. HVAL is for LSC. Number of valid pixels = HVAL+ 1"; 671 }; 672 673 register isif_lscvval addr(base, 0xE4) "2D Lens Shading Correction Register" { 674 _ 16 mbz; 675 _ 2 mbz; 676 vval 14 rw "Number of valid lines in V direction. VVAL is for LSC. Number of valid lines = VVAL+ 1"; 677 }; 678 679 constants gain_mode_m_status width(3) "" { 680 GAIN_MODE_M_6 = 6 "Paxel is 64 pixels tall (M=64)"; 681 GAIN_MODE_M_1 = 1 "Reserved"; 682 GAIN_MODE_M_7 = 7 "Paxel is 128 pixels tall (M=128)"; 683 GAIN_MODE_M_0 = 0 "Reserved"; 684 GAIN_MODE_M_2 = 2 "Reserved"; 685 GAIN_MODE_M_4 = 4 "Paxel is 16 pixels tall (M=16)"; 686 GAIN_MODE_M_5 = 5 "Paxel is 32 pixels tall (M=32)"; 687 GAIN_MODE_M_3 = 3 "Paxel is 8 pixels tall (M=8)"; 688 }; 689 690 constants gain_mode_n_status width(3) "" { 691 GAIN_MODE_N_6 = 6 "Paxel is 64 pixels tall (N=64)"; 692 GAIN_MODE_N_1 = 1 "Reserved"; 693 GAIN_MODE_N_7 = 7 "Paxel is 128 pixels tall (N=128)"; 694 GAIN_MODE_N_0 = 0 "Reserved"; 695 GAIN_MODE_N_2 = 2 "Reserved"; 696 GAIN_MODE_N_4 = 4 "Paxel is 16 pixels tall (N=16)"; 697 GAIN_MODE_N_5 = 5 "Paxel is 32 pixels tall (N=32)"; 698 GAIN_MODE_N_3 = 3 "Paxel is 8 pixels tall (N=8)"; 699 }; 700 701 constants busy_status width(1) "" { 702 BUSY_1_r = 1 "Busy"; 703 BUSY_0_r = 0 "Idle"; 704 }; 705 706 constants gain_format_status width(3) "" { 707 GAIN_FORMAT_6 = 6 "Coded as 3-bit integer, 5-bit fraction Range from 0 to 7+31/32"; 708 GAIN_FORMAT_1 = 1 "Coded as 8-bit fraction + 1.0 of base Range from 1 to 1+255/256"; 709 GAIN_FORMAT_7 = 7 "Coded as 3-bit integer, 5-bit fraction + 1.0 Range from 1 to 8+31/32"; 710 GAIN_FORMAT_0 = 0 "Coded as 8-bit fraction Range from 0 to 255/256"; 711 GAIN_FORMAT_2 = 2 "Coded as 1-bit integer, 7-bit fraction Range from 0 to 1+127/128"; 712 GAIN_FORMAT_4 = 4 "Coded as 2-bit integer, 6-bit fraction Range from 0 to 3+63/64"; 713 GAIN_FORMAT_5 = 5 "Coded as 2-bit integer, 6-bit fraction + 1.0 Range from 1 to 4+63/64"; 714 GAIN_FORMAT_3 = 3 "Coded as 1-bit integer, 7-bit fraction + 1.0 Range from 1 to 2+127/128"; 715 }; 716 717 constants enable_status width(1) "" { 718 ENABLE_0 = 0 "Disables the module at the end of the current frame."; 719 ENABLE_1 = 1 "Enables the module."; 720 }; 721 722 register isif_2dlsccfg addr(base, 0xE8) "2D Lens Shading Correction Register" { 723 _ 16 mbz; 724 _ 1 mbz; 725 gain_mode_m 3 rw type(gain_mode_m_status) "Define the horizontal dimension of a paxel. Possible values are listed below."; 726 _ 1 mbz; 727 gain_mode_n 3 rw type(gain_mode_n_status) "Define the vertical dimension of a paxel. Possible values are listed below."; 728 busy 1 ro type(busy_status) "Busy bit"; 729 _ 3 mbz; 730 gain_format 3 rw type(gain_format_status) "Sets gain table format"; 731 enable 1 rw type(enable_status) "Enables/disables LSC"; 732 }; 733 734 constants ofstsft_status width(3) "" { 735 OFSTSFT_6 = 6 "Reserved"; 736 OFSTSFT_1 = 1 "1bit left shift"; 737 OFSTSFT_7 = 7 "Reserved"; 738 OFSTSFT_0 = 0 "No shift"; 739 OFSTSFT_2 = 2 "2bits left shift"; 740 OFSTSFT_4 = 4 "4bits left shift"; 741 OFSTSFT_5 = 5 "5bits left shift"; 742 OFSTSFT_3 = 3 "3bits left shift"; 743 }; 744 745 register isif_2dlscofst addr(base, 0xEC) "2D Lens Shading Correction Register" { 746 _ 16 mbz; 747 ofstsf 8 rw "Scaling factor for Offsets (U8Q7) Range: 0 to 1+127/128"; 748 _ 1 mbz; 749 ofstsft 3 rw type(ofstsft_status) "Shift up value for Offsets (S8Q0)"; 750 _ 3 mbz; 751 ofsten 1 rw type(dwen_status) "Enables/disables Offset control in LSC"; 752 }; 753 754 register isif_2dlscini addr(base, 0xF0) "2D Lens Shading Correction Register" { 755 _ 16 mbz; 756 _ 1 mbz; 757 y 7 rw "Initial Y Y position, in pixels, of the first active pixel in reference to the first active paxel. Must be an even number."; 758 _ 1 mbz; 759 x 7 rw "Initial X X position, in pixels, of the first active pixel in reference to the first active paxel. Must be an even number."; 760 }; 761 762 register isif_2dlscgrbu addr(base, 0xF4) "2D Lens Shading Correction Register" { 763 _ 16 mbz; 764 base31_16 16 rw "Gain Table address base (Upper 16-bits) Table address in bytes. Table is 32-bit aligned so this register must be a multiple of 4. This bit field sets the address of the gain table in memory."; 765 }; 766 767 register isif_2dlscgrbl addr(base, 0xF8) "2D Lens Shading Correction Register" { 768 _ 16 mbz; 769 base15_0 16 rw "Gain Table address base (Lower 16-bits) Table address in bytes. Table is 32-bit aligned so this register must be a multiple of 4. This bit field sets the address of the gain table in memory."; 770 }; 771 772 register isif_2dlscgrof addr(base, 0xFC) "2D Lens Shading Correction Register" { 773 _ 16 mbz; 774 offset 16 rw "Gain Table offset Defines the length, in bytes, of one row of the table. Table is 32-bit aligned, so this value must be a multiple of 4. Note that the row in memory could be longer than what LSC uses."; 775 }; 776 777 register isif_2dlscorbu addr(base, 0x100) "2D Lens Shading Correction Register" { 778 _ 16 mbz; 779 base 16 rw "Offset Table address base (Upper 16-bits) Table address in bytes. Table is 32-bit aligned so this register must be a multiple of 4. This bit field sets the address of the gain table in memory."; 780 }; 781 782 register isif_2dlscorbl addr(base, 0x104) "2D Lens Shading Correction Register" { 783 _ 16 mbz; 784 base 16 rw "Offset Table address base (Lower 16-bits) Table address in bytes. Table is 32-bit aligned so this register must be a multiple of 4. This bit field sets the address of the gain table in memory."; 785 }; 786 787 register isif_2dlscorof addr(base, 0x108) "2D Lens Shading Correction Register" { 788 _ 16 mbz; 789 offset 16 rw "Offset Table offset Defines the length, in bytes, of one row of the table. Table is 32-bit aligned, so this value must be a multiple of 4. Note that the row in memory could be longer than what LSC uses."; 790 }; 791 792 constants sof_status width(1) "" { 793 SOF_0 = 0 "Interrupt is masked"; 794 SOF_1 = 1 "Interrupt is enabled"; 795 }; 796 797 register isif_2dlscirqen addr(base, 0x10C) "" { 798 _ 16 mbz; 799 _ 12 mbz; 800 sof 1 rw type(sof_status) "Interrupt status for LSC SOF Indicates the start of the LSC valid region. LSC configuration registers can be updated after LSC SOF for the next frame."; 801 prefetch_completed 1 rw type(sof_status) "Interrupt enable for Prefetch Complete Indicates current state of the prefetch buffer. Could be used to start sending the data once the buffer is full to minimize the risk of an underflow. This event is triggered when the buffer contains 3 full paxel rows."; 802 prefetch_error 1 rw type(sof_status) "Interrupt enable for Prefetch Error The prefetch error indicates when the gain table was read to slowly from SDRAM. When this event is pending the module goes into transparent mode (output=input). Normal operation can be resumed at the start of the next frame after 1) clearing this event 2) disabling the LSC module 3) enabling it"; 803 done 1 rw type(sof_status) "Interrupt enable for LSC Done The event is triggered when the internal state of LSC toggles from BUSY to IDLE."; 804 }; 805 806 register isif_2dlscirqst addr(base, 0x110) "2D Lens Shading Correction Register" { 807 _ 16 mbz; 808 _ 12 mbz; 809 sof 1 rw type(clvrvsl_status) "Interrupt status for LSC SOF Indicates the start of the LSC valid region. LSC configuration registers can be updated after LSC SOF for the next frame."; 810 prefetch_completed 1 rw type(clvrvsl_status) "Interrupt status for Prefetch Complete Indicates current state of the prefetch buffer. Could be used to start sending the data once the buffer is full to minimize the risk of an underflow. This event is triggered when the buffer contains 3 full paxel rows. It could be used to minimize buffer underflow risks."; 811 prefetch_error 1 rw type(clvrvsl_status) "Interrupt status for Prefetch Error The prefetch error indicates when the gain table was read to slowly from SDRAM. When this event is pending the module goes into transparent mode (output=input). Normal operation can be resumed at the start of the next frame after 1) clearing this event 2) disabling the LSC module 3) enabling it"; 812 done 1 rw type(clvrvsl_status) "Interrupt status for LSC Done The event is triggered when the internal state of LSC toggles from BUSY to IDLE."; 813 }; 814 815 constants lnum_status width(2) "" { 816 LNUM_0 = 0 "1 output line"; 817 LNUM_1 = 1 "1 input line -> 2 output lines (FMTCBL=0) 2 input lines -> 1 output line (FMTCBL=1)"; 818 LNUM_3 = 3 "1 input line -> 4 output lines (FMTCBL=0) 4 input lines -> 1 output line (FMTCBL=1)"; 819 LNUM_2 = 2 "1 input line -> 3 output lines (FMTCBL=0) 3 input lines -> 1 output line (FMTCBL=1)"; 820 }; 821 822 constants lnalt_status width(1) "" { 823 LNALT_0 = 0 "Normal mode"; 824 LNALT_1 = 1 "Line alternative mode"; 825 }; 826 827 register isif_fmtcfg addr(base, 0x114) "Input Data Formatter Register" { 828 _ 20 mbz; 829 fmtainc 4 rw "Address increment Address increment = (FMTAINC + 1) Range (1-16) *This bit is latched by VD."; 830 _ 2 mbz; 831 lnum 2 rw type(lnum_status) "Split/Combine number of lines *This bit is latched by VD."; 832 _ 1 mbz; 833 lnalt 1 rw type(lnalt_status) "Line alternating *This bit is latched by VD."; 834 fmtcbl 1 rw type(clvrvsl_status) "Combine Input lines *This bit is latched by VD."; 835 fmten 1 rw type(dwen_status) "CCD Formatter enable *This bit is latched by VD."; 836 }; 837 838 register isif_fmtplen addr(base, 0x118) "Input Data Formatter Register" { 839 _ 17 mbz; 840 fmtplen3 3 rw "Number of program entries for SET3 Number of entries = (FMTPLEN3 + 1) Range: 1-8 Valid only if FMTCBL is set *This bit is latched by VD."; 841 _ 1 mbz; 842 fmtplen2 3 rw "Number of program entries for SET2 Number of entries = (FMTPLEN2 + 1) Range: 1-8 Valid only if FMTCBL is set *This bit is latched by VD."; 843 fmtplen1 4 rw "Number of program entries for SET1 Number of entries = (FMTPLEN1 + 1) Range: 1-16 (FMTCBL = 0) 1-8 (FMTCBL = 1) Setting a value greater than 7 to FMTPLEN1 is not allowed if FMTCBL is set *This bit is latched by VD."; 844 fmtplen0 4 rw "Number of program entries for SET0 Number of entries = (PLEN0 + 1) Range: 1-16 (FMTCBL = 0) 1-8 (FMTCBL = 1) Setting a value greater than 7 to FMTPLEN1 is not allowed if FMTCBL is set *This bit is latched by VD."; 845 }; 846 847 register isif_fmtsph addr(base, 0x11C) "Input Data Formatter Register" { 848 _ 19 mbz; 849 fmtsph 13 rw "The first pixel in a line fed into the formatter"; 850 }; 851 852 register isif_fmtlnh addr(base, 0x120) "Input Data Formatter Register" { 853 _ 19 mbz; 854 fmtlnh 13 rw "Number of pixels in a line fed to the formatter. Number of pixels = FMTLNH + 1"; 855 }; 856 857 register isif_fmtlsv addr(base, 0x124) "Input Data Formatter Register" { 858 _ 19 mbz; 859 fmtslv 13 rw "Start line vertical"; 860 }; 861 862 register isif_fmtlnv addr(base, 0x128) "Input Data Formatter Register" { 863 _ 17 mbz; 864 fmtlnv 15 rw "Number of lines in vertical Number of lines = FMTLNV + 1"; 865 }; 866 867 register isif_fmtrlen addr(base, 0x12C) "Input Data Formatter Register" { 868 _ 19 mbz; 869 fmtrlen 13 rw "Number of pixels in an output line Maximum value = 4480"; 870 }; 871 872 register isif_fmthcnt addr(base, 0x130) "Input Data Formatter Register" { 873 _ 19 mbz; 874 fmthcnt 13 rw "HD interval for output lines Set all 0 to this register if combining multiple lines into a single line"; 875 }; 876 877 constants line_status width(2) "" { 878 LINE_0 = 0 "1st line"; 879 LINE_1 = 1 "2nd line"; 880 LINE_3 = 3 "4th line"; 881 LINE_2 = 2 "3rd line"; 882 }; 883 884 register isif_fmtaptr0 addr(base, 0x134) "Input Data Formatter Register" { 885 _ 17 mbz; 886 line 2 rw type(line_status) "The output line the address belongs to Valid only if FMTCBL is cleared"; 887 init 13 rw "Initial address value for address pointer 0 This address can not exceed FMTRLEN - 1"; 888 }; 889 890 register isif_fmtaptr1 addr(base, 0x138) "Input Data Formatter Register" { 891 _ 17 mbz; 892 line 2 rw type(line_status) "The output line the address belongs to Valid only if FMTCBL is cleared"; 893 init 13 rw "Initial address value for address pointer 1 This address can not exceed FMTRLEN - 1"; 894 }; 895 896 register isif_fmtaptr2 addr(base, 0x13C) "Input Data Formatter Register" { 897 _ 17 mbz; 898 line 2 rw type(line_status) "The output line the address belongs to Valid only if FMTCBL is cleared"; 899 init 13 rw "Initial address value for address pointer 2 This address can not exceed FMTRLEN - 1"; 900 }; 901 902 register isif_fmtaptr3 addr(base, 0x140) "Input Data Formatter Register" { 903 _ 17 mbz; 904 line 2 rw type(line_status) "The output line the address belongs to Valid only if FMTCBL is cleared"; 905 init 13 rw "Initial address value for address pointer 3 This address can not exceed FMTRLEN - 1"; 906 }; 907 908 register isif_fmtaptr4 addr(base, 0x144) "Input Data Formatter Register" { 909 _ 17 mbz; 910 line 2 rw type(line_status) "The output line the address belongs to Valid only if FMTCBL is cleared"; 911 init 13 rw "Initial address value for address pointer 4 This address can not exceed FMTRLEN - 1"; 912 }; 913 914 register isif_fmtaptr5 addr(base, 0x148) "Input Data Formatter Register" { 915 _ 17 mbz; 916 line 2 rw type(line_status) "The output line the address belongs to Valid only if FMTCBL is cleared"; 917 init 13 rw "Initial address value for address pointer 5 This address can not exceed FMTRLEN - 1"; 918 }; 919 920 register isif_fmtaptr6 addr(base, 0x14C) "Input Data Formatter Register" { 921 _ 17 mbz; 922 line 2 rw type(line_status) "The output line the address belongs to Valid only if FMTCBL is cleared"; 923 init 13 rw "Initial address value for address pointer 6 This address can not exceed FMTRLEN - 1"; 924 }; 925 926 register isif_fmtaptr7 addr(base, 0x150) "Input Data Formatter Register" { 927 _ 17 mbz; 928 line 2 rw type(line_status) "The output line the address belongs to Valid only if FMTCBL is cleared"; 929 init 13 rw "Initial address value for address pointer 7 This address can not exceed FMTRLEN - 1"; 930 }; 931 932 register isif_fmtaptr8 addr(base, 0x154) "Input Data Formatter Register" { 933 _ 17 mbz; 934 line 2 rw type(line_status) "The output line the address belongs to Valid only if FMTCBL is cleared"; 935 init 13 rw "Initial address value for address pointer 8 This address can not exceed FMTRLEN - 1"; 936 }; 937 938 register isif_fmtaptr9 addr(base, 0x158) "Input Data Formatter Register" { 939 _ 17 mbz; 940 line 2 rw type(line_status) "The output line the address belongs to Valid only if FMTCBL is cleared"; 941 init 13 rw "Initial address value for address pointer 9 This address can not exceed FMTRLEN - 1"; 942 }; 943 944 register isif_fmtaptr10 addr(base, 0x15C) "Input Data Formatter Register" { 945 _ 17 mbz; 946 line 2 rw type(line_status) "The output line the address belongs to Valid only if FMTCBL is cleared"; 947 init 13 rw "Initial address value for address pointer 10 This address can not exceed FMTRLEN - 1"; 948 }; 949 950 register isif_fmtaptr11 addr(base, 0x160) "Input Data Formatter Register" { 951 _ 17 mbz; 952 line 2 rw type(line_status) "The output line the address belongs to Valid only if FMTCBL is cleared"; 953 init 13 rw "Initial address value for address pointer 11 This address can not exceed FMTRLEN - 1"; 954 }; 955 956 register isif_fmtaptr12 addr(base, 0x164) "Input Data Formatter Register" { 957 _ 17 mbz; 958 line 2 rw type(line_status) "The output line the address belongs to Valid only if FMTCBL is cleared"; 959 init 13 rw "Initial address value for address pointer 12 This address can not exceed FMTRLEN - 1"; 960 }; 961 962 register isif_fmtaptr13 addr(base, 0x168) "Input Data Formatter Register" { 963 _ 17 mbz; 964 line 2 rw type(line_status) "The output line the address belongs to Valid only if FMTCBL is cleared"; 965 init 13 rw "Initial address value for address pointer 13 This address can not exceed FMTRLEN - 1"; 966 }; 967 968 register isif_fmtaptr14 addr(base, 0x16C) "Input Data Formatter Register" { 969 _ 17 mbz; 970 line 2 rw type(line_status) "The output line the address belongs to Valid only if FMTCBL is cleared"; 971 init 13 rw "Initial address value for address pointer 14 This address can not exceed FMTRLEN - 1"; 972 }; 973 974 register isif_fmtaptr15 addr(base, 0x170) "Input Data Formatter Register" { 975 _ 17 mbz; 976 line 2 rw type(line_status) "The output line the address belongs to Valid only if FMTCBL is cleared"; 977 init 13 rw "Initial address value for address pointer 15 This address can not exceed FMTRLEN - 1"; 978 }; 979 980 constants pgm15en_status width(1) "" { 981 PGM15EN_0 = 0 "Skip this pixel"; 982 PGM15EN_1 = 1 "This pixel is valid"; 983 }; 984 985 register isif_fmtpgmvf0 addr(base, 0x174) "Input Data Formatter Register" { 986 _ 16 mbz; 987 pgm15en 1 rw type(pgm15en_status) "Program 15 Valid Flag"; 988 pgm14en 1 rw type(pgm15en_status) "Program 14 Valid Flag"; 989 pgm13en 1 rw type(pgm15en_status) "Program 13 Valid Flag"; 990 pgm12en 1 rw type(pgm15en_status) "Program 12 Valid Flag"; 991 pgm11en 1 rw type(pgm15en_status) "Program 11 Valid Flag"; 992 pgm10en 1 rw type(pgm15en_status) "Program 10 Valid Flag"; 993 pgm09en 1 rw type(pgm15en_status) "Program 9 Valid Flag"; 994 pgm08en 1 rw type(pgm15en_status) "Program 8 Valid Flag"; 995 pgm07en 1 rw type(pgm15en_status) "Program 7 Valid Flag"; 996 pgm06en 1 rw type(pgm15en_status) "Program 6 Valid Flag"; 997 pgm05en 1 rw type(pgm15en_status) "Program 5 Valid Flag"; 998 pgm04en 1 rw type(pgm15en_status) "Program 4 Valid Flag"; 999 pgm03en 1 rw type(pgm15en_status) "Program 3 Valid Flag"; 1000 pgm02en 1 rw type(pgm15en_status) "Program 2 Valid Flag"; 1001 pgm01en 1 rw type(pgm15en_status) "Program 1 Valid Flag"; 1002 pgm00en 1 rw type(pgm15en_status) "Program 0 Valid Flag"; 1003 }; 1004 1005 register isif_fmtpgmvf1 addr(base, 0x178) "Input Data Formatter Register" { 1006 _ 16 mbz; 1007 pgm31en 1 rw type(pgm15en_status) "Program 31 Valid Flag"; 1008 pgm30en 1 rw type(pgm15en_status) "Program 30 Valid Flag"; 1009 pgm29en 1 rw type(pgm15en_status) "Program 29 Valid Flag"; 1010 pgm28en 1 rw type(pgm15en_status) "Program 28 Valid Flag"; 1011 pgm27en 1 rw type(pgm15en_status) "Program 27 Valid Flag"; 1012 pgm26en 1 rw type(pgm15en_status) "Program 26 Valid Flag"; 1013 pgm25en 1 rw type(pgm15en_status) "Program 25 Valid Flag"; 1014 pgm24en 1 rw type(pgm15en_status) "Program 24 Valid Flag"; 1015 pgm23en 1 rw type(pgm15en_status) "Program 23 Valid Flag"; 1016 pgm22en 1 rw type(pgm15en_status) "Program 22 Valid Flag"; 1017 pgm21en 1 rw type(pgm15en_status) "Program 21 Valid Flag"; 1018 pgm20en 1 rw type(pgm15en_status) "Program 20 Valid Flag"; 1019 pgm19en 1 rw type(pgm15en_status) "Program 19 Valid Flag"; 1020 pgm18en 1 rw type(pgm15en_status) "Program 18 Valid Flag"; 1021 pgm17en 1 rw type(pgm15en_status) "Program 17 Valid Flag"; 1022 pgm16en 1 rw type(pgm15en_status) "Program 16 Valid Flag"; 1023 }; 1024 1025 constants pgm15updt_status width(1) "" { 1026 PGM15UPDT_0 = 0 "APTR* + N (Auto increment)"; 1027 PGM15UPDT_1 = 1 "APTR* - N (Auto decrement)"; 1028 }; 1029 1030 register isif_fmtpgmapu0 addr(base, 0x17C) "Input Data Formatter Register" { 1031 _ 16 mbz; 1032 pgm15updt 1 rw type(pgm15updt_status) "Program 15 Address Pointer Update"; 1033 pgm14updt 1 rw type(pgm15updt_status) "Program 14 Address Pointer Update"; 1034 pgm13updt 1 rw type(pgm15updt_status) "Program 13 Address Pointer Update"; 1035 pgm12updt 1 rw type(pgm15updt_status) "Program 12 Address Pointer Update"; 1036 pgm11updt 1 rw type(pgm15updt_status) "Program 11 Address Pointer Update"; 1037 pgm10updt 1 rw type(pgm15updt_status) "Program 10 Address Pointer Update"; 1038 pgm9updt 1 rw type(pgm15updt_status) "Program 9 Address Pointer Update"; 1039 pgm8updt 1 rw type(pgm15updt_status) "Program 8 Address Pointer Update"; 1040 pgm7updt 1 rw type(pgm15updt_status) "Program 7 Address Pointer Update"; 1041 pgm6updt 1 rw type(pgm15updt_status) "Program 6 Address Pointer Update"; 1042 pgm5updt 1 rw type(pgm15updt_status) "Program 5 Address Pointer Update"; 1043 pgm4updt 1 rw type(pgm15updt_status) "Program 4 Address Pointer Update"; 1044 pgm3updt 1 rw type(pgm15updt_status) "Program 3 Address Pointer Update"; 1045 pgm2updt 1 rw type(pgm15updt_status) "Program 2 Address Pointer Update"; 1046 pgm1updt 1 rw type(pgm15updt_status) "Program 1 Address Pointer Update"; 1047 pgm0updt 1 rw type(pgm15updt_status) "Program 0 Address Pointer Update"; 1048 }; 1049 1050 register isif_fmtpgmapu1 addr(base, 0x180) "Input Data Formatter Register" { 1051 _ 16 mbz; 1052 pgm31updt 1 rw type(pgm15updt_status) "Program 31 Address Pointer Update"; 1053 pgm30updt 1 rw type(pgm15updt_status) "Program 30 Address Pointer Update"; 1054 pgm29updt 1 rw type(pgm15updt_status) "Program 29 Address Pointer Update"; 1055 pgm28updt 1 rw type(pgm15updt_status) "Program 28 Address Pointer Update"; 1056 pgm27updt 1 rw type(pgm15updt_status) "Program 27 Address Pointer Update"; 1057 pgm26updt 1 rw type(pgm15updt_status) "Program 26 Address Pointer Update"; 1058 pgm25updt 1 rw type(pgm15updt_status) "Program 25 Address Pointer Update"; 1059 pgm24updt 1 rw type(pgm15updt_status) "Program 24 Address Pointer Update"; 1060 pgm23updt 1 rw type(pgm15updt_status) "Program 23 Address Pointer Update"; 1061 pgm22updt 1 rw type(pgm15updt_status) "Program 22 Address Pointer Update"; 1062 pgm21updt 1 rw type(pgm15updt_status) "Program 21 Address Pointer Update"; 1063 pgm20updt 1 rw type(pgm15updt_status) "Program 20 Address Pointer Update"; 1064 pgm19updt 1 rw type(pgm15updt_status) "Program 19 Address Pointer Update"; 1065 pgm18updt 1 rw type(pgm15updt_status) "Program 18 Address Pointer Update"; 1066 pgm17updt 1 rw type(pgm15updt_status) "Program 17 Address Pointer Update"; 1067 pgm16updt 1 rw type(pgm15updt_status) "Program 16 Address Pointer Update"; 1068 }; 1069 1070 register isif_fmtpgmaps0 addr(base, 0x184) "Input Data Formatter Register" { 1071 _ 16 mbz; 1072 pgm3aptr 4 rw "Program 3 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)"; 1073 pgm2aptr 4 rw "Program 2 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)"; 1074 pgm1aptr 4 rw "Program 1 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)"; 1075 pgm0aptr 4 rw "Program 0 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)"; 1076 }; 1077 1078 register isif_fmtpgmaps1 addr(base, 0x188) "Input Data Formatter Register" { 1079 _ 16 mbz; 1080 pgm7aptr 4 rw "Program 7 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)"; 1081 pgm6aptr 4 rw "Program 6 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)"; 1082 pgm5aptr 4 rw "Program 5 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)"; 1083 pgm4aptr 4 rw "Program 0 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)"; 1084 }; 1085 1086 register isif_fmtpgmaps2 addr(base, 0x18C) "Input Data Formatter Register" { 1087 _ 16 mbz; 1088 pgm11aptr 4 rw "Program 11 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)"; 1089 pgm10aptr 4 rw "Program 10 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)"; 1090 pgm9aptr 4 rw "Program 9 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)"; 1091 pgm8aptr 4 rw "Program 8 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)"; 1092 }; 1093 1094 register isif_fmtpgmaps3 addr(base, 0x190) "Input Data Formatter Register" { 1095 _ 16 mbz; 1096 pgm15aptr 4 rw "Program 15 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)"; 1097 pgm14aptr 4 rw "Program 14 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)"; 1098 pgm13aptr 4 rw "Program 13 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)"; 1099 pgm12aptr 4 rw "Program 12 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)"; 1100 }; 1101 1102 register isif_fmtpgmaps4 addr(base, 0x194) "Input Data Formatter Register" { 1103 _ 16 mbz; 1104 pgm19aptr 4 rw "Program 19 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)"; 1105 pgm18aptr 4 rw "Program 18 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)"; 1106 pgm17aptr 4 rw "Program 17 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)"; 1107 pgm16aptr 4 rw "Program 16 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)"; 1108 }; 1109 1110 register isif_fmtpgmaps5 addr(base, 0x198) "Input Data Formatter Register" { 1111 _ 16 mbz; 1112 pgm23aptr 4 rw "Program 23 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)"; 1113 pgm22aptr 4 rw "Program 22 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)"; 1114 pgm21aptr 4 rw "Program 21 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)"; 1115 pgm20aptr 4 rw "Program 20 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)"; 1116 }; 1117 1118 register isif_fmtpgmaps6 addr(base, 0x19C) "Input Data Formatter Register" { 1119 _ 16 mbz; 1120 pgm27aptr 4 rw "Program 27 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)"; 1121 pgm26aptr 4 rw "Program 26 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)"; 1122 pgm25aptr 4 rw "Program 25 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)"; 1123 pgm24aptr 4 rw "Program 24 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)"; 1124 }; 1125 1126 register isif_fmtpgmaps7 addr(base, 0x1A0) "Input Data Formatter Register" { 1127 _ 16 mbz; 1128 pgm31aptr 4 rw "Program 31 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)"; 1129 pgm30aptr 4 rw "Program 30 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)"; 1130 pgm29aptr 4 rw "Program 29 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)"; 1131 pgm28aptr 4 rw "Program 28 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)"; 1132 }; 1133 1134 register isif_cscctl addr(base, 0x1A4) "Color Space Converter Register" { 1135 _ 16 mbz; 1136 _ 15 mbz; 1137 cscen 1 rw type(dwen_status) "Controls ON/OFF of Color Space converter."; 1138 }; 1139 1140 register isif_cscm0 addr(base, 0x1A8) "Color Space Converter Register" { 1141 _ 16 mbz; 1142 cscm01 8 rw "Color Space convert coefficient value M01: This value is signed 8-bit with the 5-bits decimal."; 1143 cscm00 8 rw "Color Space convert coefficient value M00: This value is signed 8-bit with the 5-bits decimal."; 1144 }; 1145 1146 register isif_cscm1 addr(base, 0x1AC) "Color Space Converter Register" { 1147 _ 16 mbz; 1148 cscm03 8 rw "Color Space convert coefficient value M03: This value is signed 8-bit with the 5-bits decimal."; 1149 cscm02 8 rw "Color Space convert coefficient value M02: This value is signed 8-bit with the 5-bits decimal."; 1150 }; 1151 1152 register isif_cscm2 addr(base, 0x1B0) "Color Space Converter Register" { 1153 _ 16 mbz; 1154 cscm11 8 rw "Color Space convert coefficient value M11: This value is signed 8-bit with the 5-bits decimal."; 1155 cscm10 8 rw "Color Space convert coefficient value M10: This value is signed 8-bit with the 5-bits decimal."; 1156 }; 1157 1158 register isif_cscm3 addr(base, 0x1B4) "Color Space Converter Register" { 1159 _ 16 mbz; 1160 cscm13 8 rw "Color Space convert coefficient value M13: This value is signed 8-bit with the 5-bits decimal."; 1161 cscm12 8 rw "Color Space convert coefficient value M12: This value is signed 8-bit with the 5-bits decimal."; 1162 }; 1163 1164 register isif_cscm4 addr(base, 0x1B8) "Color Space Converter Register" { 1165 _ 16 mbz; 1166 cscm21 8 rw "Color Space convert coefficient value M21: This value is signed 8-bit with the 5-bits decimal."; 1167 cscm20 8 rw "Color Space convert coefficient value M20: This value is signed 8-bit with the 5-bits decimal."; 1168 }; 1169 1170 register isif_cscm5 addr(base, 0x1BC) "Color Space Converter Register" { 1171 _ 16 mbz; 1172 cscm23 8 rw "Color Space convert coefficient value M23: This value is signed 8-bit with the 5-bits decimal."; 1173 cscm22 8 rw "Color Space convert coefficient value M22: This value is signed 8-bit with the 5-bits decimal."; 1174 }; 1175 1176 register isif_cscm6 addr(base, 0x1C0) "Color Space Converter Register" { 1177 _ 16 mbz; 1178 cscm31 8 rw "Color Space convert coefficient value M31: This value is signed 8-bit with the 5-bits decimal."; 1179 cscm30 8 rw "Color Space convert coefficient value M30: This value is signed 8-bit with the 5-bits decimal."; 1180 }; 1181 1182 register isif_cscm7 addr(base, 0x1C4) "Color Space Converter Register" { 1183 _ 16 mbz; 1184 cscm33 8 rw "Color Space convert coefficient value M33: This value is signed 8-bit with the 5-bits decimal."; 1185 cscm32 8 rw "Color Space convert coefficient value M32: This value is signed 8-bit with the 5-bits decimal."; 1186 }; 1187 1188 constants clken1_status width(1) "" { 1189 CLKEN1_0 = 0 "normal mode"; 1190 CLKEN1_1 = 1 "force isif_clken1 to be active"; 1191 }; 1192 1193 constants clken2_status width(1) "" { 1194 CLKEN2_0 = 0 "normal mode"; 1195 CLKEN2_1 = 1 "force isif_clken2 to be active"; 1196 }; 1197 1198 register isif_clkctl addr(base, 0x1F8) "" { 1199 _ 16 mbz; 1200 _ 14 mbz; 1201 clken1 1 rw type(clken1_status) "Forces isif_clken1 to be active. (Test mode)"; 1202 clken2 1 rw type(clken2_status) "Forces isif_clken2 to be active. (Test mode)"; 1203 }; 1204};