1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstr. 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_iss_ipipe.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_iss_ipipe msbfirst ( addr base ) "" { 29 30 31 constants en_status width(1) "" { 32 EN_0 = 0 "waiting"; 33 EN_1 = 1 "start/busy"; 34 }; 35 36 register ipipe_src_en addr(base, 0x0) "This register is not shadowed" { 37 _ 16 mbz; 38 _ 15 mbz; 39 en 1 rw type(en_status) "The start flag of the IPIPE module. When EN is 1, the IPIPE module starts a processing from the next rising edge of the VD. If the processing mode of the IPIPE module is one shot, the EN is cleared to 0 immediately after the processing has started."; 40 }; 41 42 constants wrt_status width(1) "" { 43 WRT_0 = 0 "Disable"; 44 WRT_1 = 1 "Enable"; 45 }; 46 47 constants ost_status width(1) "" { 48 OST_0 = 0 "Free run"; 49 OST_1 = 1 "One shot"; 50 }; 51 52 register ipipe_src_mode addr(base, 0x4) "" { 53 _ 16 mbz; 54 _ 14 mbz; 55 wrt 1 rw type(wrt_status) "The mode selection of the ipipeif_wrt which is an input port of the IPIPE module. If WRT is 0, the IPIPE module does not use the ipipeif_wrt. Else the IPIPE module uses it."; 56 ost 1 rw type(ost_status) "The processing mode selection of the IPIPE module. Value 0 indicates the mode of free run, value 1 indicates the mode of one shot."; 57 }; 58 59 constants fmt_status width(2) "" { 60 FMT_0 = 0 "IN: RAW BAYER OUT: YUV4:2:2 Note that the IPIPE YUV4:2:2 output goes to the RESIZER module where it can be further be converted in YUV4:2:0 or RGB format."; 61 FMT_1 = 1 "IN: RAW BAYER OUT: RAW BAYER The data are output after the White Balance module. It enables to bypass a large part of the IPIPE module."; 62 FMT_3 = 3 "IN: YUV4:2:2 OUT: YUV4:2:2 Note that the IPIPE YUV4:2:2 output goes to the RESIZER module where it can be further be converted in YUV4:2:0 or RGB format."; 63 FMT_2 = 2 "IN: RAW BAYER OUT: DISABLED The data are only going to BOXCAR and HISTOGRAM modules."; 64 }; 65 66 register ipipe_src_fmt addr(base, 0x8) "" { 67 _ 16 mbz; 68 _ 14 mbz; 69 fmt 2 rw type(fmt_status) "IPIPE module data path selection"; 70 }; 71 72 constants oo_status width(2) "" { 73 OO_0 = 0 "R"; 74 OO_1 = 1 "Gr"; 75 OO_3 = 3 "B"; 76 OO_2 = 2 "Gb"; 77 }; 78 79 register ipipe_src_col addr(base, 0xC) "" { 80 _ 16 mbz; 81 _ 8 mbz; 82 oo 2 rw type(oo_status) "The color pattern of the odd line and odd pixel. This parameter is valid when IPIPE_SRC[FMT] is 0,1,2."; 83 oe 2 rw type(oo_status) "The color pattern of the odd line and even pixel. This parameter is valid when IPIPE_SRC[FMT] is 0,1,2."; 84 eo 2 rw type(oo_status) "The color pattern of the even line and odd pixel. This parameter is valid when IPIPE_SRC[FMT] is 0,1,2."; 85 ee 2 rw type(oo_status) "The color pattern of the even line and even pixel. This parameter is valid when IPIPE_SRC[FMT] is 0,1,2."; 86 }; 87 88 register ipipe_src_vps addr(base, 0x10) "" { 89 _ 16 mbz; 90 val 16 rw "The vertical position of the global frame from the rising edge of the VD. The IPIPE module will start an image processing from VAL line."; 91 }; 92 93 register ipipe_src_vsz addr(base, 0x14) "" { 94 _ 16 mbz; 95 _ 3 mbz; 96 val 13 rw "The vertical size of the processing area. The VAL0 can not be written. The IPIPE module will process (VAL+1) lines."; 97 }; 98 99 register ipipe_src_hps addr(base, 0x18) "" { 100 _ 16 mbz; 101 val 16 rw "The horizontal position of the global frame from the rising edge of the HD. The IPIPE module will start an image processing from VAL clock."; 102 }; 103 104 register ipipe_src_hsz addr(base, 0x1C) "" { 105 _ 19 mbz; 106 val 12 rw "The horizontal size of the processing area. The VAL0 is fixed. The IPIPE module processes (VAL+1) clocks."; 107 val_0 1 ro "This is the LSB of the VAL[12:0]. This bit is read only."; 108 }; 109 110 constants edof_status width(1) "" { 111 EDOF_0 = 0 "Not used"; 112 EDOF_1 = 1 "Used"; 113 }; 114 115 register ipipe_sel_sbu addr(base, 0x20) "" { 116 _ 16 mbz; 117 _ 15 mbz; 118 edof 1 rw type(edof_status) "EDOF port selection This bit must not be enabled since the EDOF module is not implemented. This is a provision for a future revision of the IP."; 119 }; 120 121 register ipipe_src_sta addr(base, 0x24) "IPIPE STATUS REGISTER" { 122 _ 16 mbz; 123 _ 11 mbz; 124 val4 1 ro "Status of Histogram Process (busy status)."; 125 val3 1 ro "Status of Histogram bank select."; 126 val2 1 ro "Status of BSC process (busy status)."; 127 val1 1 ro "Status of Boxcar process (busy status)."; 128 val0 1 ro "Status of Boxcar process (error status). This bit will be triggered when an overflow happens while transferring the boxcar data to memory. Instead of polling for this register, it is preferable to use the IPIPE_BOXCAR_OVF interrupt. Overflow errors are non recoverable at ISP level and require a software reset at ISS level."; 129 }; 130 131 constants reg_status width(1) "" { 132 REG_0 = 0 "Off"; 133 REG_1 = 1 "On"; 134 }; 135 136 register ipipe_gck_mmr addr(base, 0x28) "" { 137 _ 16 mbz; 138 _ 15 mbz; 139 reg 1 rw type(reg_status) "The on/off selection of the clk_arm_g0 which is used for some ARM register access."; 140 }; 141 142 register ipipe_gck_pix addr(base, 0x2C) "This register is not shadowed" { 143 _ 16 mbz; 144 _ 12 mbz; 145 g3 1 rw type(wrt_status) "The on/off selection of the clk_pix_g3 which is use for the IPIPE processes of EE and 'CAR'."; 146 g2 1 rw type(wrt_status) "The on/off selection of the clk_pix_g2 which is use for the IPIPE processes of CFA to '422', 'Histogram(YCbCr input)', and 'Boundary Signal Calculator'."; 147 g1 1 rw type(wrt_status) "The on/off selection of the clk_pix_g1 which is used for the IPIPE processes of 'DefectCorrection' to 'WhiteBalance', and 'Histogram(RAW input)'."; 148 g0 1 rw type(wrt_status) "The on/off selection of the clk_pix_g0 which is used for the IPIPE processing of 'Boxcar'."; 149 }; 150 151 register ipipe_dpc_lut_en addr(base, 0x34) "" { 152 _ 16 mbz; 153 _ 15 mbz; 154 en 1 rw type(reg_status) "Enable of LUT defect pixel correction."; 155 }; 156 157 constants tbl_status width(1) "" { 158 TBL_0 = 0 "Up to 1024 entries. (use)"; 159 TBL_1 = 1 "infinity number of entries. (not use)"; 160 }; 161 162 constants dot_status width(1) "" { 163 DOT_0 = 0 "Replace with black dot"; 164 DOT_1 = 1 "Replace with white dot"; 165 }; 166 167 register ipipe_dpc_lut_sel addr(base, 0x38) "" { 168 _ 16 mbz; 169 _ 14 mbz; 170 tbl 1 rw type(tbl_status) "LUT table type selection."; 171 dot 1 rw type(dot_status) "Replace dot selection on processing method 0."; 172 }; 173 174 register ipipe_dpc_lut_adr addr(base, 0x3C) "" { 175 _ 16 mbz; 176 _ 6 mbz; 177 adr 10 rw "The address of the first valid data in look-up-table"; 178 }; 179 180 register ipipe_dpc_lut_siz addr(base, 0x40) "" { 181 _ 16 mbz; 182 _ 6 mbz; 183 siz 10 rw "The number of valid data in look-up-table. (SIZ+1)"; 184 }; 185 186 register ipipe_lsc_voft addr(base, 0x90) "LSC VOFT" { 187 _ 16 mbz; 188 _ 3 mbz; 189 lsc_voft 13 rw ""; 190 }; 191 192 register ipipe_lsc_va2 addr(base, 0x94) "" { 193 _ 16 mbz; 194 _ 3 mbz; 195 val 13 rw "LSC VA2"; 196 }; 197 198 register ipipe_lsc_va1 addr(base, 0x98) "" { 199 _ 16 mbz; 200 _ 3 mbz; 201 val 13 rw "LSC VA1"; 202 }; 203 204 register ipipe_lsc_vs addr(base, 0x9C) "" { 205 _ 16 mbz; 206 _ 8 mbz; 207 vs2 4 rw "LSC VS1"; 208 vs1 4 rw "LSC VS1"; 209 }; 210 211 register ipipe_lsc_hoft addr(base, 0xA0) "" { 212 _ 16 mbz; 213 _ 3 mbz; 214 val 13 rw "LSC HOFT"; 215 }; 216 217 register ipipe_lsc_ha2 addr(base, 0xA4) "" { 218 _ 16 mbz; 219 _ 3 mbz; 220 val 13 rw "LSC HA2"; 221 }; 222 223 register ipipe_lsc_ha1 addr(base, 0xA8) "" { 224 _ 16 mbz; 225 _ 3 mbz; 226 val 13 rw "LSC HA1"; 227 }; 228 229 register ipipe_lsc_hs addr(base, 0xAC) "" { 230 _ 16 mbz; 231 _ 8 mbz; 232 hs2 4 rw "LSC HS1"; 233 hs1 4 rw "LSC HS1"; 234 }; 235 236 register ipipe_lsc_gan_r addr(base, 0xB0) "" { 237 _ 16 mbz; 238 _ 8 mbz; 239 val 8 rw "GAN R"; 240 }; 241 242 register ipipe_lsc_gan_gr addr(base, 0xB4) "" { 243 _ 16 mbz; 244 _ 8 mbz; 245 val 8 rw "GAN GR"; 246 }; 247 248 register ipipe_lsc_gan_gb addr(base, 0xB8) "" { 249 _ 16 mbz; 250 _ 8 mbz; 251 val 8 rw "GAN GB"; 252 }; 253 254 register ipipe_lsc_gan_b addr(base, 0xBC) "" { 255 _ 16 mbz; 256 _ 8 mbz; 257 val 8 rw "GAN B"; 258 }; 259 260 register ipipe_lsc_oft_r addr(base, 0xC0) "" { 261 _ 16 mbz; 262 _ 8 mbz; 263 val 8 rw "LSC OFT R"; 264 }; 265 266 register ipipe_lsc_oft_gr addr(base, 0xC4) "" { 267 _ 16 mbz; 268 _ 8 mbz; 269 val 8 rw "LSC OFT GR"; 270 }; 271 272 register ipipe_lsc_oft_gb addr(base, 0xC8) "" { 273 _ 16 mbz; 274 _ 8 mbz; 275 val 8 rw "LSC OFT GB"; 276 }; 277 278 register ipipe_lsc_oft_b addr(base, 0xCC) "" { 279 _ 16 mbz; 280 _ 8 mbz; 281 val 8 rw "LSC OFT B"; 282 }; 283 284 register ipipe_lsc_shf addr(base, 0xD0) "" { 285 _ 16 mbz; 286 _ 12 mbz; 287 val 4 rw "LSC SHV"; 288 }; 289 290 register ipipe_lsc_max addr(base, 0xD4) "" { 291 _ 16 mbz; 292 _ 7 mbz; 293 val 9 rw "LSC MAX"; 294 }; 295 296 register ipipe_wb2_oft_r addr(base, 0x1D0) "White Balance Register" { 297 _ 16 mbz; 298 _ 4 mbz; 299 val 12 rw "Offset before white balance (S12) -2048 to +2047"; 300 }; 301 302 register ipipe_wb2_oft_gr addr(base, 0x1D4) "White Balance Register" { 303 _ 16 mbz; 304 _ 4 mbz; 305 val 12 rw "Offset before white balance (S12) -2048 to +2047"; 306 }; 307 308 register ipipe_wb2_oft_gb addr(base, 0x1D8) "White Balance Register" { 309 _ 16 mbz; 310 _ 4 mbz; 311 val 12 rw "Offset before white balance (S12) -2048 to +2047"; 312 }; 313 314 register ipipe_wb2_oft_b addr(base, 0x1DC) "White Balance Register" { 315 _ 16 mbz; 316 _ 4 mbz; 317 val 12 rw "Offset before white balance (S12) -2048 to +2047"; 318 }; 319 320 register ipipe_wb2_wgn_r addr(base, 0x1E0) "White Balance Register" { 321 _ 16 mbz; 322 _ 3 mbz; 323 val 13 rw "White balance gain for R in U4.9 format 0 to +15.998"; 324 }; 325 326 register ipipe_wb2_wgn_gr addr(base, 0x1E4) "White Balance Register" { 327 _ 16 mbz; 328 _ 3 mbz; 329 val 13 rw "White balance gain for Gr in U4.9 format 0 to +15.998"; 330 }; 331 332 register ipipe_wb2_wgn_gb addr(base, 0x1E8) "White Balance Register" { 333 _ 16 mbz; 334 _ 3 mbz; 335 val 13 rw "White balance gain for Gb in U4.9 format 0 to +15.998"; 336 }; 337 338 register ipipe_wb2_wgn_b addr(base, 0x1EC) "White Balance Register" { 339 _ 16 mbz; 340 _ 3 mbz; 341 val 13 rw "White balance gain for B in U4.9 format 0 to +15.998"; 342 }; 343 344 register ipipe_rgb1_mul_rr addr(base, 0x22C) "RGB to RGB Conversion Register" { 345 _ 16 mbz; 346 _ 4 mbz; 347 val 12 rw "The matrix coefficient. 011111111111 = 2047/256 = 7.99609375 011111111110 = 2046/256 [...] 000011111111 = 255/256 000100000000 = 256/256 = 1 000100000001 = 257/256 [...] 000000000001 = 1/256 000000000000 = 0/256 = 0 111111111111 = -1/256 = -0.00390625 111111111110 = -2/256 [...] 100000000001 = -2047/256 100000000000 = -2048/256 = -8."; 348 }; 349 350 register ipipe_rgb1_mul_gr addr(base, 0x230) "RGB to RGB Conversion Register" { 351 _ 16 mbz; 352 _ 4 mbz; 353 val 12 rw "The matrix coefficient."; 354 }; 355 356 register ipipe_rgb1_mul_br addr(base, 0x234) "RGB to RGB Conversion Register" { 357 _ 16 mbz; 358 _ 4 mbz; 359 val 12 rw "The matrix coefficient."; 360 }; 361 362 register ipipe_rgb1_mul_rg addr(base, 0x238) "RGB to RGB Conversion Register" { 363 _ 16 mbz; 364 _ 4 mbz; 365 val 12 rw "The matrix coefficient."; 366 }; 367 368 register ipipe_rgb1_mul_gg addr(base, 0x23C) "RGB to RGB Conversion Register" { 369 _ 16 mbz; 370 _ 4 mbz; 371 val 12 rw "The matrix coefficient."; 372 }; 373 374 register ipipe_rgb1_mul_bg addr(base, 0x240) "RGB to RGB Conversion Register" { 375 _ 16 mbz; 376 _ 4 mbz; 377 val 12 rw "The matrix coefficient."; 378 }; 379 380 register ipipe_rgb1_mul_rb addr(base, 0x244) "RGB to RGB Conversion Register" { 381 _ 16 mbz; 382 _ 4 mbz; 383 val 12 rw "The matrix coefficient."; 384 }; 385 386 register ipipe_rgb1_mul_gb addr(base, 0x248) "RGB to RGB Conversion Register" { 387 _ 16 mbz; 388 _ 4 mbz; 389 val 12 rw "The matrix coefficient."; 390 }; 391 392 register ipipe_rgb1_mul_bb addr(base, 0x24C) "RGB to RGB Conversion Register" { 393 _ 16 mbz; 394 _ 4 mbz; 395 val 12 rw "The matrix coefficient."; 396 }; 397 398 register ipipe_rgb1_oft_or addr(base, 0x250) "RGB to RGB Conversion Register" { 399 _ 16 mbz; 400 _ 3 mbz; 401 val 13 rw "The output offset value for R. (s13) -4096 to +4095"; 402 }; 403 404 register ipipe_rgb1_oft_og addr(base, 0x254) "RGB to RGB Conversion Register" { 405 _ 16 mbz; 406 _ 3 mbz; 407 val 13 rw "The output offset value for G. (s13) -4096 to +4095"; 408 }; 409 410 register ipipe_rgb1_oft_ob addr(base, 0x258) "RGB to RGB Conversion Register" { 411 _ 16 mbz; 412 _ 3 mbz; 413 val 13 rw "The output offset value for B. (s13) -4096 to +4095"; 414 }; 415 416 constants siz_status width(2) "" { 417 SIZ_0 = 0 "64 words"; 418 SIZ_1 = 1 "128 words"; 419 SIZ_3 = 3 "512 words"; 420 SIZ_2 = 2 "256 words"; 421 }; 422 423 constants tbl_status1 width(1) "" { 424 TBL_0_1 = 0 "RAM"; 425 TBL_1_1 = 1 "ROM"; 426 }; 427 428 constants bypb_status width(1) "" { 429 BYPB_0 = 0 "Not bypassed"; 430 BYPB_1 = 1 "Bypassed"; 431 }; 432 433 register ipipe_gmm_cfg addr(base, 0x25C) "RGB to RGB Conversion Register" { 434 _ 16 mbz; 435 _ 9 mbz; 436 siz 2 rw type(siz_status) "The size of the gamma table."; 437 tbl 1 rw type(tbl_status1) "Selection of Gamma table."; 438 _ 1 mbz; 439 bypb 1 rw type(bypb_status) "Gamma correction mode for B"; 440 bypg 1 rw type(bypb_status) "Gamma correction mode for G"; 441 bypr 1 rw type(bypb_status) "Gamma correction mode for R"; 442 }; 443 444 register ipipe_rgb2_mul_rr addr(base, 0x260) "RGB to RGB conversion after gamma" { 445 _ 16 mbz; 446 _ 5 mbz; 447 val 11 rw "The matrix coefficient. 011111111111 = 2047/256 = 7.99609375 011111111110 = 2046/256 000011111111 = 255/256 000100000000 = 256/256 = 1 000100000001 = 257/256 000000000001 = 1/256 000000000000 = 0/256 = 0 111111111111 = -1/256 = -0.00390625 111111111110 = -2/256 100000000001 = -2047/256 100000000000 = -2048/256 = -8."; 448 }; 449 450 register ipipe_rgb2_mul_gr addr(base, 0x264) "RGB to RGB conversion after gamma" { 451 _ 16 mbz; 452 _ 5 mbz; 453 val 11 rw "The matrix coefficient."; 454 }; 455 456 register ipipe_rgb2_mul_br addr(base, 0x268) "RGB to RGB conversion after gamma" { 457 _ 16 mbz; 458 _ 5 mbz; 459 val 11 rw "The matrix coefficient."; 460 }; 461 462 register ipipe_rgb2_mul_rg addr(base, 0x26C) "RGB to RGB conversion after gamma" { 463 _ 16 mbz; 464 _ 5 mbz; 465 val 11 rw "The matrix coefficient."; 466 }; 467 468 register ipipe_rgb2_mul_gg addr(base, 0x270) "RGB to RGB conversion after gamma" { 469 _ 16 mbz; 470 _ 5 mbz; 471 val 11 rw "The matrix coefficient."; 472 }; 473 474 register ipipe_rgb2_mul_bg addr(base, 0x274) "RGB to RGB conversion after gamma" { 475 _ 16 mbz; 476 _ 5 mbz; 477 val 11 rw "The matrix coefficient."; 478 }; 479 480 register ipipe_rgb2_mul_rb addr(base, 0x278) "RGB to RGB conversion after gamma" { 481 _ 16 mbz; 482 _ 5 mbz; 483 val 11 rw "The matrix coefficient."; 484 }; 485 486 register ipipe_rgb2_mul_gb addr(base, 0x27C) "RGB to RGB conversion after gamma" { 487 _ 16 mbz; 488 _ 5 mbz; 489 val 11 rw "The matrix coefficient."; 490 }; 491 492 register ipipe_rgb2_mul_bb addr(base, 0x280) "RGB to RGB conversion after gamma" { 493 _ 16 mbz; 494 _ 5 mbz; 495 val 11 rw "The matrix coefficient."; 496 }; 497 498 register ipipe_rgb2_oft_or addr(base, 0x284) "RGB to RGB conversion after gamma" { 499 _ 16 mbz; 500 _ 5 mbz; 501 val 11 rw "The output offset value for R S10 number: -1024 to + 1023"; 502 }; 503 504 register ipipe_rgb2_oft_og addr(base, 0x288) "RGB to RGB conversion after gamma" { 505 _ 16 mbz; 506 _ 5 mbz; 507 val 11 rw "The output offset value for G S10 number: -1024 to + 1023"; 508 }; 509 510 register ipipe_rgb2_oft_ob addr(base, 0x28C) "RGB to RGB conversion after gamma" { 511 _ 16 mbz; 512 _ 5 mbz; 513 val 11 rw "The output offset value for B S10 number: -1024 to + 1023"; 514 }; 515 516 register ipipe_yuv_adj addr(base, 0x294) "RGB to YUV Conversion Register" { 517 _ 16 mbz; 518 brt 8 rw "The offset value for brightness control."; 519 crt 8 rw "The multiplier coefficient value for contrast control. 00000000 = 0/16 = 0 00000001 = 1/16 00001111 = 15/16 00010000 = 16/16 = 1 00010001 = 17/16 11111110 = 254/16 11111111 = 255/16 = 15.9375"; 520 }; 521 522 register ipipe_yuv_mul_ry addr(base, 0x298) "RGB to YUV Conversion Register" { 523 _ 16 mbz; 524 _ 4 mbz; 525 val 12 rw "Matrix Coefficient for RY (S4.8 = -8 - +7.996)"; 526 }; 527 528 register ipipe_yuv_mul_gy addr(base, 0x29C) "RGB to YUV Conversion Register" { 529 _ 16 mbz; 530 _ 4 mbz; 531 val 12 rw "Matrix Coefficient for GY (S4.8 = -8 - +7.996)"; 532 }; 533 534 register ipipe_yuv_mul_by addr(base, 0x2A0) "RGB to YUV Conversion Register" { 535 _ 16 mbz; 536 _ 4 mbz; 537 val 12 rw "Matrix Coefficient for BY (S4.8 = -8 - +7.996)"; 538 }; 539 540 register ipipe_yuv_mul_rcb addr(base, 0x2A4) "RGB to YUV Conversion Register" { 541 _ 16 mbz; 542 _ 4 mbz; 543 val 12 rw "The matrix coefficient."; 544 }; 545 546 register ipipe_yuv_mul_gcb addr(base, 0x2A8) "RGB to YUV Conversion Register" { 547 _ 16 mbz; 548 _ 4 mbz; 549 val 12 rw "The matrix coefficient."; 550 }; 551 552 register ipipe_yuv_mul_bcb addr(base, 0x2AC) "RGB to YUV Conversion Register" { 553 _ 16 mbz; 554 _ 4 mbz; 555 val 12 rw "The matrix coefficient."; 556 }; 557 558 register ipipe_yuv_mul_rcr addr(base, 0x2B0) "RGB to YUV Conversion Register" { 559 _ 16 mbz; 560 _ 4 mbz; 561 val 12 rw "The matrix coefficient."; 562 }; 563 564 register ipipe_yuv_mul_gcr addr(base, 0x2B4) "RGB to YUV Conversion Register" { 565 _ 16 mbz; 566 _ 4 mbz; 567 val 12 rw "The matrix coefficient."; 568 }; 569 570 register ipipe_yuv_mul_bcr addr(base, 0x2B8) "RGB to YUV Conversion Register" { 571 _ 16 mbz; 572 _ 4 mbz; 573 val 12 rw "The matrix coefficient."; 574 }; 575 576 register ipipe_yuv_oft_y addr(base, 0x2BC) "RGB to YUV Conversion Register" { 577 _ 16 mbz; 578 _ 5 mbz; 579 val 11 rw "The output offset value for Y"; 580 }; 581 582 register ipipe_yuv_oft_cb addr(base, 0x2C0) "RGB to YUV Conversion Register" { 583 _ 16 mbz; 584 _ 5 mbz; 585 val 11 rw "The output offset value for Cb For Cb/Cr, set (0x80 + offset value) here. (0x80 for zero offset.)"; 586 }; 587 588 register ipipe_yuv_oft_cr addr(base, 0x2C4) "RGB to YUV Conversion Register" { 589 _ 16 mbz; 590 _ 5 mbz; 591 val 11 rw "The output offset value for Cr For Cb/Cr, set (0x80 + offset value) here. (0x80 for zero offset.)"; 592 }; 593 594 constants lpf_status width(1) "" { 595 LPF_0 = 0 "off"; 596 LPF_1 = 1 "on"; 597 }; 598 599 constants pos_status width(1) "" { 600 POS_0 = 0 "Cosited = same position with luminance"; 601 POS_1 = 1 "Centered = middle of the luminance"; 602 }; 603 604 register ipipe_yuv_phs addr(base, 0x2C8) "YUV4:2:2 down sampling register. This register controls the YUV4:4:4 to YUV4:2:2 chroma downsampling. This register is valid if .FMT = 0 (RAW input and YUV output). = 0 leads to pure subsampling, no filtering, cosited chroma output. = 1 leads to (1, 1) >> 1 filtering, centered chroma output. = 2 leads to (1, 2, 1) >> 1 filtering, cosited chroma output. = 3 leads to (1, 3, 3, 1) >> 3 filtering, centered chroma output. When the chroma output is cosited, and that downsampling is enabled in the RESIZER module, one need to take care that the averager disrupts the relative phase for luma and chroma color components. The and registers need to be used to fix the disruption." { 605 _ 16 mbz; 606 _ 14 mbz; 607 lpf 1 rw type(lpf_status) "121-LPF enable for chrominance samples. This register is valid if IPIPE_SRC_FMT.FMT = 0 (RAW input and YUV output)."; 608 pos 1 rw type(pos_status) "This bit sets the output position of the chrominance sample with regards to the luma sample positions. One can choose between centered and cosited. This register is valid if IPIPE_SRC_FMT.FMT = 0 (RAW input and YUV output). The RESIZER module does not change the relative position of the chroma samples vs. the luma samples between the input and output and the chroma position at the output of the IPIPE module and at the output of the RESIZER module must be identical. In other words, we must have RSZ_YUV_PHS.POS = IPIPE_YUV_PHS.POS."; 609 }; 610 611 register ipipe_yee_en addr(base, 0x2D4) "Edge Enhancer Register" { 612 _ 16 mbz; 613 _ 15 mbz; 614 en 1 rw type(wrt_status) "The on/off selection of the Edge enhancer."; 615 }; 616 617 constants sel_status width(1) "" { 618 SEL_0 = 0 "EE + ES"; 619 SEL_1 = 1 "Maximum (EE, ES)"; 620 }; 621 622 register ipipe_yee_typ addr(base, 0x2D8) "Edge Enhancer Register" { 623 _ 16 mbz; 624 _ 14 mbz; 625 hal 1 rw "Halo reduction in Edge Sharpener module"; 626 sel 1 rw type(sel_status) "Merging method between Edge Enhancer and Edge Sharpener"; 627 }; 628 629 register ipipe_yee_shf addr(base, 0x2DC) "Edge Enhancer Register" { 630 _ 16 mbz; 631 _ 12 mbz; 632 shf 4 rw "Down shift length of high pass filter (HPF) in edge enhancer."; 633 }; 634 635 register ipipe_yee_mul_00 addr(base, 0x2E0) "Edge Enhancer Register" { 636 _ 16 mbz; 637 _ 6 mbz; 638 val 10 rw "Multiplier coefficient in HPF. 0111111111 = 511 0111111110 = 510 0000000001 = 1 0000000000 = 0 1111111111 = -1 1000000001 = -511 1000000000 = -512"; 639 }; 640 641 register ipipe_yee_mul_01 addr(base, 0x2E4) "Edge Enhancer Register" { 642 _ 16 mbz; 643 _ 6 mbz; 644 val 10 rw "Multiplier coefficient in HPF."; 645 }; 646 647 register ipipe_yee_mul_02 addr(base, 0x2E8) "Edge Enhancer Register" { 648 _ 16 mbz; 649 _ 6 mbz; 650 val 10 rw "Multiplier coefficient in HPF."; 651 }; 652 653 register ipipe_yee_mul_10 addr(base, 0x2EC) "Edge Enhancer Register" { 654 _ 16 mbz; 655 _ 6 mbz; 656 val 10 rw "Multiplier coefficient in HPF."; 657 }; 658 659 register ipipe_yee_mul_11 addr(base, 0x2F0) "Edge Enhancer Register" { 660 _ 16 mbz; 661 _ 6 mbz; 662 val 10 rw "Multiplier coefficient in HPF."; 663 }; 664 665 register ipipe_yee_mul_12 addr(base, 0x2F4) "Edge Enhancer Register" { 666 _ 16 mbz; 667 _ 6 mbz; 668 val 10 rw "Multiplier coefficient in HPF."; 669 }; 670 671 register ipipe_yee_mul_20 addr(base, 0x2F8) "Edge Enhancer Register" { 672 _ 16 mbz; 673 _ 6 mbz; 674 val 10 rw "Multiplier coefficient in HPF."; 675 }; 676 677 register ipipe_yee_mul_21 addr(base, 0x2FC) "Edge Enhancer Register" { 678 _ 16 mbz; 679 _ 6 mbz; 680 val 10 rw "Multiplier coefficient in HPF."; 681 }; 682 683 register ipipe_yee_mul_22 addr(base, 0x300) "Edge Enhancer Register" { 684 _ 16 mbz; 685 _ 6 mbz; 686 val 10 rw "Multiplier coefficient in HPF."; 687 }; 688 689 register ipipe_yee_thr addr(base, 0x304) "Edge Enhancer Register" { 690 _ 16 mbz; 691 _ 10 mbz; 692 val 6 rw "Edge Enhancer lower threshold before referring to LUT. If HPF < IPIPE_YEE_THR -> output is HPF + IPIPE_YEE_THR If HPF > IPIPE_YEE_THR -> output is HPF - IPIPE_YEE_THR Otherwise, output is zero."; 693 }; 694 695 register ipipe_yee_e_gan addr(base, 0x308) "Edge Enhancer Register" { 696 _ 16 mbz; 697 _ 4 mbz; 698 val 12 rw "Edge sharpener gain"; 699 }; 700 701 register ipipe_yee_e_thr_1 addr(base, 0x30C) "Edge Enhancer Register" { 702 _ 16 mbz; 703 _ 4 mbz; 704 val 12 rw "Edge sharpener HPF value lower limit"; 705 }; 706 707 register ipipe_yee_e_thr_2 addr(base, 0x310) "Edge Enhancer Register" { 708 _ 16 mbz; 709 _ 10 mbz; 710 val 6 rw "Edge sharpener HPF value upper limit (after 6 bit right shift)"; 711 }; 712 713 register ipipe_yee_g_gan addr(base, 0x314) "Edge Enhancer Register" { 714 _ 16 mbz; 715 _ 8 mbz; 716 val 8 rw "Edge sharpener, gain value on gradient"; 717 }; 718 719 register ipipe_yee_g_oft addr(base, 0x318) "Edge Enhancer Register" { 720 _ 16 mbz; 721 _ 10 mbz; 722 val 6 rw "Edge sharpener, offset value on gradient"; 723 }; 724 725 register ipipe_box_en addr(base, 0x380) "Boxcar Register" { 726 _ 16 mbz; 727 _ 15 mbz; 728 en 1 rw type(wrt_status) "This bit enables or disables the BOXCAR functionality. The BOXCAR output is written to SDRAM. One need to set the IPIPE_BOX_SDR_SAD_H and IPIPE_BOX_SDR_SAD_L registers with the appropriate address."; 729 }; 730 731 register ipipe_box_mode addr(base, 0x384) "Boxcar Register" { 732 _ 16 mbz; 733 _ 15 mbz; 734 ost 1 rw type(ost_status) "The processing mode selection of the Boxcar function. A 0 indicates the mode of the free run, a 1 indicates the mode of the one shot."; 735 }; 736 737 constants sel_status1 width(1) "" { 738 SEL_0_1 = 0 "8x8"; 739 SEL_1_1 = 1 "16x16"; 740 }; 741 742 register ipipe_box_typ addr(base, 0x388) "Boxcar Register" { 743 _ 16 mbz; 744 _ 15 mbz; 745 sel 1 rw type(sel_status1) "Block size in boxcar sampling"; 746 }; 747 748 register ipipe_box_shf addr(base, 0x38C) "Boxcar Register" { 749 _ 16 mbz; 750 _ 13 mbz; 751 val 3 rw "The down shift value applied to the boxcar computation result. R out = SUM (Rij) >> SHF G out = (SUM (Gr ij)/2 + SUM (Gr ij)/2) >> SHF B out = SUM (Gij) >> SHF"; 752 }; 753 754 register ipipe_box_sdr_sad_h addr(base, 0x390) "Boxcar Register" { 755 _ 16 mbz; 756 val 16 rw "The higher 11 bits of the first address of output in memory."; 757 }; 758 759 register ipipe_box_sdr_sad_l addr(base, 0x394) "Boxcar Register" { 760 _ 16 mbz; 761 val 11 rw "The lower 16 bits of the first address of output in memory."; 762 val_reserved 5 ro "Ensures 32-byte alignment."; 763 }; 764 765 constants en_status1 width(1) "" { 766 EN_0_4 = 0 "disable"; 767 EN_1_4 = 1 "start/busy"; 768 }; 769 770 register ipipe_hst_en addr(base, 0x39C) "Histogram" { 771 _ 16 mbz; 772 _ 15 mbz; 773 en 1 rw type(en_status1) "This bit enables or disables the HISTOGRAM functionality. When enabled, the HISTOGRAM computation will start the processing from the next rising edge of the VD pulse. If the processing mode of the HISTOGRAM is one shot, the enable bit will be cleared to 0 immediately after the processing has started."; 774 }; 775 776 register ipipe_hst_mode addr(base, 0x3A0) "Histogram" { 777 _ 16 mbz; 778 _ 15 mbz; 779 ost 1 rw type(ost_status) "The processing mode selection of the Histogram module. A 0 indicates the mode of the free run, a 1 indicates the mode of the one shot."; 780 }; 781 782 constants sel_status2 width(1) "" { 783 SEL_0_2 = 0 "From noise filter input"; 784 SEL_1_2 = 1 "From RGBtoYUV"; 785 }; 786 787 constants typ_status width(2) "" { 788 TYP_0 = 0 "Gb"; 789 TYP_1 = 1 "Gr"; 790 TYP_3 = 3 "Reserved"; 791 TYP_2 = 2 "(Gb+Gr)/2"; 792 }; 793 794 register ipipe_hst_sel addr(base, 0x3A4) "Histogram" { 795 _ 16 mbz; 796 _ 13 mbz; 797 sel 1 rw type(sel_status2) "Input selection. When SEL0=0, RGBY are sampled from the output of the line buffer in noise filter-2. When SEL0=1, YCbCr are sampled at the output of RGB2YCbCr module. Y is sampled twice."; 798 typ 2 rw type(typ_status) "G selection in Bayer mode (SEL0=0)"; 799 }; 800 801 constants bin_status width(2) "" { 802 BIN_0 = 0 "32"; 803 BIN_1 = 1 "64"; 804 BIN_3 = 3 "256"; 805 BIN_2 = 2 "128"; 806 }; 807 808 register ipipe_hst_para addr(base, 0x3A8) "Histogram COL0, COL1, COL2, and COL3 should be set to 1." { 809 _ 16 mbz; 810 _ 2 mbz; 811 bin 2 rw type(bin_status) "The number of the bins."; 812 shf 4 rw "The shift length of the input data. data = (INPUT >> SHF)"; 813 col3 1 rw type(wrt_status) "The on/off selection of the color pattern 3 (Y)."; 814 col2 1 rw type(wrt_status) "The on/off selection of the color pattern 2 (B)."; 815 col1 1 rw type(wrt_status) "The on/off selection of the color pattern 1 (G)."; 816 col0 1 rw type(wrt_status) "The on/off selection of the color pattern 0 (R)."; 817 rgn3 1 rw type(wrt_status) "The on/off selection of the region 3."; 818 rgn2 1 rw type(wrt_status) "The on/off selection of the region 2."; 819 rgn1 1 rw type(wrt_status) "The on/off selection of the region 1."; 820 rgn0 1 rw type(wrt_status) "The on/off selection of the region 0."; 821 }; 822 823 register ipipe_hst_0_vps addr(base, 0x3AC) "Histogram" { 824 _ 16 mbz; 825 _ 3 mbz; 826 val 12 rw "The vertical position of the region 0 from theIPIPE_SRC_VPS. The region 0 will start the Histogram processing from VAL line. VAL[0] can not be written."; 827 val_reserved 1 ro "The vertical position of the region 0 from theIPIPE_SRC_VPS. The region 0 will start the Histogram processing from VAL line. VAL[0] can not be written."; 828 }; 829 830 register ipipe_hst_0_vsz addr(base, 0x3B0) "Histogram" { 831 _ 16 mbz; 832 _ 3 mbz; 833 val 12 rw "The vertical size of the region 0. The Histogram processing of the region 0 will process (VAL+1) lines."; 834 val_reserved 1 ro "The vertical size of the region 0. The Histogram processing of the region 0 will process (VAL+1) lines. VAL[0] cannot be written."; 835 }; 836 837 register ipipe_hst_0_hps addr(base, 0x3B4) "Histogram" { 838 _ 16 mbz; 839 _ 3 mbz; 840 val 12 rw "The horizontal position of the region 0 from theIPIPE_SRC_HPS. The region 0 will start the Histogram processing from VAL clocks. VAL[0] can not be written."; 841 val_reserved 1 ro "The horizontal position of the region 0 from theIPIPE_SRC_HPS. The region 0 will start the Histogram processing from VAL clocks. VAL[0] can not be written."; 842 }; 843 844 register ipipe_hst_0_hsz addr(base, 0x3B8) "Histogram" { 845 _ 16 mbz; 846 _ 3 mbz; 847 val 12 rw "The horizontal size of the region 0. The Histogram processing of the region 0 will process (VAL+1) clocks. VAL[0] cannot be written."; 848 val_reserved 1 ro "The horizontal size of the region 0. The Histogram processing of the region 0 will process (VAL+1) clocks. VAL[0] cannot be written."; 849 }; 850 851 register ipipe_hst_1_vps addr(base, 0x3BC) "Histogram" { 852 _ 16 mbz; 853 _ 3 mbz; 854 val 12 rw "The vertical position of the region 0 from theIPIPE_SRC_VPS. The region 1 will start the Histogram processing from VAL line. VAL[0] can not be written."; 855 val_reserved 1 ro "The vertical position of the region 0 from theIPIPE_SRC_VPS. The region 1 will start the Histogram processing from VAL line. VAL[0] can not be written."; 856 }; 857 858 register ipipe_hst_1_vsz addr(base, 0x3C0) "Histogram" { 859 _ 16 mbz; 860 _ 3 mbz; 861 val 12 rw "The vertical size of the region 1. The Histogram processing of the region 1 will process (VAL+1) lines. VAL[0] cannot be written."; 862 val_reserved 1 ro "The vertical size of the region 1. The Histogram processing of the region 1 will process (VAL+1) lines. VAL[0] cannot be written."; 863 }; 864 865 register ipipe_hst_1_hps addr(base, 0x3C4) "Histogram" { 866 _ 16 mbz; 867 _ 3 mbz; 868 val 12 rw "The horizontal position of the region 0 from theIPIPE_SRC_HPS. The region 1 will start the Histogram processing from VAL clocks. VAL[0] can not be written."; 869 val_reserved 1 ro "The horizontal position of the region 0 from theIPIPE_SRC_HPS. The region 1 will start the Histogram processing from VAL clocks. VAL[0] can not be written."; 870 }; 871 872 register ipipe_hst_1_hsz addr(base, 0x3C8) "Histogram" { 873 _ 16 mbz; 874 _ 3 mbz; 875 val 12 rw "The horizontal size of the region 1. The Histogram processing of the region 1 will process (VAL+1) clocks. VAL[0] cannot be written."; 876 val_reserved 1 ro "The horizontal size of the region 1. The Histogram processing of the region 1 will process (VAL+1) clocks. VAL[0] cannot be written."; 877 }; 878 879 register ipipe_hst_2_vps addr(base, 0x3CC) "Histogram" { 880 _ 16 mbz; 881 _ 3 mbz; 882 val 12 rw "The vertical position of the region 0 from theIPIPE_SRC_VPS. The region 2 will start the Histogram processing from VAL line. VAL[0] can not be written."; 883 val_reserved 1 ro "The vertical position of the region 0 from theIPIPE_SRC_VPS. The region 2 will start the Histogram processing from VAL line. VAL[0] can not be written."; 884 }; 885 886 register ipipe_hst_2_vsz addr(base, 0x3D0) "Histogram" { 887 _ 16 mbz; 888 _ 3 mbz; 889 val 12 rw "The vertical size of the region 2. The Histogram processing of the region 2 will process (VAL+1) lines. VAL[0] cannot be written."; 890 val_reserved 1 ro "The vertical size of the region 2. The Histogram processing of the region 2 will process (VAL+1) lines. VAL[0] cannot be written."; 891 }; 892 893 register ipipe_hst_2_hps addr(base, 0x3D4) "Histogram" { 894 _ 16 mbz; 895 _ 3 mbz; 896 val 12 rw "The horizontal position of the region 0 from theIPIPE_SRC_HPS. The region 2 will start the Histogram processing from VAL clocks. VAL[0] can not be written."; 897 val_reserved 1 ro "The horizontal position of the region 0 from theIPIPE_SRC_HPS. The region 2 will start the Histogram processing from VAL clocks. VAL[0] can not be written."; 898 }; 899 900 register ipipe_hst_2_hsz addr(base, 0x3D8) "Histogram" { 901 _ 16 mbz; 902 _ 3 mbz; 903 val 12 rw "The horizontal size of the region 2. The Histogram processing of the region 2 will process (VAL+1) clocks. VAL[0] cannot be written."; 904 val_reserved 1 ro "The horizontal size of the region 2. The Histogram processing of the region 2 will process (VAL+1) clocks. VAL[0] cannot be written."; 905 }; 906 907 register ipipe_hst_3_vps addr(base, 0x3DC) "Histogram" { 908 _ 16 mbz; 909 _ 3 mbz; 910 val 12 rw "The vertical position of the region 0 from theIPIPE_SRC_VPS. The region 3 will start the Histogram processing from VAL line. VAL[0] can not be written."; 911 val_reserved 1 ro "The vertical position of the region 0 from theIPIPE_SRC_VPS. The region 3 will start the Histogram processing from VAL line. VAL[0] can not be written."; 912 }; 913 914 register ipipe_hst_3_vsz addr(base, 0x3E0) "Histogram" { 915 _ 16 mbz; 916 _ 3 mbz; 917 val 12 rw "The vertical size of the region 3. The Histogram processing of the region 3 will process (VAL+1) lines. VAL[0] cannot be written."; 918 val_reserved 1 ro "The vertical size of the region 3. The Histogram processing of the region 3 will process (VAL+1) lines. VAL[0] cannot be written."; 919 }; 920 921 register ipipe_hst_3_hps addr(base, 0x3E4) "Histogram" { 922 _ 16 mbz; 923 _ 3 mbz; 924 val 12 rw "The horizontal position of the region 0 from theIPIPE_SRC_HPS. The region 3 will start the Histogram processing from VAL clocks. VAL[0] can not be written."; 925 val_reserved 1 ro "The horizontal position of the region 0 from theIPIPE_SRC_HPS. The region 3 will start the Histogram processing from VAL clocks. VAL[0] can not be written."; 926 }; 927 928 register ipipe_hst_3_hsz addr(base, 0x3E8) "Histogram" { 929 _ 16 mbz; 930 _ 3 mbz; 931 val 12 rw "The horizontal size of the region 3. The Histogram processing of the region 3 will process (VAL+1) clocks. VAL[0] cannot be written."; 932 val_reserved 1 ro "The horizontal size of the region 3. The Histogram processing of the region 3 will process (VAL+1) clocks. VAL[0] cannot be written."; 933 }; 934 935 constants sel_status3 width(1) "" { 936 SEL_0_3 = 0 "Use Table 0 and 1 = 4KB in the memory ISP map."; 937 SEL_1_3 = 1 "Use Table 2 and 3 = 4KB in the memory ISP map."; 938 }; 939 940 register ipipe_hst_tbl addr(base, 0x3EC) "Histogram" { 941 _ 16 mbz; 942 _ 14 mbz; 943 clr 1 rw type(wrt_status) "Histogram memory clear. The histogram can be cleared before the start of operations. However, the clear takes 512 cycles and therefore: + if line size > 512, the first line must not be used for histogram computation. + if line size < 512, ceil (512/line size) lines must not be used for histogram computation. It's the programmer's responsibility to set the histogram computation area outside the 'clear' area."; 944 sel 1 rw type(sel_status3) "This bit must be used to select which memory is used to store the histogram data. By selecting alternatively one or the other bit, one can double buffer the histogram output buffer. The 4 KB memory can either be read by the CPU or a DMA request."; 945 }; 946 947 register ipipe_hst_mul_r addr(base, 0x3F0) "Histogram" { 948 _ 16 mbz; 949 _ 8 mbz; 950 gain 8 rw "Gain"; 951 }; 952 953 register ipipe_hst_mul_gr addr(base, 0x3F4) "Histogram" { 954 _ 16 mbz; 955 _ 8 mbz; 956 gain 8 rw "Gain"; 957 }; 958 959 register ipipe_hst_mul_gb addr(base, 0x3F8) "Histogram" { 960 _ 16 mbz; 961 _ 8 mbz; 962 gain 8 rw "Gain"; 963 }; 964 965 register ipipe_hst_mul_b addr(base, 0x3FC) "Histogram" { 966 _ 16 mbz; 967 _ 8 mbz; 968 gain 8 rw "Gain"; 969 }; 970};