1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstr. 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_iss_bte.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_iss_bte msbfirst ( addr base ) "" { 29 30 31 register bte_hl_revision ro addr(base, 0x0) "IP revision identifier (X.Y.R) Used by software to track features, bugs, and compatibility" type(uint32); 32 33 constants respfifo_status width(3) "" { 34 RESPFIFO_3_r = 3 "64 x 128 bits"; 35 RESPFIFO_4_r = 4 "128 x 128 bits"; 36 RESPFIFO_2_r = 2 "32 x 128 bits"; 37 RESPFIFO_0_r = 0 "Reserved"; 38 RESPFIFO_6_r = 6 "Reserved"; 39 RESPFIFO_1_r = 1 "16 x 128 bits"; 40 RESPFIFO_7_r = 7 "Reserved"; 41 RESPFIFO_5_r = 5 "Reserved"; 42 }; 43 44 constants contexts_status width(2) "" { 45 CONTEXTS_3_r = 3 "Reserved"; 46 CONTEXTS_2_r = 2 "8 contexts"; 47 CONTEXTS_1_r = 1 "4 contexts"; 48 CONTEXTS_0_r = 0 "2 contexts"; 49 }; 50 51 register bte_hl_hwinfo addr(base, 0x4) "Information about the hardware configuration of the IP module; that is, typically, the HDL generics (if any) of the module." { 52 _ 8 mbz; 53 respfifo 3 ro type(respfifo_status) "Response FIFO size"; 54 contexts 2 ro type(contexts_status) "Number of contexts"; 55 _ 19 rsvd; 56 }; 57 58 constants idlemode_status width(2) "" { 59 IDLEMODE_0 = 0 "An IDLE request is acknowledged unconditionally"; 60 IDLEMODE_1 = 1 "An IDLE request is never acknowledged"; 61 IDLEMODE_3 = 3 "Reserved. Do not use"; 62 IDLEMODE_2 = 2 "Smart-idle mode. Acknowledgment to an IDLE request is given based on the internal activity of the module."; 63 }; 64 65 constants softreset_status width(1) "" { 66 SOFTRESET_0_w = 0 "No action"; 67 SOFTRESET_1_w = 1 "Initiate software reset"; 68 SOFTRESET_1_r = 1 "Reset (software or other) ongoing"; 69 SOFTRESET_0_r = 0 "Reset done, no pending action"; 70 }; 71 72 register bte_hl_sysconfig addr(base, 0x10) "Clock management configuration" { 73 _ 28 mbz; 74 idlemode 2 rw type(idlemode_status) "Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state."; 75 _ 1 mbz; 76 softreset 1 rw type(softreset_status) "Software reset."; 77 }; 78 79 constants irq_ctx3_err_status width(1) "" { 80 IRQ_CTX3_ERR_0_w = 0 "No action"; 81 IRQ_CTX3_ERR_1_w = 1 "Set event (debug)"; 82 IRQ_CTX3_ERR_1_r = 1 "Event pending"; 83 IRQ_CTX3_ERR_0_r = 0 "No event pending"; 84 }; 85 86 register bte_hl_irqstatus_raw addr(base, 0x20) "Per-event raw interrupt status vector Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." { 87 _ 4 mbz; 88 irq_ctx3_err 1 rw type(irq_ctx3_err_status) "Read request received before sufficient data has been prefetched."; 89 irq_ctx2_err 1 rw type(irq_ctx3_err_status) "Read request received before sufficient data has been prefetched."; 90 irq_ctx1_err 1 rw type(irq_ctx3_err_status) "Read request received before sufficient data has been prefetched."; 91 irq_ctx0_err 1 rw type(irq_ctx3_err_status) "Read request received before sufficient data has been prefetched."; 92 _ 4 mbz; 93 irq_ctx3_invalid 1 rw type(irq_ctx3_err_status) "Invalid access."; 94 irq_ctx2_invalid 1 rw type(irq_ctx3_err_status) "Invalid access."; 95 irq_ctx1_invalid 1 rw type(irq_ctx3_err_status) "Invalid access."; 96 irq_ctx0_invalid 1 rw type(irq_ctx3_err_status) "Invalid access."; 97 _ 4 mbz; 98 irq_ctx3_done 1 rw type(irq_ctx3_err_status) "Context has been fully transferred to the TILER"; 99 irq_ctx2_done 1 rw type(irq_ctx3_err_status) "Context has been fully transferred to the TILER"; 100 irq_ctx1_done 1 rw type(irq_ctx3_err_status) "Context has been fully transferred to the TILER"; 101 irq_ctx0_done 1 rw type(irq_ctx3_err_status) "Write mode: Context has been fully transferred to the TILER Read mode: Context prefetch has completed."; 102 _ 6 mbz; 103 irq_invalid 1 rw type(irq_ctx3_err_status) "Invalid access to the virtual space"; 104 irq_ocp_err 1 rw type(irq_ctx3_err_status) "OCP error received from OCP master port."; 105 }; 106 107 constants irq_ctx3_err_status1 width(1) "" { 108 IRQ_CTX3_ERR_0_w_1 = 0 "No action"; 109 IRQ_CTX3_ERR_1_w_1 = 1 "Clear (raw) event"; 110 IRQ_CTX3_ERR_1_r_1 = 1 "Event pending"; 111 IRQ_CTX3_ERR_0_r_1 = 0 "No (enabled) event pending"; 112 }; 113 114 register bte_hl_irqstatus addr(base, 0x24) "Per-event 'enabled' interrupt status vector. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." { 115 _ 4 mbz; 116 irq_ctx3_err 1 rw1c type(irq_ctx3_err_status1) "Read request received before sufficient data has been prefetched."; 117 irq_ctx2_err 1 rw1c type(irq_ctx3_err_status1) "Read request received before sufficient data has been prefetched."; 118 irq_ctx1_err 1 rw1c type(irq_ctx3_err_status1) "Read request received before sufficient data has been prefetched."; 119 irq_ctx0_err 1 rw1c type(irq_ctx3_err_status1) "Read request received before sufficient data has been prefetched."; 120 _ 4 mbz; 121 irq_ctx3_invalid 1 rw1c type(irq_ctx3_err_status1) "Invalid access."; 122 irq_ctx2_invalid 1 rw1c type(irq_ctx3_err_status1) "Invalid access."; 123 irq_ctx1_invalid 1 rw1c type(irq_ctx3_err_status1) "Invalid access."; 124 irq_ctx0_invalid 1 rw1c type(irq_ctx3_err_status1) "Invalid access."; 125 _ 4 mbz; 126 irq_ctx3_done 1 rw1c type(irq_ctx3_err_status1) "Context has been fully transferred to the TILER"; 127 irq_ctx2_done 1 rw1c type(irq_ctx3_err_status1) "Context has been fully transferred to the TILER"; 128 irq_ctx1_done 1 rw1c type(irq_ctx3_err_status1) "Context has been fully transferred to the TILER"; 129 irq_ctx0_done 1 rw1c type(irq_ctx3_err_status1) "Write mode: Context has been fully transferred to the TILER Read mode: Context prefetch has completed."; 130 _ 6 mbz; 131 irq_invalid 1 rw1c type(irq_ctx3_err_status1) "Invalid access to the virtual space"; 132 irq_ocp_err 1 rw1c type(irq_ctx3_err_status1) "OCP error received from OCP master port."; 133 }; 134 135 constants irq_ctx3_err_status2 width(1) "" { 136 IRQ_CTX3_ERR_0_w_2 = 0 "No action"; 137 IRQ_CTX3_ERR_1_w_2 = 1 "Enable interrupt"; 138 IRQ_CTX3_ERR_1_r_2 = 1 "Interrupt enabled"; 139 IRQ_CTX3_ERR_0_r_2 = 0 "Interrupt disabled (masked)"; 140 }; 141 142 register bte_hl_irqenable_set addr(base, 0x28) "Per-event interrupt enable bit vector Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." { 143 _ 4 mbz; 144 irq_ctx3_err 1 rw type(irq_ctx3_err_status2) "Read request received before sufficient data has been prefetched."; 145 irq_ctx2_err 1 rw type(irq_ctx3_err_status2) "Read request received before sufficient data has been prefetched."; 146 irq_ctx1_err 1 rw type(irq_ctx3_err_status2) "Read request received before sufficient data has been prefetched."; 147 irq_ctx0_err 1 rw type(irq_ctx3_err_status2) "Read request received before sufficient data has been prefetched."; 148 _ 4 mbz; 149 irq_ctx3_invalid 1 rw type(irq_ctx3_err_status2) "Invalid access."; 150 irq_ctx2_invalid 1 rw type(irq_ctx3_err_status2) "Invalid access."; 151 irq_ctx1_invalid 1 rw type(irq_ctx3_err_status2) "Invalid access."; 152 irq_ctx0_invalid 1 rw type(irq_ctx3_err_status2) "Invalid access."; 153 _ 4 mbz; 154 irq_ctx3_done 1 rw type(irq_ctx3_err_status2) "Context has been fully transferred to the TILER"; 155 irq_ctx2_done 1 rw type(irq_ctx3_err_status2) "Context has been fully transferred to the TILER"; 156 irq_ctx1_done 1 rw type(irq_ctx3_err_status2) "Context has been fully transferred to the TILER"; 157 irq_ctx0_done 1 rw type(irq_ctx3_err_status2) "Write mode: Context has been fully transferred to the TILER Read mode: Context prefetch has completed."; 158 _ 6 mbz; 159 irq_invalid 1 rw type(irq_ctx3_err_status2) "Invalid access to the virtual space"; 160 irq_ocp_err 1 rw type(irq_ctx3_err_status2) "OCP error received from OCP master port."; 161 }; 162 163 constants irq_ctx3_err_status3 width(1) "" { 164 IRQ_CTX3_ERR_0_w_3 = 0 "No action"; 165 IRQ_CTX3_ERR_1_w_3 = 1 "Disable interrupt"; 166 IRQ_CTX3_ERR_1_r_3 = 1 "Interrupt enabled"; 167 IRQ_CTX3_ERR_0_r_3 = 0 "Interrupt disabled (masked)"; 168 }; 169 170 register bte_hl_irqenable_clr addr(base, 0x2C) "Per-event interrupt enable bit vector Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." { 171 _ 4 mbz; 172 irq_ctx3_err 1 rw1c type(irq_ctx3_err_status3) "Read request received before sufficient data has been prefetched."; 173 irq_ctx2_err 1 rw1c type(irq_ctx3_err_status3) "Read request received before sufficient data has been prefetched."; 174 irq_ctx1_err 1 rw1c type(irq_ctx3_err_status3) "Read request received before sufficient data has been prefetched."; 175 irq_ctx0_err 1 rw1c type(irq_ctx3_err_status3) "Read request received before sufficient data has been prefetched."; 176 _ 4 mbz; 177 irq_ctx3_invalid 1 rw1c type(irq_ctx3_err_status3) "Invalid access."; 178 irq_ctx2_invalid 1 rw1c type(irq_ctx3_err_status3) "Invalid access."; 179 irq_ctx1_invalid 1 rw1c type(irq_ctx3_err_status3) "Invalid access."; 180 irq_ctx0_invalid 1 rw1c type(irq_ctx3_err_status3) "Invalid access."; 181 _ 4 mbz; 182 irq_ctx3_done 1 rw1c type(irq_ctx3_err_status3) "Context has been fully transferred to the TILER"; 183 irq_ctx2_done 1 rw1c type(irq_ctx3_err_status3) "Context has been fully transferred to the TILER"; 184 irq_ctx1_done 1 rw1c type(irq_ctx3_err_status3) "Context has been fully transferred to the TILER"; 185 irq_ctx0_done 1 rw1c type(irq_ctx3_err_status3) "Write mode: Context has been fully transferred to the TILER Read mode: Context prefetch has completed."; 186 _ 6 mbz; 187 irq_invalid 1 rw1c type(irq_ctx3_err_status3) "Invalid access to the virtual space"; 188 irq_ocp_err 1 rw1c type(irq_ctx3_err_status3) "OCP error received from OCP master port."; 189 }; 190 191 constants posted_status width(1) "" { 192 POSTED_0 = 0 "Use non posted writes"; 193 POSTED_1 = 1 "Use posted writes"; 194 }; 195 196 register bte_ctrl addr(base, 0x30) "BTE control register" { 197 bw_limiter 10 rw "Minimum number of OCP cycles between two consecutive buffer flushing or prefetch requests. Used to limit the bandwidth used to fill/empty buffers. 0: Maximum speed. Up to 1 request every 8 cycles (3.2GB @ 200 MHz) 1: Up to 1 request every 9 cycles. 1023: Minimum speed. Up to 1 request every 1031 cycles (24MB @ 200 MHz)"; 198 _ 10 mbz; 199 base 4 rw "Base address of the virtual space translated by the BTE. Start address = BASE*512MB End address = (BASE+1)*512MB - 1 For example: BASE=3 => 0x 0 6000 0000 - 0x 0 7FFF FFFF"; 200 _ 2 mbz; 201 posted 1 rw type(posted_status) "Select among posted and nonposted writes for translated requests."; 202 _ 1 mbz; 203 tag_cnt 4 rw "BTE could use up to TAG_CNT+1 tags on OCPO. There could only be one outstanding request per tag. TAG_CNT does not control the number of requests it could handle on OCPI. This register is internally shadowed. Modifications are taken into account when there are no outstanding transactions on OCPO. TAG ID 0 to TAG_CNT are used on OCPO."; 204 }; 205 206 register bte_ctrl1 addr(base, 0x34) "BTE control register" { 207 _ 25 mbz; 208 resp_fifo_thr 7 rw "The BTE stops accepting new requests from OCPI (on a clean burst boundary) when the response FIFO contains more than RESP_FIFO_THR words. The reset value is FIFO_SIZE - 16 - 1. FIFO_SIZE = 8 * 2"; 209 }; 210 211 constants autoflush_status width(1) "" { 212 AUTOFLUSH_0 = 0 "Disabled"; 213 AUTOFLUSH_1 = 1 "Enabled"; 214 }; 215 216 constants oneshot_status width(1) "" { 217 ONESHOT_0 = 0 "The context is automatically re-enabled when its end is reached."; 218 ONESHOT_1 = 1 "The context is disabled when the end of a frame has been reached."; 219 }; 220 221 constants grid_status width(2) "" { 222 GRID_0 = 0 "Stride = 16k Subtile = 4x4 bytes Tile = 32x32 bytes"; 223 GRID_1 = 1 "Stride = 8k Subtile = 4x4 bytes Tile = 32x32 bytes"; 224 GRID_3 = 3 "Stride = 16k Subtile = 8x2 bytes Tile = 64x16 bytes"; 225 GRID_2 = 2 "Stride = 32k Subtile = 8x2 bytes Tile = 64x16 bytes"; 226 }; 227 228 constants mode_status width(2) "" { 229 MODE_0 = 0 "Write translation"; 230 MODE_1 = 1 "Read translation"; 231 MODE_3 = 3 "reserved"; 232 MODE_2 = 2 "Direct access to local buffer"; 233 }; 234 235 constants flush_status width(1) "" { 236 FLUSH_0_w = 0 "No effect"; 237 FLUSH_1_w = 1 "Flush"; 238 }; 239 240 constants stop_status width(1) "" { 241 STOP_0_w = 0 "No effect"; 242 STOP_1_w = 1 "Stop the context"; 243 }; 244 245 constants start_status width(1) "" { 246 START_0_w = 0 "No effect"; 247 START_1_w = 1 "Reset + Enable"; 248 }; 249 250 register bte_context_ctrl_i_0 addr(base, 0x40) "Context control register" { 251 _ 2 mbz; 252 trigger 14 rw "Threshold used to trigger translated requests to OCPO. Unit: words or 16 bytes Valid range: 3 lines + 2 ... 4 lines WRITE: a 2D write is issued to OCPO when the internal buffer level (including masked accesses) is superior or equal to TRIGGER READ: a 2D read is issued to OCPO when the internal buffer level (including masked accesses) is inferior to TRIGGER."; 253 initsx 1 rw "Reset value to be used for SX__x. Check the section describing the local buffer management for details."; 254 initsy 2 rw "Reset value to be used for SY__x. Check the section describing the local buffer management for details. Must be 0 when ONESHOT = 0."; 255 addr32 1 rw "Controls the value of the OCP address bit 32 to be used for translated accesses"; 256 autoflush 1 rw type(autoflush_status) "Controls automatic context flushing when an IDLE request is received"; 257 oneshot 1 rw type(oneshot_status) "Selects one-shot or continuous mode"; 258 grid 2 rw type(grid_status) "Grid used to access the TILER"; 259 mode 2 rw type(mode_status) "Select the translation mode for the context"; 260 _ 3 mbz; 261 flush 1 wo type(flush_status) "Flushes all remaining data of the context to the TILER."; 262 stop 1 wo type(stop_status) "Stops the context on a clean OCP transaction boundary."; 263 start 1 wo type(start_status) "Resets the contexts internal state and enables the context on a clean OCP transaction boundary."; 264 }; 265 266 register bte_context_ctrl_i_1 addr(base, 0x60) "Context control register" { 267 _ 2 mbz; 268 trigger 14 rw "Threshold used to trigger translated requests to OCPO. Unit: words or 16 bytes Valid range: 3 lines + 2 ... 4 lines WRITE: a 2D write is issued to OCPO when the internal buffer level (including masked accesses) is superior or equal to TRIGGER READ: a 2D read is issued to OCPO when the internal buffer level (including masked accesses) is inferior to TRIGGER."; 269 initsx 1 rw "Reset value to be used for SX__x. Check the section describing the local buffer management for details."; 270 initsy 2 rw "Reset value to be used for SY__x. Check the section describing the local buffer management for details. Must be 0 when ONESHOT = 0."; 271 addr32 1 rw "Controls the value of the OCP address bit 32 to be used for translated accesses"; 272 autoflush 1 rw type(autoflush_status) "Controls automatic context flushing when an IDLE request is received"; 273 oneshot 1 rw type(grid_status) "Selects one-shot or continuous mode"; 274 grid 2 rw type(grid_status) "Grid used to access the TILER"; 275 mode 2 rw type(mode_status) "Select the translation mode for the context"; 276 _ 3 mbz; 277 flush 1 wo type(flush_status) "Flushes all remaining data of the context to the TILER."; 278 stop 1 wo type(stop_status) "Stops the context on a clean OCP transaction boundary."; 279 start 1 wo type(start_status) "Resets the contexts internal state and enables the context on a clean OCP transaction boundary."; 280 }; 281 282 register bte_context_ctrl_i_2 addr(base, 0x80) "Context control register" { 283 _ 2 mbz; 284 trigger 14 rw "Threshold used to trigger translated requests to OCPO. Unit: words or 16 bytes Valid range: 3 lines + 2 ... 4 lines WRITE: a 2D write is issued to OCPO when the internal buffer level (including masked accesses) is superior or equal to TRIGGER READ: a 2D read is issued to OCPO when the internal buffer level (including masked accesses) is inferior to TRIGGER."; 285 initsx 1 rw "Reset value to be used for SX__x. Check the section describing the local buffer management for details."; 286 initsy 2 rw "Reset value to be used for SY__x. Check the section describing the local buffer management for details. Must be 0 when ONESHOT = 0."; 287 addr32 1 rw "Controls the value of the OCP address bit 32 to be used for translated accesses"; 288 autoflush 1 rw type(autoflush_status) "Controls automatic context flushing when an IDLE request is received"; 289 oneshot 1 rw type(grid_status) "Selects one-shot or continuous mode"; 290 grid 2 rw type(grid_status) "Grid used to access the TILER"; 291 mode 2 rw type(mode_status) "Select the translation mode for the context"; 292 _ 3 mbz; 293 flush 1 wo type(flush_status) "Flushes all remaining data of the context to the TILER."; 294 stop 1 wo type(stop_status) "Stops the context on a clean OCP transaction boundary."; 295 start 1 wo type(start_status) "Resets the contexts internal state and enables the context on a clean OCP transaction boundary."; 296 }; 297 298 register bte_context_ctrl_i_3 addr(base, 0xA0) "Context control register" { 299 _ 2 mbz; 300 trigger 14 rw "Threshold used to trigger translated requests to OCPO. Unit: words or 16 bytes Valid range: 3 lines + 2 ... 4 lines WRITE: a 2D write is issued to OCPO when the internal buffer level (including masked accesses) is superior or equal to TRIGGER READ: a 2D read is issued to OCPO when the internal buffer level (including masked accesses) is inferior to TRIGGER."; 301 initsx 1 rw "Reset value to be used for SX__x. Check the section describing the local buffer management for details."; 302 initsy 2 rw "Reset value to be used for SY__x. Check the section describing the local buffer management for details. Must be 0 when ONESHOT = 0."; 303 addr32 1 rw "Controls the value of the OCP address bit 32 to be used for translated accesses"; 304 autoflush 1 rw type(autoflush_status) "Controls automatic context flushing when an IDLE request is received"; 305 oneshot 1 rw type(grid_status) "Selects one-shot or continuous mode"; 306 grid 2 rw type(grid_status) "Grid used to access the TILER"; 307 mode 2 rw type(mode_status) "Select the translation mode for the context"; 308 _ 3 mbz; 309 flush 1 wo type(flush_status) "Flushes all remaining data of the context to the TILER."; 310 stop 1 wo type(stop_status) "Stops the context on a clean OCP transaction boundary."; 311 start 1 wo type(start_status) "Resets the contexts internal state and enables the context on a clean OCP transaction boundary."; 312 }; 313 314 register bte_context_base_i_0 addr(base, 0x44) "Address of the frame buffer in the TILER address space." { 315 addr 27 rw "Address"; 316 _ 5 mbz; 317 }; 318 319 register bte_context_base_i_1 addr(base, 0x64) "Address of the frame buffer in the TILER address space." { 320 addr 27 rw "Address"; 321 _ 5 mbz; 322 }; 323 324 register bte_context_base_i_2 addr(base, 0x84) "Address of the frame buffer in the TILER address space." { 325 addr 27 rw "Address"; 326 _ 5 mbz; 327 }; 328 329 register bte_context_base_i_3 addr(base, 0xA4) "Address of the frame buffer in the TILER address space." { 330 addr 27 rw "Address"; 331 _ 5 mbz; 332 }; 333 334 register bte_context_start_i_0 addr(base, 0x48) "Top-left corner of the context." { 335 _ 16 mbz; 336 x 9 rw "Address, in 128-byte words"; 337 _ 7 mbz; 338 }; 339 340 register bte_context_start_i_1 addr(base, 0x68) "Top-left corner of the context." { 341 _ 16 mbz; 342 x 9 rw "Address, in 128-byte words"; 343 _ 7 mbz; 344 }; 345 346 register bte_context_start_i_2 addr(base, 0x88) "Top-left corner of the context." { 347 _ 16 mbz; 348 x 9 rw "Address, in 128-byte words"; 349 _ 7 mbz; 350 }; 351 352 register bte_context_start_i_3 addr(base, 0xA8) "Top-left corner of the context." { 353 _ 16 mbz; 354 x 9 rw "Address, in 128-byte words"; 355 _ 7 mbz; 356 }; 357 358 register bte_context_end_i_0 addr(base, 0x4C) "Bottom-right corner of the context." { 359 _ 3 mbz; 360 y 13 rw "Last line number for the context (0 corresponds to a context of 1 line) Must be 7 when ONESHOT = 0."; 361 x 12 rw "Address, in 128-bit words, of the last column of the context"; 362 _ 4 mbz; 363 }; 364 365 register bte_context_end_i_1 addr(base, 0x6C) "Bottom-right corner of the context." { 366 _ 3 mbz; 367 y 13 rw "Last line number for the context (0 corresponds to a context of 1 line) Must be 7 when ONESHOT = 0."; 368 x 12 rw "Address, in 128-bit words, of the last column of the context"; 369 _ 4 mbz; 370 }; 371 372 register bte_context_end_i_2 addr(base, 0x8C) "Bottom-right corner of the context." { 373 _ 3 mbz; 374 y 13 rw "Last line number for the context (0 corresponds to a context of 1 line) Must be 7 when ONESHOT = 0."; 375 x 12 rw "Address, in 128-bit words, of the last column of the context"; 376 _ 4 mbz; 377 }; 378 379 register bte_context_end_i_3 addr(base, 0xAC) "Bottom-right corner of the context." { 380 _ 3 mbz; 381 y 13 rw "Last line number for the context (0 corresponds to a context of 1 line) Must be 7 when ONESHOT = 0."; 382 x 12 rw "Address, in 128-bit words, of the last column of the context"; 383 _ 4 mbz; 384 }; 385};