1/*
2 * Copyright (c) 2007, 2008, ETH Zurich. All rights reserved.
3 *
4 * This file is distributed under the terms in the attached LICENSE file.
5 * If you do not find this file, copies can be found by writing to:
6 * ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group.
7 */
8
9/*
10 * hpet.dev
11 *
12 * DESCRIPTION: Intel 631xESB/632xESB I/O Controller Hub --
13 *              High-Precision Event Timer Registers
14 *
15 * This is derived from the "Intel 631xESB/632xESB IO/Controller Hub
16 * Datasheet", chapter 26, "High-Precision Event Timer Registers".
17 * See also, Intel's "IA-PC HPET (High Precision Event Timers)
18 * Specification", Revision 1.0a, October 2004. 
19 */
20
21device HPET lsbfirst ( addr base ) "High-Precision Event Timer" {
22    // 26.1.1
23    register gcap_id ro addr(base, 0x0) "General Capabilities and Identification" {
24	rev_id	   	      8	   "Revision Identification";
25	num_tim_cap	      5	   "Number of Timers";
26	count_size_cap	      1	   "Counter Size";
27	_		      1	   mbz;
28	leg_rt_cap	      1	   "Legacy Replacement Rout Capable";
29	vendor_id_cap	      16   "Vendor ID";
30	counter_clk_per_cap   32   "Main Counter Tick Period";
31    };
32    
33    // 26.1.2
34    register gen_conf rw addr(base, 0x10) "General Configuration" {
35	enable_cnf  1	       "Overall Enable";
36	leg_rt_cnf  1	       "Legacy Replacement Rout";
37	_	    62	       mbz;
38    };
39
40    // 26.1.3
41    register gintr_sta rw addr(base, 0x20) "General Interrupt Status" {
42	t00_int_sts  1		"Timer 0 interrupt active";
43	t01_int_sts  1		"Timer 1 interrupt active";
44	t02_int_sts  1		"Timer 2 interrupt active";
45	_	     61		mbz;
46    };
47
48    // 26.1.4
49    register main_cnt rw addr(base, 0xf0) "Main Counter Value" type(uint64);
50    
51    // 26.1.5
52    regtype tim_conf "Timer Configuration and Capabilities" {
53	_	       		     1      mbz;
54	timer_int_type_cnf	     1	    "Timer Interrupt Type";
55	timer_int_enb_cnf	     1	    "Timer Interrupt Enable";
56	timer_type_cnf		     1	    "Timer Type";
57	timer_per_int_cap	     1	    "Periodic Interrupt Capable";
58	timer_size_cap		     1	    "Timer Size";
59	timer_val_set_cnf	     1	    "Timer Value Set";
60	_			     1	    mbz;
61	timer_32mode_cnf	     1	    "Timer 32-bit mode";
62	timer_int_rout_cnf	     5	    "Interrupt Rout";
63	_			     29	    mbz;
64	timer2_int11_rout_cap	     1	    "Timer 2 IRQ 11 Rout Capability";
65	_			     8	    mbz;
66	timer_int_rout_cap	     4	    "Timer Interrupt Rout Capability";
67	_			     8	    mbz;
68    };
69    
70    register tim1_conf rw addr(base, 0x100) "Timer 0 Configuration and Capabilities" type(tim_conf);
71    register tim1_comp rw addr(base, 0x108) "Timer 0 Comparator Value" type(uint64);
72    
73    register tim2_conf rw addr(base, 0x120) "Timer 1 Configuration and Capabilities" type(tim_conf);
74    register tim2_comp rw addr(base, 0x128) "Timer 1 Comparator Value" type(uint64);
75    
76    register tim3_conf rw addr(base, 0x140) "Timer 2 Configuration and Capabilities" type(tim_conf);
77    register tim3_comp rw addr(base, 0x148) "Timer 2 Comparator Value" type(uint64);
78};
79