1/* 2 * Copyright (c) 2016, 2017 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetstr. 6, CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * armv8.dev 11 * 12 * DESCRIPTION: ARMv8 architecture definitions 13 * 14 * See: 15 * ARM Architecture Reference Manual 16 */ 17 18device armv8_cache_ctrl msbfirst () "ARMv8 Cache Control registers" { 19 20 space cache_ctrl(name) registerwise "Cache control register"; 21 22 register DC_CSIW wo cache_ctrl(cisw) "Data or unified Cache line Clean and Invalidate by Set/Way" { 23 _ 32 mbz; 24 SetWay 28 "Set and ways. depends on the cache settings"; 25 Level 3 "Cache level to operate on, minus 1."; 26 _ 1 mbz; 27 }; 28 29 register DC_CIVAC wo cache_ctrl(civac) "Data or unified Cache line Clean and Invalidate by VA to PoC" { 30 addr 64 "Virtual address to use."; 31 }; 32 33 register DC_CSW wo cache_ctrl(csw) "Data or unified Cache line Clean by Set/Way" { 34 _ 32 mbz; 35 SetWay 28 "Set and ways. depends on the cache settings"; 36 Level 3 "Cache level to operate on, minus 1."; 37 _ 1 mbz; 38 }; 39 40 register DC_CVAC wo cache_ctrl(cvac) "Data or unified Cache line Clean by VA to PoC" { 41 addr 64 "Virtual address to use."; 42 }; 43 44 register DC_CVAU wo cache_ctrl(cvau) "Data or unified Cache line Clean by VA to PoU" { 45 addr 64 "Virtual address to use."; 46 }; 47 48 register DC_ISW wo cache_ctrl(isw) "Data or unified Cache line Invalidate by Set/Way" { 49 _ 32 mbz; 50 SetWay 28 "Set and ways. depends on the cache settings"; 51 Level 3 "Cache level to operate on, minus 1."; 52 _ 1 mbz; 53 }; 54 55 register DC_IVAC wo cache_ctrl(ivac) "Data or unified Cache line Invalidate by VA to PoC" { 56 addr 64 "Virtual address to use."; 57 }; 58 59 register DC_ZVA wo cache_ctrl(zva) "Data or unified Cache line Invalidate by VA to PoC" { 60 addr 64 "Virtual address to use."; 61 }; 62}; 63