1#include "sim-main.h" 2#include "v850_sim.h" 3#include "simops.h" 4 5#include <sys/types.h> 6 7#ifdef HAVE_UTIME_H 8#include <utime.h> 9#endif 10 11#ifdef HAVE_TIME_H 12#include <time.h> 13#endif 14 15#ifdef HAVE_UNISTD_H 16#include <unistd.h> 17#endif 18 19#ifdef HAVE_STRING_H 20#include <string.h> 21#else 22#ifdef HAVE_STRINGS_H 23#include <strings.h> 24#endif 25#endif 26 27#include "targ-vals.h" 28 29#include "libiberty.h" 30 31#include <errno.h> 32#if !defined(__GO32__) && !defined(_WIN32) 33#include <sys/stat.h> 34#include <sys/times.h> 35#include <sys/time.h> 36#endif 37 38/* This is an array of the bit positions of registers r20 .. r31 in 39 that order in a prepare/dispose instruction. */ 40int type1_regs[12] = { 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 0, 21 }; 41/* This is an array of the bit positions of registers r16 .. r31 in 42 that order in a push/pop instruction. */ 43int type2_regs[16] = { 3, 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21}; 44/* This is an array of the bit positions of registers r1 .. r15 in 45 that order in a push/pop instruction. */ 46int type3_regs[15] = { 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21}; 47 48#ifdef DEBUG 49#ifndef SIZE_INSTRUCTION 50#define SIZE_INSTRUCTION 18 51#endif 52 53#ifndef SIZE_VALUES 54#define SIZE_VALUES 11 55#endif 56 57 58unsigned32 trace_values[3]; 59int trace_num_values; 60unsigned32 trace_pc; 61const char *trace_name; 62int trace_module; 63 64 65void 66trace_input (name, type, size) 67 char *name; 68 enum op_types type; 69 int size; 70{ 71 72 if (!TRACE_ALU_P (STATE_CPU (simulator, 0))) 73 return; 74 75 trace_pc = PC; 76 trace_name = name; 77 trace_module = TRACE_ALU_IDX; 78 79 switch (type) 80 { 81 default: 82 case OP_UNKNOWN: 83 case OP_NONE: 84 case OP_TRAP: 85 trace_num_values = 0; 86 break; 87 88 case OP_REG: 89 case OP_REG_REG_MOVE: 90 trace_values[0] = State.regs[OP[0]]; 91 trace_num_values = 1; 92 break; 93 94 case OP_BIT_CHANGE: 95 case OP_REG_REG: 96 case OP_REG_REG_CMP: 97 trace_values[0] = State.regs[OP[1]]; 98 trace_values[1] = State.regs[OP[0]]; 99 trace_num_values = 2; 100 break; 101 102 case OP_IMM_REG: 103 case OP_IMM_REG_CMP: 104 trace_values[0] = SEXT5 (OP[0]); 105 trace_values[1] = OP[1]; 106 trace_num_values = 2; 107 break; 108 109 case OP_IMM_REG_MOVE: 110 trace_values[0] = SEXT5 (OP[0]); 111 trace_num_values = 1; 112 break; 113 114 case OP_COND_BR: 115 trace_values[0] = State.pc; 116 trace_values[1] = SEXT9 (OP[0]); 117 trace_values[2] = PSW; 118 trace_num_values = 3; 119 break; 120 121 case OP_LOAD16: 122 trace_values[0] = OP[1] * size; 123 trace_values[1] = State.regs[30]; 124 trace_num_values = 2; 125 break; 126 127 case OP_STORE16: 128 trace_values[0] = State.regs[OP[0]]; 129 trace_values[1] = OP[1] * size; 130 trace_values[2] = State.regs[30]; 131 trace_num_values = 3; 132 break; 133 134 case OP_LOAD32: 135 trace_values[0] = EXTEND16 (OP[2]); 136 trace_values[1] = State.regs[OP[0]]; 137 trace_num_values = 2; 138 break; 139 140 case OP_STORE32: 141 trace_values[0] = State.regs[OP[1]]; 142 trace_values[1] = EXTEND16 (OP[2]); 143 trace_values[2] = State.regs[OP[0]]; 144 trace_num_values = 3; 145 break; 146 147 case OP_JUMP: 148 trace_values[0] = SEXT22 (OP[0]); 149 trace_values[1] = State.pc; 150 trace_num_values = 2; 151 break; 152 153 case OP_IMM_REG_REG: 154 trace_values[0] = EXTEND16 (OP[0]) << size; 155 trace_values[1] = State.regs[OP[1]]; 156 trace_num_values = 2; 157 break; 158 159 case OP_IMM16_REG_REG: 160 trace_values[0] = EXTEND16 (OP[2]) << size; 161 trace_values[1] = State.regs[OP[1]]; 162 trace_num_values = 2; 163 break; 164 165 case OP_UIMM_REG_REG: 166 trace_values[0] = (OP[0] & 0xffff) << size; 167 trace_values[1] = State.regs[OP[1]]; 168 trace_num_values = 2; 169 break; 170 171 case OP_UIMM16_REG_REG: 172 trace_values[0] = (OP[2]) << size; 173 trace_values[1] = State.regs[OP[1]]; 174 trace_num_values = 2; 175 break; 176 177 case OP_BIT: 178 trace_num_values = 0; 179 break; 180 181 case OP_EX1: 182 trace_values[0] = PSW; 183 trace_num_values = 1; 184 break; 185 186 case OP_EX2: 187 trace_num_values = 0; 188 break; 189 190 case OP_LDSR: 191 trace_values[0] = State.regs[OP[0]]; 192 trace_num_values = 1; 193 break; 194 195 case OP_STSR: 196 trace_values[0] = State.sregs[OP[1]]; 197 trace_num_values = 1; 198 } 199 200} 201 202void 203trace_result (int has_result, unsigned32 result) 204{ 205 char buf[1000]; 206 char *chp; 207 208 buf[0] = '\0'; 209 chp = buf; 210 211 /* write out the values saved during the trace_input call */ 212 { 213 int i; 214 for (i = 0; i < trace_num_values; i++) 215 { 216 sprintf (chp, "%*s0x%.8lx", SIZE_VALUES - 10, "", 217 (long) trace_values[i]); 218 chp = strchr (chp, '\0'); 219 } 220 while (i++ < 3) 221 { 222 sprintf (chp, "%*s", SIZE_VALUES, ""); 223 chp = strchr (chp, '\0'); 224 } 225 } 226 227 /* append any result to the end of the buffer */ 228 if (has_result) 229 sprintf (chp, " :: 0x%.8lx", (unsigned long)result); 230 231 trace_generic (simulator, STATE_CPU (simulator, 0), trace_module, buf); 232} 233 234void 235trace_output (result) 236 enum op_types result; 237{ 238 if (!TRACE_ALU_P (STATE_CPU (simulator, 0))) 239 return; 240 241 switch (result) 242 { 243 default: 244 case OP_UNKNOWN: 245 case OP_NONE: 246 case OP_TRAP: 247 case OP_REG: 248 case OP_REG_REG_CMP: 249 case OP_IMM_REG_CMP: 250 case OP_COND_BR: 251 case OP_STORE16: 252 case OP_STORE32: 253 case OP_BIT: 254 case OP_EX2: 255 trace_result (0, 0); 256 break; 257 258 case OP_LOAD16: 259 case OP_STSR: 260 trace_result (1, State.regs[OP[0]]); 261 break; 262 263 case OP_REG_REG: 264 case OP_REG_REG_MOVE: 265 case OP_IMM_REG: 266 case OP_IMM_REG_MOVE: 267 case OP_LOAD32: 268 case OP_EX1: 269 trace_result (1, State.regs[OP[1]]); 270 break; 271 272 case OP_IMM_REG_REG: 273 case OP_UIMM_REG_REG: 274 case OP_IMM16_REG_REG: 275 case OP_UIMM16_REG_REG: 276 trace_result (1, State.regs[OP[1]]); 277 break; 278 279 case OP_JUMP: 280 if (OP[1] != 0) 281 trace_result (1, State.regs[OP[1]]); 282 else 283 trace_result (0, 0); 284 break; 285 286 case OP_LDSR: 287 trace_result (1, State.sregs[OP[1]]); 288 break; 289 } 290} 291#endif 292 293 294/* Returns 1 if the specific condition is met, returns 0 otherwise. */ 295int 296condition_met (unsigned code) 297{ 298 unsigned int psw = PSW; 299 300 switch (code & 0xf) 301 { 302 case 0x0: return ((psw & PSW_OV) != 0); 303 case 0x1: return ((psw & PSW_CY) != 0); 304 case 0x2: return ((psw & PSW_Z) != 0); 305 case 0x3: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0); 306 case 0x4: return ((psw & PSW_S) != 0); 307 /*case 0x5: return 1;*/ 308 case 0x6: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0); 309 case 0x7: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) != 0); 310 case 0x8: return ((psw & PSW_OV) == 0); 311 case 0x9: return ((psw & PSW_CY) == 0); 312 case 0xa: return ((psw & PSW_Z) == 0); 313 case 0xb: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0); 314 case 0xc: return ((psw & PSW_S) == 0); 315 case 0xd: return ((psw & PSW_SAT) != 0); 316 case 0xe: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0); 317 case 0xf: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) == 0); 318 } 319 320 return 1; 321} 322 323static unsigned long 324Add32 (unsigned long a1, unsigned long a2, int * carry) 325{ 326 unsigned long result = (a1 + a2); 327 328 * carry = (result < a1); 329 330 return result; 331} 332 333static void 334Multiply64 (int sign, unsigned long op0) 335{ 336 unsigned long op1; 337 unsigned long lo; 338 unsigned long mid1; 339 unsigned long mid2; 340 unsigned long hi; 341 unsigned long RdLo; 342 unsigned long RdHi; 343 int carry; 344 345 op1 = State.regs[ OP[1] ]; 346 347 if (sign) 348 { 349 /* Compute sign of result and adjust operands if necessary. */ 350 351 sign = (op0 ^ op1) & 0x80000000; 352 353 if (((signed long) op0) < 0) 354 op0 = - op0; 355 356 if (((signed long) op1) < 0) 357 op1 = - op1; 358 } 359 360 /* We can split the 32x32 into four 16x16 operations. This ensures 361 that we do not lose precision on 32bit only hosts: */ 362 lo = ( (op0 & 0xFFFF) * (op1 & 0xFFFF)); 363 mid1 = ( (op0 & 0xFFFF) * ((op1 >> 16) & 0xFFFF)); 364 mid2 = (((op0 >> 16) & 0xFFFF) * (op1 & 0xFFFF)); 365 hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF)); 366 367 /* We now need to add all of these results together, taking care 368 to propogate the carries from the additions: */ 369 RdLo = Add32 (lo, (mid1 << 16), & carry); 370 RdHi = carry; 371 RdLo = Add32 (RdLo, (mid2 << 16), & carry); 372 RdHi += (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi); 373 374 if (sign) 375 { 376 /* Negate result if necessary. */ 377 378 RdLo = ~ RdLo; 379 RdHi = ~ RdHi; 380 if (RdLo == 0xFFFFFFFF) 381 { 382 RdLo = 0; 383 RdHi += 1; 384 } 385 else 386 RdLo += 1; 387 } 388 389 /* Don't store into register 0. */ 390 if (OP[1]) 391 State.regs[ OP[1] ] = RdLo; 392 if (OP[2] >> 11) 393 State.regs[ OP[2] >> 11 ] = RdHi; 394 395 return; 396} 397 398 399/* Read a null terminated string from memory, return in a buffer */ 400static char * 401fetch_str (sd, addr) 402 SIM_DESC sd; 403 address_word addr; 404{ 405 char *buf; 406 int nr = 0; 407 while (sim_core_read_1 (STATE_CPU (sd, 0), 408 PC, read_map, addr + nr) != 0) 409 nr++; 410 buf = NZALLOC (char, nr + 1); 411 sim_read (simulator, addr, buf, nr); 412 return buf; 413} 414 415/* Read a null terminated argument vector from memory, return in a 416 buffer */ 417static char ** 418fetch_argv (sd, addr) 419 SIM_DESC sd; 420 address_word addr; 421{ 422 int max_nr = 64; 423 int nr = 0; 424 char **buf = xmalloc (max_nr * sizeof (char*)); 425 while (1) 426 { 427 unsigned32 a = sim_core_read_4 (STATE_CPU (sd, 0), 428 PC, read_map, addr + nr * 4); 429 if (a == 0) break; 430 buf[nr] = fetch_str (sd, a); 431 nr ++; 432 if (nr == max_nr - 1) 433 { 434 max_nr += 50; 435 buf = xrealloc (buf, max_nr * sizeof (char*)); 436 } 437 } 438 buf[nr] = 0; 439 return buf; 440} 441 442 443/* sst.b */ 444int 445OP_380 () 446{ 447 trace_input ("sst.b", OP_STORE16, 1); 448 449 store_mem (State.regs[30] + (OP[3] & 0x7f), 1, State.regs[ OP[1] ]); 450 451 trace_output (OP_STORE16); 452 453 return 2; 454} 455 456/* sst.h */ 457int 458OP_480 () 459{ 460 trace_input ("sst.h", OP_STORE16, 2); 461 462 store_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 2, State.regs[ OP[1] ]); 463 464 trace_output (OP_STORE16); 465 466 return 2; 467} 468 469/* sst.w */ 470int 471OP_501 () 472{ 473 trace_input ("sst.w", OP_STORE16, 4); 474 475 store_mem (State.regs[30] + ((OP[3] & 0x7e) << 1), 4, State.regs[ OP[1] ]); 476 477 trace_output (OP_STORE16); 478 479 return 2; 480} 481 482/* ld.b */ 483int 484OP_700 () 485{ 486 int adr; 487 488 trace_input ("ld.b", OP_LOAD32, 1); 489 490 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]); 491 492 State.regs[ OP[1] ] = EXTEND8 (load_mem (adr, 1)); 493 494 trace_output (OP_LOAD32); 495 496 return 4; 497} 498 499/* ld.h */ 500int 501OP_720 () 502{ 503 int adr; 504 505 trace_input ("ld.h", OP_LOAD32, 2); 506 507 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]); 508 adr &= ~0x1; 509 510 State.regs[ OP[1] ] = EXTEND16 (load_mem (adr, 2)); 511 512 trace_output (OP_LOAD32); 513 514 return 4; 515} 516 517/* ld.w */ 518int 519OP_10720 () 520{ 521 int adr; 522 523 trace_input ("ld.w", OP_LOAD32, 4); 524 525 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1); 526 adr &= ~0x3; 527 528 State.regs[ OP[1] ] = load_mem (adr, 4); 529 530 trace_output (OP_LOAD32); 531 532 return 4; 533} 534 535/* st.b */ 536int 537OP_740 () 538{ 539 trace_input ("st.b", OP_STORE32, 1); 540 541 store_mem (State.regs[ OP[0] ] + EXTEND16 (OP[2]), 1, State.regs[ OP[1] ]); 542 543 trace_output (OP_STORE32); 544 545 return 4; 546} 547 548/* st.h */ 549int 550OP_760 () 551{ 552 int adr; 553 554 trace_input ("st.h", OP_STORE32, 2); 555 556 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]); 557 adr &= ~1; 558 559 store_mem (adr, 2, State.regs[ OP[1] ]); 560 561 trace_output (OP_STORE32); 562 563 return 4; 564} 565 566/* st.w */ 567int 568OP_10760 () 569{ 570 int adr; 571 572 trace_input ("st.w", OP_STORE32, 4); 573 574 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1); 575 adr &= ~3; 576 577 store_mem (adr, 4, State.regs[ OP[1] ]); 578 579 trace_output (OP_STORE32); 580 581 return 4; 582} 583 584/* add reg, reg */ 585int 586OP_1C0 () 587{ 588 unsigned int op0, op1, result, z, s, cy, ov; 589 590 trace_input ("add", OP_REG_REG, 0); 591 592 /* Compute the result. */ 593 594 op0 = State.regs[ OP[0] ]; 595 op1 = State.regs[ OP[1] ]; 596 597 result = op0 + op1; 598 599 /* Compute the condition codes. */ 600 z = (result == 0); 601 s = (result & 0x80000000); 602 cy = (result < op0 || result < op1); 603 ov = ((op0 & 0x80000000) == (op1 & 0x80000000) 604 && (op0 & 0x80000000) != (result & 0x80000000)); 605 606 /* Store the result and condition codes. */ 607 State.regs[OP[1]] = result; 608 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); 609 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 610 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); 611 trace_output (OP_REG_REG); 612 613 return 2; 614} 615 616/* add sign_extend(imm5), reg */ 617int 618OP_240 () 619{ 620 unsigned int op0, op1, result, z, s, cy, ov; 621 int temp; 622 623 trace_input ("add", OP_IMM_REG, 0); 624 625 /* Compute the result. */ 626 temp = SEXT5 (OP[0]); 627 op0 = temp; 628 op1 = State.regs[OP[1]]; 629 result = op0 + op1; 630 631 /* Compute the condition codes. */ 632 z = (result == 0); 633 s = (result & 0x80000000); 634 cy = (result < op0 || result < op1); 635 ov = ((op0 & 0x80000000) == (op1 & 0x80000000) 636 && (op0 & 0x80000000) != (result & 0x80000000)); 637 638 /* Store the result and condition codes. */ 639 State.regs[OP[1]] = result; 640 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); 641 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 642 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); 643 trace_output (OP_IMM_REG); 644 645 return 2; 646} 647 648/* addi sign_extend(imm16), reg, reg */ 649int 650OP_600 () 651{ 652 unsigned int op0, op1, result, z, s, cy, ov; 653 654 trace_input ("addi", OP_IMM16_REG_REG, 0); 655 656 /* Compute the result. */ 657 658 op0 = EXTEND16 (OP[2]); 659 op1 = State.regs[ OP[0] ]; 660 result = op0 + op1; 661 662 /* Compute the condition codes. */ 663 z = (result == 0); 664 s = (result & 0x80000000); 665 cy = (result < op0 || result < op1); 666 ov = ((op0 & 0x80000000) == (op1 & 0x80000000) 667 && (op0 & 0x80000000) != (result & 0x80000000)); 668 669 /* Store the result and condition codes. */ 670 State.regs[OP[1]] = result; 671 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); 672 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 673 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); 674 trace_output (OP_IMM16_REG_REG); 675 676 return 4; 677} 678 679/* sub reg1, reg2 */ 680int 681OP_1A0 () 682{ 683 unsigned int op0, op1, result, z, s, cy, ov; 684 685 trace_input ("sub", OP_REG_REG, 0); 686 /* Compute the result. */ 687 op0 = State.regs[ OP[0] ]; 688 op1 = State.regs[ OP[1] ]; 689 result = op1 - op0; 690 691 /* Compute the condition codes. */ 692 z = (result == 0); 693 s = (result & 0x80000000); 694 cy = (op1 < op0); 695 ov = ((op1 & 0x80000000) != (op0 & 0x80000000) 696 && (op1 & 0x80000000) != (result & 0x80000000)); 697 698 /* Store the result and condition codes. */ 699 State.regs[OP[1]] = result; 700 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); 701 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 702 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); 703 trace_output (OP_REG_REG); 704 705 return 2; 706} 707 708/* subr reg1, reg2 */ 709int 710OP_180 () 711{ 712 unsigned int op0, op1, result, z, s, cy, ov; 713 714 trace_input ("subr", OP_REG_REG, 0); 715 /* Compute the result. */ 716 op0 = State.regs[ OP[0] ]; 717 op1 = State.regs[ OP[1] ]; 718 result = op0 - op1; 719 720 /* Compute the condition codes. */ 721 z = (result == 0); 722 s = (result & 0x80000000); 723 cy = (op0 < op1); 724 ov = ((op0 & 0x80000000) != (op1 & 0x80000000) 725 && (op0 & 0x80000000) != (result & 0x80000000)); 726 727 /* Store the result and condition codes. */ 728 State.regs[OP[1]] = result; 729 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); 730 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 731 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); 732 trace_output (OP_REG_REG); 733 734 return 2; 735} 736 737/* sxh reg1 */ 738int 739OP_E0 () 740{ 741 trace_input ("mulh", OP_REG_REG, 0); 742 743 State.regs[ OP[1] ] = (EXTEND16 (State.regs[ OP[1] ]) * EXTEND16 (State.regs[ OP[0] ])); 744 745 trace_output (OP_REG_REG); 746 747 return 2; 748} 749 750/* mulh sign_extend(imm5), reg2 */ 751int 752OP_2E0 () 753{ 754 trace_input ("mulh", OP_IMM_REG, 0); 755 756 State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[1] ]) * SEXT5 (OP[0]); 757 758 trace_output (OP_IMM_REG); 759 760 return 2; 761} 762 763/* mulhi imm16, reg1, reg2 */ 764int 765OP_6E0 () 766{ 767 trace_input ("mulhi", OP_IMM16_REG_REG, 0); 768 769 State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[0] ]) * EXTEND16 (OP[2]); 770 771 trace_output (OP_IMM16_REG_REG); 772 773 return 4; 774} 775 776/* cmp reg, reg */ 777int 778OP_1E0 () 779{ 780 unsigned int op0, op1, result, z, s, cy, ov; 781 782 trace_input ("cmp", OP_REG_REG_CMP, 0); 783 /* Compute the result. */ 784 op0 = State.regs[ OP[0] ]; 785 op1 = State.regs[ OP[1] ]; 786 result = op1 - op0; 787 788 /* Compute the condition codes. */ 789 z = (result == 0); 790 s = (result & 0x80000000); 791 cy = (op1 < op0); 792 ov = ((op1 & 0x80000000) != (op0 & 0x80000000) 793 && (op1 & 0x80000000) != (result & 0x80000000)); 794 795 /* Set condition codes. */ 796 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); 797 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 798 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); 799 trace_output (OP_REG_REG_CMP); 800 801 return 2; 802} 803 804/* cmp sign_extend(imm5), reg */ 805int 806OP_260 () 807{ 808 unsigned int op0, op1, result, z, s, cy, ov; 809 int temp; 810 811 /* Compute the result. */ 812 trace_input ("cmp", OP_IMM_REG_CMP, 0); 813 temp = SEXT5 (OP[0]); 814 op0 = temp; 815 op1 = State.regs[OP[1]]; 816 result = op1 - op0; 817 818 /* Compute the condition codes. */ 819 z = (result == 0); 820 s = (result & 0x80000000); 821 cy = (op1 < op0); 822 ov = ((op1 & 0x80000000) != (op0 & 0x80000000) 823 && (op1 & 0x80000000) != (result & 0x80000000)); 824 825 /* Set condition codes. */ 826 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); 827 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 828 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); 829 trace_output (OP_IMM_REG_CMP); 830 831 return 2; 832} 833 834/* setf cccc,reg2 */ 835int 836OP_7E0 () 837{ 838 trace_input ("setf", OP_EX1, 0); 839 840 State.regs[ OP[1] ] = condition_met (OP[0]); 841 842 trace_output (OP_EX1); 843 844 return 4; 845} 846 847/* satadd reg,reg */ 848int 849OP_C0 () 850{ 851 unsigned int op0, op1, result, z, s, cy, ov, sat; 852 853 trace_input ("satadd", OP_REG_REG, 0); 854 /* Compute the result. */ 855 op0 = State.regs[ OP[0] ]; 856 op1 = State.regs[ OP[1] ]; 857 result = op0 + op1; 858 859 /* Compute the condition codes. */ 860 z = (result == 0); 861 s = (result & 0x80000000); 862 cy = (result < op0 || result < op1); 863 ov = ((op0 & 0x80000000) == (op1 & 0x80000000) 864 && (op0 & 0x80000000) != (result & 0x80000000)); 865 sat = ov; 866 867 /* Store the result and condition codes. */ 868 State.regs[OP[1]] = result; 869 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); 870 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 871 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0) 872 | (sat ? PSW_SAT : 0)); 873 874 /* Handle saturated results. */ 875 if (sat && s) 876 State.regs[OP[1]] = 0x80000000; 877 else if (sat) 878 State.regs[OP[1]] = 0x7fffffff; 879 trace_output (OP_REG_REG); 880 881 return 2; 882} 883 884/* satadd sign_extend(imm5), reg */ 885int 886OP_220 () 887{ 888 unsigned int op0, op1, result, z, s, cy, ov, sat; 889 890 int temp; 891 892 trace_input ("satadd", OP_IMM_REG, 0); 893 894 /* Compute the result. */ 895 temp = SEXT5 (OP[0]); 896 op0 = temp; 897 op1 = State.regs[OP[1]]; 898 result = op0 + op1; 899 900 /* Compute the condition codes. */ 901 z = (result == 0); 902 s = (result & 0x80000000); 903 cy = (result < op0 || result < op1); 904 ov = ((op0 & 0x80000000) == (op1 & 0x80000000) 905 && (op0 & 0x80000000) != (result & 0x80000000)); 906 sat = ov; 907 908 /* Store the result and condition codes. */ 909 State.regs[OP[1]] = result; 910 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); 911 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 912 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0) 913 | (sat ? PSW_SAT : 0)); 914 915 /* Handle saturated results. */ 916 if (sat && s) 917 State.regs[OP[1]] = 0x80000000; 918 else if (sat) 919 State.regs[OP[1]] = 0x7fffffff; 920 trace_output (OP_IMM_REG); 921 922 return 2; 923} 924 925/* satsub reg1, reg2 */ 926int 927OP_A0 () 928{ 929 unsigned int op0, op1, result, z, s, cy, ov, sat; 930 931 trace_input ("satsub", OP_REG_REG, 0); 932 933 /* Compute the result. */ 934 op0 = State.regs[ OP[0] ]; 935 op1 = State.regs[ OP[1] ]; 936 result = op1 - op0; 937 938 /* Compute the condition codes. */ 939 z = (result == 0); 940 s = (result & 0x80000000); 941 cy = (op1 < op0); 942 ov = ((op1 & 0x80000000) != (op0 & 0x80000000) 943 && (op1 & 0x80000000) != (result & 0x80000000)); 944 sat = ov; 945 946 /* Store the result and condition codes. */ 947 State.regs[OP[1]] = result; 948 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); 949 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 950 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0) 951 | (sat ? PSW_SAT : 0)); 952 953 /* Handle saturated results. */ 954 if (sat && s) 955 State.regs[OP[1]] = 0x80000000; 956 else if (sat) 957 State.regs[OP[1]] = 0x7fffffff; 958 trace_output (OP_REG_REG); 959 return 2; 960} 961 962/* satsubi sign_extend(imm16), reg */ 963int 964OP_660 () 965{ 966 unsigned int op0, op1, result, z, s, cy, ov, sat; 967 int temp; 968 969 trace_input ("satsubi", OP_IMM_REG, 0); 970 971 /* Compute the result. */ 972 temp = EXTEND16 (OP[2]); 973 op0 = temp; 974 op1 = State.regs[ OP[0] ]; 975 result = op1 - op0; 976 977 /* Compute the condition codes. */ 978 z = (result == 0); 979 s = (result & 0x80000000); 980 cy = (op1 < op0); 981 ov = ((op1 & 0x80000000) != (op0 & 0x80000000) 982 && (op1 & 0x80000000) != (result & 0x80000000)); 983 sat = ov; 984 985 /* Store the result and condition codes. */ 986 State.regs[OP[1]] = result; 987 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); 988 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 989 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0) 990 | (sat ? PSW_SAT : 0)); 991 992 /* Handle saturated results. */ 993 if (sat && s) 994 State.regs[OP[1]] = 0x80000000; 995 else if (sat) 996 State.regs[OP[1]] = 0x7fffffff; 997 trace_output (OP_IMM_REG); 998 999 return 4; 1000} 1001 1002/* satsubr reg,reg */ 1003int 1004OP_80 () 1005{ 1006 unsigned int op0, op1, result, z, s, cy, ov, sat; 1007 1008 trace_input ("satsubr", OP_REG_REG, 0); 1009 1010 /* Compute the result. */ 1011 op0 = State.regs[ OP[0] ]; 1012 op1 = State.regs[ OP[1] ]; 1013 result = op0 - op1; 1014 1015 /* Compute the condition codes. */ 1016 z = (result == 0); 1017 s = (result & 0x80000000); 1018 cy = (result < op0); 1019 ov = ((op1 & 0x80000000) != (op0 & 0x80000000) 1020 && (op1 & 0x80000000) != (result & 0x80000000)); 1021 sat = ov; 1022 1023 /* Store the result and condition codes. */ 1024 State.regs[OP[1]] = result; 1025 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); 1026 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 1027 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0) 1028 | (sat ? PSW_SAT : 0)); 1029 1030 /* Handle saturated results. */ 1031 if (sat && s) 1032 State.regs[OP[1]] = 0x80000000; 1033 else if (sat) 1034 State.regs[OP[1]] = 0x7fffffff; 1035 trace_output (OP_REG_REG); 1036 1037 return 2; 1038} 1039 1040/* tst reg,reg */ 1041int 1042OP_160 () 1043{ 1044 unsigned int op0, op1, result, z, s; 1045 1046 trace_input ("tst", OP_REG_REG_CMP, 0); 1047 1048 /* Compute the result. */ 1049 op0 = State.regs[ OP[0] ]; 1050 op1 = State.regs[ OP[1] ]; 1051 result = op0 & op1; 1052 1053 /* Compute the condition codes. */ 1054 z = (result == 0); 1055 s = (result & 0x80000000); 1056 1057 /* Store the condition codes. */ 1058 PSW &= ~(PSW_Z | PSW_S | PSW_OV); 1059 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); 1060 trace_output (OP_REG_REG_CMP); 1061 1062 return 2; 1063} 1064 1065/* mov sign_extend(imm5), reg */ 1066int 1067OP_200 () 1068{ 1069 int value = SEXT5 (OP[0]); 1070 1071 trace_input ("mov", OP_IMM_REG_MOVE, 0); 1072 1073 State.regs[ OP[1] ] = value; 1074 1075 trace_output (OP_IMM_REG_MOVE); 1076 1077 return 2; 1078} 1079 1080/* movhi imm16, reg, reg */ 1081int 1082OP_640 () 1083{ 1084 trace_input ("movhi", OP_UIMM16_REG_REG, 16); 1085 1086 State.regs[ OP[1] ] = State.regs[ OP[0] ] + (OP[2] << 16); 1087 1088 trace_output (OP_UIMM16_REG_REG); 1089 1090 return 4; 1091} 1092 1093/* sar zero_extend(imm5),reg1 */ 1094int 1095OP_2A0 () 1096{ 1097 unsigned int op0, op1, result, z, s, cy; 1098 1099 trace_input ("sar", OP_IMM_REG, 0); 1100 op0 = OP[0]; 1101 op1 = State.regs[ OP[1] ]; 1102 result = (signed)op1 >> op0; 1103 1104 /* Compute the condition codes. */ 1105 z = (result == 0); 1106 s = (result & 0x80000000); 1107 cy = (op1 & (1 << (op0 - 1))); 1108 1109 /* Store the result and condition codes. */ 1110 State.regs[ OP[1] ] = result; 1111 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); 1112 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 1113 | (cy ? PSW_CY : 0)); 1114 trace_output (OP_IMM_REG); 1115 1116 return 2; 1117} 1118 1119/* sar reg1, reg2 */ 1120int 1121OP_A007E0 () 1122{ 1123 unsigned int op0, op1, result, z, s, cy; 1124 1125 trace_input ("sar", OP_REG_REG, 0); 1126 1127 op0 = State.regs[ OP[0] ] & 0x1f; 1128 op1 = State.regs[ OP[1] ]; 1129 result = (signed)op1 >> op0; 1130 1131 /* Compute the condition codes. */ 1132 z = (result == 0); 1133 s = (result & 0x80000000); 1134 cy = (op1 & (1 << (op0 - 1))); 1135 1136 /* Store the result and condition codes. */ 1137 State.regs[OP[1]] = result; 1138 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); 1139 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 1140 | (cy ? PSW_CY : 0)); 1141 trace_output (OP_REG_REG); 1142 1143 return 4; 1144} 1145 1146/* shl zero_extend(imm5),reg1 */ 1147int 1148OP_2C0 () 1149{ 1150 unsigned int op0, op1, result, z, s, cy; 1151 1152 trace_input ("shl", OP_IMM_REG, 0); 1153 op0 = OP[0]; 1154 op1 = State.regs[ OP[1] ]; 1155 result = op1 << op0; 1156 1157 /* Compute the condition codes. */ 1158 z = (result == 0); 1159 s = (result & 0x80000000); 1160 cy = (op1 & (1 << (32 - op0))); 1161 1162 /* Store the result and condition codes. */ 1163 State.regs[OP[1]] = result; 1164 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); 1165 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 1166 | (cy ? PSW_CY : 0)); 1167 trace_output (OP_IMM_REG); 1168 1169 return 2; 1170} 1171 1172/* shl reg1, reg2 */ 1173int 1174OP_C007E0 () 1175{ 1176 unsigned int op0, op1, result, z, s, cy; 1177 1178 trace_input ("shl", OP_REG_REG, 0); 1179 op0 = State.regs[ OP[0] ] & 0x1f; 1180 op1 = State.regs[ OP[1] ]; 1181 result = op1 << op0; 1182 1183 /* Compute the condition codes. */ 1184 z = (result == 0); 1185 s = (result & 0x80000000); 1186 cy = (op1 & (1 << (32 - op0))); 1187 1188 /* Store the result and condition codes. */ 1189 State.regs[OP[1]] = result; 1190 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); 1191 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 1192 | (cy ? PSW_CY : 0)); 1193 trace_output (OP_REG_REG); 1194 1195 return 4; 1196} 1197 1198/* shr zero_extend(imm5),reg1 */ 1199int 1200OP_280 () 1201{ 1202 unsigned int op0, op1, result, z, s, cy; 1203 1204 trace_input ("shr", OP_IMM_REG, 0); 1205 op0 = OP[0]; 1206 op1 = State.regs[ OP[1] ]; 1207 result = op1 >> op0; 1208 1209 /* Compute the condition codes. */ 1210 z = (result == 0); 1211 s = (result & 0x80000000); 1212 cy = (op1 & (1 << (op0 - 1))); 1213 1214 /* Store the result and condition codes. */ 1215 State.regs[OP[1]] = result; 1216 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); 1217 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 1218 | (cy ? PSW_CY : 0)); 1219 trace_output (OP_IMM_REG); 1220 1221 return 2; 1222} 1223 1224/* shr reg1, reg2 */ 1225int 1226OP_8007E0 () 1227{ 1228 unsigned int op0, op1, result, z, s, cy; 1229 1230 trace_input ("shr", OP_REG_REG, 0); 1231 op0 = State.regs[ OP[0] ] & 0x1f; 1232 op1 = State.regs[ OP[1] ]; 1233 result = op1 >> op0; 1234 1235 /* Compute the condition codes. */ 1236 z = (result == 0); 1237 s = (result & 0x80000000); 1238 cy = (op1 & (1 << (op0 - 1))); 1239 1240 /* Store the result and condition codes. */ 1241 State.regs[OP[1]] = result; 1242 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); 1243 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) 1244 | (cy ? PSW_CY : 0)); 1245 trace_output (OP_REG_REG); 1246 1247 return 4; 1248} 1249 1250/* or reg, reg */ 1251int 1252OP_100 () 1253{ 1254 unsigned int op0, op1, result, z, s; 1255 1256 trace_input ("or", OP_REG_REG, 0); 1257 1258 /* Compute the result. */ 1259 op0 = State.regs[ OP[0] ]; 1260 op1 = State.regs[ OP[1] ]; 1261 result = op0 | op1; 1262 1263 /* Compute the condition codes. */ 1264 z = (result == 0); 1265 s = (result & 0x80000000); 1266 1267 /* Store the result and condition codes. */ 1268 State.regs[OP[1]] = result; 1269 PSW &= ~(PSW_Z | PSW_S | PSW_OV); 1270 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); 1271 trace_output (OP_REG_REG); 1272 1273 return 2; 1274} 1275 1276/* ori zero_extend(imm16), reg, reg */ 1277int 1278OP_680 () 1279{ 1280 unsigned int op0, op1, result, z, s; 1281 1282 trace_input ("ori", OP_UIMM16_REG_REG, 0); 1283 op0 = OP[2]; 1284 op1 = State.regs[ OP[0] ]; 1285 result = op0 | op1; 1286 1287 /* Compute the condition codes. */ 1288 z = (result == 0); 1289 s = (result & 0x80000000); 1290 1291 /* Store the result and condition codes. */ 1292 State.regs[OP[1]] = result; 1293 PSW &= ~(PSW_Z | PSW_S | PSW_OV); 1294 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); 1295 trace_output (OP_UIMM16_REG_REG); 1296 1297 return 4; 1298} 1299 1300/* and reg, reg */ 1301int 1302OP_140 () 1303{ 1304 unsigned int op0, op1, result, z, s; 1305 1306 trace_input ("and", OP_REG_REG, 0); 1307 1308 /* Compute the result. */ 1309 op0 = State.regs[ OP[0] ]; 1310 op1 = State.regs[ OP[1] ]; 1311 result = op0 & op1; 1312 1313 /* Compute the condition codes. */ 1314 z = (result == 0); 1315 s = (result & 0x80000000); 1316 1317 /* Store the result and condition codes. */ 1318 State.regs[OP[1]] = result; 1319 PSW &= ~(PSW_Z | PSW_S | PSW_OV); 1320 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); 1321 trace_output (OP_REG_REG); 1322 1323 return 2; 1324} 1325 1326/* andi zero_extend(imm16), reg, reg */ 1327int 1328OP_6C0 () 1329{ 1330 unsigned int result, z; 1331 1332 trace_input ("andi", OP_UIMM16_REG_REG, 0); 1333 1334 result = OP[2] & State.regs[ OP[0] ]; 1335 1336 /* Compute the condition codes. */ 1337 z = (result == 0); 1338 1339 /* Store the result and condition codes. */ 1340 State.regs[ OP[1] ] = result; 1341 1342 PSW &= ~(PSW_Z | PSW_S | PSW_OV); 1343 PSW |= (z ? PSW_Z : 0); 1344 1345 trace_output (OP_UIMM16_REG_REG); 1346 1347 return 4; 1348} 1349 1350/* xor reg, reg */ 1351int 1352OP_120 () 1353{ 1354 unsigned int op0, op1, result, z, s; 1355 1356 trace_input ("xor", OP_REG_REG, 0); 1357 1358 /* Compute the result. */ 1359 op0 = State.regs[ OP[0] ]; 1360 op1 = State.regs[ OP[1] ]; 1361 result = op0 ^ op1; 1362 1363 /* Compute the condition codes. */ 1364 z = (result == 0); 1365 s = (result & 0x80000000); 1366 1367 /* Store the result and condition codes. */ 1368 State.regs[OP[1]] = result; 1369 PSW &= ~(PSW_Z | PSW_S | PSW_OV); 1370 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); 1371 trace_output (OP_REG_REG); 1372 1373 return 2; 1374} 1375 1376/* xori zero_extend(imm16), reg, reg */ 1377int 1378OP_6A0 () 1379{ 1380 unsigned int op0, op1, result, z, s; 1381 1382 trace_input ("xori", OP_UIMM16_REG_REG, 0); 1383 op0 = OP[2]; 1384 op1 = State.regs[ OP[0] ]; 1385 result = op0 ^ op1; 1386 1387 /* Compute the condition codes. */ 1388 z = (result == 0); 1389 s = (result & 0x80000000); 1390 1391 /* Store the result and condition codes. */ 1392 State.regs[OP[1]] = result; 1393 PSW &= ~(PSW_Z | PSW_S | PSW_OV); 1394 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); 1395 trace_output (OP_UIMM16_REG_REG); 1396 1397 return 4; 1398} 1399 1400/* not reg1, reg2 */ 1401int 1402OP_20 () 1403{ 1404 unsigned int op0, result, z, s; 1405 1406 trace_input ("not", OP_REG_REG_MOVE, 0); 1407 /* Compute the result. */ 1408 op0 = State.regs[ OP[0] ]; 1409 result = ~op0; 1410 1411 /* Compute the condition codes. */ 1412 z = (result == 0); 1413 s = (result & 0x80000000); 1414 1415 /* Store the result and condition codes. */ 1416 State.regs[OP[1]] = result; 1417 PSW &= ~(PSW_Z | PSW_S | PSW_OV); 1418 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); 1419 trace_output (OP_REG_REG_MOVE); 1420 1421 return 2; 1422} 1423 1424/* set1 */ 1425int 1426OP_7C0 () 1427{ 1428 unsigned int op0, op1, op2; 1429 int temp; 1430 1431 trace_input ("set1", OP_BIT, 0); 1432 op0 = State.regs[ OP[0] ]; 1433 op1 = OP[1] & 0x7; 1434 temp = EXTEND16 (OP[2]); 1435 op2 = temp; 1436 temp = load_mem (op0 + op2, 1); 1437 PSW &= ~PSW_Z; 1438 if ((temp & (1 << op1)) == 0) 1439 PSW |= PSW_Z; 1440 temp |= (1 << op1); 1441 store_mem (op0 + op2, 1, temp); 1442 trace_output (OP_BIT); 1443 1444 return 4; 1445} 1446 1447/* not1 */ 1448int 1449OP_47C0 () 1450{ 1451 unsigned int op0, op1, op2; 1452 int temp; 1453 1454 trace_input ("not1", OP_BIT, 0); 1455 op0 = State.regs[ OP[0] ]; 1456 op1 = OP[1] & 0x7; 1457 temp = EXTEND16 (OP[2]); 1458 op2 = temp; 1459 temp = load_mem (op0 + op2, 1); 1460 PSW &= ~PSW_Z; 1461 if ((temp & (1 << op1)) == 0) 1462 PSW |= PSW_Z; 1463 temp ^= (1 << op1); 1464 store_mem (op0 + op2, 1, temp); 1465 trace_output (OP_BIT); 1466 1467 return 4; 1468} 1469 1470/* clr1 */ 1471int 1472OP_87C0 () 1473{ 1474 unsigned int op0, op1, op2; 1475 int temp; 1476 1477 trace_input ("clr1", OP_BIT, 0); 1478 op0 = State.regs[ OP[0] ]; 1479 op1 = OP[1] & 0x7; 1480 temp = EXTEND16 (OP[2]); 1481 op2 = temp; 1482 temp = load_mem (op0 + op2, 1); 1483 PSW &= ~PSW_Z; 1484 if ((temp & (1 << op1)) == 0) 1485 PSW |= PSW_Z; 1486 temp &= ~(1 << op1); 1487 store_mem (op0 + op2, 1, temp); 1488 trace_output (OP_BIT); 1489 1490 return 4; 1491} 1492 1493/* tst1 */ 1494int 1495OP_C7C0 () 1496{ 1497 unsigned int op0, op1, op2; 1498 int temp; 1499 1500 trace_input ("tst1", OP_BIT, 0); 1501 op0 = State.regs[ OP[0] ]; 1502 op1 = OP[1] & 0x7; 1503 temp = EXTEND16 (OP[2]); 1504 op2 = temp; 1505 temp = load_mem (op0 + op2, 1); 1506 PSW &= ~PSW_Z; 1507 if ((temp & (1 << op1)) == 0) 1508 PSW |= PSW_Z; 1509 trace_output (OP_BIT); 1510 1511 return 4; 1512} 1513 1514/* di */ 1515int 1516OP_16007E0 () 1517{ 1518 trace_input ("di", OP_NONE, 0); 1519 PSW |= PSW_ID; 1520 trace_output (OP_NONE); 1521 1522 return 4; 1523} 1524 1525/* ei */ 1526int 1527OP_16087E0 () 1528{ 1529 trace_input ("ei", OP_NONE, 0); 1530 PSW &= ~PSW_ID; 1531 trace_output (OP_NONE); 1532 1533 return 4; 1534} 1535 1536/* halt */ 1537int 1538OP_12007E0 () 1539{ 1540 trace_input ("halt", OP_NONE, 0); 1541 /* FIXME this should put processor into a mode where NMI still handled */ 1542 trace_output (OP_NONE); 1543 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC, 1544 sim_stopped, SIM_SIGTRAP); 1545 return 0; 1546} 1547 1548/* trap */ 1549int 1550OP_10007E0 () 1551{ 1552 trace_input ("trap", OP_TRAP, 0); 1553 trace_output (OP_TRAP); 1554 1555 /* Trap 31 is used for simulating OS I/O functions */ 1556 1557 if (OP[0] == 31) 1558 { 1559 int save_errno = errno; 1560 errno = 0; 1561 1562/* Registers passed to trap 0 */ 1563 1564#define FUNC State.regs[6] /* function number, return value */ 1565#define PARM1 State.regs[7] /* optional parm 1 */ 1566#define PARM2 State.regs[8] /* optional parm 2 */ 1567#define PARM3 State.regs[9] /* optional parm 3 */ 1568 1569/* Registers set by trap 0 */ 1570 1571#define RETVAL State.regs[10] /* return value */ 1572#define RETERR State.regs[11] /* return error code */ 1573 1574/* Turn a pointer in a register into a pointer into real memory. */ 1575 1576#define MEMPTR(x) (map (x)) 1577 1578 switch (FUNC) 1579 { 1580 1581#ifdef HAVE_FORK 1582#ifdef TARGET_SYS_fork 1583 case TARGET_SYS_fork: 1584 RETVAL = fork (); 1585 break; 1586#endif 1587#endif 1588 1589#ifdef HAVE_EXECVE 1590#ifdef TARGET_SYS_execv 1591 case TARGET_SYS_execve: 1592 { 1593 char *path = fetch_str (simulator, PARM1); 1594 char **argv = fetch_argv (simulator, PARM2); 1595 char **envp = fetch_argv (simulator, PARM3); 1596 RETVAL = execve (path, argv, envp); 1597 zfree (path); 1598 freeargv (argv); 1599 freeargv (envp); 1600 break; 1601 } 1602#endif 1603#endif 1604 1605#if HAVE_EXECV 1606#ifdef TARGET_SYS_execv 1607 case TARGET_SYS_execv: 1608 { 1609 char *path = fetch_str (simulator, PARM1); 1610 char **argv = fetch_argv (simulator, PARM2); 1611 RETVAL = execv (path, argv); 1612 zfree (path); 1613 freeargv (argv); 1614 break; 1615 } 1616#endif 1617#endif 1618 1619#if 0 1620#ifdef TARGET_SYS_pipe 1621 case TARGET_SYS_pipe: 1622 { 1623 reg_t buf; 1624 int host_fd[2]; 1625 1626 buf = PARM1; 1627 RETVAL = pipe (host_fd); 1628 SW (buf, host_fd[0]); 1629 buf += sizeof(uint16); 1630 SW (buf, host_fd[1]); 1631 } 1632 break; 1633#endif 1634#endif 1635 1636#if 0 1637#ifdef TARGET_SYS_wait 1638 case TARGET_SYS_wait: 1639 { 1640 int status; 1641 1642 RETVAL = wait (&status); 1643 SW (PARM1, status); 1644 } 1645 break; 1646#endif 1647#endif 1648 1649#ifdef TARGET_SYS_read 1650 case TARGET_SYS_read: 1651 { 1652 char *buf = zalloc (PARM3); 1653 RETVAL = sim_io_read (simulator, PARM1, buf, PARM3); 1654 sim_write (simulator, PARM2, buf, PARM3); 1655 zfree (buf); 1656 break; 1657 } 1658#endif 1659 1660#ifdef TARGET_SYS_write 1661 case TARGET_SYS_write: 1662 { 1663 char *buf = zalloc (PARM3); 1664 sim_read (simulator, PARM2, buf, PARM3); 1665 if (PARM1 == 1) 1666 RETVAL = sim_io_write_stdout (simulator, buf, PARM3); 1667 else 1668 RETVAL = sim_io_write (simulator, PARM1, buf, PARM3); 1669 zfree (buf); 1670 break; 1671 } 1672#endif 1673 1674#ifdef TARGET_SYS_lseek 1675 case TARGET_SYS_lseek: 1676 RETVAL = sim_io_lseek (simulator, PARM1, PARM2, PARM3); 1677 break; 1678#endif 1679 1680#ifdef TARGET_SYS_close 1681 case TARGET_SYS_close: 1682 RETVAL = sim_io_close (simulator, PARM1); 1683 break; 1684#endif 1685 1686#ifdef TARGET_SYS_open 1687 case TARGET_SYS_open: 1688 { 1689 char *buf = fetch_str (simulator, PARM1); 1690 RETVAL = sim_io_open (simulator, buf, PARM2); 1691 zfree (buf); 1692 break; 1693 } 1694#endif 1695 1696#ifdef TARGET_SYS_exit 1697 case TARGET_SYS_exit: 1698 if ((PARM1 & 0xffff0000) == 0xdead0000 && (PARM1 & 0xffff) != 0) 1699 /* get signal encoded by kill */ 1700 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC, 1701 sim_signalled, PARM1 & 0xffff); 1702 else if (PARM1 == 0xdead) 1703 /* old libraries */ 1704 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC, 1705 sim_stopped, SIM_SIGABRT); 1706 else 1707 /* PARM1 has exit status */ 1708 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC, 1709 sim_exited, PARM1); 1710 break; 1711#endif 1712 1713#if !defined(__GO32__) && !defined(_WIN32) 1714#ifdef TARGET_SYS_stat 1715 case TARGET_SYS_stat: /* added at hmsi */ 1716 /* stat system call */ 1717 { 1718 struct stat host_stat; 1719 reg_t buf; 1720 char *path = fetch_str (simulator, PARM1); 1721 1722 RETVAL = stat (path, &host_stat); 1723 1724 zfree (path); 1725 buf = PARM2; 1726 1727 /* Just wild-assed guesses. */ 1728 store_mem (buf, 2, host_stat.st_dev); 1729 store_mem (buf + 2, 2, host_stat.st_ino); 1730 store_mem (buf + 4, 4, host_stat.st_mode); 1731 store_mem (buf + 8, 2, host_stat.st_nlink); 1732 store_mem (buf + 10, 2, host_stat.st_uid); 1733 store_mem (buf + 12, 2, host_stat.st_gid); 1734 store_mem (buf + 14, 2, host_stat.st_rdev); 1735 store_mem (buf + 16, 4, host_stat.st_size); 1736 store_mem (buf + 20, 4, host_stat.st_atime); 1737 store_mem (buf + 28, 4, host_stat.st_mtime); 1738 store_mem (buf + 36, 4, host_stat.st_ctime); 1739 } 1740 break; 1741#endif 1742#endif 1743 1744#ifdef HAVE_CHOWN 1745#ifdef TARGET_SYS_chown 1746 case TARGET_SYS_chown: 1747 { 1748 char *path = fetch_str (simulator, PARM1); 1749 RETVAL = chown (path, PARM2, PARM3); 1750 zfree (path); 1751 } 1752 break; 1753#endif 1754#endif 1755 1756#if HAVE_CHMOD 1757#ifdef TARGET_SYS_chmod 1758 case TARGET_SYS_chmod: 1759 { 1760 char *path = fetch_str (simulator, PARM1); 1761 RETVAL = chmod (path, PARM2); 1762 zfree (path); 1763 } 1764 break; 1765#endif 1766#endif 1767 1768#ifdef TARGET_SYS_time 1769#if HAVE_TIME 1770 case TARGET_SYS_time: 1771 { 1772 time_t now; 1773 RETVAL = time (&now); 1774 store_mem (PARM1, 4, now); 1775 } 1776 break; 1777#endif 1778#endif 1779 1780#if !defined(__GO32__) && !defined(_WIN32) 1781#ifdef TARGET_SYS_times 1782 case TARGET_SYS_times: 1783 { 1784 struct tms tms; 1785 RETVAL = times (&tms); 1786 store_mem (PARM1, 4, tms.tms_utime); 1787 store_mem (PARM1 + 4, 4, tms.tms_stime); 1788 store_mem (PARM1 + 8, 4, tms.tms_cutime); 1789 store_mem (PARM1 + 12, 4, tms.tms_cstime); 1790 break; 1791 } 1792#endif 1793#endif 1794 1795#ifdef TARGET_SYS_gettimeofday 1796#if !defined(__GO32__) && !defined(_WIN32) 1797 case TARGET_SYS_gettimeofday: 1798 { 1799 struct timeval t; 1800 struct timezone tz; 1801 RETVAL = gettimeofday (&t, &tz); 1802 store_mem (PARM1, 4, t.tv_sec); 1803 store_mem (PARM1 + 4, 4, t.tv_usec); 1804 store_mem (PARM2, 4, tz.tz_minuteswest); 1805 store_mem (PARM2 + 4, 4, tz.tz_dsttime); 1806 break; 1807 } 1808#endif 1809#endif 1810 1811#ifdef TARGET_SYS_utime 1812#if HAVE_UTIME 1813 case TARGET_SYS_utime: 1814 { 1815 /* Cast the second argument to void *, to avoid type mismatch 1816 if a prototype is present. */ 1817 sim_io_error (simulator, "Utime not supported"); 1818 /* RETVAL = utime (path, (void *) MEMPTR (PARM2)); */ 1819 } 1820 break; 1821#endif 1822#endif 1823 1824 default: 1825 abort (); 1826 } 1827 RETERR = errno; 1828 errno = save_errno; 1829 1830 return 4; 1831 } 1832 else 1833 { /* Trap 0 -> 30 */ 1834 EIPC = PC + 4; 1835 EIPSW = PSW; 1836 /* Mask out EICC */ 1837 ECR &= 0xffff0000; 1838 ECR |= 0x40 + OP[0]; 1839 /* Flag that we are now doing exception processing. */ 1840 PSW |= PSW_EP | PSW_ID; 1841 PC = (OP[0] < 0x10) ? 0x40 : 0x50; 1842 1843 return 0; 1844 } 1845} 1846 1847/* tst1 reg2, [reg1] */ 1848int 1849OP_E607E0 (void) 1850{ 1851 int temp; 1852 1853 trace_input ("tst1", OP_BIT, 1); 1854 1855 temp = load_mem (State.regs[ OP[0] ], 1); 1856 1857 PSW &= ~PSW_Z; 1858 if ((temp & (1 << (State.regs[ OP[1] ] & 0x7))) == 0) 1859 PSW |= PSW_Z; 1860 1861 trace_output (OP_BIT); 1862 1863 return 4; 1864} 1865 1866/* mulu reg1, reg2, reg3 */ 1867int 1868OP_22207E0 (void) 1869{ 1870 trace_input ("mulu", OP_REG_REG_REG, 0); 1871 1872 Multiply64 (0, State.regs[ OP[0] ]); 1873 1874 trace_output (OP_REG_REG_REG); 1875 1876 return 4; 1877} 1878 1879#define BIT_CHANGE_OP( name, binop ) \ 1880 unsigned int bit; \ 1881 unsigned int temp; \ 1882 \ 1883 trace_input (name, OP_BIT_CHANGE, 0); \ 1884 \ 1885 bit = 1 << (State.regs[ OP[1] ] & 0x7); \ 1886 temp = load_mem (State.regs[ OP[0] ], 1); \ 1887 \ 1888 PSW &= ~PSW_Z; \ 1889 if ((temp & bit) == 0) \ 1890 PSW |= PSW_Z; \ 1891 temp binop bit; \ 1892 \ 1893 store_mem (State.regs[ OP[0] ], 1, temp); \ 1894 \ 1895 trace_output (OP_BIT_CHANGE); \ 1896 \ 1897 return 4; 1898 1899/* clr1 reg2, [reg1] */ 1900int 1901OP_E407E0 (void) 1902{ 1903 BIT_CHANGE_OP ("clr1", &= ~ ); 1904} 1905 1906/* not1 reg2, [reg1] */ 1907int 1908OP_E207E0 (void) 1909{ 1910 BIT_CHANGE_OP ("not1", ^= ); 1911} 1912 1913/* set1 */ 1914int 1915OP_E007E0 (void) 1916{ 1917 BIT_CHANGE_OP ("set1", |= ); 1918} 1919 1920/* sasf */ 1921int 1922OP_20007E0 (void) 1923{ 1924 trace_input ("sasf", OP_EX1, 0); 1925 1926 State.regs[ OP[1] ] = (State.regs[ OP[1] ] << 1) | condition_met (OP[0]); 1927 1928 trace_output (OP_EX1); 1929 1930 return 4; 1931} 1932 1933/* This function is courtesy of Sugimoto at NEC, via Seow Tan 1934 (Soew_Tan@el.nec.com) */ 1935void 1936divun 1937( 1938 unsigned int N, 1939 unsigned long int als, 1940 unsigned long int sfi, 1941 unsigned32 /*unsigned long int*/ * quotient_ptr, 1942 unsigned32 /*unsigned long int*/ * remainder_ptr, 1943 int * overflow_ptr 1944) 1945{ 1946 unsigned long ald = sfi >> (N - 1); 1947 unsigned long alo = als; 1948 unsigned int Q = 1; 1949 unsigned int C; 1950 unsigned int S = 0; 1951 unsigned int i; 1952 unsigned int R1 = 1; 1953 unsigned int DBZ = (als == 0) ? 1 : 0; 1954 unsigned long alt = Q ? ~als : als; 1955 1956 /* 1st Loop */ 1957 alo = ald + alt + Q; 1958 C = (((alt >> 31) & (ald >> 31)) 1959 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31))); 1960 C = C ^ Q; 1961 Q = ~(C ^ S) & 1; 1962 R1 = (alo == 0) ? 0 : (R1 & Q); 1963 if ((S ^ (alo>>31)) && !C) 1964 { 1965 DBZ = 1; 1966 } 1967 S = alo >> 31; 1968 sfi = (sfi << (32-N+1)) | Q; 1969 ald = (alo << 1) | (sfi >> 31); 1970 1971 /* 2nd - N-1th Loop */ 1972 for (i = 2; i < N; i++) 1973 { 1974 alt = Q ? ~als : als; 1975 alo = ald + alt + Q; 1976 C = (((alt >> 31) & (ald >> 31)) 1977 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31))); 1978 C = C ^ Q; 1979 Q = ~(C ^ S) & 1; 1980 R1 = (alo == 0) ? 0 : (R1 & Q); 1981 if ((S ^ (alo>>31)) && !C && !DBZ) 1982 { 1983 DBZ = 1; 1984 } 1985 S = alo >> 31; 1986 sfi = (sfi << 1) | Q; 1987 ald = (alo << 1) | (sfi >> 31); 1988 } 1989 1990 /* Nth Loop */ 1991 alt = Q ? ~als : als; 1992 alo = ald + alt + Q; 1993 C = (((alt >> 31) & (ald >> 31)) 1994 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31))); 1995 C = C ^ Q; 1996 Q = ~(C ^ S) & 1; 1997 R1 = (alo == 0) ? 0 : (R1 & Q); 1998 if ((S ^ (alo>>31)) && !C) 1999 { 2000 DBZ = 1; 2001 } 2002 2003 * quotient_ptr = (sfi << 1) | Q; 2004 * remainder_ptr = Q ? alo : (alo + als); 2005 * overflow_ptr = DBZ | R1; 2006} 2007 2008/* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */ 2009void 2010divn 2011( 2012 unsigned int N, 2013 unsigned long int als, 2014 unsigned long int sfi, 2015 signed32 /*signed long int*/ * quotient_ptr, 2016 signed32 /*signed long int*/ * remainder_ptr, 2017 int * overflow_ptr 2018) 2019{ 2020 unsigned long ald = (signed long) sfi >> (N - 1); 2021 unsigned long alo = als; 2022 unsigned int SS = als >> 31; 2023 unsigned int SD = sfi >> 31; 2024 unsigned int R1 = 1; 2025 unsigned int OV; 2026 unsigned int DBZ = als == 0 ? 1 : 0; 2027 unsigned int Q = ~(SS ^ SD) & 1; 2028 unsigned int C; 2029 unsigned int S; 2030 unsigned int i; 2031 unsigned long alt = Q ? ~als : als; 2032 2033 2034 /* 1st Loop */ 2035 2036 alo = ald + alt + Q; 2037 C = (((alt >> 31) & (ald >> 31)) 2038 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31))); 2039 Q = C ^ SS; 2040 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD))); 2041 S = alo >> 31; 2042 sfi = (sfi << (32-N+1)) | Q; 2043 ald = (alo << 1) | (sfi >> 31); 2044 if ((alo >> 31) ^ (ald >> 31)) 2045 { 2046 DBZ = 1; 2047 } 2048 2049 /* 2nd - N-1th Loop */ 2050 2051 for (i = 2; i < N; i++) 2052 { 2053 alt = Q ? ~als : als; 2054 alo = ald + alt + Q; 2055 C = (((alt >> 31) & (ald >> 31)) 2056 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31))); 2057 Q = C ^ SS; 2058 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD))); 2059 S = alo >> 31; 2060 sfi = (sfi << 1) | Q; 2061 ald = (alo << 1) | (sfi >> 31); 2062 if ((alo >> 31) ^ (ald >> 31)) 2063 { 2064 DBZ = 1; 2065 } 2066 } 2067 2068 /* Nth Loop */ 2069 alt = Q ? ~als : als; 2070 alo = ald + alt + Q; 2071 C = (((alt >> 31) & (ald >> 31)) 2072 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31))); 2073 Q = C ^ SS; 2074 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD))); 2075 sfi = (sfi << (32-N+1)); 2076 ald = alo; 2077 2078 /* End */ 2079 if (alo != 0) 2080 { 2081 alt = Q ? ~als : als; 2082 alo = ald + alt + Q; 2083 } 2084 R1 = R1 & ((~alo >> 31) ^ SD); 2085 if ((alo != 0) && ((Q ^ (SS ^ SD)) ^ R1)) alo = ald; 2086 if (N != 32) 2087 ald = sfi = (long) ((sfi >> 1) | (SS ^ SD) << 31) >> (32-N-1) | Q; 2088 else 2089 ald = sfi = sfi | Q; 2090 2091 OV = DBZ | ((alo == 0) ? 0 : R1); 2092 2093 * remainder_ptr = alo; 2094 2095 /* Adj */ 2096 if (((alo != 0) && ((SS ^ SD) ^ R1)) 2097 || ((alo == 0) && (SS ^ R1))) 2098 alo = ald + 1; 2099 else 2100 alo = ald; 2101 2102 OV = (DBZ | R1) ? OV : ((alo >> 31) & (~ald >> 31)); 2103 2104 * quotient_ptr = alo; 2105 * overflow_ptr = OV; 2106} 2107 2108/* sdivun imm5, reg1, reg2, reg3 */ 2109int 2110OP_1C207E0 (void) 2111{ 2112 unsigned32 /*unsigned long int*/ quotient; 2113 unsigned32 /*unsigned long int*/ remainder; 2114 unsigned long int divide_by; 2115 unsigned long int divide_this; 2116 int overflow = 0; 2117 unsigned int imm5; 2118 2119 trace_input ("sdivun", OP_IMM_REG_REG_REG, 0); 2120 2121 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17); 2122 2123 divide_by = State.regs[ OP[0] ]; 2124 divide_this = State.regs[ OP[1] ] << imm5; 2125 2126 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow); 2127 2128 State.regs[ OP[1] ] = quotient; 2129 State.regs[ OP[2] >> 11 ] = remainder; 2130 2131 /* Set condition codes. */ 2132 PSW &= ~(PSW_Z | PSW_S | PSW_OV); 2133 2134 if (overflow) PSW |= PSW_OV; 2135 if (quotient == 0) PSW |= PSW_Z; 2136 if (quotient & 0x80000000) PSW |= PSW_S; 2137 2138 trace_output (OP_IMM_REG_REG_REG); 2139 2140 return 4; 2141} 2142 2143/* sdivn imm5, reg1, reg2, reg3 */ 2144int 2145OP_1C007E0 (void) 2146{ 2147 signed32 /*signed long int*/ quotient; 2148 signed32 /*signed long int*/ remainder; 2149 signed long int divide_by; 2150 signed long int divide_this; 2151 int overflow = 0; 2152 unsigned int imm5; 2153 2154 trace_input ("sdivn", OP_IMM_REG_REG_REG, 0); 2155 2156 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17); 2157 2158 divide_by = State.regs[ OP[0] ]; 2159 divide_this = State.regs[ OP[1] ] << imm5; 2160 2161 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow); 2162 2163 State.regs[ OP[1] ] = quotient; 2164 State.regs[ OP[2] >> 11 ] = remainder; 2165 2166 /* Set condition codes. */ 2167 PSW &= ~(PSW_Z | PSW_S | PSW_OV); 2168 2169 if (overflow) PSW |= PSW_OV; 2170 if (quotient == 0) PSW |= PSW_Z; 2171 if (quotient < 0) PSW |= PSW_S; 2172 2173 trace_output (OP_IMM_REG_REG_REG); 2174 2175 return 4; 2176} 2177 2178/* sdivhun imm5, reg1, reg2, reg3 */ 2179int 2180OP_18207E0 (void) 2181{ 2182 unsigned32 /*unsigned long int*/ quotient; 2183 unsigned32 /*unsigned long int*/ remainder; 2184 unsigned long int divide_by; 2185 unsigned long int divide_this; 2186 int overflow = 0; 2187 unsigned int imm5; 2188 2189 trace_input ("sdivhun", OP_IMM_REG_REG_REG, 0); 2190 2191 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17); 2192 2193 divide_by = State.regs[ OP[0] ] & 0xffff; 2194 divide_this = State.regs[ OP[1] ] << imm5; 2195 2196 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow); 2197 2198 State.regs[ OP[1] ] = quotient; 2199 State.regs[ OP[2] >> 11 ] = remainder; 2200 2201 /* Set condition codes. */ 2202 PSW &= ~(PSW_Z | PSW_S | PSW_OV); 2203 2204 if (overflow) PSW |= PSW_OV; 2205 if (quotient == 0) PSW |= PSW_Z; 2206 if (quotient & 0x80000000) PSW |= PSW_S; 2207 2208 trace_output (OP_IMM_REG_REG_REG); 2209 2210 return 4; 2211} 2212 2213/* sdivhn imm5, reg1, reg2, reg3 */ 2214int 2215OP_18007E0 (void) 2216{ 2217 signed32 /*signed long int*/ quotient; 2218 signed32 /*signed long int*/ remainder; 2219 signed long int divide_by; 2220 signed long int divide_this; 2221 int overflow = 0; 2222 unsigned int imm5; 2223 2224 trace_input ("sdivhn", OP_IMM_REG_REG_REG, 0); 2225 2226 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17); 2227 2228 divide_by = EXTEND16 (State.regs[ OP[0] ]); 2229 divide_this = State.regs[ OP[1] ] << imm5; 2230 2231 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow); 2232 2233 State.regs[ OP[1] ] = quotient; 2234 State.regs[ OP[2] >> 11 ] = remainder; 2235 2236 /* Set condition codes. */ 2237 PSW &= ~(PSW_Z | PSW_S | PSW_OV); 2238 2239 if (overflow) PSW |= PSW_OV; 2240 if (quotient == 0) PSW |= PSW_Z; 2241 if (quotient < 0) PSW |= PSW_S; 2242 2243 trace_output (OP_IMM_REG_REG_REG); 2244 2245 return 4; 2246} 2247 2248/* divu reg1, reg2, reg3 */ 2249int 2250OP_2C207E0 (void) 2251{ 2252 unsigned long int quotient; 2253 unsigned long int remainder; 2254 unsigned long int divide_by; 2255 unsigned long int divide_this; 2256 int overflow = 0; 2257 2258 trace_input ("divu", OP_REG_REG_REG, 0); 2259 2260 /* Compute the result. */ 2261 2262 divide_by = State.regs[ OP[0] ]; 2263 divide_this = State.regs[ OP[1] ]; 2264 2265 if (divide_by == 0) 2266 { 2267 overflow = 1; 2268 divide_by = 1; 2269 } 2270 2271 State.regs[ OP[1] ] = quotient = divide_this / divide_by; 2272 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by; 2273 2274 /* Set condition codes. */ 2275 PSW &= ~(PSW_Z | PSW_S | PSW_OV); 2276 2277 if (overflow) PSW |= PSW_OV; 2278 if (quotient == 0) PSW |= PSW_Z; 2279 if (quotient & 0x80000000) PSW |= PSW_S; 2280 2281 trace_output (OP_REG_REG_REG); 2282 2283 return 4; 2284} 2285 2286/* div reg1, reg2, reg3 */ 2287int 2288OP_2C007E0 (void) 2289{ 2290 signed long int quotient; 2291 signed long int remainder; 2292 signed long int divide_by; 2293 signed long int divide_this; 2294 int overflow = 0; 2295 2296 trace_input ("div", OP_REG_REG_REG, 0); 2297 2298 /* Compute the result. */ 2299 2300 divide_by = State.regs[ OP[0] ]; 2301 divide_this = State.regs[ OP[1] ]; 2302 2303 if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31))) 2304 { 2305 overflow = 1; 2306 divide_by = 1; 2307 } 2308 2309 State.regs[ OP[1] ] = quotient = divide_this / divide_by; 2310 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by; 2311 2312 /* Set condition codes. */ 2313 PSW &= ~(PSW_Z | PSW_S | PSW_OV); 2314 2315 if (overflow) PSW |= PSW_OV; 2316 if (quotient == 0) PSW |= PSW_Z; 2317 if (quotient < 0) PSW |= PSW_S; 2318 2319 trace_output (OP_REG_REG_REG); 2320 2321 return 4; 2322} 2323 2324/* divhu reg1, reg2, reg3 */ 2325int 2326OP_28207E0 (void) 2327{ 2328 unsigned long int quotient; 2329 unsigned long int remainder; 2330 unsigned long int divide_by; 2331 unsigned long int divide_this; 2332 int overflow = 0; 2333 2334 trace_input ("divhu", OP_REG_REG_REG, 0); 2335 2336 /* Compute the result. */ 2337 2338 divide_by = State.regs[ OP[0] ] & 0xffff; 2339 divide_this = State.regs[ OP[1] ]; 2340 2341 if (divide_by == 0) 2342 { 2343 overflow = 1; 2344 divide_by = 1; 2345 } 2346 2347 State.regs[ OP[1] ] = quotient = divide_this / divide_by; 2348 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by; 2349 2350 /* Set condition codes. */ 2351 PSW &= ~(PSW_Z | PSW_S | PSW_OV); 2352 2353 if (overflow) PSW |= PSW_OV; 2354 if (quotient == 0) PSW |= PSW_Z; 2355 if (quotient & 0x80000000) PSW |= PSW_S; 2356 2357 trace_output (OP_REG_REG_REG); 2358 2359 return 4; 2360} 2361 2362/* divh reg1, reg2, reg3 */ 2363int 2364OP_28007E0 (void) 2365{ 2366 signed long int quotient; 2367 signed long int remainder; 2368 signed long int divide_by; 2369 signed long int divide_this; 2370 int overflow = 0; 2371 2372 trace_input ("divh", OP_REG_REG_REG, 0); 2373 2374 /* Compute the result. */ 2375 2376 divide_by = State.regs[ OP[0] ]; 2377 divide_this = EXTEND16 (State.regs[ OP[1] ]); 2378 2379 if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31))) 2380 { 2381 overflow = 1; 2382 divide_by = 1; 2383 } 2384 2385 State.regs[ OP[1] ] = quotient = divide_this / divide_by; 2386 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by; 2387 2388 /* Set condition codes. */ 2389 PSW &= ~(PSW_Z | PSW_S | PSW_OV); 2390 2391 if (overflow) PSW |= PSW_OV; 2392 if (quotient == 0) PSW |= PSW_Z; 2393 if (quotient < 0) PSW |= PSW_S; 2394 2395 trace_output (OP_REG_REG_REG); 2396 2397 return 4; 2398} 2399 2400/* mulu imm9, reg2, reg3 */ 2401int 2402OP_24207E0 (void) 2403{ 2404 trace_input ("mulu", OP_IMM_REG_REG, 0); 2405 2406 Multiply64 (0, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0)); 2407 2408 trace_output (OP_IMM_REG_REG); 2409 2410 return 4; 2411} 2412 2413/* mul imm9, reg2, reg3 */ 2414int 2415OP_24007E0 (void) 2416{ 2417 trace_input ("mul", OP_IMM_REG_REG, 0); 2418 2419 Multiply64 (1, SEXT9 ((OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0))); 2420 2421 trace_output (OP_IMM_REG_REG); 2422 2423 return 4; 2424} 2425 2426/* ld.hu */ 2427int 2428OP_107E0 (void) 2429{ 2430 int adr; 2431 2432 trace_input ("ld.hu", OP_LOAD32, 2); 2433 2434 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1); 2435 adr &= ~0x1; 2436 2437 State.regs[ OP[1] ] = load_mem (adr, 2); 2438 2439 trace_output (OP_LOAD32); 2440 2441 return 4; 2442} 2443 2444 2445/* ld.bu */ 2446int 2447OP_10780 (void) 2448{ 2449 int adr; 2450 2451 trace_input ("ld.bu", OP_LOAD32, 1); 2452 2453 adr = (State.regs[ OP[0] ] 2454 + (EXTEND16 (OP[2] & ~1) | ((OP[3] >> 5) & 1))); 2455 2456 State.regs[ OP[1] ] = load_mem (adr, 1); 2457 2458 trace_output (OP_LOAD32); 2459 2460 return 4; 2461} 2462 2463/* prepare list12, imm5, imm32 */ 2464int 2465OP_1B0780 (void) 2466{ 2467 int i; 2468 2469 trace_input ("prepare", OP_PUSHPOP1, 0); 2470 2471 /* Store the registers with lower number registers being placed at higher addresses. */ 2472 for (i = 0; i < 12; i++) 2473 if ((OP[3] & (1 << type1_regs[ i ]))) 2474 { 2475 SP -= 4; 2476 store_mem (SP, 4, State.regs[ 20 + i ]); 2477 } 2478 2479 SP -= (OP[3] & 0x3e) << 1; 2480 2481 EP = load_mem (PC + 4, 4); 2482 2483 trace_output (OP_PUSHPOP1); 2484 2485 return 8; 2486} 2487 2488/* prepare list12, imm5, imm16-32 */ 2489int 2490OP_130780 (void) 2491{ 2492 int i; 2493 2494 trace_input ("prepare", OP_PUSHPOP1, 0); 2495 2496 /* Store the registers with lower number registers being placed at higher addresses. */ 2497 for (i = 0; i < 12; i++) 2498 if ((OP[3] & (1 << type1_regs[ i ]))) 2499 { 2500 SP -= 4; 2501 store_mem (SP, 4, State.regs[ 20 + i ]); 2502 } 2503 2504 SP -= (OP[3] & 0x3e) << 1; 2505 2506 EP = load_mem (PC + 4, 2) << 16; 2507 2508 trace_output (OP_PUSHPOP1); 2509 2510 return 6; 2511} 2512 2513/* prepare list12, imm5, imm16 */ 2514int 2515OP_B0780 (void) 2516{ 2517 int i; 2518 2519 trace_input ("prepare", OP_PUSHPOP1, 0); 2520 2521 /* Store the registers with lower number registers being placed at higher addresses. */ 2522 for (i = 0; i < 12; i++) 2523 if ((OP[3] & (1 << type1_regs[ i ]))) 2524 { 2525 SP -= 4; 2526 store_mem (SP, 4, State.regs[ 20 + i ]); 2527 } 2528 2529 SP -= (OP[3] & 0x3e) << 1; 2530 2531 EP = EXTEND16 (load_mem (PC + 4, 2)); 2532 2533 trace_output (OP_PUSHPOP1); 2534 2535 return 6; 2536} 2537 2538/* prepare list12, imm5, sp */ 2539int 2540OP_30780 (void) 2541{ 2542 int i; 2543 2544 trace_input ("prepare", OP_PUSHPOP1, 0); 2545 2546 /* Store the registers with lower number registers being placed at higher addresses. */ 2547 for (i = 0; i < 12; i++) 2548 if ((OP[3] & (1 << type1_regs[ i ]))) 2549 { 2550 SP -= 4; 2551 store_mem (SP, 4, State.regs[ 20 + i ]); 2552 } 2553 2554 SP -= (OP[3] & 0x3e) << 1; 2555 2556 EP = SP; 2557 2558 trace_output (OP_PUSHPOP1); 2559 2560 return 4; 2561} 2562 2563/* mul reg1, reg2, reg3 */ 2564int 2565OP_22007E0 (void) 2566{ 2567 trace_input ("mul", OP_REG_REG_REG, 0); 2568 2569 Multiply64 (1, State.regs[ OP[0] ]); 2570 2571 trace_output (OP_REG_REG_REG); 2572 2573 return 4; 2574} 2575 2576/* popmh list18 */ 2577int 2578OP_307F0 (void) 2579{ 2580 int i; 2581 2582 trace_input ("popmh", OP_PUSHPOP2, 0); 2583 2584 if (OP[3] & (1 << 19)) 2585 { 2586 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0)) 2587 { 2588 FEPSW = load_mem ( SP & ~ 3, 4); 2589 FEPC = load_mem ((SP + 4) & ~ 3, 4); 2590 } 2591 else 2592 { 2593 EIPSW = load_mem ( SP & ~ 3, 4); 2594 EIPC = load_mem ((SP + 4) & ~ 3, 4); 2595 } 2596 2597 SP += 8; 2598 } 2599 2600 /* Load the registers with lower number registers being retrieved from higher addresses. */ 2601 for (i = 16; i--;) 2602 if ((OP[3] & (1 << type2_regs[ i ]))) 2603 { 2604 State.regs[ i + 16 ] = load_mem (SP & ~ 3, 4); 2605 SP += 4; 2606 } 2607 2608 trace_output (OP_PUSHPOP2); 2609 2610 return 4; 2611} 2612 2613/* popml lsit18 */ 2614int 2615OP_107F0 (void) 2616{ 2617 int i; 2618 2619 trace_input ("popml", OP_PUSHPOP3, 0); 2620 2621 if (OP[3] & (1 << 19)) 2622 { 2623 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0)) 2624 { 2625 FEPSW = load_mem ( SP & ~ 3, 4); 2626 FEPC = load_mem ((SP + 4) & ~ 3, 4); 2627 } 2628 else 2629 { 2630 EIPSW = load_mem ( SP & ~ 3, 4); 2631 EIPC = load_mem ((SP + 4) & ~ 3, 4); 2632 } 2633 2634 SP += 8; 2635 } 2636 2637 if (OP[3] & (1 << 3)) 2638 { 2639 PSW = load_mem (SP & ~ 3, 4); 2640 SP += 4; 2641 } 2642 2643 /* Load the registers with lower number registers being retrieved from higher addresses. */ 2644 for (i = 15; i--;) 2645 if ((OP[3] & (1 << type3_regs[ i ]))) 2646 { 2647 State.regs[ i + 1 ] = load_mem (SP & ~ 3, 4); 2648 SP += 4; 2649 } 2650 2651 trace_output (OP_PUSHPOP2); 2652 2653 return 4; 2654} 2655 2656/* pushmh list18 */ 2657int 2658OP_307E0 (void) 2659{ 2660 int i; 2661 2662 trace_input ("pushmh", OP_PUSHPOP2, 0); 2663 2664 /* Store the registers with lower number registers being placed at higher addresses. */ 2665 for (i = 0; i < 16; i++) 2666 if ((OP[3] & (1 << type2_regs[ i ]))) 2667 { 2668 SP -= 4; 2669 store_mem (SP & ~ 3, 4, State.regs[ i + 16 ]); 2670 } 2671 2672 if (OP[3] & (1 << 19)) 2673 { 2674 SP -= 8; 2675 2676 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0)) 2677 { 2678 store_mem ((SP + 4) & ~ 3, 4, FEPC); 2679 store_mem ( SP & ~ 3, 4, FEPSW); 2680 } 2681 else 2682 { 2683 store_mem ((SP + 4) & ~ 3, 4, EIPC); 2684 store_mem ( SP & ~ 3, 4, EIPSW); 2685 } 2686 } 2687 2688 trace_output (OP_PUSHPOP2); 2689 2690 return 4; 2691} 2692 2693