1# sh testcase for fsca 2# mach: sh 3# as(sh): -defsym sim_cpu=0 4 5 .include "testutils.inc" 6 7 start 8fsca: 9 set_grs_a5a5 10 set_fprs_a5a5 11 # Start with angle zero 12 mov.l zero, r0 13 lds r0, fpul 14 fsca fpul, dr2 15 assert_fpreg_i 0, fr2 16 assert_fpreg_i 1, fr3 17 18 mov.l plus_90, r0 19 lds r0, fpul 20 fsca fpul, dr2 21 assert_fpreg_i 1, fr2 22 assert_fpreg_i 0, fr3 23 24 mov.l plus_180, r0 25 lds r0, fpul 26 fsca fpul, dr2 27 assert_fpreg_i 0, fr2 28 assert_fpreg_i -1, fr3 29 30 mov.l plus_270, r0 31 lds r0, fpul 32 fsca fpul, dr2 33 assert_fpreg_i -1, fr2 34 assert_fpreg_i 0, fr3 35 36 mov.l plus_360, r0 37 lds r0, fpul 38 fsca fpul, dr2 39 assert_fpreg_i 0, fr2 40 assert_fpreg_i 1, fr3 41 42 mov.l minus_90, r0 43 lds r0, fpul 44 fsca fpul, dr2 45 assert_fpreg_i -1, fr2 46 assert_fpreg_i 0, fr3 47 48 mov.l minus_180, r0 49 lds r0, fpul 50 fsca fpul, dr2 51 assert_fpreg_i 0, fr2 52 assert_fpreg_i -1, fr3 53 54 mov.l minus_270, r0 55 lds r0, fpul 56 fsca fpul, dr2 57 assert_fpreg_i 1, fr2 58 assert_fpreg_i 0, fr3 59 60 mov.l minus_360, r0 61 lds r0, fpul 62 fsca fpul, dr2 63 assert_fpreg_i 0, fr2 64 assert_fpreg_i 1, fr3 65 66 assertreg0 0xffff0000 67 set_greg 0xa5a5a5a5, r0 68 test_grs_a5a5 69 test_fpr_a5a5 fr0 70 test_fpr_a5a5 fr1 71 test_fpr_a5a5 fr4 72 test_fpr_a5a5 fr5 73 test_fpr_a5a5 fr6 74 test_fpr_a5a5 fr7 75 test_fpr_a5a5 fr8 76 test_fpr_a5a5 fr9 77 test_fpr_a5a5 fr10 78 test_fpr_a5a5 fr11 79 test_fpr_a5a5 fr12 80 test_fpr_a5a5 fr13 81 test_fpr_a5a5 fr14 82 test_fpr_a5a5 fr15 83 pass 84 exit 0 85 86 .align 2 87zero: .long 0 88one_bitty: .long 1 89plus_90: .long 0x04000 90plus_180: .long 0x08000 91plus_270: .long 0x0c000 92plus_360: .long 0x10000 93minus_90: .long 0xffffc000 94minus_180: .long 0xffff8000 95minus_270: .long 0xffff4000 96minus_360: .long 0xffff0000 97minus_1_bitty: .long 0xffffffff 98