1#include <stdio.h> 2#include <ctype.h> 3#include "ansidecl.h" 4#include "gdb/callback.h" 5#include "opcode/mn10300.h" 6#include <limits.h> 7#include "gdb/remote-sim.h" 8#include "bfd.h" 9#include "sim-fpu.h" 10 11#ifndef INLINE 12#ifdef __GNUC__ 13#define INLINE inline 14#else 15#define INLINE 16#endif 17#endif 18 19extern host_callback *mn10300_callback; 20extern SIM_DESC simulator; 21 22#define DEBUG_TRACE 0x00000001 23#define DEBUG_VALUES 0x00000002 24 25extern int mn10300_debug; 26 27#if UCHAR_MAX == 255 28typedef unsigned char uint8; 29typedef signed char int8; 30#else 31#error "Char is not an 8-bit type" 32#endif 33 34#if SHRT_MAX == 32767 35typedef unsigned short uint16; 36typedef signed short int16; 37#else 38#error "Short is not a 16-bit type" 39#endif 40 41#if INT_MAX == 2147483647 42 43typedef unsigned int uint32; 44typedef signed int int32; 45 46#else 47# if LONG_MAX == 2147483647 48 49typedef unsigned long uint32; 50typedef signed long int32; 51 52# else 53# error "Neither int nor long is a 32-bit type" 54# endif 55#endif 56 57typedef struct 58{ 59 uint32 low, high; 60} dword; 61typedef uint32 reg_t; 62 63struct simops 64{ 65 long opcode; 66 long mask; 67 void (*func)(); 68 int length; 69 int format; 70 int numops; 71 int operands[16]; 72}; 73 74/* The current state of the processor; registers, memory, etc. */ 75 76struct _state 77{ 78 reg_t regs[32]; /* registers, d0-d3, a0-a3, sp, pc, mdr, psw, 79 lir, lar, mdrq, plus some room for processor 80 specific regs. */ 81 union 82 { 83 reg_t fs[32]; /* FS0-31 */ 84 dword fd[16]; /* FD0,2,...,30 */ 85 } fpregs; 86 uint8 *mem; /* main memory */ 87 int exception; 88 int exited; 89 90 /* All internal state modified by signal_exception() that may need to be 91 rolled back for passing moment-of-exception image back to gdb. */ 92 reg_t exc_trigger_regs[32]; 93 reg_t exc_suspend_regs[32]; 94 int exc_suspended; 95 96#define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mn10300_cpu_exception_trigger(SD,CPU,CIA) 97#define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mn10300_cpu_exception_suspend(SD,CPU,EXC) 98#define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mn10300_cpu_exception_resume(SD,CPU,EXC) 99}; 100 101extern struct _state State; 102extern uint32 OP[4]; 103extern struct simops Simops[]; 104 105#define PC (State.regs[REG_PC]) 106#define SP (State.regs[REG_SP]) 107 108#define PSW (State.regs[11]) 109#define PSW_Z 0x1 110#define PSW_N 0x2 111#define PSW_C 0x4 112#define PSW_V 0x8 113#define PSW_IE LSBIT (11) 114#define PSW_LM LSMASK (10, 8) 115 116#define EXTRACT_PSW_LM LSEXTRACTED16 (PSW, 10, 8) 117#define INSERT_PSW_LM(l) LSINSERTED16 ((l), 10, 8) 118 119#define REG_D0 0 120#define REG_A0 4 121#define REG_SP 8 122#define REG_PC 9 123#define REG_MDR 10 124#define REG_PSW 11 125#define REG_LIR 12 126#define REG_LAR 13 127#define REG_MDRQ 14 128#define REG_E0 15 129#define REG_SSP 23 130#define REG_MSP 24 131#define REG_USP 25 132#define REG_MCRH 26 133#define REG_MCRL 27 134#define REG_MCVF 28 135 136#define REG_FPCR 29 137 138#define FPCR (State.regs[REG_FPCR]) 139 140#define FCC_MASK LSMASK (21, 18) 141#define RM_MASK LSMASK (17, 16) /* Must always be zero. */ 142#define EC_MASK LSMASK (14, 10) 143#define EE_MASK LSMASK ( 9, 5) 144#define EF_MASK LSMASK ( 4, 0) 145#define FPCR_MASK (FCC_MASK | EC_MASK | EE_MASK | EF_MASK) 146 147#define FCC_L LSBIT (21) 148#define FCC_G LSBIT (20) 149#define FCC_E LSBIT (19) 150#define FCC_U LSBIT (18) 151 152#define EC_V LSBIT (14) 153#define EC_Z LSBIT (13) 154#define EC_O LSBIT (12) 155#define EC_U LSBIT (11) 156#define EC_I LSBIT (10) 157 158#define EE_V LSBIT (9) 159#define EE_Z LSBIT (8) 160#define EE_O LSBIT (7) 161#define EE_U LSBIT (6) 162#define EE_I LSBIT (5) 163 164#define EF_V LSBIT (4) 165#define EF_Z LSBIT (3) 166#define EF_O LSBIT (2) 167#define EF_U LSBIT (1) 168#define EF_I LSBIT (0) 169 170#define PSW_FE LSBIT(20) 171#define FPU_DISABLED !(PSW & PSW_FE) 172 173#define XS2FS(X,S) State.fpregs.fs[((X<<4)|(S))] 174#define AS2FS(A,S) State.fpregs.fs[((A<<2)|(S))] 175#define Xf2FD(X,f) State.fpregs.fd[((X<<3)|(f))] 176 177#define FS2FPU(FS,F) sim_fpu_32to (&(F), (FS)) 178#define FD2FPU(FD,F) sim_fpu_232to (&(F), ((FD).high), ((FD).low)) 179#define FPU2FS(F,FS) sim_fpu_to32 (&(FS), &(F)) 180#define FPU2FD(F,FD) sim_fpu_to232 (&((FD).high), &((FD).low), &(F)) 181 182#ifdef _WIN32 183#define SIGTRAP 5 184#define SIGQUIT 3 185#endif 186 187#define FETCH32(a,b,c,d) \ 188 ((a)+((b)<<8)+((c)<<16)+((d)<<24)) 189 190#define FETCH24(a,b,c) \ 191 ((a)+((b)<<8)+((c)<<16)) 192 193#define FETCH16(a,b) ((a)+((b)<<8)) 194 195#define load_byte(ADDR) \ 196sim_core_read_unaligned_1 (STATE_CPU (simulator, 0), PC, read_map, (ADDR)) 197 198#define load_half(ADDR) \ 199sim_core_read_unaligned_2 (STATE_CPU (simulator, 0), PC, read_map, (ADDR)) 200 201#define load_word(ADDR) \ 202sim_core_read_unaligned_4 (STATE_CPU (simulator, 0), PC, read_map, (ADDR)) 203 204#define load_dword(ADDR) \ 205u642dw (sim_core_read_unaligned_8 (STATE_CPU (simulator, 0), \ 206 PC, read_map, (ADDR))) 207 208static INLINE dword 209u642dw (unsigned64 dw) 210{ 211 dword r; 212 213 r.low = (unsigned32)dw; 214 r.high = (unsigned32)(dw >> 32); 215 return r; 216} 217 218#define store_byte(ADDR, DATA) \ 219sim_core_write_unaligned_1 (STATE_CPU (simulator, 0), \ 220 PC, write_map, (ADDR), (DATA)) 221 222 223#define store_half(ADDR, DATA) \ 224sim_core_write_unaligned_2 (STATE_CPU (simulator, 0), \ 225 PC, write_map, (ADDR), (DATA)) 226 227 228#define store_word(ADDR, DATA) \ 229sim_core_write_unaligned_4 (STATE_CPU (simulator, 0), \ 230 PC, write_map, (ADDR), (DATA)) 231#define store_dword(ADDR, DATA) \ 232sim_core_write_unaligned_8 (STATE_CPU (simulator, 0), \ 233 PC, write_map, (ADDR), dw2u64 (DATA)) 234 235static INLINE unsigned64 236dw2u64 (dword data) 237{ 238 return data.low | (((unsigned64)data.high) << 32); 239} 240 241/* Function declarations. */ 242 243uint32 get_word (uint8 *); 244uint16 get_half (uint8 *); 245uint8 get_byte (uint8 *); 246void put_word (uint8 *, uint32); 247void put_half (uint8 *, uint16); 248void put_byte (uint8 *, uint8); 249 250extern uint8 *map (SIM_ADDR addr); 251 252INLINE_SIM_MAIN (void) genericAdd (unsigned32 source, unsigned32 destReg); 253INLINE_SIM_MAIN (void) genericSub (unsigned32 source, unsigned32 destReg); 254INLINE_SIM_MAIN (void) genericCmp (unsigned32 leftOpnd, unsigned32 rightOpnd); 255INLINE_SIM_MAIN (void) genericOr (unsigned32 source, unsigned32 destReg); 256INLINE_SIM_MAIN (void) genericXor (unsigned32 source, unsigned32 destReg); 257INLINE_SIM_MAIN (void) genericBtst (unsigned32 leftOpnd, unsigned32 rightOpnd); 258INLINE_SIM_MAIN (int) syscall_read_mem (host_callback *cb, 259 struct cb_syscall *sc, 260 unsigned long taddr, 261 char *buf, 262 int bytes); 263INLINE_SIM_MAIN (int) syscall_write_mem (host_callback *cb, 264 struct cb_syscall *sc, 265 unsigned long taddr, 266 const char *buf, 267 int bytes); 268INLINE_SIM_MAIN (void) do_syscall (void); 269void program_interrupt (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, SIM_SIGNAL sig); 270 271void mn10300_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc); 272void mn10300_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception); 273void mn10300_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception); 274 275void fpu_disabled_exception (SIM_DESC, sim_cpu *, address_word); 276void fpu_unimp_exception (SIM_DESC, sim_cpu *, address_word); 277void fpu_check_signal_exception (SIM_DESC, sim_cpu *, address_word); 278 279extern const struct fp_prec_t 280{ 281 void (* reg2val) (const void *, sim_fpu *); 282 int (* round) (sim_fpu *); 283 void (* val2reg) (const sim_fpu *, void *); 284} fp_single_prec, fp_double_prec; 285 286#define FP_SINGLE (&fp_single_prec) 287#define FP_DOUBLE (&fp_double_prec) 288 289void fpu_rsqrt (SIM_DESC, sim_cpu *, address_word, const void *, void *, const struct fp_prec_t *); 290void fpu_sqrt (SIM_DESC, sim_cpu *, address_word, const void *, void *, const struct fp_prec_t *); 291void fpu_cmp (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const struct fp_prec_t *); 292void fpu_add (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *); 293void fpu_sub (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *); 294void fpu_mul (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *); 295void fpu_div (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *); 296void fpu_fmadd (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *); 297void fpu_fmsub (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *); 298void fpu_fnmadd (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *); 299void fpu_fnmsub (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *); 300