1/* Simulator model support for m32r2f.
2
3THIS FILE IS MACHINE GENERATED WITH CGEN.
4
5Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
6
7This file is part of the GNU simulators.
8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 3 of the License, or
12(at your option) any later version.
13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License
20along with this program.  If not, see <http://www.gnu.org/licenses/>.
21
22*/
23
24#define WANT_CPU m32r2f
25#define WANT_CPU_M32R2F
26
27#include "sim-main.h"
28
29/* The profiling data is recorded here, but is accessed via the profiling
30   mechanism.  After all, this is information for profiling.  */
31
32#if WITH_PROFILE_MODEL_P
33
34/* Model handlers for each insn.  */
35
36static int
37model_m32r2_add (SIM_CPU *current_cpu, void *sem_arg)
38{
39#define FLD(f) abuf->fields.sfmt_add.f
40  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
41  const IDESC * UNUSED idesc = abuf->idesc;
42  int cycles = 0;
43  {
44    int referenced = 0;
45    int UNUSED insn_referenced = abuf->written;
46    INT in_sr = -1;
47    INT in_dr = -1;
48    INT out_dr = -1;
49    in_sr = FLD (in_sr);
50    in_dr = FLD (in_dr);
51    out_dr = FLD (out_dr);
52    referenced |= 1 << 0;
53    referenced |= 1 << 1;
54    referenced |= 1 << 2;
55    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
56  }
57  return cycles;
58#undef FLD
59}
60
61static int
62model_m32r2_add3 (SIM_CPU *current_cpu, void *sem_arg)
63{
64#define FLD(f) abuf->fields.sfmt_add3.f
65  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
66  const IDESC * UNUSED idesc = abuf->idesc;
67  int cycles = 0;
68  {
69    int referenced = 0;
70    int UNUSED insn_referenced = abuf->written;
71    INT in_sr = -1;
72    INT in_dr = -1;
73    INT out_dr = -1;
74    in_sr = FLD (in_sr);
75    out_dr = FLD (out_dr);
76    referenced |= 1 << 0;
77    referenced |= 1 << 2;
78    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
79  }
80  return cycles;
81#undef FLD
82}
83
84static int
85model_m32r2_and (SIM_CPU *current_cpu, void *sem_arg)
86{
87#define FLD(f) abuf->fields.sfmt_add.f
88  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
89  const IDESC * UNUSED idesc = abuf->idesc;
90  int cycles = 0;
91  {
92    int referenced = 0;
93    int UNUSED insn_referenced = abuf->written;
94    INT in_sr = -1;
95    INT in_dr = -1;
96    INT out_dr = -1;
97    in_sr = FLD (in_sr);
98    in_dr = FLD (in_dr);
99    out_dr = FLD (out_dr);
100    referenced |= 1 << 0;
101    referenced |= 1 << 1;
102    referenced |= 1 << 2;
103    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
104  }
105  return cycles;
106#undef FLD
107}
108
109static int
110model_m32r2_and3 (SIM_CPU *current_cpu, void *sem_arg)
111{
112#define FLD(f) abuf->fields.sfmt_and3.f
113  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
114  const IDESC * UNUSED idesc = abuf->idesc;
115  int cycles = 0;
116  {
117    int referenced = 0;
118    int UNUSED insn_referenced = abuf->written;
119    INT in_sr = -1;
120    INT in_dr = -1;
121    INT out_dr = -1;
122    in_sr = FLD (in_sr);
123    out_dr = FLD (out_dr);
124    referenced |= 1 << 0;
125    referenced |= 1 << 2;
126    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
127  }
128  return cycles;
129#undef FLD
130}
131
132static int
133model_m32r2_or (SIM_CPU *current_cpu, void *sem_arg)
134{
135#define FLD(f) abuf->fields.sfmt_add.f
136  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
137  const IDESC * UNUSED idesc = abuf->idesc;
138  int cycles = 0;
139  {
140    int referenced = 0;
141    int UNUSED insn_referenced = abuf->written;
142    INT in_sr = -1;
143    INT in_dr = -1;
144    INT out_dr = -1;
145    in_sr = FLD (in_sr);
146    in_dr = FLD (in_dr);
147    out_dr = FLD (out_dr);
148    referenced |= 1 << 0;
149    referenced |= 1 << 1;
150    referenced |= 1 << 2;
151    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
152  }
153  return cycles;
154#undef FLD
155}
156
157static int
158model_m32r2_or3 (SIM_CPU *current_cpu, void *sem_arg)
159{
160#define FLD(f) abuf->fields.sfmt_and3.f
161  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
162  const IDESC * UNUSED idesc = abuf->idesc;
163  int cycles = 0;
164  {
165    int referenced = 0;
166    int UNUSED insn_referenced = abuf->written;
167    INT in_sr = -1;
168    INT in_dr = -1;
169    INT out_dr = -1;
170    in_sr = FLD (in_sr);
171    out_dr = FLD (out_dr);
172    referenced |= 1 << 0;
173    referenced |= 1 << 2;
174    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
175  }
176  return cycles;
177#undef FLD
178}
179
180static int
181model_m32r2_xor (SIM_CPU *current_cpu, void *sem_arg)
182{
183#define FLD(f) abuf->fields.sfmt_add.f
184  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
185  const IDESC * UNUSED idesc = abuf->idesc;
186  int cycles = 0;
187  {
188    int referenced = 0;
189    int UNUSED insn_referenced = abuf->written;
190    INT in_sr = -1;
191    INT in_dr = -1;
192    INT out_dr = -1;
193    in_sr = FLD (in_sr);
194    in_dr = FLD (in_dr);
195    out_dr = FLD (out_dr);
196    referenced |= 1 << 0;
197    referenced |= 1 << 1;
198    referenced |= 1 << 2;
199    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
200  }
201  return cycles;
202#undef FLD
203}
204
205static int
206model_m32r2_xor3 (SIM_CPU *current_cpu, void *sem_arg)
207{
208#define FLD(f) abuf->fields.sfmt_and3.f
209  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
210  const IDESC * UNUSED idesc = abuf->idesc;
211  int cycles = 0;
212  {
213    int referenced = 0;
214    int UNUSED insn_referenced = abuf->written;
215    INT in_sr = -1;
216    INT in_dr = -1;
217    INT out_dr = -1;
218    in_sr = FLD (in_sr);
219    out_dr = FLD (out_dr);
220    referenced |= 1 << 0;
221    referenced |= 1 << 2;
222    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
223  }
224  return cycles;
225#undef FLD
226}
227
228static int
229model_m32r2_addi (SIM_CPU *current_cpu, void *sem_arg)
230{
231#define FLD(f) abuf->fields.sfmt_addi.f
232  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
233  const IDESC * UNUSED idesc = abuf->idesc;
234  int cycles = 0;
235  {
236    int referenced = 0;
237    int UNUSED insn_referenced = abuf->written;
238    INT in_sr = -1;
239    INT in_dr = -1;
240    INT out_dr = -1;
241    in_dr = FLD (in_dr);
242    out_dr = FLD (out_dr);
243    referenced |= 1 << 1;
244    referenced |= 1 << 2;
245    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
246  }
247  return cycles;
248#undef FLD
249}
250
251static int
252model_m32r2_addv (SIM_CPU *current_cpu, void *sem_arg)
253{
254#define FLD(f) abuf->fields.sfmt_add.f
255  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
256  const IDESC * UNUSED idesc = abuf->idesc;
257  int cycles = 0;
258  {
259    int referenced = 0;
260    int UNUSED insn_referenced = abuf->written;
261    INT in_sr = -1;
262    INT in_dr = -1;
263    INT out_dr = -1;
264    in_sr = FLD (in_sr);
265    in_dr = FLD (in_dr);
266    out_dr = FLD (out_dr);
267    referenced |= 1 << 0;
268    referenced |= 1 << 1;
269    referenced |= 1 << 2;
270    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
271  }
272  return cycles;
273#undef FLD
274}
275
276static int
277model_m32r2_addv3 (SIM_CPU *current_cpu, void *sem_arg)
278{
279#define FLD(f) abuf->fields.sfmt_add3.f
280  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
281  const IDESC * UNUSED idesc = abuf->idesc;
282  int cycles = 0;
283  {
284    int referenced = 0;
285    int UNUSED insn_referenced = abuf->written;
286    INT in_sr = -1;
287    INT in_dr = -1;
288    INT out_dr = -1;
289    in_sr = FLD (in_sr);
290    out_dr = FLD (out_dr);
291    referenced |= 1 << 0;
292    referenced |= 1 << 2;
293    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
294  }
295  return cycles;
296#undef FLD
297}
298
299static int
300model_m32r2_addx (SIM_CPU *current_cpu, void *sem_arg)
301{
302#define FLD(f) abuf->fields.sfmt_add.f
303  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
304  const IDESC * UNUSED idesc = abuf->idesc;
305  int cycles = 0;
306  {
307    int referenced = 0;
308    int UNUSED insn_referenced = abuf->written;
309    INT in_sr = -1;
310    INT in_dr = -1;
311    INT out_dr = -1;
312    in_sr = FLD (in_sr);
313    in_dr = FLD (in_dr);
314    out_dr = FLD (out_dr);
315    referenced |= 1 << 0;
316    referenced |= 1 << 1;
317    referenced |= 1 << 2;
318    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
319  }
320  return cycles;
321#undef FLD
322}
323
324static int
325model_m32r2_bc8 (SIM_CPU *current_cpu, void *sem_arg)
326{
327#define FLD(f) abuf->fields.sfmt_bl8.f
328  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
329  const IDESC * UNUSED idesc = abuf->idesc;
330  int cycles = 0;
331  {
332    int referenced = 0;
333    int UNUSED insn_referenced = abuf->written;
334    INT in_sr = -1;
335    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
336    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
337  }
338  return cycles;
339#undef FLD
340}
341
342static int
343model_m32r2_bc24 (SIM_CPU *current_cpu, void *sem_arg)
344{
345#define FLD(f) abuf->fields.sfmt_bl24.f
346  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
347  const IDESC * UNUSED idesc = abuf->idesc;
348  int cycles = 0;
349  {
350    int referenced = 0;
351    int UNUSED insn_referenced = abuf->written;
352    INT in_sr = -1;
353    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
354    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
355  }
356  return cycles;
357#undef FLD
358}
359
360static int
361model_m32r2_beq (SIM_CPU *current_cpu, void *sem_arg)
362{
363#define FLD(f) abuf->fields.sfmt_beq.f
364  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
365  const IDESC * UNUSED idesc = abuf->idesc;
366  int cycles = 0;
367  {
368    int referenced = 0;
369    int UNUSED insn_referenced = abuf->written;
370    INT in_sr = -1;
371    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
372    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
373  }
374  {
375    int referenced = 0;
376    int UNUSED insn_referenced = abuf->written;
377    INT in_src1 = -1;
378    INT in_src2 = -1;
379    in_src1 = FLD (in_src1);
380    in_src2 = FLD (in_src2);
381    referenced |= 1 << 0;
382    referenced |= 1 << 1;
383    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
384  }
385  return cycles;
386#undef FLD
387}
388
389static int
390model_m32r2_beqz (SIM_CPU *current_cpu, void *sem_arg)
391{
392#define FLD(f) abuf->fields.sfmt_beq.f
393  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
394  const IDESC * UNUSED idesc = abuf->idesc;
395  int cycles = 0;
396  {
397    int referenced = 0;
398    int UNUSED insn_referenced = abuf->written;
399    INT in_sr = -1;
400    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
401    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
402  }
403  {
404    int referenced = 0;
405    int UNUSED insn_referenced = abuf->written;
406    INT in_src1 = -1;
407    INT in_src2 = -1;
408    in_src2 = FLD (in_src2);
409    referenced |= 1 << 1;
410    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
411  }
412  return cycles;
413#undef FLD
414}
415
416static int
417model_m32r2_bgez (SIM_CPU *current_cpu, void *sem_arg)
418{
419#define FLD(f) abuf->fields.sfmt_beq.f
420  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
421  const IDESC * UNUSED idesc = abuf->idesc;
422  int cycles = 0;
423  {
424    int referenced = 0;
425    int UNUSED insn_referenced = abuf->written;
426    INT in_sr = -1;
427    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
428    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
429  }
430  {
431    int referenced = 0;
432    int UNUSED insn_referenced = abuf->written;
433    INT in_src1 = -1;
434    INT in_src2 = -1;
435    in_src2 = FLD (in_src2);
436    referenced |= 1 << 1;
437    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
438  }
439  return cycles;
440#undef FLD
441}
442
443static int
444model_m32r2_bgtz (SIM_CPU *current_cpu, void *sem_arg)
445{
446#define FLD(f) abuf->fields.sfmt_beq.f
447  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
448  const IDESC * UNUSED idesc = abuf->idesc;
449  int cycles = 0;
450  {
451    int referenced = 0;
452    int UNUSED insn_referenced = abuf->written;
453    INT in_sr = -1;
454    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
455    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
456  }
457  {
458    int referenced = 0;
459    int UNUSED insn_referenced = abuf->written;
460    INT in_src1 = -1;
461    INT in_src2 = -1;
462    in_src2 = FLD (in_src2);
463    referenced |= 1 << 1;
464    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
465  }
466  return cycles;
467#undef FLD
468}
469
470static int
471model_m32r2_blez (SIM_CPU *current_cpu, void *sem_arg)
472{
473#define FLD(f) abuf->fields.sfmt_beq.f
474  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
475  const IDESC * UNUSED idesc = abuf->idesc;
476  int cycles = 0;
477  {
478    int referenced = 0;
479    int UNUSED insn_referenced = abuf->written;
480    INT in_sr = -1;
481    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
482    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
483  }
484  {
485    int referenced = 0;
486    int UNUSED insn_referenced = abuf->written;
487    INT in_src1 = -1;
488    INT in_src2 = -1;
489    in_src2 = FLD (in_src2);
490    referenced |= 1 << 1;
491    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
492  }
493  return cycles;
494#undef FLD
495}
496
497static int
498model_m32r2_bltz (SIM_CPU *current_cpu, void *sem_arg)
499{
500#define FLD(f) abuf->fields.sfmt_beq.f
501  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
502  const IDESC * UNUSED idesc = abuf->idesc;
503  int cycles = 0;
504  {
505    int referenced = 0;
506    int UNUSED insn_referenced = abuf->written;
507    INT in_sr = -1;
508    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
509    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
510  }
511  {
512    int referenced = 0;
513    int UNUSED insn_referenced = abuf->written;
514    INT in_src1 = -1;
515    INT in_src2 = -1;
516    in_src2 = FLD (in_src2);
517    referenced |= 1 << 1;
518    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
519  }
520  return cycles;
521#undef FLD
522}
523
524static int
525model_m32r2_bnez (SIM_CPU *current_cpu, void *sem_arg)
526{
527#define FLD(f) abuf->fields.sfmt_beq.f
528  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
529  const IDESC * UNUSED idesc = abuf->idesc;
530  int cycles = 0;
531  {
532    int referenced = 0;
533    int UNUSED insn_referenced = abuf->written;
534    INT in_sr = -1;
535    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
536    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
537  }
538  {
539    int referenced = 0;
540    int UNUSED insn_referenced = abuf->written;
541    INT in_src1 = -1;
542    INT in_src2 = -1;
543    in_src2 = FLD (in_src2);
544    referenced |= 1 << 1;
545    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
546  }
547  return cycles;
548#undef FLD
549}
550
551static int
552model_m32r2_bl8 (SIM_CPU *current_cpu, void *sem_arg)
553{
554#define FLD(f) abuf->fields.sfmt_bl8.f
555  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
556  const IDESC * UNUSED idesc = abuf->idesc;
557  int cycles = 0;
558  {
559    int referenced = 0;
560    int UNUSED insn_referenced = abuf->written;
561    INT in_sr = -1;
562    referenced |= 1 << 1;
563    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
564  }
565  return cycles;
566#undef FLD
567}
568
569static int
570model_m32r2_bl24 (SIM_CPU *current_cpu, void *sem_arg)
571{
572#define FLD(f) abuf->fields.sfmt_bl24.f
573  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
574  const IDESC * UNUSED idesc = abuf->idesc;
575  int cycles = 0;
576  {
577    int referenced = 0;
578    int UNUSED insn_referenced = abuf->written;
579    INT in_sr = -1;
580    referenced |= 1 << 1;
581    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
582  }
583  return cycles;
584#undef FLD
585}
586
587static int
588model_m32r2_bcl8 (SIM_CPU *current_cpu, void *sem_arg)
589{
590#define FLD(f) abuf->fields.sfmt_bl8.f
591  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
592  const IDESC * UNUSED idesc = abuf->idesc;
593  int cycles = 0;
594  {
595    int referenced = 0;
596    int UNUSED insn_referenced = abuf->written;
597    INT in_sr = -1;
598    if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
599    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
600  }
601  return cycles;
602#undef FLD
603}
604
605static int
606model_m32r2_bcl24 (SIM_CPU *current_cpu, void *sem_arg)
607{
608#define FLD(f) abuf->fields.sfmt_bl24.f
609  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
610  const IDESC * UNUSED idesc = abuf->idesc;
611  int cycles = 0;
612  {
613    int referenced = 0;
614    int UNUSED insn_referenced = abuf->written;
615    INT in_sr = -1;
616    if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
617    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
618  }
619  return cycles;
620#undef FLD
621}
622
623static int
624model_m32r2_bnc8 (SIM_CPU *current_cpu, void *sem_arg)
625{
626#define FLD(f) abuf->fields.sfmt_bl8.f
627  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
628  const IDESC * UNUSED idesc = abuf->idesc;
629  int cycles = 0;
630  {
631    int referenced = 0;
632    int UNUSED insn_referenced = abuf->written;
633    INT in_sr = -1;
634    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
635    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
636  }
637  return cycles;
638#undef FLD
639}
640
641static int
642model_m32r2_bnc24 (SIM_CPU *current_cpu, void *sem_arg)
643{
644#define FLD(f) abuf->fields.sfmt_bl24.f
645  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
646  const IDESC * UNUSED idesc = abuf->idesc;
647  int cycles = 0;
648  {
649    int referenced = 0;
650    int UNUSED insn_referenced = abuf->written;
651    INT in_sr = -1;
652    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
653    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
654  }
655  return cycles;
656#undef FLD
657}
658
659static int
660model_m32r2_bne (SIM_CPU *current_cpu, void *sem_arg)
661{
662#define FLD(f) abuf->fields.sfmt_beq.f
663  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
664  const IDESC * UNUSED idesc = abuf->idesc;
665  int cycles = 0;
666  {
667    int referenced = 0;
668    int UNUSED insn_referenced = abuf->written;
669    INT in_sr = -1;
670    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
671    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
672  }
673  {
674    int referenced = 0;
675    int UNUSED insn_referenced = abuf->written;
676    INT in_src1 = -1;
677    INT in_src2 = -1;
678    in_src1 = FLD (in_src1);
679    in_src2 = FLD (in_src2);
680    referenced |= 1 << 0;
681    referenced |= 1 << 1;
682    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
683  }
684  return cycles;
685#undef FLD
686}
687
688static int
689model_m32r2_bra8 (SIM_CPU *current_cpu, void *sem_arg)
690{
691#define FLD(f) abuf->fields.sfmt_bl8.f
692  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
693  const IDESC * UNUSED idesc = abuf->idesc;
694  int cycles = 0;
695  {
696    int referenced = 0;
697    int UNUSED insn_referenced = abuf->written;
698    INT in_sr = -1;
699    referenced |= 1 << 1;
700    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
701  }
702  return cycles;
703#undef FLD
704}
705
706static int
707model_m32r2_bra24 (SIM_CPU *current_cpu, void *sem_arg)
708{
709#define FLD(f) abuf->fields.sfmt_bl24.f
710  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
711  const IDESC * UNUSED idesc = abuf->idesc;
712  int cycles = 0;
713  {
714    int referenced = 0;
715    int UNUSED insn_referenced = abuf->written;
716    INT in_sr = -1;
717    referenced |= 1 << 1;
718    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
719  }
720  return cycles;
721#undef FLD
722}
723
724static int
725model_m32r2_bncl8 (SIM_CPU *current_cpu, void *sem_arg)
726{
727#define FLD(f) abuf->fields.sfmt_bl8.f
728  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
729  const IDESC * UNUSED idesc = abuf->idesc;
730  int cycles = 0;
731  {
732    int referenced = 0;
733    int UNUSED insn_referenced = abuf->written;
734    INT in_sr = -1;
735    if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
736    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
737  }
738  return cycles;
739#undef FLD
740}
741
742static int
743model_m32r2_bncl24 (SIM_CPU *current_cpu, void *sem_arg)
744{
745#define FLD(f) abuf->fields.sfmt_bl24.f
746  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
747  const IDESC * UNUSED idesc = abuf->idesc;
748  int cycles = 0;
749  {
750    int referenced = 0;
751    int UNUSED insn_referenced = abuf->written;
752    INT in_sr = -1;
753    if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
754    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
755  }
756  return cycles;
757#undef FLD
758}
759
760static int
761model_m32r2_cmp (SIM_CPU *current_cpu, void *sem_arg)
762{
763#define FLD(f) abuf->fields.sfmt_st_plus.f
764  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
765  const IDESC * UNUSED idesc = abuf->idesc;
766  int cycles = 0;
767  {
768    int referenced = 0;
769    int UNUSED insn_referenced = abuf->written;
770    INT in_src1 = -1;
771    INT in_src2 = -1;
772    in_src1 = FLD (in_src1);
773    in_src2 = FLD (in_src2);
774    referenced |= 1 << 0;
775    referenced |= 1 << 1;
776    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
777  }
778  return cycles;
779#undef FLD
780}
781
782static int
783model_m32r2_cmpi (SIM_CPU *current_cpu, void *sem_arg)
784{
785#define FLD(f) abuf->fields.sfmt_st_d.f
786  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
787  const IDESC * UNUSED idesc = abuf->idesc;
788  int cycles = 0;
789  {
790    int referenced = 0;
791    int UNUSED insn_referenced = abuf->written;
792    INT in_src1 = -1;
793    INT in_src2 = -1;
794    in_src2 = FLD (in_src2);
795    referenced |= 1 << 1;
796    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
797  }
798  return cycles;
799#undef FLD
800}
801
802static int
803model_m32r2_cmpu (SIM_CPU *current_cpu, void *sem_arg)
804{
805#define FLD(f) abuf->fields.sfmt_st_plus.f
806  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
807  const IDESC * UNUSED idesc = abuf->idesc;
808  int cycles = 0;
809  {
810    int referenced = 0;
811    int UNUSED insn_referenced = abuf->written;
812    INT in_src1 = -1;
813    INT in_src2 = -1;
814    in_src1 = FLD (in_src1);
815    in_src2 = FLD (in_src2);
816    referenced |= 1 << 0;
817    referenced |= 1 << 1;
818    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
819  }
820  return cycles;
821#undef FLD
822}
823
824static int
825model_m32r2_cmpui (SIM_CPU *current_cpu, void *sem_arg)
826{
827#define FLD(f) abuf->fields.sfmt_st_d.f
828  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
829  const IDESC * UNUSED idesc = abuf->idesc;
830  int cycles = 0;
831  {
832    int referenced = 0;
833    int UNUSED insn_referenced = abuf->written;
834    INT in_src1 = -1;
835    INT in_src2 = -1;
836    in_src2 = FLD (in_src2);
837    referenced |= 1 << 1;
838    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
839  }
840  return cycles;
841#undef FLD
842}
843
844static int
845model_m32r2_cmpeq (SIM_CPU *current_cpu, void *sem_arg)
846{
847#define FLD(f) abuf->fields.sfmt_st_plus.f
848  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
849  const IDESC * UNUSED idesc = abuf->idesc;
850  int cycles = 0;
851  {
852    int referenced = 0;
853    int UNUSED insn_referenced = abuf->written;
854    INT in_src1 = -1;
855    INT in_src2 = -1;
856    in_src1 = FLD (in_src1);
857    in_src2 = FLD (in_src2);
858    referenced |= 1 << 0;
859    referenced |= 1 << 1;
860    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
861  }
862  return cycles;
863#undef FLD
864}
865
866static int
867model_m32r2_cmpz (SIM_CPU *current_cpu, void *sem_arg)
868{
869#define FLD(f) abuf->fields.sfmt_st_plus.f
870  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
871  const IDESC * UNUSED idesc = abuf->idesc;
872  int cycles = 0;
873  {
874    int referenced = 0;
875    int UNUSED insn_referenced = abuf->written;
876    INT in_src1 = -1;
877    INT in_src2 = -1;
878    in_src2 = FLD (in_src2);
879    referenced |= 1 << 1;
880    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
881  }
882  return cycles;
883#undef FLD
884}
885
886static int
887model_m32r2_div (SIM_CPU *current_cpu, void *sem_arg)
888{
889#define FLD(f) abuf->fields.sfmt_add.f
890  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
891  const IDESC * UNUSED idesc = abuf->idesc;
892  int cycles = 0;
893  {
894    int referenced = 0;
895    int UNUSED insn_referenced = abuf->written;
896    INT in_sr = -1;
897    INT in_dr = -1;
898    INT out_dr = -1;
899    in_sr = FLD (in_sr);
900    in_dr = FLD (in_dr);
901    out_dr = FLD (out_dr);
902    referenced |= 1 << 0;
903    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
904    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
905    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
906  }
907  return cycles;
908#undef FLD
909}
910
911static int
912model_m32r2_divu (SIM_CPU *current_cpu, void *sem_arg)
913{
914#define FLD(f) abuf->fields.sfmt_add.f
915  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
916  const IDESC * UNUSED idesc = abuf->idesc;
917  int cycles = 0;
918  {
919    int referenced = 0;
920    int UNUSED insn_referenced = abuf->written;
921    INT in_sr = -1;
922    INT in_dr = -1;
923    INT out_dr = -1;
924    in_sr = FLD (in_sr);
925    in_dr = FLD (in_dr);
926    out_dr = FLD (out_dr);
927    referenced |= 1 << 0;
928    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
929    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
930    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
931  }
932  return cycles;
933#undef FLD
934}
935
936static int
937model_m32r2_rem (SIM_CPU *current_cpu, void *sem_arg)
938{
939#define FLD(f) abuf->fields.sfmt_add.f
940  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
941  const IDESC * UNUSED idesc = abuf->idesc;
942  int cycles = 0;
943  {
944    int referenced = 0;
945    int UNUSED insn_referenced = abuf->written;
946    INT in_sr = -1;
947    INT in_dr = -1;
948    INT out_dr = -1;
949    in_sr = FLD (in_sr);
950    in_dr = FLD (in_dr);
951    out_dr = FLD (out_dr);
952    referenced |= 1 << 0;
953    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
954    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
955    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
956  }
957  return cycles;
958#undef FLD
959}
960
961static int
962model_m32r2_remu (SIM_CPU *current_cpu, void *sem_arg)
963{
964#define FLD(f) abuf->fields.sfmt_add.f
965  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
966  const IDESC * UNUSED idesc = abuf->idesc;
967  int cycles = 0;
968  {
969    int referenced = 0;
970    int UNUSED insn_referenced = abuf->written;
971    INT in_sr = -1;
972    INT in_dr = -1;
973    INT out_dr = -1;
974    in_sr = FLD (in_sr);
975    in_dr = FLD (in_dr);
976    out_dr = FLD (out_dr);
977    referenced |= 1 << 0;
978    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
979    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
980    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
981  }
982  return cycles;
983#undef FLD
984}
985
986static int
987model_m32r2_remh (SIM_CPU *current_cpu, void *sem_arg)
988{
989#define FLD(f) abuf->fields.sfmt_add.f
990  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
991  const IDESC * UNUSED idesc = abuf->idesc;
992  int cycles = 0;
993  {
994    int referenced = 0;
995    int UNUSED insn_referenced = abuf->written;
996    INT in_sr = -1;
997    INT in_dr = -1;
998    INT out_dr = -1;
999    in_sr = FLD (in_sr);
1000    in_dr = FLD (in_dr);
1001    out_dr = FLD (out_dr);
1002    referenced |= 1 << 0;
1003    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
1004    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
1005    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1006  }
1007  return cycles;
1008#undef FLD
1009}
1010
1011static int
1012model_m32r2_remuh (SIM_CPU *current_cpu, void *sem_arg)
1013{
1014#define FLD(f) abuf->fields.sfmt_add.f
1015  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1016  const IDESC * UNUSED idesc = abuf->idesc;
1017  int cycles = 0;
1018  {
1019    int referenced = 0;
1020    int UNUSED insn_referenced = abuf->written;
1021    INT in_sr = -1;
1022    INT in_dr = -1;
1023    INT out_dr = -1;
1024    in_sr = FLD (in_sr);
1025    in_dr = FLD (in_dr);
1026    out_dr = FLD (out_dr);
1027    referenced |= 1 << 0;
1028    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
1029    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
1030    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1031  }
1032  return cycles;
1033#undef FLD
1034}
1035
1036static int
1037model_m32r2_remb (SIM_CPU *current_cpu, void *sem_arg)
1038{
1039#define FLD(f) abuf->fields.sfmt_add.f
1040  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1041  const IDESC * UNUSED idesc = abuf->idesc;
1042  int cycles = 0;
1043  {
1044    int referenced = 0;
1045    int UNUSED insn_referenced = abuf->written;
1046    INT in_sr = -1;
1047    INT in_dr = -1;
1048    INT out_dr = -1;
1049    in_sr = FLD (in_sr);
1050    in_dr = FLD (in_dr);
1051    out_dr = FLD (out_dr);
1052    referenced |= 1 << 0;
1053    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
1054    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
1055    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1056  }
1057  return cycles;
1058#undef FLD
1059}
1060
1061static int
1062model_m32r2_remub (SIM_CPU *current_cpu, void *sem_arg)
1063{
1064#define FLD(f) abuf->fields.sfmt_add.f
1065  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1066  const IDESC * UNUSED idesc = abuf->idesc;
1067  int cycles = 0;
1068  {
1069    int referenced = 0;
1070    int UNUSED insn_referenced = abuf->written;
1071    INT in_sr = -1;
1072    INT in_dr = -1;
1073    INT out_dr = -1;
1074    in_sr = FLD (in_sr);
1075    in_dr = FLD (in_dr);
1076    out_dr = FLD (out_dr);
1077    referenced |= 1 << 0;
1078    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
1079    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
1080    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1081  }
1082  return cycles;
1083#undef FLD
1084}
1085
1086static int
1087model_m32r2_divuh (SIM_CPU *current_cpu, void *sem_arg)
1088{
1089#define FLD(f) abuf->fields.sfmt_add.f
1090  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1091  const IDESC * UNUSED idesc = abuf->idesc;
1092  int cycles = 0;
1093  {
1094    int referenced = 0;
1095    int UNUSED insn_referenced = abuf->written;
1096    INT in_sr = -1;
1097    INT in_dr = -1;
1098    INT out_dr = -1;
1099    in_sr = FLD (in_sr);
1100    in_dr = FLD (in_dr);
1101    out_dr = FLD (out_dr);
1102    referenced |= 1 << 0;
1103    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
1104    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
1105    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1106  }
1107  return cycles;
1108#undef FLD
1109}
1110
1111static int
1112model_m32r2_divb (SIM_CPU *current_cpu, void *sem_arg)
1113{
1114#define FLD(f) abuf->fields.sfmt_add.f
1115  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1116  const IDESC * UNUSED idesc = abuf->idesc;
1117  int cycles = 0;
1118  {
1119    int referenced = 0;
1120    int UNUSED insn_referenced = abuf->written;
1121    INT in_sr = -1;
1122    INT in_dr = -1;
1123    INT out_dr = -1;
1124    in_sr = FLD (in_sr);
1125    in_dr = FLD (in_dr);
1126    out_dr = FLD (out_dr);
1127    referenced |= 1 << 0;
1128    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
1129    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
1130    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1131  }
1132  return cycles;
1133#undef FLD
1134}
1135
1136static int
1137model_m32r2_divub (SIM_CPU *current_cpu, void *sem_arg)
1138{
1139#define FLD(f) abuf->fields.sfmt_add.f
1140  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1141  const IDESC * UNUSED idesc = abuf->idesc;
1142  int cycles = 0;
1143  {
1144    int referenced = 0;
1145    int UNUSED insn_referenced = abuf->written;
1146    INT in_sr = -1;
1147    INT in_dr = -1;
1148    INT out_dr = -1;
1149    in_sr = FLD (in_sr);
1150    in_dr = FLD (in_dr);
1151    out_dr = FLD (out_dr);
1152    referenced |= 1 << 0;
1153    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
1154    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
1155    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1156  }
1157  return cycles;
1158#undef FLD
1159}
1160
1161static int
1162model_m32r2_divh (SIM_CPU *current_cpu, void *sem_arg)
1163{
1164#define FLD(f) abuf->fields.sfmt_add.f
1165  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1166  const IDESC * UNUSED idesc = abuf->idesc;
1167  int cycles = 0;
1168  {
1169    int referenced = 0;
1170    int UNUSED insn_referenced = abuf->written;
1171    INT in_sr = -1;
1172    INT in_dr = -1;
1173    INT out_dr = -1;
1174    in_sr = FLD (in_sr);
1175    in_dr = FLD (in_dr);
1176    out_dr = FLD (out_dr);
1177    referenced |= 1 << 0;
1178    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
1179    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
1180    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1181  }
1182  return cycles;
1183#undef FLD
1184}
1185
1186static int
1187model_m32r2_jc (SIM_CPU *current_cpu, void *sem_arg)
1188{
1189#define FLD(f) abuf->fields.sfmt_jl.f
1190  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1191  const IDESC * UNUSED idesc = abuf->idesc;
1192  int cycles = 0;
1193  {
1194    int referenced = 0;
1195    int UNUSED insn_referenced = abuf->written;
1196    INT in_sr = -1;
1197    in_sr = FLD (in_sr);
1198    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
1199    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
1200    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
1201  }
1202  return cycles;
1203#undef FLD
1204}
1205
1206static int
1207model_m32r2_jnc (SIM_CPU *current_cpu, void *sem_arg)
1208{
1209#define FLD(f) abuf->fields.sfmt_jl.f
1210  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1211  const IDESC * UNUSED idesc = abuf->idesc;
1212  int cycles = 0;
1213  {
1214    int referenced = 0;
1215    int UNUSED insn_referenced = abuf->written;
1216    INT in_sr = -1;
1217    in_sr = FLD (in_sr);
1218    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
1219    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
1220    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
1221  }
1222  return cycles;
1223#undef FLD
1224}
1225
1226static int
1227model_m32r2_jl (SIM_CPU *current_cpu, void *sem_arg)
1228{
1229#define FLD(f) abuf->fields.sfmt_jl.f
1230  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1231  const IDESC * UNUSED idesc = abuf->idesc;
1232  int cycles = 0;
1233  {
1234    int referenced = 0;
1235    int UNUSED insn_referenced = abuf->written;
1236    INT in_sr = -1;
1237    in_sr = FLD (in_sr);
1238    referenced |= 1 << 0;
1239    referenced |= 1 << 1;
1240    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
1241  }
1242  return cycles;
1243#undef FLD
1244}
1245
1246static int
1247model_m32r2_jmp (SIM_CPU *current_cpu, void *sem_arg)
1248{
1249#define FLD(f) abuf->fields.sfmt_jl.f
1250  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1251  const IDESC * UNUSED idesc = abuf->idesc;
1252  int cycles = 0;
1253  {
1254    int referenced = 0;
1255    int UNUSED insn_referenced = abuf->written;
1256    INT in_sr = -1;
1257    in_sr = FLD (in_sr);
1258    referenced |= 1 << 0;
1259    referenced |= 1 << 1;
1260    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
1261  }
1262  return cycles;
1263#undef FLD
1264}
1265
1266static int
1267model_m32r2_ld (SIM_CPU *current_cpu, void *sem_arg)
1268{
1269#define FLD(f) abuf->fields.sfmt_ld_plus.f
1270  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1271  const IDESC * UNUSED idesc = abuf->idesc;
1272  int cycles = 0;
1273  {
1274    int referenced = 0;
1275    int UNUSED insn_referenced = abuf->written;
1276    INT in_sr = 0;
1277    INT out_dr = 0;
1278    in_sr = FLD (in_sr);
1279    out_dr = FLD (out_dr);
1280    referenced |= 1 << 0;
1281    referenced |= 1 << 1;
1282    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1283  }
1284  return cycles;
1285#undef FLD
1286}
1287
1288static int
1289model_m32r2_ld_d (SIM_CPU *current_cpu, void *sem_arg)
1290{
1291#define FLD(f) abuf->fields.sfmt_add3.f
1292  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1293  const IDESC * UNUSED idesc = abuf->idesc;
1294  int cycles = 0;
1295  {
1296    int referenced = 0;
1297    int UNUSED insn_referenced = abuf->written;
1298    INT in_sr = 0;
1299    INT out_dr = 0;
1300    in_sr = FLD (in_sr);
1301    out_dr = FLD (out_dr);
1302    referenced |= 1 << 0;
1303    referenced |= 1 << 1;
1304    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1305  }
1306  return cycles;
1307#undef FLD
1308}
1309
1310static int
1311model_m32r2_ldb (SIM_CPU *current_cpu, void *sem_arg)
1312{
1313#define FLD(f) abuf->fields.sfmt_ld_plus.f
1314  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1315  const IDESC * UNUSED idesc = abuf->idesc;
1316  int cycles = 0;
1317  {
1318    int referenced = 0;
1319    int UNUSED insn_referenced = abuf->written;
1320    INT in_sr = 0;
1321    INT out_dr = 0;
1322    in_sr = FLD (in_sr);
1323    out_dr = FLD (out_dr);
1324    referenced |= 1 << 0;
1325    referenced |= 1 << 1;
1326    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1327  }
1328  return cycles;
1329#undef FLD
1330}
1331
1332static int
1333model_m32r2_ldb_d (SIM_CPU *current_cpu, void *sem_arg)
1334{
1335#define FLD(f) abuf->fields.sfmt_add3.f
1336  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1337  const IDESC * UNUSED idesc = abuf->idesc;
1338  int cycles = 0;
1339  {
1340    int referenced = 0;
1341    int UNUSED insn_referenced = abuf->written;
1342    INT in_sr = 0;
1343    INT out_dr = 0;
1344    in_sr = FLD (in_sr);
1345    out_dr = FLD (out_dr);
1346    referenced |= 1 << 0;
1347    referenced |= 1 << 1;
1348    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1349  }
1350  return cycles;
1351#undef FLD
1352}
1353
1354static int
1355model_m32r2_ldh (SIM_CPU *current_cpu, void *sem_arg)
1356{
1357#define FLD(f) abuf->fields.sfmt_ld_plus.f
1358  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1359  const IDESC * UNUSED idesc = abuf->idesc;
1360  int cycles = 0;
1361  {
1362    int referenced = 0;
1363    int UNUSED insn_referenced = abuf->written;
1364    INT in_sr = 0;
1365    INT out_dr = 0;
1366    in_sr = FLD (in_sr);
1367    out_dr = FLD (out_dr);
1368    referenced |= 1 << 0;
1369    referenced |= 1 << 1;
1370    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1371  }
1372  return cycles;
1373#undef FLD
1374}
1375
1376static int
1377model_m32r2_ldh_d (SIM_CPU *current_cpu, void *sem_arg)
1378{
1379#define FLD(f) abuf->fields.sfmt_add3.f
1380  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1381  const IDESC * UNUSED idesc = abuf->idesc;
1382  int cycles = 0;
1383  {
1384    int referenced = 0;
1385    int UNUSED insn_referenced = abuf->written;
1386    INT in_sr = 0;
1387    INT out_dr = 0;
1388    in_sr = FLD (in_sr);
1389    out_dr = FLD (out_dr);
1390    referenced |= 1 << 0;
1391    referenced |= 1 << 1;
1392    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1393  }
1394  return cycles;
1395#undef FLD
1396}
1397
1398static int
1399model_m32r2_ldub (SIM_CPU *current_cpu, void *sem_arg)
1400{
1401#define FLD(f) abuf->fields.sfmt_ld_plus.f
1402  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1403  const IDESC * UNUSED idesc = abuf->idesc;
1404  int cycles = 0;
1405  {
1406    int referenced = 0;
1407    int UNUSED insn_referenced = abuf->written;
1408    INT in_sr = 0;
1409    INT out_dr = 0;
1410    in_sr = FLD (in_sr);
1411    out_dr = FLD (out_dr);
1412    referenced |= 1 << 0;
1413    referenced |= 1 << 1;
1414    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1415  }
1416  return cycles;
1417#undef FLD
1418}
1419
1420static int
1421model_m32r2_ldub_d (SIM_CPU *current_cpu, void *sem_arg)
1422{
1423#define FLD(f) abuf->fields.sfmt_add3.f
1424  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1425  const IDESC * UNUSED idesc = abuf->idesc;
1426  int cycles = 0;
1427  {
1428    int referenced = 0;
1429    int UNUSED insn_referenced = abuf->written;
1430    INT in_sr = 0;
1431    INT out_dr = 0;
1432    in_sr = FLD (in_sr);
1433    out_dr = FLD (out_dr);
1434    referenced |= 1 << 0;
1435    referenced |= 1 << 1;
1436    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1437  }
1438  return cycles;
1439#undef FLD
1440}
1441
1442static int
1443model_m32r2_lduh (SIM_CPU *current_cpu, void *sem_arg)
1444{
1445#define FLD(f) abuf->fields.sfmt_ld_plus.f
1446  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1447  const IDESC * UNUSED idesc = abuf->idesc;
1448  int cycles = 0;
1449  {
1450    int referenced = 0;
1451    int UNUSED insn_referenced = abuf->written;
1452    INT in_sr = 0;
1453    INT out_dr = 0;
1454    in_sr = FLD (in_sr);
1455    out_dr = FLD (out_dr);
1456    referenced |= 1 << 0;
1457    referenced |= 1 << 1;
1458    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1459  }
1460  return cycles;
1461#undef FLD
1462}
1463
1464static int
1465model_m32r2_lduh_d (SIM_CPU *current_cpu, void *sem_arg)
1466{
1467#define FLD(f) abuf->fields.sfmt_add3.f
1468  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1469  const IDESC * UNUSED idesc = abuf->idesc;
1470  int cycles = 0;
1471  {
1472    int referenced = 0;
1473    int UNUSED insn_referenced = abuf->written;
1474    INT in_sr = 0;
1475    INT out_dr = 0;
1476    in_sr = FLD (in_sr);
1477    out_dr = FLD (out_dr);
1478    referenced |= 1 << 0;
1479    referenced |= 1 << 1;
1480    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1481  }
1482  return cycles;
1483#undef FLD
1484}
1485
1486static int
1487model_m32r2_ld_plus (SIM_CPU *current_cpu, void *sem_arg)
1488{
1489#define FLD(f) abuf->fields.sfmt_ld_plus.f
1490  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1491  const IDESC * UNUSED idesc = abuf->idesc;
1492  int cycles = 0;
1493  {
1494    int referenced = 0;
1495    int UNUSED insn_referenced = abuf->written;
1496    INT in_sr = 0;
1497    INT out_dr = 0;
1498    in_sr = FLD (in_sr);
1499    out_dr = FLD (out_dr);
1500    referenced |= 1 << 0;
1501    referenced |= 1 << 1;
1502    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1503  }
1504  {
1505    int referenced = 0;
1506    int UNUSED insn_referenced = abuf->written;
1507    INT in_sr = -1;
1508    INT in_dr = -1;
1509    INT out_dr = -1;
1510    in_dr = FLD (in_sr);
1511    out_dr = FLD (out_sr);
1512    referenced |= 1 << 0;
1513    referenced |= 1 << 2;
1514    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
1515  }
1516  return cycles;
1517#undef FLD
1518}
1519
1520static int
1521model_m32r2_ld24 (SIM_CPU *current_cpu, void *sem_arg)
1522{
1523#define FLD(f) abuf->fields.sfmt_ld24.f
1524  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1525  const IDESC * UNUSED idesc = abuf->idesc;
1526  int cycles = 0;
1527  {
1528    int referenced = 0;
1529    int UNUSED insn_referenced = abuf->written;
1530    INT in_sr = -1;
1531    INT in_dr = -1;
1532    INT out_dr = -1;
1533    out_dr = FLD (out_dr);
1534    referenced |= 1 << 2;
1535    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1536  }
1537  return cycles;
1538#undef FLD
1539}
1540
1541static int
1542model_m32r2_ldi8 (SIM_CPU *current_cpu, void *sem_arg)
1543{
1544#define FLD(f) abuf->fields.sfmt_addi.f
1545  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1546  const IDESC * UNUSED idesc = abuf->idesc;
1547  int cycles = 0;
1548  {
1549    int referenced = 0;
1550    int UNUSED insn_referenced = abuf->written;
1551    INT in_sr = -1;
1552    INT in_dr = -1;
1553    INT out_dr = -1;
1554    out_dr = FLD (out_dr);
1555    referenced |= 1 << 2;
1556    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1557  }
1558  return cycles;
1559#undef FLD
1560}
1561
1562static int
1563model_m32r2_ldi16 (SIM_CPU *current_cpu, void *sem_arg)
1564{
1565#define FLD(f) abuf->fields.sfmt_add3.f
1566  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1567  const IDESC * UNUSED idesc = abuf->idesc;
1568  int cycles = 0;
1569  {
1570    int referenced = 0;
1571    int UNUSED insn_referenced = abuf->written;
1572    INT in_sr = -1;
1573    INT in_dr = -1;
1574    INT out_dr = -1;
1575    out_dr = FLD (out_dr);
1576    referenced |= 1 << 2;
1577    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1578  }
1579  return cycles;
1580#undef FLD
1581}
1582
1583static int
1584model_m32r2_lock (SIM_CPU *current_cpu, void *sem_arg)
1585{
1586#define FLD(f) abuf->fields.sfmt_ld_plus.f
1587  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1588  const IDESC * UNUSED idesc = abuf->idesc;
1589  int cycles = 0;
1590  {
1591    int referenced = 0;
1592    int UNUSED insn_referenced = abuf->written;
1593    INT in_sr = 0;
1594    INT out_dr = 0;
1595    in_sr = FLD (in_sr);
1596    out_dr = FLD (out_dr);
1597    referenced |= 1 << 0;
1598    referenced |= 1 << 1;
1599    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1600  }
1601  return cycles;
1602#undef FLD
1603}
1604
1605static int
1606model_m32r2_machi_a (SIM_CPU *current_cpu, void *sem_arg)
1607{
1608#define FLD(f) abuf->fields.sfmt_machi_a.f
1609  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1610  const IDESC * UNUSED idesc = abuf->idesc;
1611  int cycles = 0;
1612  {
1613    int referenced = 0;
1614    int UNUSED insn_referenced = abuf->written;
1615    INT in_src1 = -1;
1616    INT in_src2 = -1;
1617    in_src1 = FLD (in_src1);
1618    in_src2 = FLD (in_src2);
1619    referenced |= 1 << 0;
1620    referenced |= 1 << 1;
1621    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1622  }
1623  return cycles;
1624#undef FLD
1625}
1626
1627static int
1628model_m32r2_maclo_a (SIM_CPU *current_cpu, void *sem_arg)
1629{
1630#define FLD(f) abuf->fields.sfmt_machi_a.f
1631  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1632  const IDESC * UNUSED idesc = abuf->idesc;
1633  int cycles = 0;
1634  {
1635    int referenced = 0;
1636    int UNUSED insn_referenced = abuf->written;
1637    INT in_src1 = -1;
1638    INT in_src2 = -1;
1639    in_src1 = FLD (in_src1);
1640    in_src2 = FLD (in_src2);
1641    referenced |= 1 << 0;
1642    referenced |= 1 << 1;
1643    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1644  }
1645  return cycles;
1646#undef FLD
1647}
1648
1649static int
1650model_m32r2_macwhi_a (SIM_CPU *current_cpu, void *sem_arg)
1651{
1652#define FLD(f) abuf->fields.sfmt_machi_a.f
1653  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1654  const IDESC * UNUSED idesc = abuf->idesc;
1655  int cycles = 0;
1656  {
1657    int referenced = 0;
1658    int UNUSED insn_referenced = abuf->written;
1659    INT in_src1 = -1;
1660    INT in_src2 = -1;
1661    in_src1 = FLD (in_src1);
1662    in_src2 = FLD (in_src2);
1663    referenced |= 1 << 0;
1664    referenced |= 1 << 1;
1665    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1666  }
1667  return cycles;
1668#undef FLD
1669}
1670
1671static int
1672model_m32r2_macwlo_a (SIM_CPU *current_cpu, void *sem_arg)
1673{
1674#define FLD(f) abuf->fields.sfmt_machi_a.f
1675  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1676  const IDESC * UNUSED idesc = abuf->idesc;
1677  int cycles = 0;
1678  {
1679    int referenced = 0;
1680    int UNUSED insn_referenced = abuf->written;
1681    INT in_src1 = -1;
1682    INT in_src2 = -1;
1683    in_src1 = FLD (in_src1);
1684    in_src2 = FLD (in_src2);
1685    referenced |= 1 << 0;
1686    referenced |= 1 << 1;
1687    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1688  }
1689  return cycles;
1690#undef FLD
1691}
1692
1693static int
1694model_m32r2_mul (SIM_CPU *current_cpu, void *sem_arg)
1695{
1696#define FLD(f) abuf->fields.sfmt_add.f
1697  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1698  const IDESC * UNUSED idesc = abuf->idesc;
1699  int cycles = 0;
1700  {
1701    int referenced = 0;
1702    int UNUSED insn_referenced = abuf->written;
1703    INT in_sr = -1;
1704    INT in_dr = -1;
1705    INT out_dr = -1;
1706    in_sr = FLD (in_sr);
1707    in_dr = FLD (in_dr);
1708    out_dr = FLD (out_dr);
1709    referenced |= 1 << 0;
1710    referenced |= 1 << 1;
1711    referenced |= 1 << 2;
1712    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1713  }
1714  return cycles;
1715#undef FLD
1716}
1717
1718static int
1719model_m32r2_mulhi_a (SIM_CPU *current_cpu, void *sem_arg)
1720{
1721#define FLD(f) abuf->fields.sfmt_machi_a.f
1722  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1723  const IDESC * UNUSED idesc = abuf->idesc;
1724  int cycles = 0;
1725  {
1726    int referenced = 0;
1727    int UNUSED insn_referenced = abuf->written;
1728    INT in_src1 = -1;
1729    INT in_src2 = -1;
1730    in_src1 = FLD (in_src1);
1731    in_src2 = FLD (in_src2);
1732    referenced |= 1 << 0;
1733    referenced |= 1 << 1;
1734    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1735  }
1736  return cycles;
1737#undef FLD
1738}
1739
1740static int
1741model_m32r2_mullo_a (SIM_CPU *current_cpu, void *sem_arg)
1742{
1743#define FLD(f) abuf->fields.sfmt_machi_a.f
1744  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1745  const IDESC * UNUSED idesc = abuf->idesc;
1746  int cycles = 0;
1747  {
1748    int referenced = 0;
1749    int UNUSED insn_referenced = abuf->written;
1750    INT in_src1 = -1;
1751    INT in_src2 = -1;
1752    in_src1 = FLD (in_src1);
1753    in_src2 = FLD (in_src2);
1754    referenced |= 1 << 0;
1755    referenced |= 1 << 1;
1756    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1757  }
1758  return cycles;
1759#undef FLD
1760}
1761
1762static int
1763model_m32r2_mulwhi_a (SIM_CPU *current_cpu, void *sem_arg)
1764{
1765#define FLD(f) abuf->fields.sfmt_machi_a.f
1766  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1767  const IDESC * UNUSED idesc = abuf->idesc;
1768  int cycles = 0;
1769  {
1770    int referenced = 0;
1771    int UNUSED insn_referenced = abuf->written;
1772    INT in_src1 = -1;
1773    INT in_src2 = -1;
1774    in_src1 = FLD (in_src1);
1775    in_src2 = FLD (in_src2);
1776    referenced |= 1 << 0;
1777    referenced |= 1 << 1;
1778    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1779  }
1780  return cycles;
1781#undef FLD
1782}
1783
1784static int
1785model_m32r2_mulwlo_a (SIM_CPU *current_cpu, void *sem_arg)
1786{
1787#define FLD(f) abuf->fields.sfmt_machi_a.f
1788  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1789  const IDESC * UNUSED idesc = abuf->idesc;
1790  int cycles = 0;
1791  {
1792    int referenced = 0;
1793    int UNUSED insn_referenced = abuf->written;
1794    INT in_src1 = -1;
1795    INT in_src2 = -1;
1796    in_src1 = FLD (in_src1);
1797    in_src2 = FLD (in_src2);
1798    referenced |= 1 << 0;
1799    referenced |= 1 << 1;
1800    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1801  }
1802  return cycles;
1803#undef FLD
1804}
1805
1806static int
1807model_m32r2_mv (SIM_CPU *current_cpu, void *sem_arg)
1808{
1809#define FLD(f) abuf->fields.sfmt_ld_plus.f
1810  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1811  const IDESC * UNUSED idesc = abuf->idesc;
1812  int cycles = 0;
1813  {
1814    int referenced = 0;
1815    int UNUSED insn_referenced = abuf->written;
1816    INT in_sr = -1;
1817    INT in_dr = -1;
1818    INT out_dr = -1;
1819    in_sr = FLD (in_sr);
1820    out_dr = FLD (out_dr);
1821    referenced |= 1 << 0;
1822    referenced |= 1 << 2;
1823    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1824  }
1825  return cycles;
1826#undef FLD
1827}
1828
1829static int
1830model_m32r2_mvfachi_a (SIM_CPU *current_cpu, void *sem_arg)
1831{
1832#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
1833  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1834  const IDESC * UNUSED idesc = abuf->idesc;
1835  int cycles = 0;
1836  {
1837    int referenced = 0;
1838    int UNUSED insn_referenced = abuf->written;
1839    INT in_sr = -1;
1840    INT in_dr = -1;
1841    INT out_dr = -1;
1842    out_dr = FLD (out_dr);
1843    referenced |= 1 << 2;
1844    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1845  }
1846  return cycles;
1847#undef FLD
1848}
1849
1850static int
1851model_m32r2_mvfaclo_a (SIM_CPU *current_cpu, void *sem_arg)
1852{
1853#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
1854  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1855  const IDESC * UNUSED idesc = abuf->idesc;
1856  int cycles = 0;
1857  {
1858    int referenced = 0;
1859    int UNUSED insn_referenced = abuf->written;
1860    INT in_sr = -1;
1861    INT in_dr = -1;
1862    INT out_dr = -1;
1863    out_dr = FLD (out_dr);
1864    referenced |= 1 << 2;
1865    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1866  }
1867  return cycles;
1868#undef FLD
1869}
1870
1871static int
1872model_m32r2_mvfacmi_a (SIM_CPU *current_cpu, void *sem_arg)
1873{
1874#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
1875  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1876  const IDESC * UNUSED idesc = abuf->idesc;
1877  int cycles = 0;
1878  {
1879    int referenced = 0;
1880    int UNUSED insn_referenced = abuf->written;
1881    INT in_sr = -1;
1882    INT in_dr = -1;
1883    INT out_dr = -1;
1884    out_dr = FLD (out_dr);
1885    referenced |= 1 << 2;
1886    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1887  }
1888  return cycles;
1889#undef FLD
1890}
1891
1892static int
1893model_m32r2_mvfc (SIM_CPU *current_cpu, void *sem_arg)
1894{
1895#define FLD(f) abuf->fields.sfmt_ld_plus.f
1896  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1897  const IDESC * UNUSED idesc = abuf->idesc;
1898  int cycles = 0;
1899  {
1900    int referenced = 0;
1901    int UNUSED insn_referenced = abuf->written;
1902    INT in_sr = -1;
1903    INT in_dr = -1;
1904    INT out_dr = -1;
1905    out_dr = FLD (out_dr);
1906    referenced |= 1 << 2;
1907    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1908  }
1909  return cycles;
1910#undef FLD
1911}
1912
1913static int
1914model_m32r2_mvtachi_a (SIM_CPU *current_cpu, void *sem_arg)
1915{
1916#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
1917  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1918  const IDESC * UNUSED idesc = abuf->idesc;
1919  int cycles = 0;
1920  {
1921    int referenced = 0;
1922    int UNUSED insn_referenced = abuf->written;
1923    INT in_sr = -1;
1924    INT in_dr = -1;
1925    INT out_dr = -1;
1926    in_sr = FLD (in_src1);
1927    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1928  }
1929  return cycles;
1930#undef FLD
1931}
1932
1933static int
1934model_m32r2_mvtaclo_a (SIM_CPU *current_cpu, void *sem_arg)
1935{
1936#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
1937  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1938  const IDESC * UNUSED idesc = abuf->idesc;
1939  int cycles = 0;
1940  {
1941    int referenced = 0;
1942    int UNUSED insn_referenced = abuf->written;
1943    INT in_sr = -1;
1944    INT in_dr = -1;
1945    INT out_dr = -1;
1946    in_sr = FLD (in_src1);
1947    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1948  }
1949  return cycles;
1950#undef FLD
1951}
1952
1953static int
1954model_m32r2_mvtc (SIM_CPU *current_cpu, void *sem_arg)
1955{
1956#define FLD(f) abuf->fields.sfmt_ld_plus.f
1957  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1958  const IDESC * UNUSED idesc = abuf->idesc;
1959  int cycles = 0;
1960  {
1961    int referenced = 0;
1962    int UNUSED insn_referenced = abuf->written;
1963    INT in_sr = -1;
1964    INT in_dr = -1;
1965    INT out_dr = -1;
1966    in_sr = FLD (in_sr);
1967    referenced |= 1 << 0;
1968    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1969  }
1970  return cycles;
1971#undef FLD
1972}
1973
1974static int
1975model_m32r2_neg (SIM_CPU *current_cpu, void *sem_arg)
1976{
1977#define FLD(f) abuf->fields.sfmt_ld_plus.f
1978  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1979  const IDESC * UNUSED idesc = abuf->idesc;
1980  int cycles = 0;
1981  {
1982    int referenced = 0;
1983    int UNUSED insn_referenced = abuf->written;
1984    INT in_sr = -1;
1985    INT in_dr = -1;
1986    INT out_dr = -1;
1987    in_sr = FLD (in_sr);
1988    out_dr = FLD (out_dr);
1989    referenced |= 1 << 0;
1990    referenced |= 1 << 2;
1991    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1992  }
1993  return cycles;
1994#undef FLD
1995}
1996
1997static int
1998model_m32r2_nop (SIM_CPU *current_cpu, void *sem_arg)
1999{
2000#define FLD(f) abuf->fields.fmt_empty.f
2001  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2002  const IDESC * UNUSED idesc = abuf->idesc;
2003  int cycles = 0;
2004  {
2005    int referenced = 0;
2006    int UNUSED insn_referenced = abuf->written;
2007    INT in_sr = -1;
2008    INT in_dr = -1;
2009    INT out_dr = -1;
2010    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2011  }
2012  return cycles;
2013#undef FLD
2014}
2015
2016static int
2017model_m32r2_not (SIM_CPU *current_cpu, void *sem_arg)
2018{
2019#define FLD(f) abuf->fields.sfmt_ld_plus.f
2020  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2021  const IDESC * UNUSED idesc = abuf->idesc;
2022  int cycles = 0;
2023  {
2024    int referenced = 0;
2025    int UNUSED insn_referenced = abuf->written;
2026    INT in_sr = -1;
2027    INT in_dr = -1;
2028    INT out_dr = -1;
2029    in_sr = FLD (in_sr);
2030    out_dr = FLD (out_dr);
2031    referenced |= 1 << 0;
2032    referenced |= 1 << 2;
2033    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2034  }
2035  return cycles;
2036#undef FLD
2037}
2038
2039static int
2040model_m32r2_rac_dsi (SIM_CPU *current_cpu, void *sem_arg)
2041{
2042#define FLD(f) abuf->fields.sfmt_rac_dsi.f
2043  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2044  const IDESC * UNUSED idesc = abuf->idesc;
2045  int cycles = 0;
2046  {
2047    int referenced = 0;
2048    int UNUSED insn_referenced = abuf->written;
2049    INT in_src1 = -1;
2050    INT in_src2 = -1;
2051    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2052  }
2053  return cycles;
2054#undef FLD
2055}
2056
2057static int
2058model_m32r2_rach_dsi (SIM_CPU *current_cpu, void *sem_arg)
2059{
2060#define FLD(f) abuf->fields.sfmt_rac_dsi.f
2061  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2062  const IDESC * UNUSED idesc = abuf->idesc;
2063  int cycles = 0;
2064  {
2065    int referenced = 0;
2066    int UNUSED insn_referenced = abuf->written;
2067    INT in_src1 = -1;
2068    INT in_src2 = -1;
2069    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2070  }
2071  return cycles;
2072#undef FLD
2073}
2074
2075static int
2076model_m32r2_rte (SIM_CPU *current_cpu, void *sem_arg)
2077{
2078#define FLD(f) abuf->fields.fmt_empty.f
2079  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2080  const IDESC * UNUSED idesc = abuf->idesc;
2081  int cycles = 0;
2082  {
2083    int referenced = 0;
2084    int UNUSED insn_referenced = abuf->written;
2085    INT in_sr = -1;
2086    INT in_dr = -1;
2087    INT out_dr = -1;
2088    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2089  }
2090  return cycles;
2091#undef FLD
2092}
2093
2094static int
2095model_m32r2_seth (SIM_CPU *current_cpu, void *sem_arg)
2096{
2097#define FLD(f) abuf->fields.sfmt_seth.f
2098  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2099  const IDESC * UNUSED idesc = abuf->idesc;
2100  int cycles = 0;
2101  {
2102    int referenced = 0;
2103    int UNUSED insn_referenced = abuf->written;
2104    INT in_sr = -1;
2105    INT in_dr = -1;
2106    INT out_dr = -1;
2107    out_dr = FLD (out_dr);
2108    referenced |= 1 << 2;
2109    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2110  }
2111  return cycles;
2112#undef FLD
2113}
2114
2115static int
2116model_m32r2_sll (SIM_CPU *current_cpu, void *sem_arg)
2117{
2118#define FLD(f) abuf->fields.sfmt_add.f
2119  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2120  const IDESC * UNUSED idesc = abuf->idesc;
2121  int cycles = 0;
2122  {
2123    int referenced = 0;
2124    int UNUSED insn_referenced = abuf->written;
2125    INT in_sr = -1;
2126    INT in_dr = -1;
2127    INT out_dr = -1;
2128    in_sr = FLD (in_sr);
2129    in_dr = FLD (in_dr);
2130    out_dr = FLD (out_dr);
2131    referenced |= 1 << 0;
2132    referenced |= 1 << 1;
2133    referenced |= 1 << 2;
2134    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2135  }
2136  return cycles;
2137#undef FLD
2138}
2139
2140static int
2141model_m32r2_sll3 (SIM_CPU *current_cpu, void *sem_arg)
2142{
2143#define FLD(f) abuf->fields.sfmt_add3.f
2144  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2145  const IDESC * UNUSED idesc = abuf->idesc;
2146  int cycles = 0;
2147  {
2148    int referenced = 0;
2149    int UNUSED insn_referenced = abuf->written;
2150    INT in_sr = -1;
2151    INT in_dr = -1;
2152    INT out_dr = -1;
2153    in_sr = FLD (in_sr);
2154    out_dr = FLD (out_dr);
2155    referenced |= 1 << 0;
2156    referenced |= 1 << 2;
2157    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2158  }
2159  return cycles;
2160#undef FLD
2161}
2162
2163static int
2164model_m32r2_slli (SIM_CPU *current_cpu, void *sem_arg)
2165{
2166#define FLD(f) abuf->fields.sfmt_slli.f
2167  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2168  const IDESC * UNUSED idesc = abuf->idesc;
2169  int cycles = 0;
2170  {
2171    int referenced = 0;
2172    int UNUSED insn_referenced = abuf->written;
2173    INT in_sr = -1;
2174    INT in_dr = -1;
2175    INT out_dr = -1;
2176    in_dr = FLD (in_dr);
2177    out_dr = FLD (out_dr);
2178    referenced |= 1 << 1;
2179    referenced |= 1 << 2;
2180    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2181  }
2182  return cycles;
2183#undef FLD
2184}
2185
2186static int
2187model_m32r2_sra (SIM_CPU *current_cpu, void *sem_arg)
2188{
2189#define FLD(f) abuf->fields.sfmt_add.f
2190  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2191  const IDESC * UNUSED idesc = abuf->idesc;
2192  int cycles = 0;
2193  {
2194    int referenced = 0;
2195    int UNUSED insn_referenced = abuf->written;
2196    INT in_sr = -1;
2197    INT in_dr = -1;
2198    INT out_dr = -1;
2199    in_sr = FLD (in_sr);
2200    in_dr = FLD (in_dr);
2201    out_dr = FLD (out_dr);
2202    referenced |= 1 << 0;
2203    referenced |= 1 << 1;
2204    referenced |= 1 << 2;
2205    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2206  }
2207  return cycles;
2208#undef FLD
2209}
2210
2211static int
2212model_m32r2_sra3 (SIM_CPU *current_cpu, void *sem_arg)
2213{
2214#define FLD(f) abuf->fields.sfmt_add3.f
2215  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2216  const IDESC * UNUSED idesc = abuf->idesc;
2217  int cycles = 0;
2218  {
2219    int referenced = 0;
2220    int UNUSED insn_referenced = abuf->written;
2221    INT in_sr = -1;
2222    INT in_dr = -1;
2223    INT out_dr = -1;
2224    in_sr = FLD (in_sr);
2225    out_dr = FLD (out_dr);
2226    referenced |= 1 << 0;
2227    referenced |= 1 << 2;
2228    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2229  }
2230  return cycles;
2231#undef FLD
2232}
2233
2234static int
2235model_m32r2_srai (SIM_CPU *current_cpu, void *sem_arg)
2236{
2237#define FLD(f) abuf->fields.sfmt_slli.f
2238  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2239  const IDESC * UNUSED idesc = abuf->idesc;
2240  int cycles = 0;
2241  {
2242    int referenced = 0;
2243    int UNUSED insn_referenced = abuf->written;
2244    INT in_sr = -1;
2245    INT in_dr = -1;
2246    INT out_dr = -1;
2247    in_dr = FLD (in_dr);
2248    out_dr = FLD (out_dr);
2249    referenced |= 1 << 1;
2250    referenced |= 1 << 2;
2251    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2252  }
2253  return cycles;
2254#undef FLD
2255}
2256
2257static int
2258model_m32r2_srl (SIM_CPU *current_cpu, void *sem_arg)
2259{
2260#define FLD(f) abuf->fields.sfmt_add.f
2261  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2262  const IDESC * UNUSED idesc = abuf->idesc;
2263  int cycles = 0;
2264  {
2265    int referenced = 0;
2266    int UNUSED insn_referenced = abuf->written;
2267    INT in_sr = -1;
2268    INT in_dr = -1;
2269    INT out_dr = -1;
2270    in_sr = FLD (in_sr);
2271    in_dr = FLD (in_dr);
2272    out_dr = FLD (out_dr);
2273    referenced |= 1 << 0;
2274    referenced |= 1 << 1;
2275    referenced |= 1 << 2;
2276    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2277  }
2278  return cycles;
2279#undef FLD
2280}
2281
2282static int
2283model_m32r2_srl3 (SIM_CPU *current_cpu, void *sem_arg)
2284{
2285#define FLD(f) abuf->fields.sfmt_add3.f
2286  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2287  const IDESC * UNUSED idesc = abuf->idesc;
2288  int cycles = 0;
2289  {
2290    int referenced = 0;
2291    int UNUSED insn_referenced = abuf->written;
2292    INT in_sr = -1;
2293    INT in_dr = -1;
2294    INT out_dr = -1;
2295    in_sr = FLD (in_sr);
2296    out_dr = FLD (out_dr);
2297    referenced |= 1 << 0;
2298    referenced |= 1 << 2;
2299    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2300  }
2301  return cycles;
2302#undef FLD
2303}
2304
2305static int
2306model_m32r2_srli (SIM_CPU *current_cpu, void *sem_arg)
2307{
2308#define FLD(f) abuf->fields.sfmt_slli.f
2309  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2310  const IDESC * UNUSED idesc = abuf->idesc;
2311  int cycles = 0;
2312  {
2313    int referenced = 0;
2314    int UNUSED insn_referenced = abuf->written;
2315    INT in_sr = -1;
2316    INT in_dr = -1;
2317    INT out_dr = -1;
2318    in_dr = FLD (in_dr);
2319    out_dr = FLD (out_dr);
2320    referenced |= 1 << 1;
2321    referenced |= 1 << 2;
2322    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2323  }
2324  return cycles;
2325#undef FLD
2326}
2327
2328static int
2329model_m32r2_st (SIM_CPU *current_cpu, void *sem_arg)
2330{
2331#define FLD(f) abuf->fields.sfmt_st_plus.f
2332  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2333  const IDESC * UNUSED idesc = abuf->idesc;
2334  int cycles = 0;
2335  {
2336    int referenced = 0;
2337    int UNUSED insn_referenced = abuf->written;
2338    INT in_src1 = 0;
2339    INT in_src2 = 0;
2340    in_src1 = FLD (in_src1);
2341    in_src2 = FLD (in_src2);
2342    referenced |= 1 << 0;
2343    referenced |= 1 << 1;
2344    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2345  }
2346  return cycles;
2347#undef FLD
2348}
2349
2350static int
2351model_m32r2_st_d (SIM_CPU *current_cpu, void *sem_arg)
2352{
2353#define FLD(f) abuf->fields.sfmt_st_d.f
2354  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2355  const IDESC * UNUSED idesc = abuf->idesc;
2356  int cycles = 0;
2357  {
2358    int referenced = 0;
2359    int UNUSED insn_referenced = abuf->written;
2360    INT in_src1 = 0;
2361    INT in_src2 = 0;
2362    in_src1 = FLD (in_src1);
2363    in_src2 = FLD (in_src2);
2364    referenced |= 1 << 0;
2365    referenced |= 1 << 1;
2366    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2367  }
2368  return cycles;
2369#undef FLD
2370}
2371
2372static int
2373model_m32r2_stb (SIM_CPU *current_cpu, void *sem_arg)
2374{
2375#define FLD(f) abuf->fields.sfmt_st_plus.f
2376  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2377  const IDESC * UNUSED idesc = abuf->idesc;
2378  int cycles = 0;
2379  {
2380    int referenced = 0;
2381    int UNUSED insn_referenced = abuf->written;
2382    INT in_src1 = 0;
2383    INT in_src2 = 0;
2384    in_src1 = FLD (in_src1);
2385    in_src2 = FLD (in_src2);
2386    referenced |= 1 << 0;
2387    referenced |= 1 << 1;
2388    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2389  }
2390  return cycles;
2391#undef FLD
2392}
2393
2394static int
2395model_m32r2_stb_d (SIM_CPU *current_cpu, void *sem_arg)
2396{
2397#define FLD(f) abuf->fields.sfmt_st_d.f
2398  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2399  const IDESC * UNUSED idesc = abuf->idesc;
2400  int cycles = 0;
2401  {
2402    int referenced = 0;
2403    int UNUSED insn_referenced = abuf->written;
2404    INT in_src1 = 0;
2405    INT in_src2 = 0;
2406    in_src1 = FLD (in_src1);
2407    in_src2 = FLD (in_src2);
2408    referenced |= 1 << 0;
2409    referenced |= 1 << 1;
2410    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2411  }
2412  return cycles;
2413#undef FLD
2414}
2415
2416static int
2417model_m32r2_sth (SIM_CPU *current_cpu, void *sem_arg)
2418{
2419#define FLD(f) abuf->fields.sfmt_st_plus.f
2420  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2421  const IDESC * UNUSED idesc = abuf->idesc;
2422  int cycles = 0;
2423  {
2424    int referenced = 0;
2425    int UNUSED insn_referenced = abuf->written;
2426    INT in_src1 = 0;
2427    INT in_src2 = 0;
2428    in_src1 = FLD (in_src1);
2429    in_src2 = FLD (in_src2);
2430    referenced |= 1 << 0;
2431    referenced |= 1 << 1;
2432    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2433  }
2434  return cycles;
2435#undef FLD
2436}
2437
2438static int
2439model_m32r2_sth_d (SIM_CPU *current_cpu, void *sem_arg)
2440{
2441#define FLD(f) abuf->fields.sfmt_st_d.f
2442  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2443  const IDESC * UNUSED idesc = abuf->idesc;
2444  int cycles = 0;
2445  {
2446    int referenced = 0;
2447    int UNUSED insn_referenced = abuf->written;
2448    INT in_src1 = 0;
2449    INT in_src2 = 0;
2450    in_src1 = FLD (in_src1);
2451    in_src2 = FLD (in_src2);
2452    referenced |= 1 << 0;
2453    referenced |= 1 << 1;
2454    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2455  }
2456  return cycles;
2457#undef FLD
2458}
2459
2460static int
2461model_m32r2_st_plus (SIM_CPU *current_cpu, void *sem_arg)
2462{
2463#define FLD(f) abuf->fields.sfmt_st_plus.f
2464  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2465  const IDESC * UNUSED idesc = abuf->idesc;
2466  int cycles = 0;
2467  {
2468    int referenced = 0;
2469    int UNUSED insn_referenced = abuf->written;
2470    INT in_src1 = 0;
2471    INT in_src2 = 0;
2472    in_src1 = FLD (in_src1);
2473    in_src2 = FLD (in_src2);
2474    referenced |= 1 << 0;
2475    referenced |= 1 << 1;
2476    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2477  }
2478  {
2479    int referenced = 0;
2480    int UNUSED insn_referenced = abuf->written;
2481    INT in_sr = -1;
2482    INT in_dr = -1;
2483    INT out_dr = -1;
2484    in_dr = FLD (in_src2);
2485    out_dr = FLD (out_src2);
2486    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
2487  }
2488  return cycles;
2489#undef FLD
2490}
2491
2492static int
2493model_m32r2_sth_plus (SIM_CPU *current_cpu, void *sem_arg)
2494{
2495#define FLD(f) abuf->fields.sfmt_st_plus.f
2496  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2497  const IDESC * UNUSED idesc = abuf->idesc;
2498  int cycles = 0;
2499  {
2500    int referenced = 0;
2501    int UNUSED insn_referenced = abuf->written;
2502    INT in_src1 = 0;
2503    INT in_src2 = 0;
2504    in_src1 = FLD (in_src1);
2505    in_src2 = FLD (in_src2);
2506    referenced |= 1 << 0;
2507    referenced |= 1 << 1;
2508    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2509  }
2510  {
2511    int referenced = 0;
2512    int UNUSED insn_referenced = abuf->written;
2513    INT in_sr = -1;
2514    INT in_dr = -1;
2515    INT out_dr = -1;
2516    in_dr = FLD (in_src2);
2517    out_dr = FLD (out_src2);
2518    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
2519  }
2520  return cycles;
2521#undef FLD
2522}
2523
2524static int
2525model_m32r2_stb_plus (SIM_CPU *current_cpu, void *sem_arg)
2526{
2527#define FLD(f) abuf->fields.sfmt_st_plus.f
2528  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2529  const IDESC * UNUSED idesc = abuf->idesc;
2530  int cycles = 0;
2531  {
2532    int referenced = 0;
2533    int UNUSED insn_referenced = abuf->written;
2534    INT in_src1 = 0;
2535    INT in_src2 = 0;
2536    in_src1 = FLD (in_src1);
2537    in_src2 = FLD (in_src2);
2538    referenced |= 1 << 0;
2539    referenced |= 1 << 1;
2540    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2541  }
2542  {
2543    int referenced = 0;
2544    int UNUSED insn_referenced = abuf->written;
2545    INT in_sr = -1;
2546    INT in_dr = -1;
2547    INT out_dr = -1;
2548    in_dr = FLD (in_src2);
2549    out_dr = FLD (out_src2);
2550    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
2551  }
2552  return cycles;
2553#undef FLD
2554}
2555
2556static int
2557model_m32r2_st_minus (SIM_CPU *current_cpu, void *sem_arg)
2558{
2559#define FLD(f) abuf->fields.sfmt_st_plus.f
2560  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2561  const IDESC * UNUSED idesc = abuf->idesc;
2562  int cycles = 0;
2563  {
2564    int referenced = 0;
2565    int UNUSED insn_referenced = abuf->written;
2566    INT in_src1 = 0;
2567    INT in_src2 = 0;
2568    in_src1 = FLD (in_src1);
2569    in_src2 = FLD (in_src2);
2570    referenced |= 1 << 0;
2571    referenced |= 1 << 1;
2572    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2573  }
2574  {
2575    int referenced = 0;
2576    int UNUSED insn_referenced = abuf->written;
2577    INT in_sr = -1;
2578    INT in_dr = -1;
2579    INT out_dr = -1;
2580    in_dr = FLD (in_src2);
2581    out_dr = FLD (out_src2);
2582    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
2583  }
2584  return cycles;
2585#undef FLD
2586}
2587
2588static int
2589model_m32r2_sub (SIM_CPU *current_cpu, void *sem_arg)
2590{
2591#define FLD(f) abuf->fields.sfmt_add.f
2592  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2593  const IDESC * UNUSED idesc = abuf->idesc;
2594  int cycles = 0;
2595  {
2596    int referenced = 0;
2597    int UNUSED insn_referenced = abuf->written;
2598    INT in_sr = -1;
2599    INT in_dr = -1;
2600    INT out_dr = -1;
2601    in_sr = FLD (in_sr);
2602    in_dr = FLD (in_dr);
2603    out_dr = FLD (out_dr);
2604    referenced |= 1 << 0;
2605    referenced |= 1 << 1;
2606    referenced |= 1 << 2;
2607    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2608  }
2609  return cycles;
2610#undef FLD
2611}
2612
2613static int
2614model_m32r2_subv (SIM_CPU *current_cpu, void *sem_arg)
2615{
2616#define FLD(f) abuf->fields.sfmt_add.f
2617  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2618  const IDESC * UNUSED idesc = abuf->idesc;
2619  int cycles = 0;
2620  {
2621    int referenced = 0;
2622    int UNUSED insn_referenced = abuf->written;
2623    INT in_sr = -1;
2624    INT in_dr = -1;
2625    INT out_dr = -1;
2626    in_sr = FLD (in_sr);
2627    in_dr = FLD (in_dr);
2628    out_dr = FLD (out_dr);
2629    referenced |= 1 << 0;
2630    referenced |= 1 << 1;
2631    referenced |= 1 << 2;
2632    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2633  }
2634  return cycles;
2635#undef FLD
2636}
2637
2638static int
2639model_m32r2_subx (SIM_CPU *current_cpu, void *sem_arg)
2640{
2641#define FLD(f) abuf->fields.sfmt_add.f
2642  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2643  const IDESC * UNUSED idesc = abuf->idesc;
2644  int cycles = 0;
2645  {
2646    int referenced = 0;
2647    int UNUSED insn_referenced = abuf->written;
2648    INT in_sr = -1;
2649    INT in_dr = -1;
2650    INT out_dr = -1;
2651    in_sr = FLD (in_sr);
2652    in_dr = FLD (in_dr);
2653    out_dr = FLD (out_dr);
2654    referenced |= 1 << 0;
2655    referenced |= 1 << 1;
2656    referenced |= 1 << 2;
2657    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2658  }
2659  return cycles;
2660#undef FLD
2661}
2662
2663static int
2664model_m32r2_trap (SIM_CPU *current_cpu, void *sem_arg)
2665{
2666#define FLD(f) abuf->fields.sfmt_trap.f
2667  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2668  const IDESC * UNUSED idesc = abuf->idesc;
2669  int cycles = 0;
2670  {
2671    int referenced = 0;
2672    int UNUSED insn_referenced = abuf->written;
2673    INT in_sr = -1;
2674    INT in_dr = -1;
2675    INT out_dr = -1;
2676    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2677  }
2678  return cycles;
2679#undef FLD
2680}
2681
2682static int
2683model_m32r2_unlock (SIM_CPU *current_cpu, void *sem_arg)
2684{
2685#define FLD(f) abuf->fields.sfmt_st_plus.f
2686  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2687  const IDESC * UNUSED idesc = abuf->idesc;
2688  int cycles = 0;
2689  {
2690    int referenced = 0;
2691    int UNUSED insn_referenced = abuf->written;
2692    INT in_sr = 0;
2693    INT out_dr = 0;
2694    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
2695  }
2696  return cycles;
2697#undef FLD
2698}
2699
2700static int
2701model_m32r2_satb (SIM_CPU *current_cpu, void *sem_arg)
2702{
2703#define FLD(f) abuf->fields.sfmt_ld_plus.f
2704  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2705  const IDESC * UNUSED idesc = abuf->idesc;
2706  int cycles = 0;
2707  {
2708    int referenced = 0;
2709    int UNUSED insn_referenced = abuf->written;
2710    INT in_sr = -1;
2711    INT in_dr = -1;
2712    INT out_dr = -1;
2713    in_sr = FLD (in_sr);
2714    out_dr = FLD (out_dr);
2715    referenced |= 1 << 0;
2716    referenced |= 1 << 2;
2717    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2718  }
2719  return cycles;
2720#undef FLD
2721}
2722
2723static int
2724model_m32r2_sath (SIM_CPU *current_cpu, void *sem_arg)
2725{
2726#define FLD(f) abuf->fields.sfmt_ld_plus.f
2727  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2728  const IDESC * UNUSED idesc = abuf->idesc;
2729  int cycles = 0;
2730  {
2731    int referenced = 0;
2732    int UNUSED insn_referenced = abuf->written;
2733    INT in_sr = -1;
2734    INT in_dr = -1;
2735    INT out_dr = -1;
2736    in_sr = FLD (in_sr);
2737    out_dr = FLD (out_dr);
2738    referenced |= 1 << 0;
2739    referenced |= 1 << 2;
2740    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2741  }
2742  return cycles;
2743#undef FLD
2744}
2745
2746static int
2747model_m32r2_sat (SIM_CPU *current_cpu, void *sem_arg)
2748{
2749#define FLD(f) abuf->fields.sfmt_ld_plus.f
2750  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2751  const IDESC * UNUSED idesc = abuf->idesc;
2752  int cycles = 0;
2753  {
2754    int referenced = 0;
2755    int UNUSED insn_referenced = abuf->written;
2756    INT in_sr = -1;
2757    INT in_dr = -1;
2758    INT out_dr = -1;
2759    in_sr = FLD (in_sr);
2760    out_dr = FLD (out_dr);
2761    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
2762    referenced |= 1 << 2;
2763    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2764  }
2765  return cycles;
2766#undef FLD
2767}
2768
2769static int
2770model_m32r2_pcmpbz (SIM_CPU *current_cpu, void *sem_arg)
2771{
2772#define FLD(f) abuf->fields.sfmt_st_plus.f
2773  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2774  const IDESC * UNUSED idesc = abuf->idesc;
2775  int cycles = 0;
2776  {
2777    int referenced = 0;
2778    int UNUSED insn_referenced = abuf->written;
2779    INT in_src1 = -1;
2780    INT in_src2 = -1;
2781    in_src2 = FLD (in_src2);
2782    referenced |= 1 << 1;
2783    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2784  }
2785  return cycles;
2786#undef FLD
2787}
2788
2789static int
2790model_m32r2_sadd (SIM_CPU *current_cpu, void *sem_arg)
2791{
2792#define FLD(f) abuf->fields.fmt_empty.f
2793  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2794  const IDESC * UNUSED idesc = abuf->idesc;
2795  int cycles = 0;
2796  {
2797    int referenced = 0;
2798    int UNUSED insn_referenced = abuf->written;
2799    INT in_src1 = -1;
2800    INT in_src2 = -1;
2801    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2802  }
2803  return cycles;
2804#undef FLD
2805}
2806
2807static int
2808model_m32r2_macwu1 (SIM_CPU *current_cpu, void *sem_arg)
2809{
2810#define FLD(f) abuf->fields.sfmt_st_plus.f
2811  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2812  const IDESC * UNUSED idesc = abuf->idesc;
2813  int cycles = 0;
2814  {
2815    int referenced = 0;
2816    int UNUSED insn_referenced = abuf->written;
2817    INT in_src1 = -1;
2818    INT in_src2 = -1;
2819    in_src1 = FLD (in_src1);
2820    in_src2 = FLD (in_src2);
2821    referenced |= 1 << 0;
2822    referenced |= 1 << 1;
2823    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2824  }
2825  return cycles;
2826#undef FLD
2827}
2828
2829static int
2830model_m32r2_msblo (SIM_CPU *current_cpu, void *sem_arg)
2831{
2832#define FLD(f) abuf->fields.sfmt_st_plus.f
2833  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2834  const IDESC * UNUSED idesc = abuf->idesc;
2835  int cycles = 0;
2836  {
2837    int referenced = 0;
2838    int UNUSED insn_referenced = abuf->written;
2839    INT in_src1 = -1;
2840    INT in_src2 = -1;
2841    in_src1 = FLD (in_src1);
2842    in_src2 = FLD (in_src2);
2843    referenced |= 1 << 0;
2844    referenced |= 1 << 1;
2845    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2846  }
2847  return cycles;
2848#undef FLD
2849}
2850
2851static int
2852model_m32r2_mulwu1 (SIM_CPU *current_cpu, void *sem_arg)
2853{
2854#define FLD(f) abuf->fields.sfmt_st_plus.f
2855  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2856  const IDESC * UNUSED idesc = abuf->idesc;
2857  int cycles = 0;
2858  {
2859    int referenced = 0;
2860    int UNUSED insn_referenced = abuf->written;
2861    INT in_src1 = -1;
2862    INT in_src2 = -1;
2863    in_src1 = FLD (in_src1);
2864    in_src2 = FLD (in_src2);
2865    referenced |= 1 << 0;
2866    referenced |= 1 << 1;
2867    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2868  }
2869  return cycles;
2870#undef FLD
2871}
2872
2873static int
2874model_m32r2_maclh1 (SIM_CPU *current_cpu, void *sem_arg)
2875{
2876#define FLD(f) abuf->fields.sfmt_st_plus.f
2877  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2878  const IDESC * UNUSED idesc = abuf->idesc;
2879  int cycles = 0;
2880  {
2881    int referenced = 0;
2882    int UNUSED insn_referenced = abuf->written;
2883    INT in_src1 = -1;
2884    INT in_src2 = -1;
2885    in_src1 = FLD (in_src1);
2886    in_src2 = FLD (in_src2);
2887    referenced |= 1 << 0;
2888    referenced |= 1 << 1;
2889    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2890  }
2891  return cycles;
2892#undef FLD
2893}
2894
2895static int
2896model_m32r2_sc (SIM_CPU *current_cpu, void *sem_arg)
2897{
2898#define FLD(f) abuf->fields.fmt_empty.f
2899  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2900  const IDESC * UNUSED idesc = abuf->idesc;
2901  int cycles = 0;
2902  {
2903    int referenced = 0;
2904    int UNUSED insn_referenced = abuf->written;
2905    INT in_sr = -1;
2906    INT in_dr = -1;
2907    INT out_dr = -1;
2908    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2909  }
2910  return cycles;
2911#undef FLD
2912}
2913
2914static int
2915model_m32r2_snc (SIM_CPU *current_cpu, void *sem_arg)
2916{
2917#define FLD(f) abuf->fields.fmt_empty.f
2918  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2919  const IDESC * UNUSED idesc = abuf->idesc;
2920  int cycles = 0;
2921  {
2922    int referenced = 0;
2923    int UNUSED insn_referenced = abuf->written;
2924    INT in_sr = -1;
2925    INT in_dr = -1;
2926    INT out_dr = -1;
2927    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2928  }
2929  return cycles;
2930#undef FLD
2931}
2932
2933static int
2934model_m32r2_clrpsw (SIM_CPU *current_cpu, void *sem_arg)
2935{
2936#define FLD(f) abuf->fields.sfmt_clrpsw.f
2937  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2938  const IDESC * UNUSED idesc = abuf->idesc;
2939  int cycles = 0;
2940  {
2941    int referenced = 0;
2942    int UNUSED insn_referenced = abuf->written;
2943    INT in_sr = -1;
2944    INT in_dr = -1;
2945    INT out_dr = -1;
2946    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2947  }
2948  return cycles;
2949#undef FLD
2950}
2951
2952static int
2953model_m32r2_setpsw (SIM_CPU *current_cpu, void *sem_arg)
2954{
2955#define FLD(f) abuf->fields.sfmt_clrpsw.f
2956  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2957  const IDESC * UNUSED idesc = abuf->idesc;
2958  int cycles = 0;
2959  {
2960    int referenced = 0;
2961    int UNUSED insn_referenced = abuf->written;
2962    INT in_sr = -1;
2963    INT in_dr = -1;
2964    INT out_dr = -1;
2965    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2966  }
2967  return cycles;
2968#undef FLD
2969}
2970
2971static int
2972model_m32r2_bset (SIM_CPU *current_cpu, void *sem_arg)
2973{
2974#define FLD(f) abuf->fields.sfmt_bset.f
2975  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2976  const IDESC * UNUSED idesc = abuf->idesc;
2977  int cycles = 0;
2978  {
2979    int referenced = 0;
2980    int UNUSED insn_referenced = abuf->written;
2981    INT in_sr = -1;
2982    INT in_dr = -1;
2983    INT out_dr = -1;
2984    in_sr = FLD (in_sr);
2985    referenced |= 1 << 0;
2986    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2987  }
2988  return cycles;
2989#undef FLD
2990}
2991
2992static int
2993model_m32r2_bclr (SIM_CPU *current_cpu, void *sem_arg)
2994{
2995#define FLD(f) abuf->fields.sfmt_bset.f
2996  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2997  const IDESC * UNUSED idesc = abuf->idesc;
2998  int cycles = 0;
2999  {
3000    int referenced = 0;
3001    int UNUSED insn_referenced = abuf->written;
3002    INT in_sr = -1;
3003    INT in_dr = -1;
3004    INT out_dr = -1;
3005    in_sr = FLD (in_sr);
3006    referenced |= 1 << 0;
3007    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
3008  }
3009  return cycles;
3010#undef FLD
3011}
3012
3013static int
3014model_m32r2_btst (SIM_CPU *current_cpu, void *sem_arg)
3015{
3016#define FLD(f) abuf->fields.sfmt_bset.f
3017  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3018  const IDESC * UNUSED idesc = abuf->idesc;
3019  int cycles = 0;
3020  {
3021    int referenced = 0;
3022    int UNUSED insn_referenced = abuf->written;
3023    INT in_sr = -1;
3024    INT in_dr = -1;
3025    INT out_dr = -1;
3026    in_sr = FLD (in_sr);
3027    referenced |= 1 << 0;
3028    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
3029  }
3030  return cycles;
3031#undef FLD
3032}
3033
3034/* We assume UNIT_NONE == 0 because the tables don't always terminate
3035   entries with it.  */
3036
3037/* Model timing data for `m32r2'.  */
3038
3039static const INSN_TIMING m32r2_timing[] = {
3040  { M32R2F_INSN_X_INVALID, 0, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3041  { M32R2F_INSN_X_AFTER, 0, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3042  { M32R2F_INSN_X_BEFORE, 0, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3043  { M32R2F_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3044  { M32R2F_INSN_X_CHAIN, 0, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3045  { M32R2F_INSN_X_BEGIN, 0, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3046  { M32R2F_INSN_ADD, model_m32r2_add, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3047  { M32R2F_INSN_ADD3, model_m32r2_add3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3048  { M32R2F_INSN_AND, model_m32r2_and, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3049  { M32R2F_INSN_AND3, model_m32r2_and3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3050  { M32R2F_INSN_OR, model_m32r2_or, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3051  { M32R2F_INSN_OR3, model_m32r2_or3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3052  { M32R2F_INSN_XOR, model_m32r2_xor, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3053  { M32R2F_INSN_XOR3, model_m32r2_xor3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3054  { M32R2F_INSN_ADDI, model_m32r2_addi, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3055  { M32R2F_INSN_ADDV, model_m32r2_addv, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3056  { M32R2F_INSN_ADDV3, model_m32r2_addv3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3057  { M32R2F_INSN_ADDX, model_m32r2_addx, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3058  { M32R2F_INSN_BC8, model_m32r2_bc8, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
3059  { M32R2F_INSN_BC24, model_m32r2_bc24, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
3060  { M32R2F_INSN_BEQ, model_m32r2_beq, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } },
3061  { M32R2F_INSN_BEQZ, model_m32r2_beqz, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } },
3062  { M32R2F_INSN_BGEZ, model_m32r2_bgez, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } },
3063  { M32R2F_INSN_BGTZ, model_m32r2_bgtz, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } },
3064  { M32R2F_INSN_BLEZ, model_m32r2_blez, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } },
3065  { M32R2F_INSN_BLTZ, model_m32r2_bltz, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } },
3066  { M32R2F_INSN_BNEZ, model_m32r2_bnez, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } },
3067  { M32R2F_INSN_BL8, model_m32r2_bl8, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
3068  { M32R2F_INSN_BL24, model_m32r2_bl24, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
3069  { M32R2F_INSN_BCL8, model_m32r2_bcl8, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
3070  { M32R2F_INSN_BCL24, model_m32r2_bcl24, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
3071  { M32R2F_INSN_BNC8, model_m32r2_bnc8, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
3072  { M32R2F_INSN_BNC24, model_m32r2_bnc24, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
3073  { M32R2F_INSN_BNE, model_m32r2_bne, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } },
3074  { M32R2F_INSN_BRA8, model_m32r2_bra8, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
3075  { M32R2F_INSN_BRA24, model_m32r2_bra24, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
3076  { M32R2F_INSN_BNCL8, model_m32r2_bncl8, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
3077  { M32R2F_INSN_BNCL24, model_m32r2_bncl24, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
3078  { M32R2F_INSN_CMP, model_m32r2_cmp, { { (int) UNIT_M32R2_U_CMP, 1, 1 } } },
3079  { M32R2F_INSN_CMPI, model_m32r2_cmpi, { { (int) UNIT_M32R2_U_CMP, 1, 1 } } },
3080  { M32R2F_INSN_CMPU, model_m32r2_cmpu, { { (int) UNIT_M32R2_U_CMP, 1, 1 } } },
3081  { M32R2F_INSN_CMPUI, model_m32r2_cmpui, { { (int) UNIT_M32R2_U_CMP, 1, 1 } } },
3082  { M32R2F_INSN_CMPEQ, model_m32r2_cmpeq, { { (int) UNIT_M32R2_U_CMP, 1, 1 } } },
3083  { M32R2F_INSN_CMPZ, model_m32r2_cmpz, { { (int) UNIT_M32R2_U_CMP, 1, 1 } } },
3084  { M32R2F_INSN_DIV, model_m32r2_div, { { (int) UNIT_M32R2_U_EXEC, 1, 37 } } },
3085  { M32R2F_INSN_DIVU, model_m32r2_divu, { { (int) UNIT_M32R2_U_EXEC, 1, 37 } } },
3086  { M32R2F_INSN_REM, model_m32r2_rem, { { (int) UNIT_M32R2_U_EXEC, 1, 37 } } },
3087  { M32R2F_INSN_REMU, model_m32r2_remu, { { (int) UNIT_M32R2_U_EXEC, 1, 37 } } },
3088  { M32R2F_INSN_REMH, model_m32r2_remh, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } },
3089  { M32R2F_INSN_REMUH, model_m32r2_remuh, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } },
3090  { M32R2F_INSN_REMB, model_m32r2_remb, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } },
3091  { M32R2F_INSN_REMUB, model_m32r2_remub, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } },
3092  { M32R2F_INSN_DIVUH, model_m32r2_divuh, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } },
3093  { M32R2F_INSN_DIVB, model_m32r2_divb, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } },
3094  { M32R2F_INSN_DIVUB, model_m32r2_divub, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } },
3095  { M32R2F_INSN_DIVH, model_m32r2_divh, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } },
3096  { M32R2F_INSN_JC, model_m32r2_jc, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
3097  { M32R2F_INSN_JNC, model_m32r2_jnc, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
3098  { M32R2F_INSN_JL, model_m32r2_jl, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
3099  { M32R2F_INSN_JMP, model_m32r2_jmp, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
3100  { M32R2F_INSN_LD, model_m32r2_ld, { { (int) UNIT_M32R2_U_LOAD, 1, 1 } } },
3101  { M32R2F_INSN_LD_D, model_m32r2_ld_d, { { (int) UNIT_M32R2_U_LOAD, 1, 2 } } },
3102  { M32R2F_INSN_LDB, model_m32r2_ldb, { { (int) UNIT_M32R2_U_LOAD, 1, 1 } } },
3103  { M32R2F_INSN_LDB_D, model_m32r2_ldb_d, { { (int) UNIT_M32R2_U_LOAD, 1, 2 } } },
3104  { M32R2F_INSN_LDH, model_m32r2_ldh, { { (int) UNIT_M32R2_U_LOAD, 1, 1 } } },
3105  { M32R2F_INSN_LDH_D, model_m32r2_ldh_d, { { (int) UNIT_M32R2_U_LOAD, 1, 2 } } },
3106  { M32R2F_INSN_LDUB, model_m32r2_ldub, { { (int) UNIT_M32R2_U_LOAD, 1, 1 } } },
3107  { M32R2F_INSN_LDUB_D, model_m32r2_ldub_d, { { (int) UNIT_M32R2_U_LOAD, 1, 2 } } },
3108  { M32R2F_INSN_LDUH, model_m32r2_lduh, { { (int) UNIT_M32R2_U_LOAD, 1, 1 } } },
3109  { M32R2F_INSN_LDUH_D, model_m32r2_lduh_d, { { (int) UNIT_M32R2_U_LOAD, 1, 2 } } },
3110  { M32R2F_INSN_LD_PLUS, model_m32r2_ld_plus, { { (int) UNIT_M32R2_U_LOAD, 1, 1 }, { (int) UNIT_M32R2_U_EXEC, 1, 0 } } },
3111  { M32R2F_INSN_LD24, model_m32r2_ld24, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3112  { M32R2F_INSN_LDI8, model_m32r2_ldi8, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3113  { M32R2F_INSN_LDI16, model_m32r2_ldi16, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3114  { M32R2F_INSN_LOCK, model_m32r2_lock, { { (int) UNIT_M32R2_U_LOAD, 1, 1 } } },
3115  { M32R2F_INSN_MACHI_A, model_m32r2_machi_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
3116  { M32R2F_INSN_MACLO_A, model_m32r2_maclo_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
3117  { M32R2F_INSN_MACWHI_A, model_m32r2_macwhi_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
3118  { M32R2F_INSN_MACWLO_A, model_m32r2_macwlo_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
3119  { M32R2F_INSN_MUL, model_m32r2_mul, { { (int) UNIT_M32R2_U_EXEC, 1, 4 } } },
3120  { M32R2F_INSN_MULHI_A, model_m32r2_mulhi_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
3121  { M32R2F_INSN_MULLO_A, model_m32r2_mullo_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
3122  { M32R2F_INSN_MULWHI_A, model_m32r2_mulwhi_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
3123  { M32R2F_INSN_MULWLO_A, model_m32r2_mulwlo_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
3124  { M32R2F_INSN_MV, model_m32r2_mv, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3125  { M32R2F_INSN_MVFACHI_A, model_m32r2_mvfachi_a, { { (int) UNIT_M32R2_U_EXEC, 1, 2 } } },
3126  { M32R2F_INSN_MVFACLO_A, model_m32r2_mvfaclo_a, { { (int) UNIT_M32R2_U_EXEC, 1, 2 } } },
3127  { M32R2F_INSN_MVFACMI_A, model_m32r2_mvfacmi_a, { { (int) UNIT_M32R2_U_EXEC, 1, 2 } } },
3128  { M32R2F_INSN_MVFC, model_m32r2_mvfc, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3129  { M32R2F_INSN_MVTACHI_A, model_m32r2_mvtachi_a, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3130  { M32R2F_INSN_MVTACLO_A, model_m32r2_mvtaclo_a, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3131  { M32R2F_INSN_MVTC, model_m32r2_mvtc, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3132  { M32R2F_INSN_NEG, model_m32r2_neg, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3133  { M32R2F_INSN_NOP, model_m32r2_nop, { { (int) UNIT_M32R2_U_EXEC, 1, 0 } } },
3134  { M32R2F_INSN_NOT, model_m32r2_not, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3135  { M32R2F_INSN_RAC_DSI, model_m32r2_rac_dsi, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
3136  { M32R2F_INSN_RACH_DSI, model_m32r2_rach_dsi, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
3137  { M32R2F_INSN_RTE, model_m32r2_rte, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3138  { M32R2F_INSN_SETH, model_m32r2_seth, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3139  { M32R2F_INSN_SLL, model_m32r2_sll, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3140  { M32R2F_INSN_SLL3, model_m32r2_sll3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3141  { M32R2F_INSN_SLLI, model_m32r2_slli, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3142  { M32R2F_INSN_SRA, model_m32r2_sra, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3143  { M32R2F_INSN_SRA3, model_m32r2_sra3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3144  { M32R2F_INSN_SRAI, model_m32r2_srai, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3145  { M32R2F_INSN_SRL, model_m32r2_srl, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3146  { M32R2F_INSN_SRL3, model_m32r2_srl3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3147  { M32R2F_INSN_SRLI, model_m32r2_srli, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3148  { M32R2F_INSN_ST, model_m32r2_st, { { (int) UNIT_M32R2_U_STORE, 1, 1 } } },
3149  { M32R2F_INSN_ST_D, model_m32r2_st_d, { { (int) UNIT_M32R2_U_STORE, 1, 2 } } },
3150  { M32R2F_INSN_STB, model_m32r2_stb, { { (int) UNIT_M32R2_U_STORE, 1, 1 } } },
3151  { M32R2F_INSN_STB_D, model_m32r2_stb_d, { { (int) UNIT_M32R2_U_STORE, 1, 2 } } },
3152  { M32R2F_INSN_STH, model_m32r2_sth, { { (int) UNIT_M32R2_U_STORE, 1, 1 } } },
3153  { M32R2F_INSN_STH_D, model_m32r2_sth_d, { { (int) UNIT_M32R2_U_STORE, 1, 2 } } },
3154  { M32R2F_INSN_ST_PLUS, model_m32r2_st_plus, { { (int) UNIT_M32R2_U_STORE, 1, 1 }, { (int) UNIT_M32R2_U_EXEC, 1, 0 } } },
3155  { M32R2F_INSN_STH_PLUS, model_m32r2_sth_plus, { { (int) UNIT_M32R2_U_STORE, 1, 1 }, { (int) UNIT_M32R2_U_EXEC, 1, 0 } } },
3156  { M32R2F_INSN_STB_PLUS, model_m32r2_stb_plus, { { (int) UNIT_M32R2_U_STORE, 1, 1 }, { (int) UNIT_M32R2_U_EXEC, 1, 0 } } },
3157  { M32R2F_INSN_ST_MINUS, model_m32r2_st_minus, { { (int) UNIT_M32R2_U_STORE, 1, 1 }, { (int) UNIT_M32R2_U_EXEC, 1, 0 } } },
3158  { M32R2F_INSN_SUB, model_m32r2_sub, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3159  { M32R2F_INSN_SUBV, model_m32r2_subv, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3160  { M32R2F_INSN_SUBX, model_m32r2_subx, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3161  { M32R2F_INSN_TRAP, model_m32r2_trap, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3162  { M32R2F_INSN_UNLOCK, model_m32r2_unlock, { { (int) UNIT_M32R2_U_LOAD, 1, 1 } } },
3163  { M32R2F_INSN_SATB, model_m32r2_satb, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3164  { M32R2F_INSN_SATH, model_m32r2_sath, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3165  { M32R2F_INSN_SAT, model_m32r2_sat, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3166  { M32R2F_INSN_PCMPBZ, model_m32r2_pcmpbz, { { (int) UNIT_M32R2_U_CMP, 1, 1 } } },
3167  { M32R2F_INSN_SADD, model_m32r2_sadd, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
3168  { M32R2F_INSN_MACWU1, model_m32r2_macwu1, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
3169  { M32R2F_INSN_MSBLO, model_m32r2_msblo, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
3170  { M32R2F_INSN_MULWU1, model_m32r2_mulwu1, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
3171  { M32R2F_INSN_MACLH1, model_m32r2_maclh1, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
3172  { M32R2F_INSN_SC, model_m32r2_sc, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3173  { M32R2F_INSN_SNC, model_m32r2_snc, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3174  { M32R2F_INSN_CLRPSW, model_m32r2_clrpsw, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3175  { M32R2F_INSN_SETPSW, model_m32r2_setpsw, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3176  { M32R2F_INSN_BSET, model_m32r2_bset, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3177  { M32R2F_INSN_BCLR, model_m32r2_bclr, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3178  { M32R2F_INSN_BTST, model_m32r2_btst, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3179};
3180
3181#endif /* WITH_PROFILE_MODEL_P */
3182
3183static void
3184m32r2_model_init (SIM_CPU *cpu)
3185{
3186  CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_M32R2_DATA));
3187}
3188
3189#if WITH_PROFILE_MODEL_P
3190#define TIMING_DATA(td) td
3191#else
3192#define TIMING_DATA(td) 0
3193#endif
3194
3195static const MODEL m32r2_models[] =
3196{
3197  { "m32r2", & m32r2_mach, MODEL_M32R2, TIMING_DATA (& m32r2_timing[0]), m32r2_model_init },
3198  { 0 }
3199};
3200
3201/* The properties of this cpu's implementation.  */
3202
3203static const MACH_IMP_PROPERTIES m32r2f_imp_properties =
3204{
3205  sizeof (SIM_CPU),
3206#if WITH_SCACHE
3207  sizeof (SCACHE)
3208#else
3209  0
3210#endif
3211};
3212
3213
3214static void
3215m32r2f_prepare_run (SIM_CPU *cpu)
3216{
3217  if (CPU_IDESC (cpu) == NULL)
3218    m32r2f_init_idesc_table (cpu);
3219}
3220
3221static const CGEN_INSN *
3222m32r2f_get_idata (SIM_CPU *cpu, int inum)
3223{
3224  return CPU_IDESC (cpu) [inum].idata;
3225}
3226
3227static void
3228m32r2_init_cpu (SIM_CPU *cpu)
3229{
3230  CPU_REG_FETCH (cpu) = m32r2f_fetch_register;
3231  CPU_REG_STORE (cpu) = m32r2f_store_register;
3232  CPU_PC_FETCH (cpu) = m32r2f_h_pc_get;
3233  CPU_PC_STORE (cpu) = m32r2f_h_pc_set;
3234  CPU_GET_IDATA (cpu) = m32r2f_get_idata;
3235  CPU_MAX_INSNS (cpu) = M32R2F_INSN__MAX;
3236  CPU_INSN_NAME (cpu) = cgen_insn_name;
3237  CPU_FULL_ENGINE_FN (cpu) = m32r2f_engine_run_full;
3238#if WITH_FAST
3239  CPU_FAST_ENGINE_FN (cpu) = m32r2f_engine_run_fast;
3240#else
3241  CPU_FAST_ENGINE_FN (cpu) = m32r2f_engine_run_full;
3242#endif
3243}
3244
3245const MACH m32r2_mach =
3246{
3247  "m32r2", "m32r2", MACH_M32R2,
3248  32, 32, & m32r2_models[0], & m32r2f_imp_properties,
3249  m32r2_init_cpu,
3250  m32r2f_prepare_run
3251};
3252
3253