1; Renesas M32C CPU description. -*- Scheme -*- 2; 3; Copyright 2005, 2006, 2007 Free Software Foundation, Inc. 4; 5; Contributed by Red Hat Inc; developed under contract from Renesas. 6; 7; This file is part of the GNU Binutils. 8; 9; This program is free software; you can redistribute it and/or modify 10; it under the terms of the GNU General Public License as published by 11; the Free Software Foundation; either version 3 of the License, or 12; (at your option) any later version. 13; 14; This program is distributed in the hope that it will be useful, 15; but WITHOUT ANY WARRANTY; without even the implied warranty of 16; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17; GNU General Public License for more details. 18; 19; You should have received a copy of the GNU General Public License 20; along with this program; if not, write to the Free Software 21; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 22; MA 02110-1301, USA. 23 24(include "simplify.inc") 25 26(define-arch 27 (name m32c) 28 (comment "Renesas M32C") 29 (default-alignment forced) 30 (insn-lsb0? #f) 31 (machs m16c m32c) 32 (isas m16c m32c) 33) 34 35(define-isa 36 (name m16c) 37 38 (default-insn-bitsize 32) 39 40 ; Number of bytes of insn we can initially fetch. 41 (base-insn-bitsize 32) 42 43 ; Used in computing bit numbers. 44 (default-insn-word-bitsize 32) 45 46 (decode-assist (0 1 2 3 4 5 6 7)) ; Initial bitnumbers to decode insns by. 47 48 ; fetches 1 insn at a time. 49 (liw-insns 1) 50 51 ; executes 1 insn at a time. 52 (parallel-insns 1) 53 ) 54 55(define-isa 56 (name m32c) 57 58 (default-insn-bitsize 32) 59 60 ; Number of bytes of insn we can initially fetch. 61 (base-insn-bitsize 32) 62 63 ; Used in computing bit numbers. 64 (default-insn-word-bitsize 32) 65 66 (decode-assist (0 1 2 3 4 5 6 7)) ; Initial bitnumbers to decode insns by. 67 68 ; fetches 1 insn at a time. 69 (liw-insns 1) 70 71 ; executes 1 insn at a time. 72 (parallel-insns 1) 73 ) 74 75(define-cpu 76 ; cpu names must be distinct from the architecture name and machine names. 77 ; The "b" suffix stands for "base" and is the convention. 78 ; The "f" suffix stands for "family" and is the convention. 79 (name m16cbf) 80 (comment "Renesas M16C base family") 81 (insn-endian big) 82 (data-endian little) 83 (word-bitsize 16) 84) 85 86(define-cpu 87 ; cpu names must be distinct from the architecture name and machine names. 88 ; The "b" suffix stands for "base" and is the convention. 89 ; The "f" suffix stands for "family" and is the convention. 90 (name m32cbf) 91 (comment "Renesas M32C base family") 92 (insn-endian big) 93 (data-endian little) 94 (word-bitsize 16) 95) 96 97(define-mach 98 (name m16c) 99 (comment "Generic M16C cpu") 100 (cpu m32cbf) 101) 102 103(define-mach 104 (name m32c) 105 (comment "Generic M32C cpu") 106 (cpu m32cbf) 107) 108 109; Model descriptions. 110 111(define-model 112 (name m16c) 113 (comment "m16c") (attrs) 114 (mach m16c) 115 116 ; `state' is a list of variables for recording model state 117 ; (state) 118 (unit u-exec "Execution Unit" () 119 1 1 ; issue done 120 () ; state 121 () ; inputs 122 () ; outputs 123 () ; profile action (default) 124 ) 125) 126 127(define-model 128 (name m32c) 129 (comment "m32c") (attrs) 130 (mach m32c) 131 132 ; `state' is a list of variables for recording model state 133 ; (state) 134 (unit u-exec "Execution Unit" () 135 1 1 ; issue done 136 () ; state 137 () ; inputs 138 () ; outputs 139 () ; profile action (default) 140 ) 141) 142 143(define-attr 144 (type enum) 145 (name RL_TYPE) 146 (values NONE JUMP 1ADDR 2ADDR) 147 (default NONE) 148 ) 149 150; Macros to simplify MACH attribute specification. 151 152(define-pmacro all-isas () (ISA m16c,m32c)) 153(define-pmacro m16c-isa () (ISA m16c)) 154(define-pmacro m32c-isa () (ISA m32c)) 155 156(define-pmacro MACH16 (MACH m16c)) 157(define-pmacro MACH32 (MACH m32c)) 158 159(define-pmacro (machine size) 160 (MACH (.sym m size c)) (ISA (.sym m size c))) 161 162(define-pmacro RL_JUMP (RL_TYPE JUMP)) 163(define-pmacro RL_1ADDR (RL_TYPE 1ADDR)) 164(define-pmacro RL_2ADDR (RL_TYPE 2ADDR)) 165 166 167;============================================================= 168; Fields 169;------------------------------------------------------------- 170; Main opcodes 171; 172(dnf f-0-1 "opcode" (all-isas) 0 1) 173(dnf f-0-2 "opcode" (all-isas) 0 2) 174(dnf f-0-3 "opcode" (all-isas) 0 3) 175(dnf f-0-4 "opcode" (all-isas) 0 4) 176(dnf f-1-3 "opcode" (all-isas) 1 3) 177(dnf f-2-2 "opcode" (all-isas) 2 2) 178(dnf f-3-4 "opcode" (all-isas) 3 4) 179(dnf f-3-1 "opcode" (all-isas) 3 1) 180(dnf f-4-1 "opcode" (all-isas) 4 1) 181(dnf f-4-3 "opcode" (all-isas) 4 3) 182(dnf f-4-4 "opcode" (all-isas) 4 4) 183(dnf f-4-6 "opcode" (all-isas) 4 6) 184(dnf f-5-1 "opcode" (all-isas) 5 1) 185(dnf f-5-3 "opcode" (all-isas) 5 3) 186(dnf f-6-2 "opcode" (all-isas) 6 2) 187(dnf f-7-1 "opcode" (all-isas) 7 1) 188(dnf f-8-1 "opcode" (all-isas) 8 1) 189(dnf f-8-2 "opcode" (all-isas) 8 2) 190(dnf f-8-3 "opcode" (all-isas) 8 3) 191(dnf f-8-4 "opcode" (all-isas) 8 4) 192(dnf f-8-8 "opcode" (all-isas) 8 8) 193(dnf f-9-3 "opcode" (all-isas) 9 3) 194(dnf f-9-1 "opcode" (all-isas) 9 1) 195(dnf f-10-1 "opcode" (all-isas) 10 1) 196(dnf f-10-2 "opcode" (all-isas) 10 2) 197(dnf f-10-3 "opcode" (all-isas) 10 3) 198(dnf f-11-1 "opcode" (all-isas) 11 1) 199(dnf f-12-1 "opcode" (all-isas) 12 1) 200(dnf f-12-2 "opcode" (all-isas) 12 2) 201(dnf f-12-3 "opcode" (all-isas) 12 3) 202(dnf f-12-4 "opcode" (all-isas) 12 4) 203(dnf f-12-6 "opcode" (all-isas) 12 6) 204(dnf f-13-3 "opcode" (all-isas) 13 3) 205(dnf f-14-1 "opcode" (all-isas) 14 1) 206(dnf f-14-2 "opcode" (all-isas) 14 2) 207(dnf f-15-1 "opcode" (all-isas) 15 1) 208(dnf f-16-1 "opcode" (all-isas) 16 1) 209(dnf f-16-2 "opcode" (all-isas) 16 2) 210(dnf f-16-4 "opcode" (all-isas) 16 4) 211(dnf f-16-8 "opcode" (all-isas) 16 8) 212(dnf f-18-1 "opcode" (all-isas) 18 1) 213(dnf f-18-2 "opcode" (all-isas) 18 2) 214(dnf f-18-3 "opcode" (all-isas) 18 3) 215(dnf f-20-1 "opcode" (all-isas) 20 1) 216(dnf f-20-3 "opcode" (all-isas) 20 3) 217(dnf f-20-2 "opcode" (all-isas) 20 2) 218(dnf f-20-4 "opcode" (all-isas) 20 4) 219(dnf f-21-3 "opcode" (all-isas) 21 3) 220(dnf f-24-2 "opcode" (all-isas) 24 2) 221(dnf f-24-8 "opcode" (all-isas) 24 8) 222(dnf f-32-16 "opcode" (all-isas) 32 16) 223 224;------------------------------------------------------------- 225; Registers 226;------------------------------------------------------------- 227 228(dnf f-src16-rn "source Rn for m16c" (MACH16 m16c-isa) 10 2) 229(dnf f-src16-an "source An for m16c" (MACH16 m16c-isa) 11 1) 230 231(dnf f-src32-an-unprefixed "destination An for m32c" (MACH32 m32c-isa) 11 1) 232(dnf f-src32-an-prefixed "destination An for m32c" (MACH32 m32c-isa) 19 1) 233 234; QI mode gr encoding for m32c is different than for m16c. The hardware 235; is indexed using the m16c encoding, so perform the transformation here. 236; register m16c m32c 237; ---------------------- 238; r0l 00'b 10'b 239; r0h 01'b 00'b 240; r1l 10'b 11'b 241; r1h 11'b 01'b 242(df f-src32-rn-unprefixed-QI "source Rn QI for m32c" (MACH32 m32c-isa) 10 2 UINT 243 ((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert 244 ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract 245) 246; QI mode gr encoding for m32c is different than for m16c. The hardware 247; is indexed using the m16c encoding, so perform the transformation here. 248; register m16c m32c 249; ---------------------- 250; r0l 00'b 10'b 251; r0h 01'b 00'b 252; r1l 10'b 11'b 253; r1h 11'b 01'b 254(df f-src32-rn-prefixed-QI "source Rn QI for m32c" (MACH32 m32c-isa) 18 2 UINT 255 ((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert 256 ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract 257) 258; HI mode gr encoding for m32c is different than for m16c. The hardware 259; is indexed using the m16c encoding, so perform the transformation here. 260; register m16c m32c 261; ---------------------- 262; r0 00'b 10'b 263; r1 01'b 11'b 264; r2 10'b 00'b 265; r3 11'b 01'b 266(df f-src32-rn-unprefixed-HI "source Rn HI for m32c" (MACH32 m32c-isa) 10 2 UINT 267 ((value pc) (mod USI (add value 2) 4)) ; insert 268 ((value pc) (mod USI (add value 2) 4)) ; extract 269) 270 271; HI mode gr encoding for m32c is different than for m16c. The hardware 272; is indexed using the m16c encoding, so perform the transformation here. 273; register m16c m32c 274; ---------------------- 275; r0 00'b 10'b 276; r1 01'b 11'b 277; r2 10'b 00'b 278; r3 11'b 01'b 279(df f-src32-rn-prefixed-HI "source Rn HI for m32c" (MACH32 m32c-isa) 18 2 UINT 280 ((value pc) (mod USI (add value 2) 4)) ; insert 281 ((value pc) (mod USI (add value 2) 4)) ; extract 282) 283 284; SI mode gr encoding for m32c is as follows: 285; register encoding index 286; ------------------------- 287; r2r0 10'b 0 288; r3r1 11'b 1 289(df f-src32-rn-unprefixed-SI "source Rn SI for m32c" (MACH32 m32c-isa) 10 2 UINT 290 ((value pc) (add USI value 2)) ; insert 291 ((value pc) (sub USI value 2)) ; extract 292) 293(df f-src32-rn-prefixed-SI "source Rn SI for m32c" (MACH32 m32c-isa) 18 2 UINT 294 ((value pc) (add USI value 2)) ; insert 295 ((value pc) (sub USI value 2)) ; extract 296) 297 298(dnf f-dst32-rn-ext-unprefixed "destination Rn for m32c" (MACH32 m32c-isa) 9 1) 299 300(dnf f-dst16-rn "destination Rn for m16c" (MACH16 m16c-isa) 14 2) 301(dnf f-dst16-rn-ext "destination Rn for m16c" (MACH16 m16c-isa) 14 1) 302(dnf f-dst16-rn-QI-s "destination Rn for m16c" (MACH16 m16c-isa) 5 1) 303 304(dnf f-dst16-an "destination An for m16c" (MACH16 m16c-isa) 15 1) 305(dnf f-dst16-an-s "destination An for m16c" (MACH16 m16c-isa) 4 1) 306 307(dnf f-dst32-an-unprefixed "destination An for m32c" (MACH32 m32c-isa) 9 1) 308(dnf f-dst32-an-prefixed "destination An for m32c" (MACH32 m32c-isa) 17 1) 309 310; QI mode gr encoding for m32c is different than for m16c. The hardware 311; is indexed using the m16c encoding, so perform the transformation here. 312; register m16c m32c 313; ---------------------- 314; r0l 00'b 10'b 315; r0h 01'b 00'b 316; r1l 10'b 11'b 317; r1h 11'b 01'b 318(df f-dst32-rn-unprefixed-QI "destination Rn QI for m32c" (MACH32 m32c-isa) 8 2 UINT 319 ((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert 320 ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract 321) 322(df f-dst32-rn-prefixed-QI "destination Rn QI for m32c" (MACH32 m32c-isa) 16 2 UINT 323 ((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert 324 ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract 325) 326; HI mode gr encoding for m32c is different than for m16c. The hardware 327; is indexed using the m16c encoding, so perform the transformation here. 328; register m16c m32c 329; ---------------------- 330; r0 00'b 10'b 331; r1 01'b 11'b 332; r2 10'b 00'b 333; r3 11'b 01'b 334(df f-dst32-rn-unprefixed-HI "destination Rn HI for m32c" (MACH32 m32c-isa) 8 2 UINT 335 ((value pc) (mod USI (add value 2) 4)) ; insert 336 ((value pc) (mod USI (add value 2) 4)) ; extract 337) 338(df f-dst32-rn-prefixed-HI "destination Rn HI for m32c" (MACH32 m32c-isa) 16 2 UINT 339 ((value pc) (mod USI (add value 2) 4)) ; insert 340 ((value pc) (mod USI (add value 2) 4)) ; extract 341) 342; SI mode gr encoding for m32c is as follows: 343; register encoding index 344; ------------------------- 345; r2r0 10'b 0 346; r3r1 11'b 1 347(df f-dst32-rn-unprefixed-SI "destination Rn SI for m32c" (MACH32 m32c-isa) 8 2 UINT 348 ((value pc) (add USI value 2)) ; insert 349 ((value pc) (sub USI value 2)) ; extract 350) 351(df f-dst32-rn-prefixed-SI "destination Rn SI for m32c" (MACH32 m32c-isa) 16 2 UINT 352 ((value pc) (add USI value 2)) ; insert 353 ((value pc) (sub USI value 2)) ; extract 354) 355 356(dnf f-dst16-1-S "destination R0[hl] for m16c" (MACH16 m16c-isa) 5 1) 357 358;------------------------------------------------------------- 359; Immediates embedded in the base insn 360;------------------------------------------------------------- 361 362(df f-imm-8-s4 "4 bit signed" (all-isas) 8 4 INT #f #f) 363(df f-imm-12-s4 "4 bit signed" (all-isas) 12 4 INT #f #f) 364(df f-imm-13-u3 "3 bit unsigned" (all-isas) 13 3 UINT #f #f) 365(df f-imm-20-s4 "4 bit signed" (all-isas) 20 4 INT #f #f) 366 367(df f-imm1-S "1 bit immediate for short format binary insns" (MACH32 m32c-isa) 2 1 UINT 368 ((value pc) (sub USI value 1)) ; insert 369 ((value pc) (add USI value 1)) ; extract 370) 371 372(dnmf f-imm3-S "3 bit unsigned for short format insns" (all-isas) UINT 373 (f-2-2 f-7-1) 374 (sequence () ; insert 375 (set (ifield f-7-1) (and (sub (ifield f-imm3-S) 1) 1)) 376 (set (ifield f-2-2) (and (srl (sub (ifield f-imm3-S) 1) 1) #x3)) 377 ) 378 (sequence () ; extract 379 (set (ifield f-imm3-S) (add (or (sll (ifield f-2-2) 1) 380 (ifield f-7-1)) 381 1)) 382 ) 383) 384 385;------------------------------------------------------------- 386; Immediates and displacements beyond the base insn 387;------------------------------------------------------------- 388 389(df f-dsp-8-u6 "6 bit unsigned" (all-isas) 8 6 UINT #f #f) 390(df f-dsp-8-u8 "8 bit unsigned" (all-isas) 8 8 UINT #f #f) 391(df f-dsp-8-s8 "8 bit signed" (all-isas) 8 8 INT #f #f) 392(df f-dsp-10-u6 "6 bit unsigned" (all-isas) 10 6 UINT #f #f) 393(df f-dsp-16-u8 "8 bit unsigned" (all-isas) 16 8 UINT #f #f) 394(df f-dsp-16-s8 "8 bit signed" (all-isas) 16 8 INT #f #f) 395(df f-dsp-24-u8 "8 bit unsigned" (all-isas) 24 8 UINT #f #f) 396(df f-dsp-24-s8 "8 bit signed" (all-isas) 24 8 INT #f #f) 397(df f-dsp-32-u8 "8 bit unsigned" (all-isas) 32 8 UINT #f #f) 398(df f-dsp-32-s8 "8 bit signed" (all-isas) 32 8 INT #f #f) 399(df f-dsp-40-u8 "8 bit unsigned" (all-isas) 40 8 UINT #f #f) 400(df f-dsp-40-s8 "8 bit signed" (all-isas) 40 8 INT #f #f) 401(df f-dsp-48-u8 "8 bit unsigned" (all-isas) 48 8 UINT #f #f) 402(df f-dsp-48-s8 "8 bit signed" (all-isas) 48 8 INT #f #f) 403(df f-dsp-56-u8 "8 bit unsigned" (all-isas) 56 8 UINT #f #f) 404(df f-dsp-56-s8 "8 bit signed" (all-isas) 56 8 INT #f #f) 405(df f-dsp-64-u8 "8 bit unsigned" (all-isas) 64 8 UINT #f #f) 406(df f-dsp-64-s8 "8 bit signed" (all-isas) 64 8 INT #f #f) 407 408; Insn opcode endianness is big, but the immediate fields are stored 409; in little endian. Handle this here at the field level for all immediate 410; fields longer that 1 byte. 411; 412; CGEN can't handle a field which spans a 32 bit word boundary, so 413; handle those as multi ifields. 414; 415; Take care in expressions using 'srl' or 'sll' as part of some larger 416; expression meant to yield sign-extended values. CGEN translates 417; uses of those operators into C expressions whose type is 'unsigned 418; int', which tends to make the whole expression 'unsigned int'. 419; Expressions like (set (ifield foo) X), however, just take X and 420; store it in some member of 'struct cgen_fields', all of whose 421; members are 'long'. On machines where 'long' is larger than 422; 'unsigned int', assigning a "sign-extended" unsigned int to a long 423; just produces a very large positive value. insert_normal will 424; range-check the field's value and produce odd error messages like 425; this: 426; 427; Error: operand out of range (4160684031 not between -2147483648 and 2147483647) `add.l #-265,-270[fb]' 428; 429; Annoyingly, the code will work fine on machines where 'long' and 430; 'unsigned int' are the same size: the assignment will produce a 431; negative number. 432; 433; Just tell yourself over and over: overflow detection is expensive, 434; and you're glad C doesn't do it, because it never happens in real 435; life. 436 437(df f-dsp-8-u16 "16 bit unsigned" (all-isas) 8 16 UINT 438 ((value pc) (or UHI 439 (and (srl value 8) #x00ff) 440 (and (sll value 8) #xff00))) ; insert 441 ((value pc) (or UHI 442 (and UHI (srl UHI value 8) #x00ff) 443 (and UHI (sll UHI value 8) #xff00))) ; extract 444) 445 446(df f-dsp-8-s16 "8 bit signed" (all-isas) 8 16 INT 447 ((value pc) (ext INT 448 (trunc HI 449 (or (and (srl value 8) #x00ff) 450 (and (sll value 8) #xff00))))) ; insert 451 ((value pc) (ext INT 452 (trunc HI 453 (or (and (srl value 8) #x00ff) 454 (and (sll value 8) #xff00))))) ; extract 455) 456 457(df f-dsp-16-u16 "16 bit unsigned" (all-isas) 16 16 UINT 458 ((value pc) (or UHI 459 (and (srl value 8) #x00ff) 460 (and (sll value 8) #xff00))) ; insert 461 ((value pc) (or UHI 462 (and UHI (srl UHI value 8) #x00ff) 463 (and UHI (sll UHI value 8) #xff00))) ; extract 464) 465 466(df f-dsp-16-s16 "16 bit signed" (all-isas) 16 16 INT 467 ((value pc) (ext INT 468 (trunc HI 469 (or (and (srl value 8) #x00ff) 470 (and (sll value 8) #xff00))))) ; insert 471 ((value pc) (ext INT 472 (trunc HI 473 (or (and (srl value 8) #x00ff) 474 (and (sll value 8) #xff00))))) ; extract 475) 476 477(dnmf f-dsp-24-u16 "16 bit unsigned" (all-isas) UINT 478 (f-dsp-24-u8 f-dsp-32-u8) 479 (sequence () ; insert 480 (set (ifield f-dsp-24-u8) (and (ifield f-dsp-24-u16) #xff)) 481 (set (ifield f-dsp-32-u8) (and (srl (ifield f-dsp-24-u16) 8) #xff)) 482 ) 483 (sequence () ; extract 484 (set (ifield f-dsp-24-u16) (or (sll (ifield f-dsp-32-u8) 8) 485 (ifield f-dsp-24-u8))) 486 ) 487) 488 489(dnmf f-dsp-24-s16 "16 bit signed" (all-isas) INT 490 (f-dsp-24-u8 f-dsp-32-u8) 491 (sequence () ; insert 492 (set (ifield f-dsp-24-u8) 493 (and (ifield f-dsp-24-s16) #xff)) 494 (set (ifield f-dsp-32-u8) 495 (and (srl (ifield f-dsp-24-s16) 8) #xff)) 496 ) 497 (sequence () ; extract 498 (set (ifield f-dsp-24-s16) 499 (ext INT 500 (trunc HI (or (sll (ifield f-dsp-32-u8) 8) 501 (ifield f-dsp-24-u8))))) 502 ) 503) 504 505(df f-dsp-32-u16 "16 bit unsigned" (all-isas) 32 16 UINT 506 ((value pc) (or UHI 507 (and (srl value 8) #x00ff) 508 (and (sll value 8) #xff00))) ; insert 509 ((value pc) (or UHI 510 (and UHI (srl UHI value 8) #x00ff) 511 (and UHI (sll UHI value 8) #xff00))) ; extract 512) 513 514(df f-dsp-32-s16 "16 bit signed" (all-isas) 32 16 INT 515 ((value pc) (ext INT 516 (trunc HI 517 (or (and (srl value 8) #x00ff) 518 (and (sll value 8) #xff00))))) ; insert 519 ((value pc) (ext INT 520 (trunc HI 521 (or (and (srl value 8) #x00ff) 522 (and (sll value 8) #xff00))))) ; extract 523) 524 525(df f-dsp-40-u16 "16 bit unsigned" (all-isas) 40 16 UINT 526 ((value pc) (or UHI 527 (and (srl value 8) #x00ff) 528 (and (sll value 8) #xff00))) ; insert 529 ((value pc) (or UHI 530 (and UHI (srl UHI value 8) #x00ff) 531 (and UHI (sll UHI value 8) #xff00))) ; extract 532) 533 534(df f-dsp-40-s16 "16 bit signed" (all-isas) 40 16 INT 535 ((value pc) (ext INT 536 (trunc HI 537 (or (and (srl value 8) #x00ff) 538 (and (sll value 8) #xff00))))) ; insert 539 ((value pc) (ext INT 540 (trunc HI 541 (or (and (srl value 8) #x00ff) 542 (and (sll value 8) #xff00))))) ; extract 543) 544 545(df f-dsp-48-u16 "16 bit unsigned" (all-isas) 48 16 UINT 546 ((value pc) (or UHI 547 (and (srl value 8) #x00ff) 548 (and (sll value 8) #xff00))) ; insert 549 ((value pc) (or UHI 550 (and UHI (srl UHI value 8) #x00ff) 551 (and UHI (sll UHI value 8) #xff00))) ; extract 552) 553 554(df f-dsp-48-s16 "16 bit signed" (all-isas) 48 16 INT 555 ((value pc) (ext INT 556 (trunc HI 557 (or (and (srl value 8) #x00ff) 558 (and (sll value 8) #xff00))))) ; insert 559 ((value pc) (ext INT 560 (trunc HI 561 (or (and (srl value 8) #x00ff) 562 (and (sll value 8) #xff00))))) ; extract 563) 564 565(df f-dsp-64-u16 "16 bit unsigned" (all-isas) 64 16 UINT 566 ((value pc) (or UHI 567 (and (srl value 8) #x00ff) 568 (and (sll value 8) #xff00))) ; insert 569 ((value pc) (or UHI 570 (and UHI (srl UHI value 8) #x00ff) 571 (and UHI (sll UHI value 8) #xff00))) ; extract 572) 573(df f-dsp-8-s24 "24 bit signed" (all-isas) 8 24 INT 574 ((value pc) (or SI 575 (or (srl value 16) (and value #xff00)) 576 (sll (ext INT (trunc QI (and value #xff))) 16))) 577 ((value pc) (or SI 578 (or (srl value 16) (and value #xff00)) 579 (sll (ext INT (trunc QI (and value #xff))) 16))) 580 ) 581 582(df f-dsp-8-u24 "24 bit unsigned" (all-isas) 8 24 UINT 583 ((value pc) (or SI 584 (or (srl value 16) (and value #xff00)) 585 (sll (and value #xff) 16))) 586 ((value pc) (or SI 587 (or (srl value 16) (and value #xff00)) 588 (sll (and value #xff) 16))) 589 ) 590 591(dnmf f-dsp-16-u24 "24 bit unsigned" (all-isas) UINT 592 (f-dsp-16-u16 f-dsp-32-u8) 593 (sequence () ; insert 594 (set (ifield f-dsp-16-u16) (and (ifield f-dsp-16-u24) #xffff)) 595 (set (ifield f-dsp-32-u8) (and (srl (ifield f-dsp-16-u24) 16) #xff)) 596 ) 597 (sequence () ; extract 598 (set (ifield f-dsp-16-u24) (or (sll (ifield f-dsp-32-u8) 16) 599 (ifield f-dsp-16-u16))) 600 ) 601) 602 603(dnmf f-dsp-24-u24 "24 bit unsigned" (all-isas) UINT 604 (f-dsp-24-u8 f-dsp-32-u16) 605 (sequence () ; insert 606 (set (ifield f-dsp-24-u8) (and (ifield f-dsp-24-u24) #xff)) 607 (set (ifield f-dsp-32-u16) (and (srl (ifield f-dsp-24-u24) 8) #xffff)) 608 ) 609 (sequence () ; extract 610 (set (ifield f-dsp-24-u24) (or (sll (ifield f-dsp-32-u16) 8) 611 (ifield f-dsp-24-u8))) 612 ) 613) 614 615(df f-dsp-32-u24 "24 bit unsigned" (all-isas) 32 24 UINT 616 ((value pc) (or USI 617 (or USI 618 (and (srl value 16) #x0000ff) 619 (and value #x00ff00)) 620 (and (sll value 16) #xff0000))) ; insert 621 ((value pc) (or USI 622 (or USI 623 (and USI (srl UHI value 16) #x0000ff) 624 (and USI value #x00ff00)) 625 (and USI (sll UHI value 16) #xff0000))) ; extract 626) 627 628(df f-dsp-40-u20 "20 bit unsigned" (all-isas) 40 20 UINT 629 ((value pc) (or USI 630 (or USI 631 (and (srl value 16) #x0000ff) 632 (and value #x00ff00)) 633 (and (sll value 16) #x0f0000))) ; insert 634 ((value pc) (or USI 635 (or USI 636 (and USI (srl UHI value 16) #x0000ff) 637 (and USI value #x00ff00)) 638 (and USI (sll UHI value 16) #x0f0000))) ; extract 639) 640(df f-dsp-40-u24 "24 bit unsigned" (all-isas) 40 24 UINT 641 ((value pc) (or USI 642 (or USI 643 (and (srl value 16) #x0000ff) 644 (and value #x00ff00)) 645 (and (sll value 16) #xff0000))) ; insert 646 ((value pc) (or USI 647 (or USI 648 (and USI (srl UHI value 16) #x0000ff) 649 (and USI value #x00ff00)) 650 (and USI (sll UHI value 16) #xff0000))) ; extract 651) 652 653(dnmf f-dsp-40-s32 "32 bit signed" (all-isas) INT 654 (f-dsp-40-u24 f-dsp-64-u8) 655 (sequence () ; insert 656 (set (ifield f-dsp-64-u8) (and (srl (ifield f-dsp-40-s32) 24) #xff)) 657 (set (ifield f-dsp-40-u24) (and (ifield f-dsp-40-s32) #xffffff)) 658 ) 659 (sequence () ; extract 660 (set (ifield f-dsp-40-s32) (or (and (ifield f-dsp-40-u24) #xffffff) 661 (and (sll (ifield f-dsp-64-u8) 24) #xff000000))) 662 ) 663) 664 665(dnmf f-dsp-48-u20 "20 bit unsigned" (all-isas) UINT 666 (f-dsp-48-u16 f-dsp-64-u8) 667 (sequence () ; insert 668 (set (ifield f-dsp-64-u8) (and (srl (ifield f-dsp-48-u20) 16) #x0f)) 669 (set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-u20) #xffff)) 670 ) 671 (sequence () ; extract 672 (set (ifield f-dsp-48-u20) (or (and (ifield f-dsp-48-u16) #xffff) 673 (and (sll (ifield f-dsp-64-u8) 16) #x0f0000))) 674 ) 675) 676(dnmf f-dsp-48-u24 "24 bit unsigned" (all-isas) UINT 677 (f-dsp-48-u16 f-dsp-64-u8) 678 (sequence () ; insert 679 (set (ifield f-dsp-64-u8) (and (srl (ifield f-dsp-48-u24) 16) #xff)) 680 (set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-u24) #xffff)) 681 ) 682 (sequence () ; extract 683 (set (ifield f-dsp-48-u24) (or (and (ifield f-dsp-48-u16) #xffff) 684 (and (sll (ifield f-dsp-64-u8) 16) #xff0000))) 685 ) 686) 687 688(dnmf f-dsp-16-s32 "32 bit signed" (all-isas) INT 689 (f-dsp-16-u16 f-dsp-32-u16) 690 (sequence () ; insert 691 (set (ifield f-dsp-32-u16) (and (srl (ifield f-dsp-16-s32) 16) #xffff)) 692 (set (ifield f-dsp-16-u16) (and (ifield f-dsp-16-s32) #xffff)) 693 ) 694 (sequence () ; extract 695 (set (ifield f-dsp-16-s32) (or (and (ifield f-dsp-16-u16) #xffff) 696 (and (sll (ifield f-dsp-32-u16) 16) #xffff0000))) 697 ) 698) 699 700(dnmf f-dsp-24-s32 "32 bit signed" (all-isas) INT 701 (f-dsp-24-u8 f-dsp-32-u24) 702 (sequence () ; insert 703 (set (ifield f-dsp-32-u24) (and (srl (ifield f-dsp-24-s32) 8) #xffffff)) 704 (set (ifield f-dsp-24-u8) (and (ifield f-dsp-24-s32) #xff)) 705 ) 706 (sequence () ; extract 707 (set (ifield f-dsp-24-s32) (or (and (ifield f-dsp-24-u8) #xff) 708 (and (sll (ifield f-dsp-32-u24) 8) #xffffff00))) 709 ) 710) 711 712(df f-dsp-32-s32 "32 bit signed" (all-isas) 32 32 INT 713 ((value pc) 714 715 ;; insert 716 (ext INT 717 (or SI 718 (or SI 719 (and (srl value 24) #x000000ff) 720 (and (srl value 8) #x0000ff00)) 721 (or SI 722 (and (sll value 8) #x00ff0000) 723 (and (sll value 24) #xff000000))))) 724 725 ;; extract 726 ((value pc) 727 (ext INT 728 (or SI 729 (or SI 730 (and (srl value 24) #x000000ff) 731 (and (srl value 8) #x0000ff00)) 732 (or SI 733 (and (sll value 8) #x00ff0000) 734 (and (sll value 24) #xff000000))))) 735) 736 737(dnmf f-dsp-48-u32 "32 bit unsigned" (all-isas) UINT 738 (f-dsp-48-u16 f-dsp-64-u16) 739 (sequence () ; insert 740 (set (ifield f-dsp-64-u16) (and (srl (ifield f-dsp-48-u32) 16) #xffff)) 741 (set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-u32) #xffff)) 742 ) 743 (sequence () ; extract 744 (set (ifield f-dsp-48-u32) (or (and (ifield f-dsp-48-u16) #xffff) 745 (and (sll (ifield f-dsp-64-u16) 16) #xffff0000))) 746 ) 747) 748 749(dnmf f-dsp-48-s32 "32 bit signed" (all-isas) INT 750 (f-dsp-48-u16 f-dsp-64-u16) 751 (sequence () ; insert 752 (set (ifield f-dsp-64-u16) (and (srl (ifield f-dsp-48-s32) 16) #xffff)) 753 (set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-s32) #xffff)) 754 ) 755 (sequence () ; extract 756 (set (ifield f-dsp-48-s32) (or (and (ifield f-dsp-48-u16) #xffff) 757 (and (sll (ifield f-dsp-64-u16) 16) #xffff0000))) 758 ) 759) 760 761(dnmf f-dsp-56-s16 "16 bit signed" (all-isas) INT 762 (f-dsp-56-u8 f-dsp-64-u8) 763 (sequence () ; insert 764 (set (ifield f-dsp-56-u8) 765 (and (ifield f-dsp-56-s16) #xff)) 766 (set (ifield f-dsp-64-u8) 767 (and (srl (ifield f-dsp-56-s16) 8) #xff)) 768 ) 769 (sequence () ; extract 770 (set (ifield f-dsp-56-s16) 771 (ext INT 772 (trunc HI (or (sll (ifield f-dsp-64-u8) 8) 773 (ifield f-dsp-56-u8))))) 774 ) 775) 776 777(df f-dsp-64-s16 " 16 bit signed" (all-isas) 64 16 INT 778 ((value pc) (ext INT 779 (trunc HI 780 (or (and (srl value 8) #x00ff) 781 (and (sll value 8) #xff00))))) ; insert 782 ((value pc) (ext INT 783 (trunc HI 784 (or (and (srl value 8) #x00ff) 785 (and (sll value 8) #xff00))))) ; extract 786) 787 788;------------------------------------------------------------- 789; Bit indices 790;------------------------------------------------------------- 791 792(dnf f-bitno16-S "bit index for m16c" (all-isas) 5 3) 793(dnf f-bitno32-prefixed "bit index for m32c" (all-isas) 21 3) 794(dnf f-bitno32-unprefixed "bit index for m32c" (all-isas) 13 3) 795 796(dnmf f-bitbase16-u11-S "unsigned bit,base:11" (all-isas) UINT 797 (f-bitno16-S f-dsp-8-u8) 798 (sequence () ; insert 799 (set (ifield f-bitno16-S) (and f-bitbase16-u11-S #x7)) 800 (set (ifield f-dsp-8-u8) (and (srl (ifield f-bitbase16-u11-S) 3) #xff)) 801 ) 802 (sequence () ; extract 803 (set (ifield f-bitbase16-u11-S) (or (sll (ifield f-dsp-8-u8) 3) 804 (ifield f-bitno16-S))) 805 ) 806) 807 808(dnmf f-bitbase32-16-u11-unprefixed "unsigned bit,base:11" (all-isas) UINT 809 (f-bitno32-unprefixed f-dsp-16-u8) 810 (sequence () ; insert 811 (set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-u11-unprefixed #x7)) 812 (set (ifield f-dsp-16-u8) (and (srl (ifield f-bitbase32-16-u11-unprefixed) 3) #xff)) 813 ) 814 (sequence () ; extract 815 (set (ifield f-bitbase32-16-u11-unprefixed) (or (sll (ifield f-dsp-16-u8) 3) 816 (ifield f-bitno32-unprefixed))) 817 ) 818) 819(dnmf f-bitbase32-16-s11-unprefixed "signed bit,base:11" (all-isas) INT 820 (f-bitno32-unprefixed f-dsp-16-s8) 821 (sequence () ; insert 822 (set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-s11-unprefixed #x7)) 823 (set (ifield f-dsp-16-s8) (sra INT (ifield f-bitbase32-16-s11-unprefixed) 3)) 824 ) 825 (sequence () ; extract 826 (set (ifield f-bitbase32-16-s11-unprefixed) (or (sll (ifield f-dsp-16-s8) 3) 827 (ifield f-bitno32-unprefixed))) 828 ) 829) 830(dnmf f-bitbase32-16-u19-unprefixed "unsigned bit,base:19" (all-isas) UINT 831 (f-bitno32-unprefixed f-dsp-16-u16) 832 (sequence () ; insert 833 (set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-u19-unprefixed #x7)) 834 (set (ifield f-dsp-16-u16) (and (srl (ifield f-bitbase32-16-u19-unprefixed) 3) #xffff)) 835 ) 836 (sequence () ; extract 837 (set (ifield f-bitbase32-16-u19-unprefixed) (or (sll (ifield f-dsp-16-u16) 3) 838 (ifield f-bitno32-unprefixed))) 839 ) 840) 841(dnmf f-bitbase32-16-s19-unprefixed "signed bit,base:11" (all-isas) INT 842 (f-bitno32-unprefixed f-dsp-16-s16) 843 (sequence () ; insert 844 (set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-s19-unprefixed #x7)) 845 (set (ifield f-dsp-16-s16) (sra INT (ifield f-bitbase32-16-s19-unprefixed) 3)) 846 ) 847 (sequence () ; extract 848 (set (ifield f-bitbase32-16-s19-unprefixed) (or (sll (ifield f-dsp-16-s16) 3) 849 (ifield f-bitno32-unprefixed))) 850 ) 851) 852; SID decoder doesn't handle multi-ifield referencing another multi-ifield :-( 853(dnmf f-bitbase32-16-u27-unprefixed "unsigned bit,base:27" (all-isas) UINT 854 (f-bitno32-unprefixed f-dsp-16-u16 f-dsp-32-u8) 855 (sequence () ; insert 856 (set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-u27-unprefixed #x7)) 857 (set (ifield f-dsp-16-u16) (and (srl (ifield f-bitbase32-16-u27-unprefixed) 3) #xffff)) 858 (set (ifield f-dsp-32-u8) (and (srl (ifield f-bitbase32-16-u27-unprefixed) 19) #xff)) 859 ) 860 (sequence () ; extract 861 (set (ifield f-bitbase32-16-u27-unprefixed) (or (sll (ifield f-dsp-16-u16) 3) 862 (or (sll (ifield f-dsp-32-u8) 19) 863 (ifield f-bitno32-unprefixed)))) 864 ) 865) 866(dnmf f-bitbase32-24-u11-prefixed "unsigned bit,base:11" (all-isas) UINT 867 (f-bitno32-prefixed f-dsp-24-u8) 868 (sequence () ; insert 869 (set (ifield f-bitno32-prefixed) (and f-bitbase32-24-u11-prefixed #x7)) 870 (set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-u11-prefixed) 3) #xff)) 871 ) 872 (sequence () ; extract 873 (set (ifield f-bitbase32-24-u11-prefixed) (or (sll (ifield f-dsp-24-u8) 3) 874 (ifield f-bitno32-prefixed))) 875 ) 876) 877(dnmf f-bitbase32-24-s11-prefixed "signed bit,base:11" (all-isas) INT 878 (f-bitno32-prefixed f-dsp-24-s8) 879 (sequence () ; insert 880 (set (ifield f-bitno32-prefixed) (and f-bitbase32-24-s11-prefixed #x7)) 881 (set (ifield f-dsp-24-s8) (sra INT (ifield f-bitbase32-24-s11-prefixed) 3)) 882 ) 883 (sequence () ; extract 884 (set (ifield f-bitbase32-24-s11-prefixed) (or (sll (ifield f-dsp-24-s8) 3) 885 (ifield f-bitno32-prefixed))) 886 ) 887) 888; SID decoder doesn't handle multi-ifield referencing another multi-ifield :-( 889(dnmf f-bitbase32-24-u19-prefixed "unsigned bit,base:19" (all-isas) UINT 890 (f-bitno32-prefixed f-dsp-24-u8 f-dsp-32-u8) 891 (sequence () ; insert 892 (set (ifield f-bitno32-prefixed) (and f-bitbase32-24-u19-prefixed #x7)) 893 (set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-u19-prefixed) 3) #xff)) 894 (set (ifield f-dsp-32-u8) (and (srl (ifield f-bitbase32-24-u19-prefixed) 11) #xff)) 895 ) 896 (sequence () ; extract 897 (set (ifield f-bitbase32-24-u19-prefixed) (or (sll (ifield f-dsp-24-u8) 3) 898 (or (sll (ifield f-dsp-32-u8) 11) 899 (ifield f-bitno32-prefixed)))) 900 ) 901) 902; SID decoder doesn't handle multi-ifield referencing another multi-ifield :-( 903(dnmf f-bitbase32-24-s19-prefixed "signed bit,base:11" (all-isas) INT 904 (f-bitno32-prefixed f-dsp-24-u8 f-dsp-32-s8) 905 (sequence () ; insert 906 (set (ifield f-bitno32-prefixed) (and f-bitbase32-24-s19-prefixed #x7)) 907 (set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-s19-prefixed) 3) #xff)) 908 (set (ifield f-dsp-32-s8) (sra INT (ifield f-bitbase32-24-s19-prefixed) 11)) 909 ) 910 (sequence () ; extract 911 (set (ifield f-bitbase32-24-s19-prefixed) (or (sll (ifield f-dsp-24-u8) 3) 912 (or (sll (ifield f-dsp-32-s8) 11) 913 (ifield f-bitno32-prefixed)))) 914 ) 915) 916; SID decoder doesn't handle multi-ifield referencing another multi-ifield :-( 917(dnmf f-bitbase32-24-u27-prefixed "unsigned bit,base:27" (all-isas) UINT 918 (f-bitno32-prefixed f-dsp-24-u8 f-dsp-32-u16) 919 (sequence () ; insert 920 (set (ifield f-bitno32-prefixed) (and f-bitbase32-24-u27-prefixed #x7)) 921 (set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-u27-prefixed) 3) #xff)) 922 (set (ifield f-dsp-32-u16) (and (srl (ifield f-bitbase32-24-u27-prefixed) 11) #xffff)) 923 ) 924 (sequence () ; extract 925 (set (ifield f-bitbase32-24-u27-prefixed) (or (sll (ifield f-dsp-24-u8) 3) 926 (or (sll (ifield f-dsp-32-u16) 11) 927 (ifield f-bitno32-prefixed)))) 928 ) 929) 930 931;------------------------------------------------------------- 932; Labels 933;------------------------------------------------------------- 934 935(df f-lab-5-3 "3 bit pc relative unsigned offset" (PCREL-ADDR all-isas) 5 3 UINT 936 ((value pc) (sub SI value (add SI pc 2))) ; insert 937 ((value pc) (add SI value (add SI pc 2))) ; extract 938) 939(dnmf f-lab32-jmp-s "unsigned 3 bit pc relative offset" (PCREL-ADDR all-isas) UINT 940 (f-2-2 f-7-1) 941 (sequence ((SI val)) ; insert 942 (set val (sub (sub (ifield f-lab32-jmp-s) pc) 2)) 943 (set (ifield f-7-1) (and val #x1)) 944 (set (ifield f-2-2) (srl val 1)) 945 ) 946 (sequence () ; extract 947 (set (ifield f-lab32-jmp-s) (add pc (add (or (sll (ifield f-2-2) 1) 948 (ifield f-7-1)) 949 2))) 950 ) 951) 952(df f-lab-8-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 8 8 INT 953 ((value pc) (sub SI value (add SI pc 1))) ; insert 954 ((value pc) (add SI value (add SI pc 1))) ; extract 955) 956(df f-lab-8-16 "16 bit pc relative signed offset" (PCREL-ADDR SIGN-OPT all-isas) 8 16 UINT 957 ((value pc) (or SI (sll (and (sub value (add pc 1)) #xff) 8) 958 (srl (and (sub value (add pc 1)) #xffff) 8))) 959 ((value pc) (add SI (or (srl (and value #xffff) 8) 960 (sra (sll (and value #xff) 24) 16)) (add pc 1))) 961 ) 962(df f-lab-8-24 "24 bit absolute" (all-isas ABS-ADDR) 8 24 UINT 963 ((value pc) (or SI 964 (or (srl value 16) (and value #xff00)) 965 (sll (and value #xff) 16))) 966 ((value pc) (or SI 967 (or (srl value 16) (and value #xff00)) 968 (sll (and value #xff) 16))) 969 ) 970(df f-lab-16-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 16 8 INT 971 ((value pc) (sub SI value (add SI pc 2))) ; insert 972 ((value pc) (add SI value (add SI pc 2))) ; extract 973) 974(df f-lab-24-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 24 8 INT 975 ((value pc) (sub SI value (add SI pc 2))) ; insert 976 ((value pc) (add SI value (add SI pc 2))) ; extract 977) 978(df f-lab-32-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 32 8 INT 979 ((value pc) (sub SI value (add SI pc 2))) ; insert 980 ((value pc) (add SI value (add SI pc 2))) ; extract 981) 982(df f-lab-40-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 40 8 INT 983 ((value pc) (sub SI value (add SI pc 2))) ; insert 984 ((value pc) (add SI value (add SI pc 2))) ; extract 985) 986 987;------------------------------------------------------------- 988; Condition codes 989;------------------------------------------------------------- 990 991(dnf f-cond16 "condition code" (all-isas) 12 4) 992(dnf f-cond16j-5 "condition code" (all-isas) 5 3) 993 994(dnmf f-cond32 "condition code" (all-isas) UINT 995 (f-9-1 f-13-3) 996 (sequence () ; insert 997 (set (ifield f-9-1) (and (srl (ifield f-cond32) 3) 1)) 998 (set (ifield f-13-3) (and (ifield f-cond32) #x7)) 999 ) 1000 (sequence () ; extract 1001 (set (ifield f-cond32) (or (sll (ifield f-9-1) 3) 1002 (ifield f-13-3))) 1003 ) 1004) 1005 1006(dnmf f-cond32j "condition code" (all-isas) UINT 1007 (f-1-3 f-7-1) 1008 (sequence () ; insert 1009 (set (ifield f-1-3) (and (srl (ifield f-cond32j) 1) #x7)) 1010 (set (ifield f-7-1) (and (ifield f-cond32j) #x1)) 1011 ) 1012 (sequence () ; extract 1013 (set (ifield f-cond32j) (or (sll (ifield f-1-3) 1) 1014 (ifield f-7-1))) 1015 ) 1016) 1017 1018;============================================================= 1019; Hardware 1020; 1021(dnh h-pc "program counter" (PC all-isas) (pc USI) () () ()) 1022 1023;------------------------------------------------------------- 1024; General registers 1025; The actual registers are 16 bits 1026;------------------------------------------------------------- 1027 1028(define-hardware 1029 (name h-gr) 1030 (comment "general 16 bit registers") 1031 (attrs all-isas CACHE-ADDR) 1032 (type register HI (4)) 1033 (indices keyword "" (("r0" 0) ("r1" 1) ("r2" 2) ("r3" 3)))) 1034 1035; Define different views of the grs as VIRTUAL with getter/setter specs 1036; 1037(define-hardware 1038 (name h-gr-QI) 1039 (comment "general 8 bit registers") 1040 (attrs all-isas VIRTUAL) 1041 (type register QI (4)) 1042 (indices keyword "" (("r0l" 0) ("r0h" 1) ("r1l" 2) ("r1h" 3))) 1043 (get (index) (and (if SI (mod index 2) 1044 (srl (reg h-gr (div index 2)) 8) 1045 (reg h-gr (div index 2))) 1046 #xff)) 1047 (set (index newval) (set (reg h-gr (div index 2)) 1048 (if SI (mod index 2) 1049 (or (and (reg h-gr (div index 2)) #xff) 1050 (sll (and newval #xff) 8)) 1051 (or (and (reg h-gr (div index 2)) #xff00) 1052 (and newval #xff)))))) 1053 1054(define-hardware 1055 (name h-gr-HI) 1056 (comment "general 16 bit registers") 1057 (attrs all-isas VIRTUAL) 1058 (type register HI (4)) 1059 (indices keyword "" (("r0" 0) ("r1" 1) ("r2" 2) ("r3" 3))) 1060 (get (index) (reg h-gr index)) 1061 (set (index newval) (set (reg h-gr index) newval))) 1062 1063(define-hardware 1064 (name h-gr-SI) 1065 (comment "general 32 bit registers") 1066 (attrs all-isas VIRTUAL) 1067 (type register SI (2)) 1068 (indices keyword "" (("r2r0" 0) ("r3r1" 1))) 1069 (get (index) (or SI 1070 (and (reg h-gr index) #xffff) 1071 (and (sll (reg h-gr (add index 2)) 16) #xffff0000))) 1072 (set (index newval) (sequence () 1073 (set (reg h-gr index) (and newval #xffff)) 1074 (set (reg h-gr (add index 2)) (srl newval 16))))) 1075 1076(define-hardware 1077 (name h-gr-ext-QI) 1078 (comment "general 16 bit registers") 1079 (attrs all-isas VIRTUAL) 1080 (type register HI (2)) 1081 (indices keyword "" (("r0l" 0) ("r1l" 1))) 1082 (get (index) (reg h-gr-QI (mul index 2))) 1083 (set (index newval) (set (reg h-gr (mul index 2)) newval))) 1084 1085(define-hardware 1086 (name h-gr-ext-HI) 1087 (comment "general 16 bit registers") 1088 (attrs all-isas VIRTUAL) 1089 (type register SI (2)) 1090 (indices keyword "" (("r0" 0) ("r1" 1))) 1091 (get (index) (reg h-gr (mul index 2))) 1092 (set (index newval) (set (reg h-gr-SI index) newval))) 1093 1094(define-hardware 1095 (name h-r0l) 1096 (comment "r0l register") 1097 (attrs all-isas VIRTUAL) 1098 (type register QI) 1099 (indices keyword "" (("r0l" 0))) 1100 (get () (reg h-gr-QI 0)) 1101 (set (newval) (set (reg h-gr-QI 0) newval))) 1102 1103(define-hardware 1104 (name h-r0h) 1105 (comment "r0h register") 1106 (attrs all-isas VIRTUAL) 1107 (type register QI) 1108 (indices keyword "" (("r0h" 0))) 1109 (get () (reg h-gr-QI 1)) 1110 (set (newval) (set (reg h-gr-QI 1) newval))) 1111 1112(define-hardware 1113 (name h-r1l) 1114 (comment "r1l register") 1115 (attrs all-isas VIRTUAL) 1116 (type register QI) 1117 (indices keyword "" (("r1l" 0))) 1118 (get () (reg h-gr-QI 2)) 1119 (set (newval) (set (reg h-gr-QI 2) newval))) 1120 1121(define-hardware 1122 (name h-r1h) 1123 (comment "r1h register") 1124 (attrs all-isas VIRTUAL) 1125 (type register QI) 1126 (indices keyword "" (("r1h" 0))) 1127 (get () (reg h-gr-QI 3)) 1128 (set (newval) (set (reg h-gr-QI 3) newval))) 1129 1130(define-hardware 1131 (name h-r0) 1132 (comment "r0 register") 1133 (attrs all-isas VIRTUAL) 1134 (type register HI) 1135 (indices keyword "" (("r0" 0))) 1136 (get () (reg h-gr 0)) 1137 (set (newval) (set (reg h-gr 0) newval))) 1138 1139(define-hardware 1140 (name h-r1) 1141 (comment "r1 register") 1142 (attrs all-isas VIRTUAL) 1143 (type register HI) 1144 (indices keyword "" (("r1" 0))) 1145 (get () (reg h-gr 1)) 1146 (set (newval) (set (reg h-gr 1) newval))) 1147 1148(define-hardware 1149 (name h-r2) 1150 (comment "r2 register") 1151 (attrs all-isas VIRTUAL) 1152 (type register HI) 1153 (indices keyword "" (("r2" 0))) 1154 (get () (reg h-gr 2)) 1155 (set (newval) (set (reg h-gr 2) newval))) 1156 1157(define-hardware 1158 (name h-r3) 1159 (comment "r3 register") 1160 (attrs all-isas VIRTUAL) 1161 (type register HI) 1162 (indices keyword "" (("r3" 0))) 1163 (get () (reg h-gr 3)) 1164 (set (newval) (set (reg h-gr 3) newval))) 1165 1166(define-hardware 1167 (name h-r0l-r0h) 1168 (comment "r0l or r0h") 1169 (attrs all-isas VIRTUAL) 1170 (type register QI (2)) 1171 (indices keyword "" (("r0l" 0) ("r0h" 1))) 1172 (get (index) (reg h-gr-QI index)) 1173 (set (index newval) (set (reg h-gr-QI index) newval))) 1174 1175(define-hardware 1176 (name h-r2r0) 1177 (comment "r2r0 register") 1178 (attrs all-isas VIRTUAL) 1179 (type register SI) 1180 (indices keyword "" (("r2r0" 0))) 1181 (get () (or (sll (reg h-gr 2) 16) (reg h-gr 0))) 1182 (set (newval) 1183 (sequence () 1184 (set (reg h-gr 0) newval) 1185 (set (reg h-gr 2) (sra newval 16))))) 1186 1187(define-hardware 1188 (name h-r3r1) 1189 (comment "r3r1 register") 1190 (attrs all-isas VIRTUAL) 1191 (type register SI) 1192 (indices keyword "" (("r3r1" 0))) 1193 (get () (or (sll (reg h-gr 3) 16) (reg h-gr 1))) 1194 (set (newval) 1195 (sequence () 1196 (set (reg h-gr 1) newval) 1197 (set (reg h-gr 3) (sra newval 16))))) 1198 1199(define-hardware 1200 (name h-r1r2r0) 1201 (comment "r1r2r0 register") 1202 (attrs all-isas VIRTUAL) 1203 (type register DI) 1204 (indices keyword "" (("r1r2r0" 0))) 1205 (get () (or DI (sll DI (reg h-gr 1) 32) (or (sll (reg h-gr 2) 16) (reg h-gr 0)))) 1206 (set (newval) 1207 (sequence () 1208 (set (reg h-gr 0) newval) 1209 (set (reg h-gr 2) (sra newval 16)) 1210 (set (reg h-gr 1) (sra newval 32))))) 1211 1212;------------------------------------------------------------- 1213; Address registers 1214;------------------------------------------------------------- 1215 1216(define-hardware 1217 (name h-ar) 1218 (comment "address registers") 1219 (attrs all-isas) 1220 (type register USI (2)) 1221 (indices keyword "" (("a0" 0) ("a1" 1))) 1222 (get (index) (c-call USI "h_ar_get_handler" index)) 1223 (set (index newval) (c-call VOID "h_ar_set_handler" index newval))) 1224 1225; Define different views of the ars as VIRTUAL with getter/setter specs 1226(define-hardware 1227 (name h-ar-QI) 1228 (comment "8 bit view of address register") 1229 (attrs all-isas VIRTUAL) 1230 (type register QI (2)) 1231 (indices keyword "" (("a0" 0) ("a1" 1))) 1232 (get (index) (reg h-ar index)) 1233 (set (index newval) (set (reg h-ar index) newval))) 1234 1235(define-hardware 1236 (name h-ar-HI) 1237 (comment "16 bit view of address register") 1238 (attrs all-isas VIRTUAL) 1239 (type register HI (2)) 1240 (indices keyword "" (("a0" 0) ("a1" 1))) 1241 (get (index) (reg h-ar index)) 1242 (set (index newval) (set (reg h-ar index) newval))) 1243 1244(define-hardware 1245 (name h-ar-SI) 1246 (comment "32 bit view of address register") 1247 (attrs all-isas VIRTUAL) 1248 (type register SI) 1249 (indices keyword "" (("a1a0" 0))) 1250 (get () (or SI (sll SI (ext SI (reg h-ar 1)) 16) (ext SI (reg h-ar 0)))) 1251 (set (newval) (sequence () 1252 (set (reg h-ar 0) (and newval #xffff)) 1253 (set (reg h-ar 1) (and (srl newval 16) #xffff))))) 1254 1255(define-hardware 1256 (name h-a0) 1257 (comment "16 bit view of address register") 1258 (attrs all-isas VIRTUAL) 1259 (type register HI) 1260 (indices keyword "" (("a0" 0))) 1261 (get () (reg h-ar 0)) 1262 (set (newval) (set (reg h-ar 0) newval))) 1263 1264(define-hardware 1265 (name h-a1) 1266 (comment "16 bit view of address register") 1267 (attrs all-isas VIRTUAL) 1268 (type register HI) 1269 (indices keyword "" (("a1" 1))) 1270 (get () (reg h-ar 1)) 1271 (set (newval) (set (reg h-ar 1) newval))) 1272 1273; SB Register 1274(define-hardware 1275 (name h-sb) 1276 (comment "SB register") 1277 (attrs all-isas) 1278 (type register USI) 1279 (get () (c-call USI "h_sb_get_handler")) 1280 (set (newval) (c-call VOID "h_sb_set_handler" newval)) 1281) 1282 1283; FB Register 1284(define-hardware 1285 (name h-fb) 1286 (comment "FB register") 1287 (attrs all-isas) 1288 (type register USI) 1289 (get () (c-call USI "h_fb_get_handler")) 1290 (set (newval) (c-call VOID "h_fb_set_handler" newval)) 1291) 1292 1293; SP Register 1294(define-hardware 1295 (name h-sp) 1296 (comment "SP register") 1297 (attrs all-isas) 1298 (type register USI) 1299 (get () (c-call USI "h_sp_get_handler")) 1300 (set (newval) (c-call VOID "h_sp_set_handler" newval)) 1301) 1302 1303;------------------------------------------------------------- 1304; condition-code bits 1305;------------------------------------------------------------- 1306 1307(define-hardware 1308 (name h-sbit) 1309 (comment "sign bit") 1310 (attrs all-isas) 1311 (type register BI) 1312) 1313 1314(define-hardware 1315 (name h-zbit) 1316 (comment "zero bit") 1317 (attrs all-isas) 1318 (type register BI) 1319) 1320 1321(define-hardware 1322 (name h-obit) 1323 (comment "overflow bit") 1324 (attrs all-isas) 1325 (type register BI) 1326) 1327 1328(define-hardware 1329 (name h-cbit) 1330 (comment "carry bit") 1331 (attrs all-isas) 1332 (type register BI) 1333) 1334 1335(define-hardware 1336 (name h-ubit) 1337 (comment "stack pointer select bit") 1338 (attrs all-isas) 1339 (type register BI) 1340) 1341 1342(define-hardware 1343 (name h-ibit) 1344 (comment "interrupt enable bit") 1345 (attrs all-isas) 1346 (type register BI) 1347) 1348 1349(define-hardware 1350 (name h-bbit) 1351 (comment "register bank select bit") 1352 (attrs all-isas) 1353 (type register BI) 1354) 1355 1356(define-hardware 1357 (name h-dbit) 1358 (comment "debug bit") 1359 (attrs all-isas) 1360 (type register BI) 1361) 1362 1363(define-hardware 1364 (name h-dct0) 1365 (comment "dma transfer count 000") 1366 (attrs all-isas) 1367 (type register UHI) 1368) 1369(define-hardware 1370 (name h-dct1) 1371 (comment "dma transfer count 001") 1372 (attrs all-isas) 1373 (type register UHI) 1374) 1375(define-hardware 1376 (name h-svf) 1377 (comment "save flag 011") 1378 (attrs all-isas) 1379 (type register UHI) 1380) 1381(define-hardware 1382 (name h-drc0) 1383 (comment "dma transfer count reload 100") 1384 (attrs all-isas) 1385 (type register UHI) 1386) 1387(define-hardware 1388 (name h-drc1) 1389 (comment "dma transfer count reload 101") 1390 (attrs all-isas) 1391 (type register UHI) 1392) 1393(define-hardware 1394 (name h-dmd0) 1395 (comment "dma mode 110") 1396 (attrs all-isas) 1397 (type register UQI) 1398) 1399(define-hardware 1400 (name h-dmd1) 1401 (comment "dma mode 111") 1402 (attrs all-isas) 1403 (type register UQI) 1404) 1405(define-hardware 1406 (name h-intb) 1407 (comment "interrupt table 000") 1408 (attrs all-isas) 1409 (type register USI) 1410) 1411(define-hardware 1412 (name h-svp) 1413 (comment "save pc 100") 1414 (attrs all-isas) 1415 (type register UHI) 1416) 1417(define-hardware 1418 (name h-vct) 1419 (comment "vector 101") 1420 (attrs all-isas) 1421 (type register USI) 1422) 1423(define-hardware 1424 (name h-isp) 1425 (comment "interrupt stack ptr 111") 1426 (attrs all-isas) 1427 (type register USI) 1428) 1429(define-hardware 1430 (name h-dma0) 1431 (comment "dma mem addr 010") 1432 (attrs all-isas) 1433 (type register USI) 1434) 1435(define-hardware 1436 (name h-dma1) 1437 (comment "dma mem addr 011") 1438 (attrs all-isas) 1439 (type register USI) 1440) 1441(define-hardware 1442 (name h-dra0) 1443 (comment "dma mem addr reload 100") 1444 (attrs all-isas) 1445 (type register USI) 1446) 1447(define-hardware 1448 (name h-dra1) 1449 (comment "dma mem addr reload 101") 1450 (attrs all-isas) 1451 (type register USI) 1452) 1453(define-hardware 1454 (name h-dsa0) 1455 (comment "dma sfr addr 110") 1456 (attrs all-isas) 1457 (type register USI) 1458) 1459(define-hardware 1460 (name h-dsa1) 1461 (comment "dma sfr addr 111") 1462 (attrs all-isas) 1463 (type register USI) 1464) 1465 1466;------------------------------------------------------------- 1467; Condition code operand hardware 1468;------------------------------------------------------------- 1469 1470(define-hardware 1471 (name h-cond16) 1472 (comment "condition code hardware for m16c") 1473 (attrs m16c-isa MACH16) 1474 (type immediate UQI) 1475 (values keyword "" 1476 (("geu" #x00) ("c" #x00) 1477 ("gtu" #x01) 1478 ("eq" #x02) ("z" #x02) 1479 ("n" #x03) 1480 ("le" #x04) 1481 ("o" #x05) 1482 ("ge" #x06) 1483 ("ltu" #xf8) ("nc" #xf8) 1484 ("leu" #xf9) 1485 ("ne" #xfa) ("nz" #xfa) 1486 ("pz" #xfb) 1487 ("gt" #xfc) 1488 ("no" #xfd) 1489 ("lt" #xfe) 1490 ) 1491 ) 1492) 1493(define-hardware 1494 (name h-cond16c) 1495 (comment "condition code hardware for m16c") 1496 (attrs m16c-isa MACH16) 1497 (type immediate UQI) 1498 (values keyword "" 1499 (("geu" #x00) ("c" #x00) 1500 ("gtu" #x01) 1501 ("eq" #x02) ("z" #x02) 1502 ("n" #x03) 1503 ("ltu" #x04) ("nc" #x04) 1504 ("leu" #x05) 1505 ("ne" #x06) ("nz" #x06) 1506 ("pz" #x07) 1507 ("le" #x08) 1508 ("o" #x09) 1509 ("ge" #x0a) 1510 ("gt" #x0c) 1511 ("no" #x0d) 1512 ("lt" #x0e) 1513 ) 1514 ) 1515) 1516(define-hardware 1517 (name h-cond16j) 1518 (comment "condition code hardware for m16c") 1519 (attrs m16c-isa MACH16) 1520 (type immediate UQI) 1521 (values keyword "" 1522 (("le" #x08) 1523 ("o" #x09) 1524 ("ge" #x0a) 1525 ("gt" #x0c) 1526 ("no" #x0d) 1527 ("lt" #x0e) 1528 ) 1529 ) 1530) 1531(define-hardware 1532 (name h-cond16j-5) 1533 (comment "condition code hardware for m16c") 1534 (attrs m16c-isa MACH16) 1535 (type immediate UQI) 1536 (values keyword "" 1537 (("geu" #x00) ("c" #x00) 1538 ("gtu" #x01) 1539 ("eq" #x02) ("z" #x02) 1540 ("n" #x03) 1541 ("ltu" #x04) ("nc" #x04) 1542 ("leu" #x05) 1543 ("ne" #x06) ("nz" #x06) 1544 ("pz" #x07) 1545 ) 1546 ) 1547) 1548 1549(define-hardware 1550 (name h-cond32) 1551 (comment "condition code hardware for m32c") 1552 (attrs m32c-isa MACH32) 1553 (type immediate UQI) 1554 (values keyword "" 1555 (("ltu" #x00) ("nc" #x00) 1556 ("leu" #x01) 1557 ("ne" #x02) ("nz" #x02) 1558 ("pz" #x03) 1559 ("no" #x04) 1560 ("gt" #x05) 1561 ("ge" #x06) 1562 ("geu" #x08) ("c" #x08) 1563 ("gtu" #x09) 1564 ("eq" #x0a) ("z" #x0a) 1565 ("n" #x0b) 1566 ("o" #x0c) 1567 ("le" #x0d) 1568 ("lt" #x0e) 1569 ) 1570 ) 1571) 1572 1573(define-hardware 1574 (name h-cr1-32) 1575 (comment "control registers") 1576 (attrs m32c-isa MACH32) 1577 (type immediate UQI) 1578 (values keyword "" (("dct0" 0) ("dct1" 1) ("flg" 2) ("svf" 3) ("drc0" 4) 1579 ("drc1" 5) ("dmd0" 6) ("dmd1" 7)))) 1580(define-hardware 1581 (name h-cr2-32) 1582 (comment "control registers") 1583 (attrs m32c-isa MACH32) 1584 (type immediate UQI) 1585 (values keyword "" (("intb" 0) ("sp" 1) ("sb" 2) ("fb" 3) ("svp" 4) 1586 ("vct" 5) ("isp" 7)))) 1587 1588(define-hardware 1589 (name h-cr3-32) 1590 (comment "control registers") 1591 (attrs m32c-isa MACH32) 1592 (type immediate UQI) 1593 (values keyword "" (("dma0" 2) ("dma1" 3) ("dra0" 4) 1594 ("dra1" 5) ("dsa0" 6) ("dsa1" 7)))) 1595(define-hardware 1596 (name h-cr-16) 1597 (comment "control registers") 1598 (attrs m16c-isa MACH16) 1599 (type immediate UQI) 1600 (values keyword "" (("intbl" 1) ("intbh" 2) ("flg" 3) ("isp" 4) 1601 ("sp" 5) ("sb" 6) ("fb" 7)))) 1602 1603(define-hardware 1604 (name h-flags) 1605 (comment "flag hardware for m32c") 1606 (attrs all-isas) 1607 (type immediate UQI) 1608 (values keyword "" 1609 (("c" #x0) 1610 ("d" #x1) 1611 ("z" #x2) 1612 ("s" #x3) 1613 ("b" #x4) 1614 ("o" #x5) 1615 ("i" #x6) 1616 ("u" #x7) 1617 ) 1618 ) 1619) 1620 1621;------------------------------------------------------------- 1622; Misc helper hardware 1623;------------------------------------------------------------- 1624 1625(define-hardware 1626 (name h-shimm) 1627 (comment "shift immediate") 1628 (attrs all-isas) 1629 (type immediate (INT 4)) 1630 (values keyword "" (("1" 0) ("2" 1) ("3" 2) ("4" 3) ("5" 4) ("6" 5) ("7" 6) 1631 ("8" 7) ("-1" -8) ("-2" -7) ("-3" -6) ("-4" -5) ("-5" -4) 1632 ("-6" -3) ("-7" -2) ("-8" -1) 1633 ))) 1634(define-hardware 1635 (name h-bit-index) 1636 (comment "bit index for the next insn") 1637 (attrs m32c-isa MACH32) 1638 (type register UHI) 1639) 1640(define-hardware 1641 (name h-src-index) 1642 (comment "source index for the next insn") 1643 (attrs m32c-isa MACH32) 1644 (type register UHI) 1645) 1646(define-hardware 1647 (name h-dst-index) 1648 (comment "destination index for the next insn") 1649 (attrs m32c-isa MACH32) 1650 (type register UHI) 1651) 1652(define-hardware 1653 (name h-src-indirect) 1654 (comment "indirect src for the next insn") 1655 (attrs all-isas) 1656 (type register UHI) 1657) 1658(define-hardware 1659 (name h-dst-indirect) 1660 (comment "indirect dst for the next insn") 1661 (attrs all-isas) 1662 (type register UHI) 1663) 1664(define-hardware 1665 (name h-none) 1666 (comment "for storing unused values") 1667 (attrs m32c-isa MACH32) 1668 (type register SI) 1669) 1670 1671;============================================================= 1672; Operands 1673;------------------------------------------------------------- 1674; Source Registers 1675;------------------------------------------------------------- 1676 1677(dnop Src16RnQI "general register QI view" (MACH16 m16c-isa) h-gr-QI f-src16-rn) 1678(dnop Src16RnHI "general register QH view" (MACH16 m16c-isa) h-gr-HI f-src16-rn) 1679 1680(dnop Src32RnUnprefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-QI f-src32-rn-unprefixed-QI) 1681(dnop Src32RnUnprefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-HI f-src32-rn-unprefixed-HI) 1682(dnop Src32RnUnprefixedSI "general register SI view" (MACH32 m32c-isa) h-gr-SI f-src32-rn-unprefixed-SI) 1683 1684(dnop Src32RnPrefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-QI f-src32-rn-prefixed-QI) 1685(dnop Src32RnPrefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-HI f-src32-rn-prefixed-HI) 1686(dnop Src32RnPrefixedSI "general register SI view" (MACH32 m32c-isa) h-gr-SI f-src32-rn-prefixed-SI) 1687 1688(dnop Src16An "address register" (MACH16 m16c-isa) h-ar f-src16-an) 1689(dnop Src16AnQI "address register QI view" (MACH16 m16c-isa) h-ar-QI f-src16-an) 1690(dnop Src16AnHI "address register HI view" (MACH16 m16c-isa) h-ar-HI f-src16-an) 1691 1692(dnop Src32AnUnprefixed "address register" (MACH32 m32c-isa) h-ar f-src32-an-unprefixed) 1693(dnop Src32AnUnprefixedQI "address register QI view" (MACH32 m32c-isa) h-ar-QI f-src32-an-unprefixed) 1694(dnop Src32AnUnprefixedHI "address register HI view" (MACH32 m32c-isa) h-ar-HI f-src32-an-unprefixed) 1695(dnop Src32AnUnprefixedSI "address register SI view" (MACH32 m32c-isa) h-ar f-src32-an-unprefixed) 1696 1697(dnop Src32AnPrefixed "address register" (MACH32 m32c-isa) h-ar f-src32-an-prefixed) 1698(dnop Src32AnPrefixedQI "address register QI view" (MACH32 m32c-isa) h-ar-QI f-src32-an-prefixed) 1699(dnop Src32AnPrefixedHI "address register HI view" (MACH32 m32c-isa) h-ar-HI f-src32-an-prefixed) 1700(dnop Src32AnPrefixedSI "address register SI view" (MACH32 m32c-isa) h-ar f-src32-an-prefixed) 1701 1702; Destination Registers 1703; 1704(dnop Dst16RnQI "general register QI view" (MACH16 m16c-isa) h-gr-QI f-dst16-rn) 1705(dnop Dst16RnHI "general register HI view" (MACH16 m16c-isa) h-gr-HI f-dst16-rn) 1706(dnop Dst16RnSI "general register SI view" (MACH16 m16c-isa) h-gr-SI f-dst16-rn) 1707(dnop Dst16RnExtQI "general register QI/HI view for 'ext' insns" (MACH16 m16c-isa) h-gr-ext-QI f-dst16-rn-ext) 1708 1709(dnop Dst32R0QI-S "general register QI view" (MACH32 m32c-isa) h-r0l f-nil) 1710(dnop Dst32R0HI-S "general register HI view" (MACH32 m32c-isa) h-r0 f-nil) 1711 1712(dnop Dst32RnUnprefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-QI f-dst32-rn-unprefixed-QI) 1713(dnop Dst32RnUnprefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-HI f-dst32-rn-unprefixed-HI) 1714(dnop Dst32RnUnprefixedSI "general register SI view" (MACH32 m32c-isa) h-gr-SI f-dst32-rn-unprefixed-SI) 1715(dnop Dst32RnExtUnprefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-ext-QI f-dst32-rn-ext-unprefixed) 1716(dnop Dst32RnExtUnprefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-ext-HI f-dst32-rn-ext-unprefixed) 1717 1718(dnop Dst32RnPrefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-QI f-dst32-rn-prefixed-QI) 1719(dnop Dst32RnPrefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-HI f-dst32-rn-prefixed-HI) 1720(dnop Dst32RnPrefixedSI "general register SI view" (MACH32 m32c-isa) h-gr-SI f-dst32-rn-prefixed-SI) 1721 1722(dnop Dst16RnQI-S "general register QI view" (MACH16 m16c-isa) h-r0l-r0h f-dst16-rn-QI-s) 1723 1724(dnop Dst16AnQI-S "address register QI view" (MACH16 m16c-isa) h-ar-QI f-dst16-rn-QI-s) 1725 1726(dnop Bit16Rn "general register bit view" (MACH16 m16c-isa) h-gr-HI f-dst16-rn) 1727 1728(dnop Bit32RnPrefixed "general register bit view" (MACH32 m32c-isa) h-gr-QI f-dst32-rn-prefixed-QI) 1729(dnop Bit32RnUnprefixed "general register bit view" (MACH32 m32c-isa) h-gr-QI f-dst32-rn-unprefixed-QI) 1730 1731(dnop R0 "r0" (all-isas) h-r0 f-nil) 1732(dnop R1 "r1" (all-isas) h-r1 f-nil) 1733(dnop R2 "r2" (all-isas) h-r2 f-nil) 1734(dnop R3 "r3" (all-isas) h-r3 f-nil) 1735(dnop R0l "r0l" (all-isas) h-r0l f-nil) 1736(dnop R0h "r0h" (all-isas) h-r0h f-nil) 1737(dnop R2R0 "r2r0" (all-isas) h-r2r0 f-nil) 1738(dnop R3R1 "r3r1" (all-isas) h-r3r1 f-nil) 1739(dnop R1R2R0 "r1r2r0" (all-isas) h-r1r2r0 f-nil) 1740 1741(dnop Dst16An "address register" (MACH16 m16c-isa) h-ar f-dst16-an) 1742(dnop Dst16AnQI "address register QI view" (MACH16 m16c-isa) h-ar-QI f-dst16-an) 1743(dnop Dst16AnHI "address register HI view" (MACH16 m16c-isa) h-ar-HI f-dst16-an) 1744(dnop Dst16AnSI "address register SI view" (MACH16 m16c-isa) h-ar-SI f-dst16-an) 1745(dnop Dst16An-S "address register HI view" (MACH16 m16c-isa) h-ar-HI f-dst16-an-s) 1746 1747(dnop Dst32AnUnprefixed "address register" (MACH32 m32c-isa) h-ar f-dst32-an-unprefixed) 1748(dnop Dst32AnUnprefixedQI "address register QI view" (MACH32 m32c-isa) h-ar-QI f-dst32-an-unprefixed) 1749(dnop Dst32AnUnprefixedHI "address register HI view" (MACH32 m32c-isa) h-ar-HI f-dst32-an-unprefixed) 1750(dnop Dst32AnUnprefixedSI "address register SI view" (MACH32 m32c-isa) h-ar f-dst32-an-unprefixed) 1751 1752(dnop Dst32AnExtUnprefixed "address register" (MACH32 m32c-isa) h-ar f-dst32-an-unprefixed) 1753 1754(dnop Dst32AnPrefixed "address register" (MACH32 m32c-isa) h-ar f-dst32-an-prefixed) 1755(dnop Dst32AnPrefixedQI "address register QI view" (MACH32 m32c-isa) h-ar-QI f-dst32-an-prefixed) 1756(dnop Dst32AnPrefixedHI "address register HI view" (MACH32 m32c-isa) h-ar-HI f-dst32-an-prefixed) 1757(dnop Dst32AnPrefixedSI "address register SI view" (MACH32 m32c-isa) h-ar f-dst32-an-prefixed) 1758 1759(dnop Bit16An "address register bit view" (MACH16 m16c-isa) h-ar f-dst16-an) 1760 1761(dnop Bit32AnPrefixed "address register bit" (MACH32 m32c-isa) h-ar f-dst32-an-prefixed) 1762(dnop Bit32AnUnprefixed "address register bit" (MACH32 m32c-isa) h-ar f-dst32-an-unprefixed) 1763 1764(dnop A0 "a0" (all-isas) h-a0 f-nil) 1765(dnop A1 "a1" (all-isas) h-a1 f-nil) 1766 1767(dnop sb "SB register" (all-isas SEM-ONLY) h-sb f-nil) 1768(dnop fb "FB register" (all-isas SEM-ONLY) h-fb f-nil) 1769(dnop sp "SP register" (all-isas SEM-ONLY) h-sp f-nil) 1770 1771(define-full-operand SrcDst16-r0l-r0h-S-normal "r0l/r0h pair" (MACH16 m16c-isa) 1772 h-sint DFLT f-5-1 1773 ((parse "r0l_r0h") (print "r0l_r0h")) () () 1774) 1775 1776(define-full-operand Regsetpop "popm regset" (all-isas) h-uint 1777 DFLT f-8-8 ((parse "pop_regset") (print "pop_regset")) () ()) 1778(define-full-operand Regsetpush "pushm regset" (all-isas) h-uint 1779 DFLT f-8-8 ((parse "push_regset") (print "push_regset")) () ()) 1780 1781(dnop Rn16-push-S "r0[lh]" (MACH16 m16c-isa) h-gr-QI f-4-1) 1782(dnop An16-push-S "a[01]" (MACH16 m16c-isa) h-ar-HI f-4-1) 1783 1784;------------------------------------------------------------- 1785; Offsets and absolutes 1786;------------------------------------------------------------- 1787 1788(define-full-operand Dsp-8-u6 "unsigned 6 bit displacement at offset 8 bits" (all-isas) 1789 h-uint DFLT f-dsp-8-u6 1790 ((parse "unsigned6")) () () 1791) 1792(define-full-operand Dsp-8-u8 "unsigned 8 bit displacement at offset 8 bits" (all-isas) 1793 h-uint DFLT f-dsp-8-u8 1794 ((parse "unsigned8")) () () 1795) 1796(define-full-operand Dsp-8-u16 "unsigned 16 bit displacement at offset 8 bits" (all-isas) 1797 h-uint DFLT f-dsp-8-u16 1798 ((parse "unsigned16")) () () 1799) 1800(define-full-operand Dsp-8-s8 "signed 8 bit displacement at offset 8 bits" (all-isas) 1801 h-sint DFLT f-dsp-8-s8 1802 ((parse "signed8")) () () 1803) 1804(define-full-operand Dsp-8-s24 "signed 24 bit displacement at offset 8 bits" (all-isas) 1805 h-sint DFLT f-dsp-8-s24 1806 ((parse "signed24")) () () 1807) 1808(define-full-operand Dsp-8-u24 "unsigned 24 bit displacement at offset 8 bits" (all-isas) 1809 h-uint DFLT f-dsp-8-u24 1810 ((parse "unsigned24")) () () 1811) 1812(define-full-operand Dsp-10-u6 "unsigned 6 bit displacement at offset 10 bits" (all-isas) 1813 h-uint DFLT f-dsp-10-u6 1814 ((parse "unsigned6")) () () 1815) 1816(define-full-operand Dsp-16-u8 "unsigned 8 bit displacement at offset 16 bits" (all-isas) 1817 h-uint DFLT f-dsp-16-u8 1818 ((parse "unsigned8")) () () 1819) 1820(define-full-operand Dsp-16-u16 "unsigned 16 bit displacement at offset 16 bits" (all-isas) 1821 h-uint DFLT f-dsp-16-u16 1822 ((parse "unsigned16")) () () 1823) 1824(define-full-operand Dsp-16-u20 "unsigned 20 bit displacement at offset 16 bits" (all-isas) 1825 h-uint DFLT f-dsp-16-u24 1826 ((parse "unsigned20")) () () 1827) 1828(define-full-operand Dsp-16-u24 "unsigned 24 bit displacement at offset 16 bits" (all-isas) 1829 h-uint DFLT f-dsp-16-u24 1830 ((parse "unsigned24")) () () 1831) 1832(define-full-operand Dsp-16-s8 "signed 8 bit displacement at offset 16 bits" (all-isas) 1833 h-sint DFLT f-dsp-16-s8 1834 ((parse "signed8")) () () 1835) 1836(define-full-operand Dsp-16-s16 "signed 16 bit displacement at offset 16 bits" (all-isas) 1837 h-sint DFLT f-dsp-16-s16 1838 ((parse "signed16")) () () 1839) 1840(define-full-operand Dsp-24-u8 "unsigned 8 bit displacement at offset 24 bits" (all-isas) 1841 h-uint DFLT f-dsp-24-u8 1842 ((parse "unsigned8")) () () 1843) 1844(define-full-operand Dsp-24-u16 "unsigned 16 bit displacement at offset 24 bits" (all-isas) 1845 h-uint DFLT f-dsp-24-u16 1846 ((parse "unsigned16")) () () 1847) 1848(define-full-operand Dsp-24-u20 "unsigned 20 bit displacement at offset 24 bits" (all-isas) 1849 h-uint DFLT f-dsp-24-u24 1850 ((parse "unsigned20")) () () 1851) 1852(define-full-operand Dsp-24-u24 "unsigned 24 bit displacement at offset 24 bits" (all-isas) 1853 h-uint DFLT f-dsp-24-u24 1854 ((parse "unsigned24")) () () 1855) 1856(define-full-operand Dsp-24-s8 "signed 8 bit displacement at offset 24 bits" (all-isas) 1857 h-sint DFLT f-dsp-24-s8 1858 ((parse "signed8")) () () 1859) 1860(define-full-operand Dsp-24-s16 "signed 16 bit displacement at offset 24 bits" (all-isas) 1861 h-sint DFLT f-dsp-24-s16 1862 ((parse "signed16")) () () 1863) 1864(define-full-operand Dsp-32-u8 "unsigned 8 bit displacement at offset 32 bits" (all-isas) 1865 h-uint DFLT f-dsp-32-u8 1866 ((parse "unsigned8")) () () 1867) 1868(define-full-operand Dsp-32-u16 "unsigned 16 bit displacement at offset 32 bits" (all-isas) 1869 h-uint DFLT f-dsp-32-u16 1870 ((parse "unsigned16")) () () 1871) 1872(define-full-operand Dsp-32-u24 "unsigned 24 bit displacement at offset 32 bits" (all-isas) 1873 h-uint DFLT f-dsp-32-u24 1874 ((parse "unsigned24")) () () 1875) 1876(define-full-operand Dsp-32-u20 "unsigned 20 bit displacement at offset 32 bits" (all-isas) 1877 h-uint DFLT f-dsp-32-u24 1878 ((parse "unsigned20")) () () 1879) 1880(define-full-operand Dsp-32-s8 "signed 8 bit displacement at offset 32 bits" (all-isas) 1881 h-sint DFLT f-dsp-32-s8 1882 ((parse "signed8")) () () 1883) 1884(define-full-operand Dsp-32-s16 "signed 16 bit displacement at offset 32 bits" (all-isas) 1885 h-sint DFLT f-dsp-32-s16 1886 ((parse "signed16")) () () 1887) 1888(define-full-operand Dsp-40-u8 "unsigned 8 bit displacement at offset 40 bits" (all-isas) 1889 h-uint DFLT f-dsp-40-u8 1890 ((parse "unsigned8")) () () 1891) 1892(define-full-operand Dsp-40-s8 "signed 8 bit displacement at offset 40 bits" (all-isas) 1893 h-sint DFLT f-dsp-40-s8 1894 ((parse "signed8")) () () 1895) 1896(define-full-operand Dsp-40-u16 "unsigned 16 bit displacement at offset 40 bits" (all-isas) 1897 h-uint DFLT f-dsp-40-u16 1898 ((parse "unsigned16")) () () 1899) 1900(define-full-operand Dsp-40-s16 "signed 16 bit displacement at offset 40 bits" (all-isas) 1901 h-sint DFLT f-dsp-40-s16 1902 ((parse "signed16")) () () 1903) 1904(define-full-operand Dsp-40-u20 "unsigned 20 bit displacement at offset 40 bits" (all-isas) 1905 h-uint DFLT f-dsp-40-u20 1906 ((parse "unsigned20")) () () 1907) 1908(define-full-operand Dsp-40-u24 "unsigned 24 bit displacement at offset 40 bits" (all-isas) 1909 h-uint DFLT f-dsp-40-u24 1910 ((parse "unsigned24")) () () 1911) 1912(define-full-operand Dsp-48-u8 "unsigned 8 bit displacement at offset 48 bits" (all-isas) 1913 h-uint DFLT f-dsp-48-u8 1914 ((parse "unsigned8")) () () 1915) 1916(define-full-operand Dsp-48-s8 "signed 8 bit displacement at offset 48 bits" (all-isas) 1917 h-sint DFLT f-dsp-48-s8 1918 ((parse "signed8")) () () 1919) 1920(define-full-operand Dsp-48-u16 "unsigned 16 bit displacement at offset 48 bits" (all-isas) 1921 h-uint DFLT f-dsp-48-u16 1922 ((parse "unsigned16")) () () 1923) 1924(define-full-operand Dsp-48-s16 "signed 16 bit displacement at offset 48 bits" (all-isas) 1925 h-sint DFLT f-dsp-48-s16 1926 ((parse "signed16")) () () 1927) 1928(define-full-operand Dsp-48-u20 "unsigned 24 bit displacement at offset 40 bits" (all-isas) 1929 h-uint DFLT f-dsp-48-u20 1930 ((parse "unsigned24")) () () 1931) 1932(define-full-operand Dsp-48-u24 "unsigned 24 bit displacement at offset 48 bits" (all-isas) 1933 h-uint DFLT f-dsp-48-u24 1934 ((parse "unsigned24")) () () 1935) 1936 1937(define-full-operand Imm-8-s4 "signed 4 bit immediate at offset 8 bits" (all-isas) 1938 h-sint DFLT f-imm-8-s4 1939 ((parse "signed4")) () () 1940) 1941(define-full-operand Imm-8-s4n "negated 4 bit immediate at offset 8 bits" (all-isas) 1942 h-sint DFLT f-imm-8-s4 1943 ((parse "signed4n") (print "signed4n")) () () 1944) 1945(define-full-operand Imm-sh-8-s4 "signed 4 bit shift immediate at offset 8 bits" (all-isas) 1946 h-shimm DFLT f-imm-8-s4 1947 () () () 1948) 1949(define-full-operand Imm-8-QI "signed 8 bit immediate at offset 8 bits" (all-isas) 1950 h-sint DFLT f-dsp-8-s8 1951 ((parse "signed8")) () () 1952) 1953(define-full-operand Imm-8-HI "signed 16 bit immediate at offset 8 bits" (all-isas) 1954 h-sint DFLT f-dsp-8-s16 1955 ((parse "signed16")) () () 1956) 1957(define-full-operand Imm-12-s4 "signed 4 bit immediate at offset 12 bits" (all-isas) 1958 h-sint DFLT f-imm-12-s4 1959 ((parse "signed4")) () () 1960) 1961(define-full-operand Imm-12-s4n "negated 4 bit immediate at offset 12 bits" (all-isas) 1962 h-sint DFLT f-imm-12-s4 1963 ((parse "signed4n") (print "signed4n")) () () 1964) 1965(define-full-operand Imm-sh-12-s4 "signed 4 bit shift immediate at offset 12 bits" (all-isas) 1966 h-shimm DFLT f-imm-12-s4 1967 () () () 1968) 1969(define-full-operand Imm-13-u3 "signed 3 bit immediate at offset 13 bits" (all-isas) 1970 h-sint DFLT f-imm-13-u3 1971 ((parse "signed4")) () () 1972) 1973(define-full-operand Imm-20-s4 "signed 4 bit immediate at offset 20 bits" (all-isas) 1974 h-sint DFLT f-imm-20-s4 1975 ((parse "signed4")) () () 1976) 1977(define-full-operand Imm-sh-20-s4 "signed 4 bit shift immediate at offset 12 bits" (all-isas) 1978 h-shimm DFLT f-imm-20-s4 1979 () () () 1980) 1981(define-full-operand Imm-16-QI "signed 8 bit immediate at offset 16 bits" (all-isas) 1982 h-sint DFLT f-dsp-16-s8 1983 ((parse "signed8")) () () 1984) 1985(define-full-operand Imm-16-HI "signed 16 bit immediate at offset 16 bits" (all-isas) 1986 h-sint DFLT f-dsp-16-s16 1987 ((parse "signed16")) () () 1988) 1989(define-full-operand Imm-16-SI "signed 32 bit immediate at offset 16 bits" (all-isas) 1990 h-sint DFLT f-dsp-16-s32 1991 ((parse "signed32")) () () 1992) 1993(define-full-operand Imm-24-QI "signed 8 bit immediate at offset 24 bits" (all-isas) 1994 h-sint DFLT f-dsp-24-s8 1995 ((parse "signed8")) () () 1996) 1997(define-full-operand Imm-24-HI "signed 16 bit immediate at offset 24 bits" (all-isas) 1998 h-sint DFLT f-dsp-24-s16 1999 ((parse "signed16")) () () 2000) 2001(define-full-operand Imm-24-SI "signed 32 bit immediate at offset 24 bits" (all-isas) 2002 h-sint DFLT f-dsp-24-s32 2003 ((parse "signed32")) () () 2004) 2005(define-full-operand Imm-32-QI "signed 8 bit immediate at offset 32 bits" (all-isas) 2006 h-sint DFLT f-dsp-32-s8 2007 ((parse "signed8")) () () 2008) 2009(define-full-operand Imm-32-SI "signed 32 bit immediate at offset 32 bits" (all-isas) 2010 h-sint DFLT f-dsp-32-s32 2011 ((parse "signed32")) () () 2012) 2013(define-full-operand Imm-32-HI "signed 16 bit immediate at offset 32 bits" (all-isas) 2014 h-sint DFLT f-dsp-32-s16 2015 ((parse "signed16")) () () 2016) 2017(define-full-operand Imm-40-QI "signed 8 bit immediate at offset 40 bits" (all-isas) 2018 h-sint DFLT f-dsp-40-s8 2019 ((parse "signed8")) () () 2020) 2021(define-full-operand Imm-40-HI "signed 16 bit immediate at offset 40 bits" (all-isas) 2022 h-sint DFLT f-dsp-40-s16 2023 ((parse "signed16")) () () 2024) 2025(define-full-operand Imm-40-SI "signed 32 bit immediate at offset 40 bits" (all-isas) 2026 h-sint DFLT f-dsp-40-s32 2027 ((parse "signed32")) () () 2028) 2029(define-full-operand Imm-48-QI "signed 8 bit immediate at offset 48 bits" (all-isas) 2030 h-sint DFLT f-dsp-48-s8 2031 ((parse "signed8")) () () 2032) 2033(define-full-operand Imm-48-HI "signed 16 bit immediate at offset 48 bits" (all-isas) 2034 h-sint DFLT f-dsp-48-s16 2035 ((parse "signed16")) () () 2036) 2037(define-full-operand Imm-48-SI "signed 32 bit immediate at offset 48 bits" (all-isas) 2038 h-sint DFLT f-dsp-48-s32 2039 ((parse "signed32")) () () 2040) 2041(define-full-operand Imm-56-QI "signed 8 bit immediate at offset 56 bits" (all-isas) 2042 h-sint DFLT f-dsp-56-s8 2043 ((parse "signed8")) () () 2044) 2045(define-full-operand Imm-56-HI "signed 16 bit immediate at offset 56 bits" (all-isas) 2046 h-sint DFLT f-dsp-56-s16 2047 ((parse "signed16")) () () 2048) 2049(define-full-operand Imm-64-HI "signed 16 bit immediate at offset 64 bits" (all-isas) 2050 h-sint DFLT f-dsp-64-s16 2051 ((parse "signed16")) () () 2052) 2053(define-full-operand Imm1-S "signed 1 bit immediate for short format binary insns" (m32c-isa) 2054 h-sint DFLT f-imm1-S 2055 ((parse "imm1_S")) () () 2056) 2057(define-full-operand Imm3-S "signed 3 bit immediate for short format binary insns" (m32c-isa) 2058 h-sint DFLT f-imm3-S 2059 ((parse "imm3_S")) () () 2060) 2061(define-full-operand Bit3-S "3 bit bit number" (m32c-isa) 2062 h-sint DFLT f-imm3-S 2063 ((parse "bit3_S")) () () 2064) 2065 2066;------------------------------------------------------------- 2067; Bit numbers 2068;------------------------------------------------------------- 2069 2070(define-full-operand Bitno16R "bit number for indexing registers" (m16c-isa) 2071 h-uint DFLT f-dsp-16-u8 2072 ((parse "Bitno16R")) () () 2073) 2074(dnop Bitno32Prefixed "bit number for indexing objects" (m32c-isa) h-uint f-bitno32-prefixed) 2075(dnop Bitno32Unprefixed "bit number for indexing objects" (m32c-isa) h-uint f-bitno32-unprefixed) 2076 2077(define-full-operand BitBase16-16-u8 "unsigned bit,base:8 at offset 16for m16c" (m16c-isa) 2078 h-uint DFLT f-dsp-16-u8 2079 ((parse "unsigned_bitbase8") (print "unsigned_bitbase")) () () 2080) 2081(define-full-operand BitBase16-16-s8 "signed bit,base:8 at offset 16for m16c" (m16c-isa) 2082 h-sint DFLT f-dsp-16-s8 2083 ((parse "signed_bitbase8") (print "signed_bitbase")) () () 2084) 2085(define-full-operand BitBase16-16-u16 "unsigned bit,base:16 at offset 16 for m16c" (m16c-isa) 2086 h-uint DFLT f-dsp-16-u16 2087 ((parse "unsigned_bitbase16") (print "unsigned_bitbase")) () () 2088) 2089(define-full-operand BitBase16-8-u11-S "signed bit,base:11 at offset 16 for m16c" (m16c-isa) 2090 h-uint DFLT f-bitbase16-u11-S 2091 ((parse "unsigned_bitbase11") (print "unsigned_bitbase")) () () 2092) 2093 2094(define-full-operand BitBase32-16-u11-Unprefixed "unsigned bit,base:11 at offset 16 for m32c" (m32c-isa) 2095 h-uint DFLT f-bitbase32-16-u11-unprefixed 2096 ((parse "unsigned_bitbase11") (print "unsigned_bitbase")) () () 2097) 2098(define-full-operand BitBase32-16-s11-Unprefixed "signed bit,base:11 at offset 16 for m32c" (m32c-isa) 2099 h-sint DFLT f-bitbase32-16-s11-unprefixed 2100 ((parse "signed_bitbase11") (print "signed_bitbase")) () () 2101) 2102(define-full-operand BitBase32-16-u19-Unprefixed "unsigned bit,base:19 at offset 16 for m32c" (m32c-isa) 2103 h-uint DFLT f-bitbase32-16-u19-unprefixed 2104 ((parse "unsigned_bitbase19") (print "unsigned_bitbase")) () () 2105) 2106(define-full-operand BitBase32-16-s19-Unprefixed "signed bit,base:19 at offset 16 for m32c" (m32c-isa) 2107 h-sint DFLT f-bitbase32-16-s19-unprefixed 2108 ((parse "signed_bitbase19") (print "signed_bitbase")) () () 2109) 2110(define-full-operand BitBase32-16-u27-Unprefixed "unsigned bit,base:27 at offset 16 for m32c" (m32c-isa) 2111 h-uint DFLT f-bitbase32-16-u27-unprefixed 2112 ((parse "unsigned_bitbase27") (print "unsigned_bitbase")) () () 2113) 2114(define-full-operand BitBase32-24-u11-Prefixed "unsigned bit,base:11 at offset 24 for m32c" (m32c-isa) 2115 h-uint DFLT f-bitbase32-24-u11-prefixed 2116 ((parse "unsigned_bitbase11") (print "unsigned_bitbase")) () () 2117) 2118(define-full-operand BitBase32-24-s11-Prefixed "signed bit,base:11 at offset 24 for m32c" (m32c-isa) 2119 h-sint DFLT f-bitbase32-24-s11-prefixed 2120 ((parse "signed_bitbase11") (print "signed_bitbase")) () () 2121) 2122(define-full-operand BitBase32-24-u19-Prefixed "unsigned bit,base:19 at offset 24 for m32c" (m32c-isa) 2123 h-uint DFLT f-bitbase32-24-u19-prefixed 2124 ((parse "unsigned_bitbase19") (print "unsigned_bitbase")) () () 2125) 2126(define-full-operand BitBase32-24-s19-Prefixed "signed bit,base:19 at offset 24 for m32c" (m32c-isa) 2127 h-sint DFLT f-bitbase32-24-s19-prefixed 2128 ((parse "signed_bitbase19") (print "signed_bitbase")) () () 2129) 2130(define-full-operand BitBase32-24-u27-Prefixed "unsigned bit,base:27 at offset 24 for m32c" (m32c-isa) 2131 h-uint DFLT f-bitbase32-24-u27-prefixed 2132 ((parse "unsigned_bitbase27") (print "unsigned_bitbase")) () () 2133) 2134;------------------------------------------------------------- 2135; Labels 2136;------------------------------------------------------------- 2137 2138(define-full-operand Lab-5-3 "3 bit label" (all-isas RELAX) 2139 h-iaddr DFLT f-lab-5-3 2140 ((parse "lab_5_3")) () () ) 2141 2142(define-full-operand Lab32-jmp-s "3 bit label" (all-isas RELAX) 2143 h-iaddr DFLT f-lab32-jmp-s 2144 ((parse "lab_5_3")) () () ) 2145 2146(dnop Lab-8-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-8-8) 2147(dnop Lab-8-16 "16 bit label" (all-isas RELAX) h-iaddr f-lab-8-16) 2148(dnop Lab-8-24 "24 bit label" (all-isas RELAX) h-iaddr f-lab-8-24) 2149(dnop Lab-16-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-16-8) 2150(dnop Lab-24-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-24-8) 2151(dnop Lab-32-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-32-8) 2152(dnop Lab-40-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-40-8) 2153 2154;------------------------------------------------------------- 2155; Condition code bits 2156;------------------------------------------------------------- 2157 2158(dnop sbit "negative bit" (SEM-ONLY all-isas) h-sbit f-nil) 2159(dnop obit "overflow bit" (SEM-ONLY all-isas) h-obit f-nil) 2160(dnop zbit "zero bit" (SEM-ONLY all-isas) h-zbit f-nil) 2161(dnop cbit "carry bit" (SEM-ONLY all-isas) h-cbit f-nil) 2162(dnop ubit "stack ptr select bit" (SEM-ONLY all-isas) h-ubit f-nil) 2163(dnop ibit "interrupt enable bit" (SEM-ONLY all-isas) h-ibit f-nil) 2164(dnop bbit "reg bank select bit" (SEM-ONLY all-isas) h-bbit f-nil) 2165(dnop dbit "debug bit" (SEM-ONLY all-isas) h-dbit f-nil) 2166 2167;------------------------------------------------------------- 2168; Condition operands 2169;------------------------------------------------------------- 2170 2171(define-pmacro (cond-operand mach offset) 2172 (dnop (.sym cond mach - offset) "condition" ((.sym m mach c-isa)) (.sym h-cond mach) (.sym f-dsp- offset -u8)) 2173) 2174 2175(cond-operand 16 16) 2176(cond-operand 16 24) 2177(cond-operand 16 32) 2178(cond-operand 32 16) 2179(cond-operand 32 24) 2180(cond-operand 32 32) 2181(cond-operand 32 40) 2182 2183(dnop cond16c "condition" (m16c-isa) h-cond16c f-cond16) 2184(dnop cond16j "condition" (m16c-isa) h-cond16j f-cond16) 2185(dnop cond16j5 "condition" (m16c-isa) h-cond16j-5 f-cond16j-5) 2186(dnop cond32 "condition" (m32c-isa) h-cond32 f-cond32) 2187(dnop cond32j "condition" (m32c-isa) h-cond32 f-cond32j) 2188(dnop sccond32 "scCND condition" (m32c-isa) h-cond32 f-cond16) 2189(dnop flags16 "flags" (m16c-isa) h-flags f-9-3) 2190(dnop flags32 "flags" (m32c-isa) h-flags f-13-3) 2191(dnop cr16 "control" (m16c-isa) h-cr-16 f-9-3) 2192(dnop cr1-Unprefixed-32 "control" (m32c-isa) h-cr1-32 f-13-3) 2193(dnop cr1-Prefixed-32 "control" (m32c-isa) h-cr1-32 f-21-3) 2194(dnop cr2-32 "control" (m32c-isa) h-cr2-32 f-13-3) 2195(dnop cr3-Unprefixed-32 "control" (m32c-isa) h-cr3-32 f-13-3) 2196(dnop cr3-Prefixed-32 "control" (m32c-isa) h-cr3-32 f-21-3) 2197 2198;------------------------------------------------------------- 2199; Suffixes 2200;------------------------------------------------------------- 2201 2202(define-full-operand Z "Suffix for zero format insns" (all-isas) 2203 h-sint DFLT f-nil 2204 ((parse "Z") (print "Z")) () () 2205) 2206(define-full-operand S "Suffix for short format insns" (all-isas) 2207 h-sint DFLT f-nil 2208 ((parse "S") (print "S")) () () 2209) 2210(define-full-operand Q "Suffix for quick format insns" (all-isas) 2211 h-sint DFLT f-nil 2212 ((parse "Q") (print "Q")) () () 2213) 2214(define-full-operand G "Suffix for general format insns" (all-isas) 2215 h-sint DFLT f-nil 2216 ((parse "G") (print "G")) () () 2217) 2218(define-full-operand X "Empty suffix" (all-isas) 2219 h-sint DFLT f-nil 2220 ((parse "X") (print "X")) () () 2221) 2222(define-full-operand size "any size specifier" (all-isas) 2223 h-sint DFLT f-nil 2224 ((parse "size") (print "size")) () () 2225) 2226;------------------------------------------------------------- 2227; Misc 2228;------------------------------------------------------------- 2229 2230(dnop BitIndex "Bit Index for the next insn" (SEM-ONLY MACH32 m32c-isa) h-bit-index f-nil) 2231(dnop SrcIndex "Source Index for the next insn" (SEM-ONLY MACH32 m32c-isa) h-src-index f-nil) 2232(dnop DstIndex "Destination Index for the next insn" (SEM-ONLY MACH32 m32c-isa) h-dst-index f-nil) 2233(dnop NoRemainder "Place holder for when the remainder is not kept" (SEM-ONLY MACH32 m32c-isa) h-none f-nil) 2234 2235;============================================================= 2236; Derived Operands 2237 2238; Memory reference macros that clip addresses appropriately. Refer to 2239; memory at ADDRESS in MODE, clipped appropriately for either the m16c 2240; or m32c. 2241(define-pmacro (mem16 mode address) 2242 (mem mode (and #xffff address))) 2243 2244(define-pmacro (mem20 mode address) 2245 (mem mode (and #xfffff address))) 2246 2247(define-pmacro (mem32 mode address) 2248 (mem mode (and #xffffff address))) 2249 2250; Like mem16 and mem32, but takes MACH as a parameter. MACH must be 2251; either 16 or 32. 2252(define-pmacro (mem-mach mach mode address) 2253 ((.sym mem mach) mode address)) 2254 2255;------------------------------------------------------------- 2256; Source 2257;------------------------------------------------------------- 2258; Rn direct 2259;------------------------------------------------------------- 2260 2261(define-pmacro (src16-Rn-direct-operand xmode) 2262 (begin 2263 (define-derived-operand 2264 (name (.sym src16-Rn-direct- xmode)) 2265 (comment (.str "m16c Rn direct source " xmode)) 2266 (attrs (machine 16)) 2267 (mode xmode) 2268 (args ((.sym Src16Rn xmode))) 2269 (syntax (.str "$Src16Rn" xmode)) 2270 (base-ifield f-8-4) 2271 (encoding (+ (f-8-2 0) (.sym Src16Rn xmode))) 2272 (ifield-assertion (eq f-8-2 0)) 2273 (getter (trunc xmode (.sym Src16Rn xmode))) 2274 (setter (set (.sym Src16Rn xmode) newval)) 2275 ) 2276 ) 2277) 2278(src16-Rn-direct-operand QI) 2279(src16-Rn-direct-operand HI) 2280 2281(define-pmacro (src32-Rn-direct-operand group base xmode) 2282 (begin 2283 (define-derived-operand 2284 (name (.sym src32-Rn-direct- group - xmode)) 2285 (comment (.str "m32c Rn direct source " xmode)) 2286 (attrs (machine 32)) 2287 (mode xmode) 2288 (args ((.sym Src32Rn group xmode))) 2289 (syntax (.str "$Src32Rn" group xmode)) 2290 (base-ifield (.sym f- base -11)) 2291 (encoding (+ ((.sym f- base -3) 4) (.sym Src32Rn group xmode))) 2292 (ifield-assertion (eq (.sym f- base -3) 4)) 2293 (getter (trunc xmode (.sym Src32Rn group xmode))) 2294 (setter (set (.sym Src32Rn group xmode) newval)) 2295 ) 2296 ) 2297) 2298 2299(src32-Rn-direct-operand Unprefixed 1 QI) 2300(src32-Rn-direct-operand Prefixed 9 QI) 2301(src32-Rn-direct-operand Unprefixed 1 HI) 2302(src32-Rn-direct-operand Prefixed 9 HI) 2303(src32-Rn-direct-operand Unprefixed 1 SI) 2304(src32-Rn-direct-operand Prefixed 9 SI) 2305 2306;------------------------------------------------------------- 2307; An direct 2308;------------------------------------------------------------- 2309 2310(define-pmacro (src16-An-direct-operand xmode) 2311 (begin 2312 (define-derived-operand 2313 (name (.sym src16-An-direct- xmode)) 2314 (comment (.str "m16c An direct destination " xmode)) 2315 (attrs (machine 16)) 2316 (mode xmode) 2317 (args ((.sym Src16An xmode))) 2318 (syntax (.str "$Src16An" xmode)) 2319 (base-ifield f-8-4) 2320 (encoding (+ (f-8-2 1) (f-10-1 0) (.sym Src16An xmode))) 2321 (ifield-assertion (andif (eq f-8-2 1) (eq f-10-1 0))) 2322 (getter (trunc xmode (.sym Src16An xmode))) 2323 (setter (set (.sym Src16An xmode) newval)) 2324 ) 2325 ) 2326) 2327(src16-An-direct-operand QI) 2328(src16-An-direct-operand HI) 2329 2330(define-pmacro (src32-An-direct-operand group base1 base2 xmode) 2331 (begin 2332 (define-derived-operand 2333 (name (.sym src32-An-direct- group - xmode)) 2334 (comment (.str "m32c An direct destination " xmode)) 2335 (attrs (machine 32)) 2336 (mode xmode) 2337 (args ((.sym Src32An group xmode))) 2338 (syntax (.str "$Src32An" group xmode)) 2339 (base-ifield (.sym f- base1 -11)) 2340 (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 1) (.sym Src32An group xmode))) 2341 (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 1))) 2342 (getter (trunc xmode (.sym Src32An group xmode))) 2343 (setter (set (.sym Src32An group xmode) newval)) 2344 ) 2345 ) 2346) 2347 2348(src32-An-direct-operand Unprefixed 1 10 QI) 2349(src32-An-direct-operand Unprefixed 1 10 HI) 2350(src32-An-direct-operand Unprefixed 1 10 SI) 2351(src32-An-direct-operand Prefixed 9 18 QI) 2352(src32-An-direct-operand Prefixed 9 18 HI) 2353(src32-An-direct-operand Prefixed 9 18 SI) 2354 2355;------------------------------------------------------------- 2356; An indirect 2357;------------------------------------------------------------- 2358 2359(define-pmacro (src16-An-indirect-operand xmode) 2360 (begin 2361 (define-derived-operand 2362 (name (.sym src16-An-indirect- xmode)) 2363 (comment (.str "m16c An indirect destination " xmode)) 2364 (attrs (machine 16)) 2365 (mode xmode) 2366 (args (Src16An)) 2367 (syntax "[$Src16An]") 2368 (base-ifield f-8-4) 2369 (encoding (+ (f-8-2 1) (f-10-1 1) Src16An)) 2370 (ifield-assertion (andif (eq f-8-2 1) (eq f-10-1 1))) 2371 (getter (mem16 xmode Src16An)) 2372 (setter (set (mem16 xmode Src16An) newval)) 2373 ) 2374 ) 2375) 2376(src16-An-indirect-operand QI) 2377(src16-An-indirect-operand HI) 2378 2379(define-pmacro (src32-An-indirect-operand group base1 base2 xmode) 2380 (begin 2381 (define-derived-operand 2382 (name (.sym src32-An-indirect- group - xmode)) 2383 (comment (.str "m32c An indirect destination " xmode)) 2384 (attrs (machine 32)) 2385 (mode xmode) 2386 (args ((.sym Src32An group))) 2387 (syntax (.str "[$Src32An" group "]")) 2388 (base-ifield (.sym f- base1 -11)) 2389 (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 0) (.sym Src32An group))) 2390 (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 0))) 2391 (getter (c-call xmode (.str "operand_getter_" xmode) (.sym Src32An group) 2392 (const 0))) 2393 (setter (c-call DFLT (.str "operand_setter_" xmode) newval 2394 (.sym Src32An group) (const 0))) 2395; (getter (mem32 xmode (.sym Src32An group))) 2396; (setter (set (mem32 xmode (.sym Src32An group)) newval)) 2397 ) 2398 ) 2399) 2400 2401(src32-An-indirect-operand Unprefixed 1 10 QI) 2402(src32-An-indirect-operand Unprefixed 1 10 HI) 2403(src32-An-indirect-operand Unprefixed 1 10 SI) 2404(src32-An-indirect-operand Prefixed 9 18 QI) 2405(src32-An-indirect-operand Prefixed 9 18 HI) 2406(src32-An-indirect-operand Prefixed 9 18 SI) 2407 2408;------------------------------------------------------------- 2409; dsp:d[r] relative 2410;------------------------------------------------------------- 2411 2412(define-pmacro (src16-relative-operand xmode) 2413 (begin 2414 (define-derived-operand 2415 (name (.sym src16-16-8-SB-relative- xmode)) 2416 (comment (.str "m16c dsp:8[sb] relative destination " xmode)) 2417 (attrs (machine 16)) 2418 (mode xmode) 2419 (args (Dsp-16-u8)) 2420 (syntax "${Dsp-16-u8}[sb]") 2421 (base-ifield f-8-4) 2422 (encoding (+ (f-8-4 #xA) Dsp-16-u8)) 2423 (ifield-assertion (eq f-8-4 #xA)) 2424 (getter (mem16 xmode (add Dsp-16-u8 (reg h-sb)))) 2425 (setter (set (mem16 xmode (add Dsp-16-u8 (reg h-sb))) newval)) 2426 ) 2427 (define-derived-operand 2428 (name (.sym src16-16-16-SB-relative- xmode)) 2429 (comment (.str "m16c dsp:16[sb] relative destination " xmode)) 2430 (attrs (machine 16)) 2431 (mode xmode) 2432 (args (Dsp-16-u16)) 2433 (syntax "${Dsp-16-u16}[sb]") 2434 (base-ifield f-8-4) 2435 (encoding (+ (f-8-4 #xE) Dsp-16-u16)) 2436 (ifield-assertion (eq f-8-4 #xE)) 2437 (getter (mem16 xmode (add Dsp-16-u16 (reg h-sb)))) 2438 (setter (set (mem16 xmode (add Dsp-16-u16 (reg h-sb))) newval)) 2439 ) 2440 (define-derived-operand 2441 (name (.sym src16-16-8-FB-relative- xmode)) 2442 (comment (.str "m16c dsp:8[fb] relative destination " xmode)) 2443 (attrs (machine 16)) 2444 (mode xmode) 2445 (args (Dsp-16-s8)) 2446 (syntax "${Dsp-16-s8}[fb]") 2447 (base-ifield f-8-4) 2448 (encoding (+ (f-8-4 #xB) Dsp-16-s8)) 2449 (ifield-assertion (eq f-8-4 #xB)) 2450 (getter (mem16 xmode (add Dsp-16-s8 (reg h-fb)))) 2451 (setter (set (mem16 xmode (add Dsp-16-s8 (reg h-fb))) newval)) 2452 ) 2453 (define-derived-operand 2454 (name (.sym src16-16-8-An-relative- xmode)) 2455 (comment (.str "m16c dsp:8[An] relative destination " xmode)) 2456 (attrs (machine 16)) 2457 (mode xmode) 2458 (args (Src16An Dsp-16-u8)) 2459 (syntax "${Dsp-16-u8}[$Src16An]") 2460 (base-ifield f-8-4) 2461 (encoding (+ (f-8-2 2) (f-10-1 0) Dsp-16-u8 Src16An)) 2462 (ifield-assertion (andif (eq f-8-2 2) (eq f-10-1 0))) 2463 (getter (mem16 xmode (add Dsp-16-u8 Src16An))) 2464 (setter (set (mem16 xmode (add Dsp-16-u8 Src16An)) newval)) 2465 ) 2466 (define-derived-operand 2467 (name (.sym src16-16-16-An-relative- xmode)) 2468 (comment (.str "m16c dsp:16[An] relative destination " xmode)) 2469 (attrs (machine 16)) 2470 (mode xmode) 2471 (args (Src16An Dsp-16-u16)) 2472 (syntax "${Dsp-16-u16}[$Src16An]") 2473 (base-ifield f-8-4) 2474 (encoding (+ (f-8-2 3) (f-10-1 0) Dsp-16-u16 Src16An)) 2475 (ifield-assertion (andif (eq f-8-2 3) (eq f-10-1 0))) 2476 (getter (mem16 xmode (add Dsp-16-u16 Src16An))) 2477 (setter (set (mem16 xmode (add Dsp-16-u16 Src16An)) newval)) 2478 ) 2479 (define-derived-operand 2480 (name (.sym src16-16-20-An-relative- xmode)) 2481 (comment (.str "m16c dsp:20[An] relative destination " xmode)) 2482 (attrs (machine 16)) 2483 (mode xmode) 2484 (args (Src16An Dsp-16-u20)) 2485 (syntax "${Dsp-16-u20}[$Src16An]") 2486 (base-ifield f-8-4) 2487 (encoding (+ (f-8-2 3) (f-10-1 0) Dsp-16-u20 Src16An)) 2488 (ifield-assertion (andif (eq f-8-2 3) (eq f-10-1 0))) 2489 (getter (mem20 xmode (add Dsp-16-u20 Src16An))) 2490 (setter (set (mem20 xmode (add Dsp-16-u20 Src16An)) newval)) 2491 ) 2492 ) 2493) 2494 2495(src16-relative-operand QI) 2496(src16-relative-operand HI) 2497 2498(define-pmacro (src32-relative-operand offset group base1 base2 xmode) 2499 (begin 2500 (define-derived-operand 2501 (name (.sym src32- offset -8-SB-relative- group - xmode)) 2502 (comment (.str "m32c dsp:8[sb] relative destination " xmode)) 2503 (attrs (machine 32)) 2504 (mode xmode) 2505 (args ((.sym Dsp- offset -u8))) 2506 (syntax (.str "${Dsp-" offset "-u8}[sb]")) 2507 (base-ifield (.sym f- base1 -11)) 2508 (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u8))) 2509 (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 2))) 2510 (getter (c-call xmode (.str "operand_getter_" xmode) sb (.sym Dsp- offset -u8))) 2511 (setter (c-call DFLT (.str "operand_setter_" xmode) newval sb (.sym Dsp- offset -u8))) 2512; (getter (mem32 xmode (add (.sym Dsp- offset -u8) (reg h-sb)))) 2513; (setter (set (mem32 xmode (add (.sym Dsp- offset -u8) (reg h-sb))) newval)) 2514 ) 2515 (define-derived-operand 2516 (name (.sym src32- offset -16-SB-relative- group - xmode)) 2517 (comment (.str "m32c dsp:16[sb] relative destination " xmode)) 2518 (attrs (machine 32)) 2519 (mode xmode) 2520 (args ((.sym Dsp- offset -u16))) 2521 (syntax (.str "${Dsp-" offset "-u16}[sb]")) 2522 (base-ifield (.sym f- base1 -11)) 2523 (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u16))) 2524 (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 2))) 2525 (getter (c-call xmode (.str "operand_getter_" xmode) sb (.sym Dsp- offset -u16))) 2526 (setter (c-call DFLT (.str "operand_setter_" xmode) newval sb (.sym Dsp- offset -u16))) 2527; (getter (mem32 xmode (add (.sym Dsp- offset -u16) (reg h-sb)))) 2528; (setter (set (mem32 xmode (add (.sym Dsp- offset -u16) (reg h-sb))) newval)) 2529 ) 2530 (define-derived-operand 2531 (name (.sym src32- offset -8-FB-relative- group - xmode)) 2532 (comment (.str "m32c dsp:8[fb] relative destination " xmode)) 2533 (attrs (machine 32)) 2534 (mode xmode) 2535 (args ((.sym Dsp- offset -s8))) 2536 (syntax (.str "${Dsp-" offset "-s8}[fb]")) 2537 (base-ifield (.sym f- base1 -11)) 2538 (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 3) (.sym Dsp- offset -s8))) 2539 (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 3))) 2540 (getter (c-call xmode (.str "operand_getter_" xmode) fb (.sym Dsp- offset -s8))) 2541 (setter (c-call DFLT (.str "operand_setter_" xmode) newval fb (.sym Dsp- offset -s8))) 2542; (getter (mem32 xmode (add (.sym Dsp- offset -s8) (reg h-fb)))) 2543; (setter (set (mem32 xmode (add (.sym Dsp- offset -s8) (reg h-fb))) newval)) 2544 ) 2545 (define-derived-operand 2546 (name (.sym src32- offset -16-FB-relative- group - xmode)) 2547 (comment (.str "m32c dsp:16[fb] relative destination " xmode)) 2548 (attrs (machine 32)) 2549 (mode xmode) 2550 (args ((.sym Dsp- offset -s16))) 2551 (syntax (.str "${Dsp-" offset "-s16}[fb]")) 2552 (base-ifield (.sym f- base1 -11)) 2553 (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 3) (.sym Dsp- offset -s16))) 2554 (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 3))) 2555 (getter (c-call xmode (.str "operand_getter_" xmode) fb (.sym Dsp- offset -s16))) 2556 (setter (c-call DFLT (.str "operand_setter_" xmode) newval fb (.sym Dsp- offset -s16))) 2557; (getter (mem32 xmode (add (.sym Dsp- offset -s16) (reg h-fb)))) 2558; (setter (set (mem32 xmode (add (.sym Dsp- offset -s16) (reg h-fb))) newval)) 2559 ) 2560 (define-derived-operand 2561 (name (.sym src32- offset -8-An-relative- group - xmode)) 2562 (comment (.str "m32c dsp:8[An] relative destination " xmode)) 2563 (attrs (machine 32)) 2564 (mode xmode) 2565 (args ((.sym Src32An group) (.sym Dsp- offset -u8))) 2566 (syntax (.str "${Dsp-" offset "-u8}[$Src32An" group "]")) 2567 (base-ifield (.sym f- base1 -11)) 2568 (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u8) (.sym Src32An group))) 2569 (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -1) 0))) 2570 (getter (c-call xmode (.str "operand_getter_" xmode) (.sym Src32An group) (.sym Dsp- offset -u8))) 2571 (setter (c-call DFLT (.str "operand_setter_" xmode) newval (.sym Src32An group) (.sym Dsp- offset -u8))) 2572; (getter (mem32 xmode (add (.sym Dsp- offset -u8) (.sym Src32An group)))) 2573; (setter (set (mem32 xmode (add (.sym Dsp- offset -u8) (.sym Src32An group))) newval)) 2574 ) 2575 (define-derived-operand 2576 (name (.sym src32- offset -16-An-relative- group - xmode)) 2577 (comment (.str "m32c dsp:16[An] relative destination " xmode)) 2578 (attrs (machine 32)) 2579 (mode xmode) 2580 (args ((.sym Src32An group) (.sym Dsp- offset -u16))) 2581 (syntax (.str "${Dsp-" offset "-u16}[$Src32An" group "]")) 2582 (base-ifield (.sym f- base1 -11)) 2583 (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u16) (.sym Src32An group))) 2584 (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -1) 0))) 2585 (getter (c-call xmode (.str "operand_getter_" xmode) (.sym Src32An group) (.sym Dsp- offset -u16))) 2586 (setter (c-call DFLT (.str "operand_setter_" xmode) newval (.sym Src32An group) (.sym Dsp- offset -u16))) 2587; (getter (mem32 xmode (add (.sym Dsp- offset -u16) (.sym Src32An group)))) 2588; (setter (set (mem32 xmode (add (.sym Dsp- offset -u16) (.sym Src32An group))) newval)) 2589 ) 2590 (define-derived-operand 2591 (name (.sym src32- offset -24-An-relative- group - xmode)) 2592 (comment (.str "m32c dsp:16[An] relative destination " xmode)) 2593 (attrs (machine 32)) 2594 (mode xmode) 2595 (args ((.sym Src32An group) (.sym Dsp- offset -u24))) 2596 (syntax (.str "${Dsp-" offset "-u24}[$Src32An" group "]")) 2597 (base-ifield (.sym f- base1 -11)) 2598 (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u24) (.sym Src32An group))) 2599 (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -1) 0))) 2600 (getter (c-call xmode (.str "operand_getter_" xmode) (.sym Src32An group) (.sym Dsp- offset -u24) )) 2601 (setter (c-call DFLT (.str "operand_setter_" xmode) newval (.sym Src32An group) (.sym Dsp- offset -u24))) 2602; (getter (mem32 xmode (add (.sym Dsp- offset -u24) (.sym Src32An group)))) 2603; (setter (set (mem32 xmode (add (.sym Dsp- offset -u24) (.sym Src32An group))) newval)) 2604 ) 2605 ) 2606) 2607 2608(src32-relative-operand 16 Unprefixed 1 10 QI) 2609(src32-relative-operand 16 Unprefixed 1 10 HI) 2610(src32-relative-operand 16 Unprefixed 1 10 SI) 2611(src32-relative-operand 24 Prefixed 9 18 QI) 2612(src32-relative-operand 24 Prefixed 9 18 HI) 2613(src32-relative-operand 24 Prefixed 9 18 SI) 2614 2615;------------------------------------------------------------- 2616; Absolute address 2617;------------------------------------------------------------- 2618 2619(define-pmacro (src16-absolute xmode) 2620 (begin 2621 (define-derived-operand 2622 (name (.sym src16-16-16-absolute- xmode)) 2623 (comment (.str "m16c absolute address " xmode)) 2624 (attrs (machine 16)) 2625 (mode xmode) 2626 (args (Dsp-16-u16)) 2627 (syntax (.str "${Dsp-16-u16}")) 2628 (base-ifield f-8-4) 2629 (encoding (+ (f-8-4 #xF) Dsp-16-u16)) 2630 (ifield-assertion (eq f-8-4 #xF)) 2631 (getter (mem16 xmode Dsp-16-u16)) 2632 (setter (set (mem16 xmode Dsp-16-u16) newval)) 2633 ) 2634 ) 2635) 2636 2637(src16-absolute QI) 2638(src16-absolute HI) 2639 2640(define-pmacro (src32-absolute offset group base1 base2 xmode) 2641 (begin 2642 (define-derived-operand 2643 (name (.sym src32- offset -16-absolute- group - xmode)) 2644 (comment (.str "m32c absolute address " xmode)) 2645 (attrs (machine 32)) 2646 (mode xmode) 2647 (args ((.sym Dsp- offset -u16))) 2648 (syntax (.str "${Dsp-" offset "-u16}")) 2649 (base-ifield (.sym f- base1 -11)) 2650 (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 3) (.sym Dsp- offset -u16))) 2651 (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 3))) 2652 (getter (c-call xmode (.str "operand_getter_" xmode) (const 0) (.sym Dsp- offset -u16))) 2653 (setter (c-call DFLT (.str "operand_setter_" xmode) newval (const 0) (.sym Dsp- offset -u16))) 2654; (getter (mem32 xmode (.sym Dsp- offset -u16))) 2655; (setter (set (mem32 xmode (.sym Dsp- offset -u16)) newval)) 2656 ) 2657 (define-derived-operand 2658 (name (.sym src32- offset -24-absolute- group - xmode)) 2659 (comment (.str "m32c absolute address " xmode)) 2660 (attrs (machine 32)) 2661 (mode xmode) 2662 (args ((.sym Dsp- offset -u24))) 2663 (syntax (.str "${Dsp-" offset "-u24}")) 2664 (base-ifield (.sym f- base1 -11)) 2665 (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u24))) 2666 (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 2))) 2667 (getter (c-call xmode (.str "operand_getter_" xmode) (const 0) (.sym Dsp- offset -u24))) 2668 (setter (c-call DFLT (.str "operand_setter_" xmode) newval (const 0) (.sym Dsp- offset -u24))) 2669; (getter (mem32 xmode (.sym Dsp- offset -u24))) 2670; (setter (set (mem32 xmode (.sym Dsp- offset -u24)) newval)) 2671 ) 2672 ) 2673) 2674 2675(src32-absolute 16 Unprefixed 1 10 QI) 2676(src32-absolute 16 Unprefixed 1 10 HI) 2677(src32-absolute 16 Unprefixed 1 10 SI) 2678(src32-absolute 24 Prefixed 9 18 QI) 2679(src32-absolute 24 Prefixed 9 18 HI) 2680(src32-absolute 24 Prefixed 9 18 SI) 2681 2682;------------------------------------------------------------- 2683; An indirect indirect 2684; 2685; Double indirect addressing uses the lower 3 bytes of the value stored 2686; at the address referenced by 'op' as the effective address. 2687;------------------------------------------------------------- 2688 2689(define-pmacro (indirect-addr op) (and USI (mem32 USI op) #x00ffffff)) 2690 2691; (define-pmacro (src-An-indirect-indirect-operand xmode) 2692; (define-derived-operand 2693; (name (.sym src32-An-indirect-indirect- xmode)) 2694; (comment (.str "m32c An indirect indirect destination " xmode)) 2695; (attrs (machine 32)) 2696; (mode xmode) 2697; (args (Src32AnPrefixed)) 2698; (syntax (.str "[[$Src32AnPrefixed]]")) 2699; (base-ifield f-9-11) 2700; (encoding (+ (f-9-3 0) (f-18-1 0) Src32AnPrefixed)) 2701; (ifield-assertion (andif (eq f-9-3 0) (eq f-18-1 0))) 2702; (getter (mem32 xmode (indirect-addr Src32AnPrefixed))) 2703; (setter (set (mem32 xmode (indirect-addr Src32AnPrefixed)) newval)) 2704; ) 2705; ) 2706 2707; (src-An-indirect-indirect-operand QI) 2708; (src-An-indirect-indirect-operand HI) 2709; (src-An-indirect-indirect-operand SI) 2710 2711;------------------------------------------------------------- 2712; Relative indirect 2713;------------------------------------------------------------- 2714 2715(define-pmacro (src-relative-indirect-operand xmode) 2716 (begin 2717; (define-derived-operand 2718; (name (.sym src32-24-8-SB-relative-indirect- xmode)) 2719; (comment (.str "m32c dsp:8[sb] relative source " xmode)) 2720; (attrs (machine 32)) 2721; (mode xmode) 2722; (args (Dsp-24-u8)) 2723; (syntax "[${Dsp-24-u8}[sb]]") 2724; (base-ifield f-9-11) 2725; (encoding (+ (f-9-3 1) (f-18-2 2) Dsp-24-u8)) 2726; (ifield-assertion (andif (eq f-9-3 1) (eq f-18-2 2))) 2727; (getter (mem32 xmode (indirect-addr (add Dsp-24-u8 (reg h-sb))))) 2728; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u8 (reg h-sb)))) newval)) 2729; ) 2730; (define-derived-operand 2731; (name (.sym src32-24-16-SB-relative-indirect- xmode)) 2732; (comment (.str "m32c dsp:16[sb] relative source " xmode)) 2733; (attrs (machine 32)) 2734; (mode xmode) 2735; (args (Dsp-24-u16)) 2736; (syntax "[${Dsp-24-u16}[sb]]") 2737; (base-ifield f-9-11) 2738; (encoding (+ (f-9-3 2) (f-18-2 2) Dsp-24-u16)) 2739; (ifield-assertion (andif (eq f-9-3 2) (eq f-18-2 2))) 2740; (getter (mem32 xmode (indirect-addr (add Dsp-24-u16 (reg h-sb))))) 2741; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u16 (reg h-sb)))) newval)) 2742; ) 2743; (define-derived-operand 2744; (name (.sym src32-24-8-FB-relative-indirect- xmode)) 2745; (comment (.str "m32c dsp:8[fb] relative source " xmode)) 2746; (attrs (machine 32)) 2747; (mode xmode) 2748; (args (Dsp-24-s8)) 2749; (syntax "[${Dsp-24-s8}[fb]]") 2750; (base-ifield f-9-11) 2751; (encoding (+ (f-9-3 1) (f-18-2 3) Dsp-24-s8)) 2752; (ifield-assertion (andif (eq f-9-3 1) (eq f-18-2 3))) 2753; (getter (mem32 xmode (indirect-addr (add Dsp-24-s8 (reg h-fb))))) 2754; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-s8 (reg h-fb)))) newval)) 2755; ) 2756; (define-derived-operand 2757; (name (.sym src32-24-16-FB-relative-indirect- xmode)) 2758; (comment (.str "m32c dsp:16[fb] relative source " xmode)) 2759; (attrs (machine 32)) 2760; (mode xmode) 2761; (args (Dsp-24-s16)) 2762; (syntax "[${Dsp-24-s16}[fb]]") 2763; (base-ifield f-9-11) 2764; (encoding (+ (f-9-3 2) (f-18-2 3) Dsp-24-s16)) 2765; (ifield-assertion (andif (eq f-9-3 2) (eq f-18-2 3))) 2766; (getter (mem32 xmode (indirect-addr (add Dsp-24-s16 (reg h-fb))))) 2767; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-s16 (reg h-fb)))) newval)) 2768; ) 2769; (define-derived-operand 2770; (name (.sym src32-24-8-An-relative-indirect- xmode)) 2771; (comment (.str "m32c dsp:8[An] relative indirect source " xmode)) 2772; (attrs (machine 32)) 2773; (mode xmode) 2774; (args (Src32AnPrefixed Dsp-24-u8)) 2775; (syntax "[${Dsp-24-u8}[$Src32AnPrefixed]]") 2776; (base-ifield f-9-11) 2777; (encoding (+ (f-9-3 1) (f-18-1 0) Dsp-24-u8 Src32AnPrefixed)) 2778; (ifield-assertion (andif (eq f-9-3 1) (eq f-18-1 0))) 2779; (getter (mem32 xmode (indirect-addr (add Dsp-24-u8 Src32AnPrefixed)))) 2780; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u8 Src32AnPrefixed))) newval)) 2781; ) 2782; (define-derived-operand 2783; (name (.sym src32-24-16-An-relative-indirect- xmode)) 2784; (comment (.str "m32c dsp:16[An] relative source " xmode)) 2785; (attrs (machine 32)) 2786; (mode xmode) 2787; (args (Src32AnPrefixed Dsp-24-u16)) 2788; (syntax "[${Dsp-24-u16}[$Src32AnPrefixed]]") 2789; (base-ifield f-9-11) 2790; (encoding (+ (f-9-3 2) (f-18-1 0) Dsp-24-u16 Src32AnPrefixed)) 2791; (ifield-assertion (andif (eq f-9-3 2) (eq f-18-1 0))) 2792; (getter (mem32 xmode (indirect-addr (add Dsp-24-u16 Src32AnPrefixed)))) 2793; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u16 Src32AnPrefixed))) newval)) 2794; ) 2795; (define-derived-operand 2796; (name (.sym src32-24-24-An-relative-indirect- xmode)) 2797; (comment (.str "m32c dsp:24[An] relative source " xmode)) 2798; (attrs (machine 32)) 2799; (mode xmode) 2800; (args (Src32AnPrefixed Dsp-24-u24)) 2801; (syntax "[${Dsp-24-u24}[$Src32AnPrefixed]]") 2802; (base-ifield f-9-11) 2803; (encoding (+ (f-9-3 3) (f-18-1 0) Dsp-24-u24 Src32AnPrefixed)) 2804; (ifield-assertion (andif (eq f-9-3 3) (eq f-18-1 0))) 2805; (getter (mem32 xmode (indirect-addr (add Dsp-24-u24 Src32AnPrefixed)))) 2806; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u24 Src32AnPrefixed))) newval)) 2807; ) 2808 ) 2809) 2810 2811; (src-relative-indirect-operand QI) 2812; (src-relative-indirect-operand HI) 2813; (src-relative-indirect-operand SI) 2814 2815;------------------------------------------------------------- 2816; Absolute Indirect address 2817;------------------------------------------------------------- 2818 2819(define-pmacro (src32-absolute-indirect offset base1 base2 xmode) 2820 (begin 2821; (define-derived-operand 2822; (name (.sym src32- offset -16-absolute-indirect-derived- xmode)) 2823; (comment (.str "m32c absolute indirect address " xmode)) 2824; (attrs (machine 32)) 2825; (mode xmode) 2826; (args ((.sym Dsp- offset -u16))) 2827; (syntax (.str "[${Dsp-" offset "-u16}]")) 2828; (base-ifield (.sym f- base1 -11)) 2829; (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 3) (.sym Dsp- offset -u16))) 2830; (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 3))) 2831; (getter (mem32 xmode (indirect-addr (.sym Dsp- offset -u16)))) 2832; (setter (set (mem32 xmode (indirect-addr (.sym Dsp- offset -u16))) newval)) 2833; ) 2834; (define-derived-operand 2835; (name (.sym src32- offset -24-absolute-indirect-derived- xmode)) 2836; (comment (.str "m32c absolute indirect address " xmode)) 2837; (attrs (machine 32)) 2838; (mode xmode) 2839; (args ((.sym Dsp- offset -u24))) 2840; (syntax (.str "[${Dsp-" offset "-u24}]")) 2841; (base-ifield (.sym f- base1 -11)) 2842; (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u24))) 2843; (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 2))) 2844; (getter (mem32 xmode (indirect-addr (.sym Dsp- offset -u24)))) 2845; (setter (set (mem32 xmode (indirect-addr (.sym Dsp- offset -u24))) newval)) 2846; ) 2847 ) 2848) 2849 2850(src32-absolute-indirect 24 9 18 QI) 2851(src32-absolute-indirect 24 9 18 HI) 2852(src32-absolute-indirect 24 9 18 SI) 2853 2854;------------------------------------------------------------- 2855; Register relative source operands for short format insns 2856;------------------------------------------------------------- 2857 2858(define-pmacro (src-2-S-operands mach xmode base opc1 opc2 opc3) 2859 (begin 2860 (define-derived-operand 2861 (name (.sym src mach -2-S-8-SB-relative- xmode)) 2862 (comment (.str "m" mach "c SB relative address")) 2863 (attrs (machine mach)) 2864 (mode xmode) 2865 (args (Dsp-8-u8)) 2866 (syntax "${Dsp-8-u8}[sb]") 2867 (base-ifield (.sym f- base -2)) 2868 (encoding (+ ((.sym f- base -2) opc1) Dsp-8-u8)) 2869 (ifield-assertion (eq (.sym f- base -2) opc1)) 2870 (getter (c-call xmode (.str "operand_getter_" xmode) sb Dsp-8-u8)) 2871 (setter (c-call DFLT (.str "operand_setter_" xmode) newval sb Dsp-8-u8)) 2872; (getter (mem-mach mach xmode (indirect-addr (add (reg h-sb) Dsp-8-u8)))) 2873; (setter (set (mem-mach mach xmode (indirect-addr (add (reg h-sb) Dsp-8-u8))) newval)) 2874 ) 2875 (define-derived-operand 2876 (name (.sym src mach -2-S-8-FB-relative- xmode)) 2877 (comment (.str "m" mach "c FB relative address")) 2878 (attrs (machine mach)) 2879 (mode xmode) 2880 (args (Dsp-8-s8)) 2881 (syntax "${Dsp-8-s8}[fb]") 2882 (base-ifield (.sym f- base -2)) 2883 (encoding (+ ((.sym f- base -2) opc2) Dsp-8-s8)) 2884 (ifield-assertion (eq (.sym f- base -2) opc2)) 2885 (getter (c-call xmode (.str "operand_getter_" xmode) fb Dsp-8-s8)) 2886 (setter (c-call DFLT (.str "operand_setter_" xmode) newval fb Dsp-8-s8)) 2887; (getter (mem-mach mach xmode (indirect-addr (add (reg h-fb) Dsp-8-s8)))) 2888; (setter (set (mem-mach mach xmode (indirect-addr (add (reg h-fb) Dsp-8-s8))) newval)) 2889 ) 2890 (define-derived-operand 2891 (name (.sym src mach -2-S-16-absolute- xmode)) 2892 (comment (.str "m" mach "c absolute address")) 2893 (attrs (machine mach)) 2894 (mode xmode) 2895 (args (Dsp-8-u16)) 2896 (syntax "${Dsp-8-u16}") 2897 (base-ifield (.sym f- base -2)) 2898 (encoding (+ ((.sym f- base -2) opc3) Dsp-8-u16)) 2899 (ifield-assertion (eq (.sym f- base -2) opc3)) 2900 (getter (c-call xmode (.str "operand_getter_" xmode) (const 0) Dsp-8-u16)) 2901 (setter (c-call DFLT (.str "operand_setter_" xmode) newval (const 0) Dsp-8-u16)) 2902; (getter (mem-mach mach xmode Dsp-8-u16)) 2903; (setter (set (mem-mach mach xmode Dsp-8-u16) newval)) 2904 ) 2905 ) 2906) 2907 2908(src-2-S-operands 16 QI 6 1 2 3) 2909(src-2-S-operands 32 QI 2 2 3 1) 2910(src-2-S-operands 32 HI 2 2 3 1) 2911 2912;============================================================= 2913; Derived Operands 2914;------------------------------------------------------------- 2915; Destination 2916;------------------------------------------------------------- 2917; Rn direct 2918;------------------------------------------------------------- 2919 2920(define-pmacro (dst16-Rn-direct-operand xmode) 2921 (begin 2922 (define-derived-operand 2923 (name (.sym dst16-Rn-direct- xmode)) 2924 (comment (.str "m16c Rn direct destination " xmode)) 2925 (attrs (machine 16)) 2926 (mode xmode) 2927 (args ((.sym Dst16Rn xmode))) 2928 (syntax (.str "$Dst16Rn" xmode)) 2929 (base-ifield f-12-4) 2930 (encoding (+ (f-12-2 0) (.sym Dst16Rn xmode))) 2931 (ifield-assertion (eq f-12-2 0)) 2932 (getter (trunc xmode (.sym Dst16Rn xmode))) 2933 (setter (set (.sym Dst16Rn xmode) newval)) 2934 ) 2935 ) 2936) 2937 2938(dst16-Rn-direct-operand QI) 2939(dst16-Rn-direct-operand HI) 2940(dst16-Rn-direct-operand SI) 2941 2942(define-derived-operand 2943 (name dst16-Rn-direct-Ext-QI) 2944 (comment "m16c Rn direct destination QI") 2945 (attrs (machine 16)) 2946 (mode HI) 2947 (args (Dst16RnExtQI)) 2948 (syntax "$Dst16RnExtQI") 2949 (base-ifield f-12-4) 2950 (encoding (+ (f-12-2 0) Dst16RnExtQI (f-15-1 0))) 2951 (ifield-assertion (andif (eq f-12-2 0) (eq f-15-1 0))) 2952 (getter (trunc QI (.sym Dst16RnExtQI))) 2953 (setter (set Dst16RnExtQI newval)) 2954) 2955 2956(define-pmacro (dst32-Rn-direct-operand group base xmode) 2957 (begin 2958 (define-derived-operand 2959 (name (.sym dst32-Rn-direct- group - xmode)) 2960 (comment (.str "m32c Rn direct destination " xmode)) 2961 (attrs (machine 32)) 2962 (mode xmode) 2963 (args ((.sym Dst32Rn group xmode))) 2964 (syntax (.str "$Dst32Rn" group xmode)) 2965 (base-ifield (.sym f- base -6)) 2966 (encoding (+ ((.sym f- base -3) 4) (.sym Dst32Rn group xmode))) 2967 (ifield-assertion (eq (.sym f- base -3) 4)) 2968 (getter (trunc xmode (.sym Dst32Rn group xmode))) 2969 (setter (set (.sym Dst32Rn group xmode) newval)) 2970 ) 2971 ) 2972) 2973 2974(dst32-Rn-direct-operand Unprefixed 4 QI) 2975(dst32-Rn-direct-operand Prefixed 12 QI) 2976(dst32-Rn-direct-operand Unprefixed 4 HI) 2977(dst32-Rn-direct-operand Prefixed 12 HI) 2978(dst32-Rn-direct-operand Unprefixed 4 SI) 2979(dst32-Rn-direct-operand Prefixed 12 SI) 2980 2981(define-pmacro (dst32-Rn-direct-Ext-operand group base1 base2 smode dmode) 2982 (begin 2983 (define-derived-operand 2984 (name (.sym dst32-Rn-direct- group - smode)) 2985 (comment (.str "m32c Rn direct destination " smode)) 2986 (attrs (machine 32)) 2987 (mode dmode) 2988 (args ((.sym Dst32Rn group smode))) 2989 (syntax (.str "$Dst32Rn" group smode)) 2990 (base-ifield (.sym f- base1 -6)) 2991 (encoding (+ ((.sym f- base1 -3) 4) ((.sym f- base2 -1) 1) (.sym Dst32Rn group smode))) 2992 (ifield-assertion (andif (eq (.sym f- base1 -3) 4) (eq (.sym f- base2 -1) 1))) 2993 (getter (trunc smode (.sym Dst32Rn group smode))) 2994 (setter (set (.sym Dst32Rn group smode) newval)) 2995 ) 2996 ) 2997) 2998 2999(dst32-Rn-direct-Ext-operand ExtUnprefixed 4 8 QI HI) 3000(dst32-Rn-direct-Ext-operand ExtUnprefixed 4 8 HI SI) 3001 3002(define-derived-operand 3003 (name dst32-R3-direct-Unprefixed-HI) 3004 (comment "m32c R3 direct HI") 3005 (attrs (machine 32)) 3006 (mode HI) 3007 (args (R3)) 3008 (syntax "$R3") 3009 (base-ifield f-4-6) 3010 (encoding (+ (f-4-3 4) (f-8-2 #x1))) 3011 (ifield-assertion (andif (eq f-4-3 4) (eq f-8-2 #x1))) 3012 (getter (trunc HI R3)) 3013 (setter (set R3 newval)) 3014) 3015;------------------------------------------------------------- 3016; An direct 3017;------------------------------------------------------------- 3018 3019(define-pmacro (dst16-An-direct-operand xmode) 3020 (begin 3021 (define-derived-operand 3022 (name (.sym dst16-An-direct- xmode)) 3023 (comment (.str "m16c An direct destination " xmode)) 3024 (attrs (machine 16)) 3025 (mode xmode) 3026 (args ((.sym Dst16An xmode))) 3027 (syntax (.str "$Dst16An" xmode)) 3028 (base-ifield f-12-4) 3029 (encoding (+ (f-12-2 1) (f-14-1 0) (.sym Dst16An xmode))) 3030 (ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 0))) 3031 (getter (trunc xmode (.sym Dst16An xmode))) 3032 (setter (set (.sym Dst16An xmode) newval)) 3033 ) 3034 ) 3035) 3036 3037(dst16-An-direct-operand QI) 3038(dst16-An-direct-operand HI) 3039(dst16-An-direct-operand SI) 3040 3041(define-pmacro (dst32-An-direct-operand group base1 base2 xmode) 3042 (begin 3043 (define-derived-operand 3044 (name (.sym dst32-An-direct- group - xmode)) 3045 (comment (.str "m32c An direct destination " xmode)) 3046 (attrs (machine 32)) 3047 (mode xmode) 3048 (args ((.sym Dst32An group xmode))) 3049 (syntax (.str "$Dst32An" group xmode)) 3050 (base-ifield (.sym f- base1 -6)) 3051 (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 1) (.sym Dst32An group xmode))) 3052 (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 1))) 3053 (getter (trunc xmode (.sym Dst32An group xmode))) 3054 (setter (set (.sym Dst32An group xmode) newval)) 3055 ) 3056 ) 3057) 3058 3059(dst32-An-direct-operand Unprefixed 4 8 QI) 3060(dst32-An-direct-operand Prefixed 12 16 QI) 3061(dst32-An-direct-operand Unprefixed 4 8 HI) 3062(dst32-An-direct-operand Prefixed 12 16 HI) 3063(dst32-An-direct-operand Unprefixed 4 8 SI) 3064(dst32-An-direct-operand Prefixed 12 16 SI) 3065 3066;------------------------------------------------------------- 3067; An indirect 3068;------------------------------------------------------------- 3069 3070(define-pmacro (dst16-An-indirect-operand xmode) 3071 (begin 3072 (define-derived-operand 3073 (name (.sym dst16-An-indirect- xmode)) 3074 (comment (.str "m16c An indirect destination " xmode)) 3075 (attrs (machine 16)) 3076 (mode xmode) 3077 (args (Dst16An)) 3078 (syntax "[$Dst16An]") 3079 (base-ifield f-12-4) 3080 (encoding (+ (f-12-2 1) (f-14-1 1) Dst16An)) 3081 (ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 1))) 3082 (getter (mem16 xmode Dst16An)) 3083 (setter (set (mem16 xmode Dst16An) newval)) 3084 ) 3085 ) 3086) 3087 3088(dst16-An-indirect-operand QI) 3089(dst16-An-indirect-operand HI) 3090(dst16-An-indirect-operand SI) 3091 3092(define-derived-operand 3093 (name dst16-An-indirect-Ext-QI) 3094 (comment "m16c An indirect destination QI") 3095 (attrs (machine 16)) 3096 (mode HI) 3097 (args (Dst16An)) 3098 (syntax "[$Dst16An]") 3099 (base-ifield f-12-4) 3100 (encoding (+ (f-12-2 1) (f-14-1 1) Dst16An)) 3101 (ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 1))) 3102 (getter (mem16 QI Dst16An)) 3103 (setter (set (mem16 HI Dst16An) newval)) 3104) 3105 3106(define-pmacro (dst32-An-indirect-operand group base1 base2 smode dmode) 3107 (begin 3108 (define-derived-operand 3109 (name (.sym dst32-An-indirect- group - smode)) 3110 (comment (.str "m32c An indirect destination " smode)) 3111 (attrs (machine 32)) 3112 (mode dmode) 3113 (args ((.sym Dst32An group))) 3114 (syntax (.str "[$Dst32An" group "]")) 3115 (base-ifield (.sym f- base1 -6)) 3116 (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 0) (.sym Dst32An group))) 3117 (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 0))) 3118 (getter (c-call dmode (.str "operand_getter_" dmode) (.sym Dst32An group) 3119 (const 0))) 3120 (setter (c-call DFLT (.str "operand_setter_" dmode) newval 3121 (.sym Dst32An group) (const 0))) 3122; (getter (mem32 smode (.sym Dst32An group))) 3123; (setter (set (mem32 dmode (.sym Dst32An group)) newval)) 3124 ) 3125 ) 3126) 3127 3128(dst32-An-indirect-operand Unprefixed 4 8 QI QI) 3129(dst32-An-indirect-operand Prefixed 12 16 QI QI) 3130(dst32-An-indirect-operand Unprefixed 4 8 HI HI) 3131(dst32-An-indirect-operand Prefixed 12 16 HI HI) 3132(dst32-An-indirect-operand Unprefixed 4 8 SI SI) 3133(dst32-An-indirect-operand Prefixed 12 16 SI SI) 3134(dst32-An-indirect-operand ExtUnprefixed 4 8 QI HI) 3135(dst32-An-indirect-operand ExtUnprefixed 4 8 HI SI) 3136 3137;------------------------------------------------------------- 3138; dsp:d[r] relative 3139;------------------------------------------------------------- 3140 3141(define-pmacro (dst16-relative-operand offset xmode) 3142 (begin 3143 (define-derived-operand 3144 (name (.sym dst16- offset -8-SB-relative- xmode)) 3145 (comment (.str "m16c dsp:8[sb] relative destination " xmode)) 3146 (attrs (machine 16)) 3147 (mode xmode) 3148 (args ((.sym Dsp- offset -u8))) 3149 (syntax (.str "${Dsp-" offset "-u8}[sb]")) 3150 (base-ifield f-12-4) 3151 (encoding (+ (f-12-4 #xA) (.sym Dsp- offset -u8))) 3152 (ifield-assertion (eq f-12-4 #xA)) 3153 (getter (mem16 xmode (add (.sym Dsp- offset -u8) (reg h-sb)))) 3154 (setter (set (mem16 xmode (add (.sym Dsp- offset -u8) (reg h-sb))) newval)) 3155 ) 3156 (define-derived-operand 3157 (name (.sym dst16- offset -16-SB-relative- xmode)) 3158 (comment (.str "m16c dsp:16[sb] relative destination " xmode)) 3159 (attrs (machine 16)) 3160 (mode xmode) 3161 (args ((.sym Dsp- offset -u16))) 3162 (syntax (.str "${Dsp-" offset "-u16}[sb]")) 3163 (base-ifield f-12-4) 3164 (encoding (+ (f-12-4 #xE) (.sym Dsp- offset -u16))) 3165 (ifield-assertion (eq f-12-4 #xE)) 3166 (getter (mem16 xmode (add (.sym Dsp- offset -u16) (reg h-sb)))) 3167 (setter (set (mem16 xmode (add (.sym Dsp- offset -u16) (reg h-sb))) newval)) 3168 ) 3169 (define-derived-operand 3170 (name (.sym dst16- offset -8-FB-relative- xmode)) 3171 (comment (.str "m16c dsp:8[fb] relative destination " xmode)) 3172 (attrs (machine 16)) 3173 (mode xmode) 3174 (args ((.sym Dsp- offset -s8))) 3175 (syntax (.str "${Dsp-" offset "-s8}[fb]")) 3176 (base-ifield f-12-4) 3177 (encoding (+ (f-12-4 #xB) (.sym Dsp- offset -s8))) 3178 (ifield-assertion (eq f-12-4 #xB)) 3179 (getter (mem16 xmode (add (.sym Dsp- offset -s8) (reg h-fb)))) 3180 (setter (set (mem16 xmode (add (.sym Dsp- offset -s8) (reg h-fb))) newval)) 3181 ) 3182 (define-derived-operand 3183 (name (.sym dst16- offset -8-An-relative- xmode)) 3184 (comment (.str "m16c dsp:8[An] relative destination " xmode)) 3185 (attrs (machine 16)) 3186 (mode xmode) 3187 (args (Dst16An (.sym Dsp- offset -u8))) 3188 (syntax (.str "${Dsp-" offset "-u8}[$Dst16An]")) 3189 (base-ifield f-12-4) 3190 (encoding (+ (f-12-2 2) (f-14-1 0) (.sym Dsp- offset -u8) Dst16An)) 3191 (ifield-assertion (andif (eq f-12-2 2) (eq f-14-1 0))) 3192 (getter (mem16 xmode (add (.sym Dsp- offset -u8) Dst16An))) 3193 (setter (set (mem16 xmode (add (.sym Dsp- offset -u8) Dst16An)) newval)) 3194 ) 3195 (define-derived-operand 3196 (name (.sym dst16- offset -16-An-relative- xmode)) 3197 (comment (.str "m16c dsp:16[An] relative destination " xmode)) 3198 (attrs (machine 16)) 3199 (mode xmode) 3200 (args (Dst16An (.sym Dsp- offset -u16))) 3201 (syntax (.str "${Dsp-" offset "-u16}[$Dst16An]")) 3202 (base-ifield f-12-4) 3203 (encoding (+ (f-12-2 3) (f-14-1 0) (.sym Dsp- offset -u16) Dst16An)) 3204 (ifield-assertion (andif (eq f-12-2 3) (eq f-14-1 0))) 3205 (getter (mem16 xmode (add (.sym Dsp- offset -u16) Dst16An))) 3206 (setter (set (mem16 xmode (add (.sym Dsp- offset -u16) Dst16An)) newval)) 3207 ) 3208 (define-derived-operand 3209 (name (.sym dst16- offset -20-An-relative- xmode)) 3210 (comment (.str "m16c dsp:20[An] relative destination " xmode)) 3211 (attrs (machine 16)) 3212 (mode xmode) 3213 (args (Dst16An (.sym Dsp- offset -u20))) 3214 (syntax (.str "${Dsp-" offset "-u20}[$Dst16An]")) 3215 (base-ifield f-12-4) 3216 (encoding (+ (f-12-2 3) (f-14-1 0) (.sym Dsp- offset -u20) Dst16An)) 3217 (ifield-assertion (andif (eq f-12-2 3) (eq f-14-1 0))) 3218 (getter (mem16 xmode (add (.sym Dsp- offset -u20) Dst16An))) 3219 (setter (set (mem16 xmode (add (.sym Dsp- offset -u20) Dst16An)) newval)) 3220 ) 3221 ) 3222) 3223 3224(dst16-relative-operand 16 QI) 3225(dst16-relative-operand 24 QI) 3226(dst16-relative-operand 32 QI) 3227(dst16-relative-operand 40 QI) 3228(dst16-relative-operand 48 QI) 3229(dst16-relative-operand 16 HI) 3230(dst16-relative-operand 24 HI) 3231(dst16-relative-operand 32 HI) 3232(dst16-relative-operand 40 HI) 3233(dst16-relative-operand 48 HI) 3234(dst16-relative-operand 16 SI) 3235(dst16-relative-operand 24 SI) 3236(dst16-relative-operand 32 SI) 3237(dst16-relative-operand 40 SI) 3238(dst16-relative-operand 48 SI) 3239 3240(define-pmacro (dst16-relative-Ext-operand offset smode dmode) 3241 (begin 3242 (define-derived-operand 3243 (name (.sym dst16- offset -8-SB-relative-Ext- smode)) 3244 (comment (.str "m16c dsp:8[sb] relative destination " smode)) 3245 (attrs (machine 16)) 3246 (mode dmode) 3247 (args ((.sym Dsp- offset -u8))) 3248 (syntax (.str "${Dsp-" offset "-u8}[sb]")) 3249 (base-ifield f-12-4) 3250 (encoding (+ (f-12-4 #xA) (.sym Dsp- offset -u8))) 3251 (ifield-assertion (eq f-12-4 #xA)) 3252 (getter (mem16 smode (add (.sym Dsp- offset -u8) (reg h-sb)))) 3253 (setter (set (mem16 dmode (add (.sym Dsp- offset -u8) (reg h-sb))) newval)) 3254 ) 3255 (define-derived-operand 3256 (name (.sym dst16- offset -16-SB-relative-Ext- smode)) 3257 (comment (.str "m16c dsp:16[sb] relative destination " smode)) 3258 (attrs (machine 16)) 3259 (mode dmode) 3260 (args ((.sym Dsp- offset -u16))) 3261 (syntax (.str "${Dsp-" offset "-u16}[sb]")) 3262 (base-ifield f-12-4) 3263 (encoding (+ (f-12-4 #xE) (.sym Dsp- offset -u16))) 3264 (ifield-assertion (eq f-12-4 #xE)) 3265 (getter (mem16 smode (add (.sym Dsp- offset -u16) (reg h-sb)))) 3266 (setter (set (mem16 dmode (add (.sym Dsp- offset -u16) (reg h-sb))) newval)) 3267 ) 3268 (define-derived-operand 3269 (name (.sym dst16- offset -8-FB-relative-Ext- smode)) 3270 (comment (.str "m16c dsp:8[fb] relative destination " smode)) 3271 (attrs (machine 16)) 3272 (mode dmode) 3273 (args ((.sym Dsp- offset -s8))) 3274 (syntax (.str "${Dsp-" offset "-s8}[fb]")) 3275 (base-ifield f-12-4) 3276 (encoding (+ (f-12-4 #xB) (.sym Dsp- offset -s8))) 3277 (ifield-assertion (eq f-12-4 #xB)) 3278 (getter (mem16 smode (add (.sym Dsp- offset -s8) (reg h-fb)))) 3279 (setter (set (mem16 dmode (add (.sym Dsp- offset -s8) (reg h-fb))) newval)) 3280 ) 3281 (define-derived-operand 3282 (name (.sym dst16- offset -8-An-relative-Ext- smode)) 3283 (comment (.str "m16c dsp:8[An] relative destination " smode)) 3284 (attrs (machine 16)) 3285 (mode dmode) 3286 (args (Dst16An (.sym Dsp- offset -u8))) 3287 (syntax (.str "${Dsp-" offset "-u8}[$Dst16An]")) 3288 (base-ifield f-12-4) 3289 (encoding (+ (f-12-2 2) (f-14-1 0) (.sym Dsp- offset -u8) Dst16An)) 3290 (ifield-assertion (andif (eq f-12-2 2) (eq f-14-1 0))) 3291 (getter (mem16 smode (add (.sym Dsp- offset -u8) Dst16An))) 3292 (setter (set (mem16 dmode (add (.sym Dsp- offset -u8) Dst16An)) newval)) 3293 ) 3294 (define-derived-operand 3295 (name (.sym dst16- offset -16-An-relative-Ext- smode)) 3296 (comment (.str "m16c dsp:16[An] relative destination " smode)) 3297 (attrs (machine 16)) 3298 (mode dmode) 3299 (args (Dst16An (.sym Dsp- offset -u16))) 3300 (syntax (.str "${Dsp-" offset "-u16}[$Dst16An]")) 3301 (base-ifield f-12-4) 3302 (encoding (+ (f-12-2 3) (f-14-1 0) (.sym Dsp- offset -u16) Dst16An)) 3303 (ifield-assertion (andif (eq f-12-2 3) (eq f-14-1 0))) 3304 (getter (mem16 smode (add (.sym Dsp- offset -u16) Dst16An))) 3305 (setter (set (mem16 dmode (add (.sym Dsp- offset -u16) Dst16An)) newval)) 3306 ) 3307 ) 3308) 3309 3310(dst16-relative-Ext-operand 16 QI HI) 3311 3312(define-pmacro (dst32-relative-operand offset group base1 base2 smode dmode) 3313 (begin 3314 (define-derived-operand 3315 (name (.sym dst32- offset -8-SB-relative- group - smode)) 3316 (comment (.str "m32c dsp:8[sb] relative destination " smode)) 3317 (attrs (machine 32)) 3318 (mode dmode) 3319 (args ((.sym Dsp- offset -u8))) 3320 (syntax (.str "${Dsp-" offset "-u8}[sb]")) 3321 (base-ifield (.sym f- base1 -6)) 3322 (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u8))) 3323 (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 2))) 3324 (getter (c-call dmode (.str "operand_getter_" dmode) sb (.sym Dsp- offset -u8))) 3325 (setter (c-call DFLT (.str "operand_setter_" dmode) newval sb (.sym Dsp- offset -u8))) 3326; (getter (mem32 smode (add (.sym Dsp- offset -u8) (reg h-sb)))) 3327; (setter (set (mem32 dmode (add (.sym Dsp- offset -u8) (reg h-sb))) newval)) 3328 ) 3329 (define-derived-operand 3330 (name (.sym dst32- offset -16-SB-relative- group - smode)) 3331 (comment (.str "m32c dsp:16[sb] relative destination " smode)) 3332 (attrs (machine 32)) 3333 (mode dmode) 3334 (args ((.sym Dsp- offset -u16))) 3335 (syntax (.str "${Dsp-" offset "-u16}[sb]")) 3336 (base-ifield (.sym f- base1 -6)) 3337 (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u16))) 3338 (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 2))) 3339 (getter (c-call dmode (.str "operand_getter_" dmode) sb (.sym Dsp- offset -u16))) 3340 (setter (c-call DFLT (.str "operand_setter_" dmode) newval sb (.sym Dsp- offset -u16))) 3341; (getter (mem32 smode (add (.sym Dsp- offset -u16) (reg h-sb)))) 3342; (setter (set (mem32 dmode (add (.sym Dsp- offset -u16) (reg h-sb))) newval)) 3343 ) 3344 (define-derived-operand 3345 (name (.sym dst32- offset -8-FB-relative- group - smode)) 3346 (comment (.str "m32c dsp:8[fb] relative destination " smode)) 3347 (attrs (machine 32)) 3348 (mode dmode) 3349 (args ((.sym Dsp- offset -s8))) 3350 (syntax (.str "${Dsp-" offset "-s8}[fb]")) 3351 (base-ifield (.sym f- base1 -6)) 3352 (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 3) (.sym Dsp- offset -s8))) 3353 (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 3))) 3354 (getter (c-call dmode (.str "operand_getter_" dmode) fb (.sym Dsp- offset -s8))) 3355 (setter (c-call DFLT (.str "operand_setter_" dmode) newval fb (.sym Dsp- offset -s8))) 3356; (getter (mem32 smode (add (.sym Dsp- offset -s8) (reg h-fb)))) 3357; (setter (set (mem32 dmode (add (.sym Dsp- offset -s8) (reg h-fb))) newval)) 3358 ) 3359 (define-derived-operand 3360 (name (.sym dst32- offset -16-FB-relative- group - smode)) 3361 (comment (.str "m32c dsp:16[fb] relative destination " smode)) 3362 (attrs (machine 32)) 3363 (mode dmode) 3364 (args ((.sym Dsp- offset -s16))) 3365 (syntax (.str "${Dsp-" offset "-s16}[fb]")) 3366 (base-ifield (.sym f- base1 -6)) 3367 (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 3) (.sym Dsp- offset -s16))) 3368 (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 3))) 3369 (getter (c-call dmode (.str "operand_getter_" dmode) fb (.sym Dsp- offset -s16))) 3370 (setter (c-call DFLT (.str "operand_setter_" dmode) newval fb (.sym Dsp- offset -s16))) 3371; (getter (mem32 smode (add (.sym Dsp- offset -s16) (reg h-fb)))) 3372; (setter (set (mem32 dmode (add (.sym Dsp- offset -s16) (reg h-fb))) newval)) 3373 ) 3374 (define-derived-operand 3375 (name (.sym dst32- offset -8-An-relative- group - smode)) 3376 (comment (.str "m32c dsp:8[An] relative destination " smode)) 3377 (attrs (machine 32)) 3378 (mode dmode) 3379 (args ((.sym Dst32An group) (.sym Dsp- offset -u8))) 3380 (syntax (.str "${Dsp-" offset "-u8}[$Dst32An" group "]")) 3381 (base-ifield (.sym f- base1 -6)) 3382 (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u8) (.sym Dst32An group))) 3383 (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -1) 0))) 3384 (getter (c-call dmode (.str "operand_getter_" dmode) (.sym Dst32An group) (.sym Dsp- offset -u8))) 3385 (setter (c-call DFLT (.str "operand_setter_" dmode) newval (.sym Dst32An group) (.sym Dsp- offset -u8))) 3386; (getter (mem32 smode (add (.sym Dsp- offset -u8) (.sym Dst32An group)))) 3387; (setter (set (mem32 dmode (add (.sym Dsp- offset -u8) (.sym Dst32An group))) newval)) 3388 ) 3389 (define-derived-operand 3390 (name (.sym dst32- offset -16-An-relative- group - smode)) 3391 (comment (.str "m32c dsp:16[An] relative destination " smode)) 3392 (attrs (machine 32)) 3393 (mode dmode) 3394 (args ((.sym Dst32An group) (.sym Dsp- offset -u16))) 3395 (syntax (.str "${Dsp-" offset "-u16}[$Dst32An" group "]")) 3396 (base-ifield (.sym f- base1 -6)) 3397 (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u16) (.sym Dst32An group))) 3398 (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -1) 0))) 3399 (getter (c-call dmode (.str "operand_getter_" dmode) (.sym Dst32An group) (.sym Dsp- offset -u16))) 3400 (setter (c-call DFLT (.str "operand_setter_" dmode) newval (.sym Dst32An group) (.sym Dsp- offset -u16))) 3401; (getter (mem32 smode (add (.sym Dsp- offset -u16) (.sym Dst32An group)))) 3402; (setter (set (mem32 dmode (add (.sym Dsp- offset -u16) (.sym Dst32An group))) newval)) 3403 ) 3404 (define-derived-operand 3405 (name (.sym dst32- offset -24-An-relative- group - smode)) 3406 (comment (.str "m32c dsp:16[An] relative destination " smode)) 3407 (attrs (machine 32)) 3408 (mode dmode) 3409 (args ((.sym Dst32An group) (.sym Dsp- offset -u24))) 3410 (syntax (.str "${Dsp-" offset "-u24}[$Dst32An" group "]")) 3411 (base-ifield (.sym f- base1 -6)) 3412 (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u24) (.sym Dst32An group))) 3413 (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -1) 0))) 3414 (getter (c-call dmode (.str "operand_getter_" dmode) (.sym Dst32An group) (.sym Dsp- offset -u24))) 3415 (setter (c-call DFLT (.str "operand_setter_" dmode) newval (.sym Dst32An group) (.sym Dsp- offset -u24))) 3416; (getter (mem32 smode (add (.sym Dsp- offset -u24) (.sym Dst32An group)))) 3417; (setter (set (mem32 dmode (add (.sym Dsp- offset -u24) (.sym Dst32An group))) newval)) 3418 ) 3419 ) 3420) 3421 3422(dst32-relative-operand 16 Unprefixed 4 8 QI QI) 3423(dst32-relative-operand 24 Unprefixed 4 8 QI QI) 3424(dst32-relative-operand 32 Unprefixed 4 8 QI QI) 3425(dst32-relative-operand 40 Unprefixed 4 8 QI QI) 3426(dst32-relative-operand 16 Unprefixed 4 8 HI HI) 3427(dst32-relative-operand 24 Unprefixed 4 8 HI HI) 3428(dst32-relative-operand 32 Unprefixed 4 8 HI HI) 3429(dst32-relative-operand 40 Unprefixed 4 8 HI HI) 3430(dst32-relative-operand 16 Unprefixed 4 8 SI SI) 3431(dst32-relative-operand 24 Unprefixed 4 8 SI SI) 3432(dst32-relative-operand 32 Unprefixed 4 8 SI SI) 3433(dst32-relative-operand 40 Unprefixed 4 8 SI SI) 3434 3435(dst32-relative-operand 24 Prefixed 12 16 QI QI) 3436(dst32-relative-operand 32 Prefixed 12 16 QI QI) 3437(dst32-relative-operand 40 Prefixed 12 16 QI QI) 3438(dst32-relative-operand 48 Prefixed 12 16 QI QI) 3439(dst32-relative-operand 24 Prefixed 12 16 HI HI) 3440(dst32-relative-operand 32 Prefixed 12 16 HI HI) 3441(dst32-relative-operand 40 Prefixed 12 16 HI HI) 3442(dst32-relative-operand 48 Prefixed 12 16 HI HI) 3443(dst32-relative-operand 24 Prefixed 12 16 SI SI) 3444(dst32-relative-operand 32 Prefixed 12 16 SI SI) 3445(dst32-relative-operand 40 Prefixed 12 16 SI SI) 3446(dst32-relative-operand 48 Prefixed 12 16 SI SI) 3447 3448(dst32-relative-operand 16 ExtUnprefixed 4 8 QI HI) 3449(dst32-relative-operand 16 ExtUnprefixed 4 8 HI SI) 3450 3451;------------------------------------------------------------- 3452; Absolute address 3453;------------------------------------------------------------- 3454 3455(define-pmacro (dst16-absolute offset xmode) 3456 (begin 3457 (define-derived-operand 3458 (name (.sym dst16- offset -16-absolute- xmode)) 3459 (comment (.str "m16c absolute address " xmode)) 3460 (attrs (machine 16)) 3461 (mode xmode) 3462 (args ((.sym Dsp- offset -u16))) 3463 (syntax (.str "${Dsp-" offset "-u16}")) 3464 (base-ifield f-12-4) 3465 (encoding (+ (f-12-4 #xF) (.sym Dsp- offset -u16))) 3466 (ifield-assertion (eq f-12-4 #xF)) 3467 (getter (mem16 xmode (.sym Dsp- offset -u16))) 3468 (setter (set (mem16 xmode (.sym Dsp- offset -u16)) newval)) 3469 ) 3470 ) 3471) 3472 3473(dst16-absolute 16 QI) 3474(dst16-absolute 24 QI) 3475(dst16-absolute 32 QI) 3476(dst16-absolute 40 QI) 3477(dst16-absolute 48 QI) 3478(dst16-absolute 16 HI) 3479(dst16-absolute 24 HI) 3480(dst16-absolute 32 HI) 3481(dst16-absolute 40 HI) 3482(dst16-absolute 48 HI) 3483(dst16-absolute 16 SI) 3484(dst16-absolute 24 SI) 3485(dst16-absolute 32 SI) 3486(dst16-absolute 40 SI) 3487(dst16-absolute 48 SI) 3488 3489(define-derived-operand 3490 (name dst16-16-16-absolute-Ext-QI) 3491 (comment "m16c absolute address QI") 3492 (attrs (machine 16)) 3493 (mode HI) 3494 (args (Dsp-16-u16)) 3495 (syntax "${Dsp-16-u16}") 3496 (base-ifield f-12-4) 3497 (encoding (+ (f-12-4 #xF) Dsp-16-u16)) 3498 (ifield-assertion (eq f-12-4 #xF)) 3499 (getter (mem16 QI Dsp-16-u16)) 3500 (setter (set (mem16 HI Dsp-16-u16) newval)) 3501) 3502 3503(define-pmacro (dst32-absolute offset group base1 base2 smode dmode) 3504 (begin 3505 (define-derived-operand 3506 (name (.sym dst32- offset -16-absolute- group - smode)) 3507 (comment (.str "m32c absolute address " smode)) 3508 (attrs (machine 32)) 3509 (mode dmode) 3510 (args ((.sym Dsp- offset -u16))) 3511 (syntax (.str "${Dsp-" offset "-u16}")) 3512 (base-ifield (.sym f- base1 -6)) 3513 (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 3) (.sym Dsp- offset -u16))) 3514 (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 3))) 3515 (getter (c-call smode (.str "operand_getter_" smode) (const 0) (.sym Dsp- offset -u16))) 3516 (setter (c-call DFLT (.str "operand_setter_" dmode) newval (const 0) (.sym Dsp- offset -u16))) 3517; (getter (mem32 smode (.sym Dsp- offset -u16))) 3518; (setter (set (mem32 dmode (.sym Dsp- offset -u16)) newval)) 3519 ) 3520 (define-derived-operand 3521 (name (.sym dst32- offset -24-absolute- group - smode)) 3522 (comment (.str "m32c absolute address " smode)) 3523 (attrs (machine 32)) 3524 (mode dmode) 3525 (args ((.sym Dsp- offset -u24))) 3526 (syntax (.str "${Dsp-" offset "-u24}")) 3527 (base-ifield (.sym f- base1 -6)) 3528 (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u24))) 3529 (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 2))) 3530 (getter (c-call smode (.str "operand_getter_" smode) (const 0) (.sym Dsp- offset -u24))) 3531 (setter (c-call DFLT (.str "operand_setter_" dmode) newval (const 0) (.sym Dsp- offset -u24))) 3532; (getter (mem32 smode (.sym Dsp- offset -u24))) 3533; (setter (set (mem32 dmode (.sym Dsp- offset -u24)) newval)) 3534 ) 3535 ) 3536) 3537 3538(dst32-absolute 16 Unprefixed 4 8 QI QI) 3539(dst32-absolute 24 Unprefixed 4 8 QI QI) 3540(dst32-absolute 32 Unprefixed 4 8 QI QI) 3541(dst32-absolute 40 Unprefixed 4 8 QI QI) 3542(dst32-absolute 16 Unprefixed 4 8 HI HI) 3543(dst32-absolute 24 Unprefixed 4 8 HI HI) 3544(dst32-absolute 32 Unprefixed 4 8 HI HI) 3545(dst32-absolute 40 Unprefixed 4 8 HI HI) 3546(dst32-absolute 16 Unprefixed 4 8 SI SI) 3547(dst32-absolute 24 Unprefixed 4 8 SI SI) 3548(dst32-absolute 32 Unprefixed 4 8 SI SI) 3549(dst32-absolute 40 Unprefixed 4 8 SI SI) 3550 3551(dst32-absolute 24 Prefixed 12 16 QI QI) 3552(dst32-absolute 32 Prefixed 12 16 QI QI) 3553(dst32-absolute 40 Prefixed 12 16 QI QI) 3554(dst32-absolute 48 Prefixed 12 16 QI QI) 3555(dst32-absolute 24 Prefixed 12 16 HI HI) 3556(dst32-absolute 32 Prefixed 12 16 HI HI) 3557(dst32-absolute 40 Prefixed 12 16 HI HI) 3558(dst32-absolute 48 Prefixed 12 16 HI HI) 3559(dst32-absolute 24 Prefixed 12 16 SI SI) 3560(dst32-absolute 32 Prefixed 12 16 SI SI) 3561(dst32-absolute 40 Prefixed 12 16 SI SI) 3562(dst32-absolute 48 Prefixed 12 16 SI SI) 3563 3564(dst32-absolute 16 ExtUnprefixed 4 8 QI HI) 3565(dst32-absolute 16 ExtUnprefixed 4 8 HI SI) 3566 3567;------------------------------------------------------------- 3568; An indirect indirect 3569;------------------------------------------------------------- 3570 3571;(define-pmacro (dst-An-indirect-indirect-operand xmode) 3572; (define-derived-operand 3573; (name (.sym dst32-An-indirect-indirect- xmode)) 3574; (comment (.str "m32c An indirect indirect destination " xmode)) 3575; (attrs (machine 32)) 3576; (mode xmode) 3577; (args (Dst32AnPrefixed)) 3578; (syntax (.str "[[$Dst32AnPrefixed]]")) 3579; (base-ifield f-12-6) 3580; (encoding (+ (f-12-3 0) (f-16-1 0) Dst32AnPrefixed)) 3581; (ifield-assertion (andif (eq f-12-3 0) (eq f-16-1 0))) 3582; (getter (mem32 xmode (indirect-addr Dst32AnPrefixed))) 3583; (setter (set (mem32 xmode (indirect-addr Dst32AnPrefixed)) newval)) 3584; ) 3585;) 3586 3587; (dst-An-indirect-indirect-operand QI) 3588; (dst-An-indirect-indirect-operand HI) 3589; (dst-An-indirect-indirect-operand SI) 3590 3591;------------------------------------------------------------- 3592; Relative indirect 3593;------------------------------------------------------------- 3594 3595(define-pmacro (dst-relative-indirect-operand offset xmode) 3596 (begin 3597; (define-derived-operand 3598; (name (.sym dst32- offset -8-SB-relative-indirect- xmode)) 3599; (comment (.str "m32c dsp:8[sb] relative destination " xmode)) 3600; (attrs (machine 32)) 3601; (mode xmode) 3602; (args ((.sym Dsp- offset -u8))) 3603; (syntax (.str "[${Dsp-" offset "-u8}[sb]]")) 3604; (base-ifield f-12-6) 3605; (encoding (+ (f-12-3 1) (f-16-2 2) (.sym Dsp- offset -u8))) 3606; (ifield-assertion (andif (eq f-12-3 1) (eq f-16-2 2))) 3607; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u8) (reg h-sb))))) 3608; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u8) (reg h-sb)))) newval)) 3609; ) 3610; (define-derived-operand 3611; (name (.sym dst32- offset -16-SB-relative-indirect- xmode)) 3612; (comment (.str "m32c dsp:16[sb] relative destination " xmode)) 3613; (attrs (machine 32)) 3614; (mode xmode) 3615; (args ((.sym Dsp- offset -u16))) 3616; (syntax (.str "[${Dsp-" offset "-u16}[sb]]")) 3617; (base-ifield f-12-6) 3618; (encoding (+ (f-12-3 2) (f-16-2 2) (.sym Dsp- offset -u16))) 3619; (ifield-assertion (andif (eq f-12-3 2) (eq f-16-2 2))) 3620; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u16) (reg h-sb))))) 3621; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u16) (reg h-sb)))) newval)) 3622; ) 3623; (define-derived-operand 3624; (name (.sym dst32- offset -8-FB-relative-indirect- xmode)) 3625; (comment (.str "m32c dsp:8[fb] relative destination " xmode)) 3626; (attrs (machine 32)) 3627; (mode xmode) 3628; (args ((.sym Dsp- offset -s8))) 3629; (syntax (.str "[${Dsp-" offset "-s8}[fb]]")) 3630; (base-ifield f-12-6) 3631; (encoding (+ (f-12-3 1) (f-16-2 3) (.sym Dsp- offset -s8))) 3632; (ifield-assertion (andif (eq f-12-3 1) (eq f-16-2 3))) 3633; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -s8) (reg h-fb))))) 3634; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -s8) (reg h-fb)))) newval)) 3635; ) 3636; (define-derived-operand 3637; (name (.sym dst32- offset -16-FB-relative-indirect- xmode)) 3638; (comment (.str "m32c dsp:16[fb] relative destination " xmode)) 3639; (attrs (machine 32)) 3640; (mode xmode) 3641; (args ((.sym Dsp- offset -s16))) 3642; (syntax (.str "[${Dsp-" offset "-s16}[fb]]")) 3643; (base-ifield f-12-6) 3644; (encoding (+ (f-12-3 2) (f-16-2 3) (.sym Dsp- offset -s16))) 3645; (ifield-assertion (andif (eq f-12-3 2) (eq f-16-2 3))) 3646; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -s16) (reg h-fb))))) 3647; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -s16) (reg h-fb)))) newval)) 3648; ) 3649; (define-derived-operand 3650; (name (.sym dst32- offset -8-An-relative-indirect- xmode)) 3651; (comment (.str "m32c dsp:8[An] relative indirect destination " xmode)) 3652; (attrs (machine 32)) 3653; (mode xmode) 3654; (args (Dst32AnPrefixed (.sym Dsp- offset -u8))) 3655; (syntax (.str "[${Dsp-" offset "-u8}[$Dst32AnPrefixed]]")) 3656; (base-ifield f-12-6) 3657; (encoding (+ (f-12-3 1) (f-16-1 0) (.sym Dsp- offset -u8) Dst32AnPrefixed)) 3658; (ifield-assertion (andif (eq f-12-3 1) (eq f-16-1 0))) 3659; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u8) Dst32AnPrefixed)))) 3660; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u8) Dst32AnPrefixed))) newval)) 3661; ) 3662; (define-derived-operand 3663; (name (.sym dst32- offset -16-An-relative-indirect- xmode)) 3664; (comment (.str "m32c dsp:16[An] relative destination " xmode)) 3665; (attrs (machine 32)) 3666; (mode xmode) 3667; (args (Dst32AnPrefixed (.sym Dsp- offset -u16))) 3668; (syntax (.str "[${Dsp-" offset "-u16}[$Dst32AnPrefixed]]")) 3669; (base-ifield f-12-6) 3670; (encoding (+ (f-12-3 2) (f-16-1 0) (.sym Dsp- offset -u16) Dst32AnPrefixed)) 3671; (ifield-assertion (andif (eq f-12-3 2) (eq f-16-1 0))) 3672; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u16) Dst32AnPrefixed)))) 3673; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u16) Dst32AnPrefixed))) newval)) 3674; ) 3675; (define-derived-operand 3676; (name (.sym dst32- offset -24-An-relative-indirect- xmode)) 3677; (comment (.str "m32c dsp:24[An] relative destination " xmode)) 3678; (attrs (machine 32)) 3679; (mode xmode) 3680; (args (Dst32AnPrefixed (.sym Dsp- offset -u24))) 3681; (syntax (.str "[${Dsp-" offset "-u24}[$Dst32AnPrefixed]]")) 3682; (base-ifield f-12-6) 3683; (encoding (+ (f-12-3 3) (f-16-1 0) (.sym Dsp- offset -u24) Dst32AnPrefixed)) 3684; (ifield-assertion (andif (eq f-12-3 3) (eq f-16-1 0))) 3685; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u24) Dst32AnPrefixed)))) 3686; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u24) Dst32AnPrefixed))) newval)) 3687; ) 3688 ) 3689) 3690 3691; (dst-relative-indirect-operand 24 QI) 3692; (dst-relative-indirect-operand 32 QI) 3693; (dst-relative-indirect-operand 40 QI) 3694; (dst-relative-indirect-operand 48 QI) 3695; (dst-relative-indirect-operand 24 HI) 3696; (dst-relative-indirect-operand 32 HI) 3697; (dst-relative-indirect-operand 40 HI) 3698; (dst-relative-indirect-operand 48 HI) 3699; (dst-relative-indirect-operand 24 SI) 3700; (dst-relative-indirect-operand 32 SI) 3701; (dst-relative-indirect-operand 40 SI) 3702; (dst-relative-indirect-operand 48 SI) 3703 3704;------------------------------------------------------------- 3705; Absolute indirect 3706;------------------------------------------------------------- 3707 3708(define-pmacro (dst-absolute-indirect offset xmode) 3709 (begin 3710; (define-derived-operand 3711; (name (.sym dst32- offset -16-absolute-indirect-derived- xmode)) 3712; (comment (.str "m32c absolute indirect address " xmode)) 3713; (attrs (machine 32)) 3714; (mode xmode) 3715; (args ((.sym Dsp- offset -u16))) 3716; (syntax (.str "[${Dsp-" offset "-u16}]")) 3717; (base-ifield f-12-6) 3718; (encoding (+ (f-12-3 3) (f-16-2 3) (.sym Dsp- offset -u16))) 3719; (ifield-assertion (andif (eq f-12-3 3) (eq f-16-2 3))) 3720; (getter (mem32 xmode (indirect-addr (.sym Dsp- offset -u16)))) 3721; (setter (set (mem32 xmode (indirect-addr (.sym Dsp- offset -u16))) newval)) 3722; ) 3723; (define-derived-operand 3724; (name (.sym dst32- offset -24-absolute-indirect-derived- xmode)) 3725; (comment (.str "m32c absolute indirect address " xmode)) 3726; (attrs (machine 32)) 3727; (mode xmode) 3728; (args ((.sym Dsp- offset -u24))) 3729; (syntax (.str "[${Dsp-" offset "-u24}]")) 3730; (base-ifield f-12-6) 3731; (encoding (+ (f-12-3 3) (f-16-2 2) (.sym Dsp- offset -u24))) 3732; (ifield-assertion (andif (eq f-12-3 3) (eq f-16-2 2))) 3733; (getter (mem32 xmode (indirect-addr (.sym Dsp- offset -u24)))) 3734; (setter (set (mem32 xmode (indirect-addr (.sym Dsp- offset -u24))) newval)) 3735; ) 3736 ) 3737) 3738 3739(dst-absolute-indirect 24 QI) 3740(dst-absolute-indirect 32 QI) 3741(dst-absolute-indirect 40 QI) 3742(dst-absolute-indirect 48 QI) 3743(dst-absolute-indirect 24 HI) 3744(dst-absolute-indirect 32 HI) 3745(dst-absolute-indirect 40 HI) 3746(dst-absolute-indirect 48 HI) 3747(dst-absolute-indirect 24 SI) 3748(dst-absolute-indirect 32 SI) 3749(dst-absolute-indirect 40 SI) 3750(dst-absolute-indirect 48 SI) 3751 3752;------------------------------------------------------------- 3753; Bit operands 3754;------------------------------------------------------------- 3755(define-pmacro (get-register-bit reg bitno) 3756 (and (srl reg bitno) 1) 3757) 3758 3759(define-pmacro (set-register-bit reg bitno value) 3760 (set reg (or (and reg (inv (sll 1 bitno))) 3761 (sll (and QI value 1) bitno))) 3762) 3763 3764(define-pmacro (get-memory-bit mach base bitno) 3765 (and (srl (mem-mach mach QI (add base (div bitno 8))) 3766 (mod bitno 8)) 3767 1) 3768) 3769 3770(define-pmacro (set-memory-bit mach base bitno value) 3771 (sequence ((USI addr)) 3772 (set addr (add base (div bitno 8))) 3773 (set (mem-mach mach QI addr) 3774 (or (and (mem-mach mach QI addr) 3775 (inv (sll 1 (mod bitno 8)))) 3776 (sll (and QI value 1) (mod bitno 8))))) 3777) 3778 3779;------------------------------------------------------------- 3780; Rn direct 3781;------------------------------------------------------------- 3782 3783(define-derived-operand 3784 (name bit16-Rn-direct) 3785 (comment "m16c Rn direct bit") 3786 (attrs (machine 16)) 3787 (mode BI) 3788 (args (Bitno16R Bit16Rn)) 3789 (syntax "$Bitno16R,$Bit16Rn") 3790 (base-ifield f-12-4) 3791 (encoding (+ (f-12-2 0) Bit16Rn Bitno16R)) 3792 (ifield-assertion (eq f-12-2 0)) 3793 (getter (get-register-bit Bit16Rn Bitno16R)) 3794 (setter (set-register-bit Bit16Rn Bitno16R newval)) 3795) 3796 3797(define-pmacro (bit32-Rn-direct-operand group base) 3798 (begin 3799 (define-derived-operand 3800 (name (.sym bit32-Rn-direct- group)) 3801 (comment "m32c Rn direct bit") 3802 (attrs (machine 32)) 3803 (mode BI) 3804 (args ((.sym Bitno32 group) (.sym Bit32Rn group))) 3805 (syntax (.str "$Bitno32" group ",$Bit32Rn" group)) 3806 (base-ifield (.sym f- base -6)) 3807 (encoding (+ ((.sym f- base -3) 4) (.sym Bit32Rn group) (.sym Bitno32 group))) 3808 (ifield-assertion (eq (.sym f- base -3) 4)) 3809 (getter (get-register-bit (.sym Bit32Rn group) (.sym Bitno32 group))) 3810 (setter (set-register-bit (.sym Bit32Rn group) (.sym Bitno32 group) newval)) 3811 ) 3812 ) 3813) 3814 3815(bit32-Rn-direct-operand Unprefixed 4) 3816(bit32-Rn-direct-operand Prefixed 12) 3817 3818;------------------------------------------------------------- 3819; An direct 3820;------------------------------------------------------------- 3821 3822(define-derived-operand 3823 (name bit16-An-direct) 3824 (comment "m16c An direct bit") 3825 (attrs (machine 16)) 3826 (mode BI) 3827 (args (Bitno16R Bit16An)) 3828 (syntax "$Bitno16R,$Bit16An") 3829 (base-ifield f-12-4) 3830 (encoding (+ (f-12-2 1) (f-14-1 0) Bit16An Bitno16R)) 3831 (ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 0))) 3832 (getter (get-register-bit Bit16An Bitno16R)) 3833 (setter (set-register-bit Bit16An Bitno16R newval)) 3834) 3835 3836(define-pmacro (bit32-An-direct-operand group base1 base2) 3837 (begin 3838 (define-derived-operand 3839 (name (.sym bit32-An-direct- group)) 3840 (comment "m32c An direct bit") 3841 (attrs (machine 32)) 3842 (mode BI) 3843 (args ((.sym Bitno32 group) (.sym Bit32An group))) 3844 (syntax (.str "$Bitno32" group ",$Bit32An" group)) 3845 (base-ifield (.sym f- base1 -6)) 3846 (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 1) (.sym Bit32An group) (.sym Bitno32 group))) 3847 (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 1))) 3848 (getter (get-register-bit (.sym Bit32An group) (.sym Bitno32 group))) 3849 (setter (set-register-bit (.sym Bit32An group) (.sym Bitno32 group) newval)) 3850 ) 3851 ) 3852) 3853 3854(bit32-An-direct-operand Unprefixed 4 8) 3855(bit32-An-direct-operand Prefixed 12 16) 3856 3857;------------------------------------------------------------- 3858; An indirect 3859;------------------------------------------------------------- 3860 3861(define-derived-operand 3862 (name bit16-An-indirect) 3863 (comment "m16c An indirect bit") 3864 (attrs (machine 16)) 3865 (mode BI) 3866 (args (Bit16An)) 3867 (syntax "[$Bit16An]") 3868 (base-ifield f-12-4) 3869 (encoding (+ (f-12-2 1) (f-14-1 1) Bit16An)) 3870 (ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 1))) 3871 (getter (get-memory-bit 16 0 Bit16An)) 3872 (setter (set-memory-bit 16 0 Bit16An newval)) 3873) 3874 3875(define-pmacro (bit32-An-indirect-operand group base1 base2) 3876 (begin 3877 (define-derived-operand 3878 (name (.sym bit32-An-indirect- group)) 3879 (comment "m32c An indirect destination ") 3880 (attrs (machine 32)) 3881 (mode BI) 3882 (args ((.sym Bitno32 group) (.sym Bit32An group))) 3883 (syntax (.str "$Bitno32" group ",[$Bit32An" group "]")) 3884 (base-ifield (.sym f- base1 -6)) 3885 (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 0) (.sym Bit32An group) (.sym Bitno32 group))) 3886 (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 0))) 3887 (getter (get-memory-bit 32 (.sym Bit32An group) (.sym Bitno32 group))) 3888 (setter (set-memory-bit 32 (.sym Bit32An group) (.sym Bitno32 group) newval)) 3889 ) 3890 ) 3891) 3892 3893(bit32-An-indirect-operand Unprefixed 4 8) 3894(bit32-An-indirect-operand Prefixed 12 16) 3895 3896;------------------------------------------------------------- 3897; dsp:d[r] relative 3898;------------------------------------------------------------- 3899 3900(define-pmacro (bit16-relative-operand offset) 3901 (begin 3902 (define-derived-operand 3903 (name (.sym bit16- offset -8-SB-relative)) 3904 (comment (.str "m16c dsp:8[sb] relative bit " xmode)) 3905 (attrs (machine 16)) 3906 (mode BI) 3907 (args ((.sym BitBase16- offset -u8))) 3908 (syntax (.str "${BitBase16-" offset "-u8}[sb]")) 3909 (base-ifield f-12-4) 3910 (encoding (+ (f-12-4 #xA) (.sym BitBase16- offset -u8))) 3911 (ifield-assertion (eq f-12-4 #xA)) 3912 (getter (get-memory-bit 16 (reg h-sb) (.sym BitBase16- offset -u8))) 3913 (setter (set-memory-bit 16 (reg h-sb) (.sym BitBase16- offset -u8) newval)) 3914 ) 3915 (define-derived-operand 3916 (name (.sym bit16- offset -16-SB-relative)) 3917 (comment (.str "m16c dsp:16[sb] relative bit " xmode)) 3918 (attrs (machine 16)) 3919 (mode BI) 3920 (args ((.sym BitBase16- offset -u16))) 3921 (syntax (.str "${BitBase16-" offset "-u16}[sb]")) 3922 (base-ifield f-12-4) 3923 (encoding (+ (f-12-4 #xE) (.sym BitBase16- offset -u16))) 3924 (ifield-assertion (eq f-12-4 #xE)) 3925 (getter (get-memory-bit 16 (reg h-sb) (.sym BitBase16- offset -u16))) 3926 (setter (set-memory-bit 16 (reg h-sb) (.sym BitBase16- offset -u16) newval)) 3927 ) 3928 (define-derived-operand 3929 (name (.sym bit16- offset -8-FB-relative)) 3930 (comment (.str "m16c dsp:8[fb] relative bit " xmode)) 3931 (attrs (machine 16)) 3932 (mode BI) 3933 (args ((.sym BitBase16- offset -s8))) 3934 (syntax (.str "${BitBase16-" offset "-s8}[fb]")) 3935 (base-ifield f-12-4) 3936 (encoding (+ (f-12-4 #xB) (.sym BitBase16- offset -s8))) 3937 (ifield-assertion (eq f-12-4 #xB)) 3938 (getter (get-memory-bit 16 (reg h-fb) (.sym BitBase16- offset -s8))) 3939 (setter (set-memory-bit 16 (reg h-fb) (.sym BitBase16- offset -s8) newval)) 3940 ) 3941 (define-derived-operand 3942 (name (.sym bit16- offset -8-An-relative)) 3943 (comment (.str "m16c dsp:8[An] relative bit " xmode)) 3944 (attrs (machine 16)) 3945 (mode BI) 3946 (args (Bit16An (.sym Dsp- offset -u8))) 3947 (syntax (.str "${Dsp-" offset "-u8}[$Bit16An]")) 3948 (base-ifield f-12-4) 3949 (encoding (+ (f-12-2 2) (f-14-1 0) (.sym Dsp- offset -u8) Bit16An)) 3950 (ifield-assertion (andif (eq f-12-2 2) (eq f-14-1 0))) 3951 (getter (get-memory-bit 16 (.sym Dsp- offset -u8) Bit16An)) 3952 (setter (set-memory-bit 16 (.sym Dsp- offset -u8) Bit16An newval)) 3953 ) 3954 (define-derived-operand 3955 (name (.sym bit16- offset -16-An-relative)) 3956 (comment (.str "m16c dsp:16[An] relative bit " xmode)) 3957 (attrs (machine 16)) 3958 (mode BI) 3959 (args (Bit16An (.sym Dsp- offset -u16))) 3960 (syntax (.str "${Dsp-" offset "-u16}[$Bit16An]")) 3961 (base-ifield f-12-4) 3962 (encoding (+ (f-12-2 3) (f-14-1 0) (.sym Dsp- offset -u16) Bit16An)) 3963 (ifield-assertion (andif (eq f-12-2 3) (eq f-14-1 0))) 3964 (getter (get-memory-bit 16 (.sym Dsp- offset -u16) Bit16An)) 3965 (setter (set-memory-bit 16 (.sym Dsp- offset -u16) Bit16An newval)) 3966 ) 3967 ) 3968) 3969 3970(bit16-relative-operand 16) 3971 3972(define-pmacro (bit32-relative-operand offset group base1 base2) 3973 (begin 3974 (define-derived-operand 3975 (name (.sym bit32- offset -11-SB-relative- group)) 3976 (comment "m32c bit,base:11[sb] relative bit") 3977 (attrs (machine 32)) 3978 (mode BI) 3979 (args ((.sym BitBase32- offset -u11- group))) 3980 (syntax (.str "${BitBase32-" offset "-u11-" group "}[sb]")) 3981 (base-ifield (.sym f- base1 -12)) 3982 (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 2) (.sym BitBase32- offset -u11- group))) 3983 (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 2))) 3984 (getter (get-memory-bit 32 (reg h-sb) (.sym BitBase32- offset -u11- group))) 3985 (setter (set-memory-bit 32 (reg h-sb) (.sym BitBase32- offset -u11- group) newval)) 3986 ) 3987 (define-derived-operand 3988 (name (.sym bit32- offset -19-SB-relative- group)) 3989 (comment "m32c bit,base:19[sb] relative bit") 3990 (attrs (machine 32)) 3991 (mode BI) 3992 (args ((.sym BitBase32- offset -u19- group))) 3993 (syntax (.str "${BitBase32-" offset "-u19-" group "}[sb]")) 3994 (base-ifield (.sym f- base1 -12)) 3995 (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 2) (.sym BitBase32- offset -u19- group))) 3996 (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 2))) 3997 (getter (get-memory-bit 32 (reg h-sb) (.sym BitBase32- offset -u19- group))) 3998 (setter (set-memory-bit 32 (reg h-sb) (.sym BitBase32- offset -u19- group) newval)) 3999 ) 4000 (define-derived-operand 4001 (name (.sym bit32- offset -11-FB-relative- group)) 4002 (comment "m32c bit,base:11[fb] relative bit") 4003 (attrs (machine 32)) 4004 (mode BI) 4005 (args ((.sym BitBase32- offset -s11- group))) 4006 (syntax (.str "${BitBase32-" offset "-s11-" group "}[fb]")) 4007 (base-ifield (.sym f- base1 -12)) 4008 (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 3) (.sym BitBase32- offset -s11- group))) 4009 (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 3))) 4010 (getter (get-memory-bit 32 (reg h-fb) (.sym BitBase32- offset -s11- group))) 4011 (setter (set-memory-bit 32 (reg h-fb) (.sym BitBase32- offset -s11- group) newval)) 4012 ) 4013 (define-derived-operand 4014 (name (.sym bit32- offset -19-FB-relative- group)) 4015 (comment "m32c bit,base:19[fb] relative bit") 4016 (attrs (machine 32)) 4017 (mode BI) 4018 (args ((.sym BitBase32- offset -s19- group))) 4019 (syntax (.str "${BitBase32-" offset "-s19-" group "}[fb]")) 4020 (base-ifield (.sym f- base1 -12)) 4021 (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 3) (.sym BitBase32- offset -s19- group))) 4022 (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 3))) 4023 (getter (get-memory-bit 32 (reg h-fb) (.sym BitBase32- offset -s19- group))) 4024 (setter (set-memory-bit 32 (reg h-fb) (.sym BitBase32- offset -s19- group) newval)) 4025 ) 4026 (define-derived-operand 4027 (name (.sym bit32- offset -11-An-relative- group)) 4028 (comment "m32c bit,base:11[An] relative bit") 4029 (attrs (machine 32)) 4030 (mode BI) 4031 (args ((.sym BitBase32- offset -u11- group) (.sym Bit32An group))) 4032 (syntax (.str "${BitBase32-" offset "-u11-" group "}[$Bit32An" group "]")) 4033 (base-ifield (.sym f- base1 -12)) 4034 (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -1) 0) (.sym BitBase32- offset -u11- group) (.sym Bit32An group))) 4035 (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -1) 0))) 4036 (getter (get-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u11- group))) 4037 (setter (set-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u11- group) newval)) 4038 ) 4039 (define-derived-operand 4040 (name (.sym bit32- offset -19-An-relative- group)) 4041 (comment "m32c bit,base:19[An] relative bit") 4042 (attrs (machine 32)) 4043 (mode BI) 4044 (args ((.sym BitBase32- offset -u19- group) (.sym Bit32An group))) 4045 (syntax (.str "${BitBase32-" offset "-u19-" group "}[$Bit32An" group "]")) 4046 (base-ifield (.sym f- base1 -12)) 4047 (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -1) 0) (.sym BitBase32- offset -u19- group) (.sym Bit32An group))) 4048 (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -1) 0))) 4049 (getter (get-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u19- group))) 4050 (setter (set-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u19- group) newval)) 4051 ) 4052 (define-derived-operand 4053 (name (.sym bit32- offset -27-An-relative- group)) 4054 (comment "m32c bit,base:27[An] relative bit") 4055 (attrs (machine 32)) 4056 (mode BI) 4057 (args ((.sym BitBase32- offset -u27- group) (.sym Bit32An group))) 4058 (syntax (.str "${BitBase32-" offset "-u27-" group "}[$Bit32An" group "]")) 4059 (base-ifield (.sym f- base1 -12)) 4060 (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -1) 0) (.sym BitBase32- offset -u27- group) (.sym Bit32An group))) 4061 (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -1) 0))) 4062 (getter (get-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u27- group))) 4063 (setter (set-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u27- group) newval)) 4064 ) 4065 ) 4066) 4067 4068(bit32-relative-operand 16 Unprefixed 4 8) 4069(bit32-relative-operand 24 Prefixed 12 16) 4070 4071(define-derived-operand 4072 (name bit16-11-SB-relative-S) 4073 (comment "m16c bit,base:11[sb] relative bit") 4074 (attrs (machine 16)) 4075 (mode BI) 4076 (args (BitBase16-8-u11-S)) 4077 (syntax "${BitBase16-8-u11-S}[sb]") 4078 (base-ifield (.sym f-5-3)) 4079 (encoding (+ BitBase16-8-u11-S)) 4080; (ifield-assertion (#t)) 4081 (getter (get-memory-bit 16 (reg h-sb) BitBase16-8-u11-S)) 4082 (setter (set-memory-bit 16 (reg h-sb) BitBase16-8-u11-S newval)) 4083) 4084 4085(define-derived-operand 4086 (name Rn16-push-S-derived) 4087 (comment "m16c r0[lh] for push,pop short version") 4088 (attrs (machine 16)) 4089 (mode QI) 4090 (args (Rn16-push-S)) 4091 (syntax "${Rn16-push-S}") 4092 (base-ifield (.sym f-4-1)) 4093 (encoding (+ Rn16-push-S)) 4094; (ifield-assertion (#t)) 4095 (getter (trunc QI Rn16-push-S)) 4096 (setter (set Rn16-push-S newval)) 4097) 4098 4099(define-derived-operand 4100 (name An16-push-S-derived) 4101 (comment "m16c r0[lh] for push,pop short version") 4102 (attrs (machine 16)) 4103 (mode HI) 4104 (args (An16-push-S)) 4105 (syntax "${An16-push-S}") 4106 (base-ifield (.sym f-4-1)) 4107 (encoding (+ An16-push-S)) 4108; (ifield-assertion (#t)) 4109 (getter (trunc QI An16-push-S)) 4110 (setter (set An16-push-S newval)) 4111) 4112 4113;------------------------------------------------------------- 4114; Absolute address 4115;------------------------------------------------------------- 4116 4117(define-pmacro (bit16-absolute offset) 4118 (begin 4119 (define-derived-operand 4120 (name (.sym bit16- offset -16-absolute)) 4121 (comment "m16c absolute address") 4122 (attrs (machine 16)) 4123 (mode BI) 4124 (args ((.sym BitBase16- offset -u16))) 4125 (syntax (.str "${BitBase16-" offset "-u16}")) 4126 (base-ifield f-12-4) 4127 (encoding (+ (f-12-4 #xF) (.sym BitBase16- offset -u16))) 4128 (ifield-assertion (eq f-12-4 #xF)) 4129 (getter (get-memory-bit 16 0 (.sym BitBase16- offset -u16))) 4130 (setter (set-memory-bit 16 0 (.sym BitBase16- offset -u16) newval)) 4131 ) 4132 ) 4133) 4134 4135(bit16-absolute 16) 4136 4137(define-pmacro (bit32-absolute offset group base1 base2) 4138 (begin 4139 (define-derived-operand 4140 (name (.sym bit32- offset -19-absolute- group)) 4141 (comment "m32c absolute address bit") 4142 (attrs (machine 32)) 4143 (mode BI) 4144 (args ((.sym BitBase32- offset -u19- group))) 4145 (syntax (.str "${BitBase32-" offset "-u19-" group "}")) 4146 (base-ifield (.sym f- base1 -12)) 4147 (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 3) (.sym BitBase32- offset -u19- group))) 4148 (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 3))) 4149 (getter (get-memory-bit 32 0 (.sym BitBase32- offset -u19- group))) 4150 (setter (set-memory-bit 32 0 (.sym BitBase32- offset -u19- group) newval)) 4151 ) 4152 (define-derived-operand 4153 (name (.sym bit32- offset -27-absolute- group)) 4154 (comment "m32c absolute address bit") 4155 (attrs (machine 32)) 4156 (mode BI) 4157 (args ((.sym BitBase32- offset -u27- group))) 4158 (syntax (.str "${BitBase32-" offset "-u27-" group "}")) 4159 (base-ifield (.sym f- base1 -12)) 4160 (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 2) (.sym BitBase32- offset -u27- group))) 4161 (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 2))) 4162 (getter (get-memory-bit 32 0 (.sym BitBase32- offset -u27- group))) 4163 (setter (set-memory-bit 32 0 (.sym BitBase32- offset -u27- group) newval)) 4164 ) 4165 ) 4166) 4167 4168(bit32-absolute 16 Unprefixed 4 8) 4169(bit32-absolute 24 Prefixed 12 16) 4170 4171;------------------------------------------------------------- 4172; Destination operands for short fomat insns 4173;------------------------------------------------------------- 4174 4175(define-derived-operand 4176 (name dst16-3-S-R0l-direct-QI) 4177 (comment "m16c R0l direct QI") 4178 (attrs (machine 16)) 4179 (mode QI) 4180 (args (R0l)) 4181 (syntax "r0l") 4182 (base-ifield f-5-3) 4183 (encoding (+ (f-5-3 4))) 4184 (ifield-assertion (eq f-5-3 4)) 4185 (getter (trunc QI R0l)) 4186 (setter (set R0l newval)) 4187) 4188(define-derived-operand 4189 (name dst16-3-S-R0h-direct-QI) 4190 (comment "m16c R0h direct QI") 4191 (attrs (machine 16)) 4192 (mode QI) 4193 (args (R0h)) 4194 (syntax "r0h") 4195 (base-ifield f-5-3) 4196 (encoding (+ (f-5-3 3))) 4197 (ifield-assertion (eq f-5-3 3)) 4198 (getter (trunc QI R0h)) 4199 (setter (set R0h newval)) 4200) 4201(define-derived-operand 4202 (name dst16-3-S-8-8-SB-relative-QI) 4203 (comment "m16c SB relative QI") 4204 (attrs (machine 16)) 4205 (mode QI) 4206 (args (Dsp-8-u8)) 4207 (syntax "${Dsp-8-u8}[sb]") 4208 (base-ifield f-5-3) 4209 (encoding (+ (f-5-3 5) Dsp-8-u8)) 4210 (ifield-assertion (eq f-5-3 5)) 4211 (getter (mem16 QI (add Dsp-8-u8 (reg h-sb)))) 4212 (setter (set (mem16 QI (add Dsp-8-u8 (reg h-sb))) newval)) 4213) 4214(define-derived-operand 4215 (name dst16-3-S-8-8-FB-relative-QI) 4216 (comment "m16c FB relative QI") 4217 (attrs (machine 16)) 4218 (mode QI) 4219 (args (Dsp-8-s8)) 4220 (syntax "${Dsp-8-s8}[fb]") 4221 (base-ifield f-5-3) 4222 (encoding (+ (f-5-3 6) Dsp-8-s8)) 4223 (ifield-assertion (eq f-5-3 6)) 4224 (getter (mem16 QI (add Dsp-8-s8 (reg h-fb)))) 4225 (setter (set (mem16 QI (add Dsp-8-s8 (reg h-fb))) newval)) 4226) 4227(define-derived-operand 4228 (name dst16-3-S-8-16-absolute-QI) 4229 (comment "m16c absolute address QI") 4230 (attrs (machine 16)) 4231 (mode QI) 4232 (args (Dsp-8-u16)) 4233 (syntax "${Dsp-8-u16}") 4234 (base-ifield f-5-3) 4235 (encoding (+ (f-5-3 7) Dsp-8-u16)) 4236 (ifield-assertion (eq f-5-3 7)) 4237 (getter (mem16 QI Dsp-8-u16)) 4238 (setter (set (mem16 QI Dsp-8-u16) newval)) 4239) 4240(define-derived-operand 4241 (name dst16-3-S-16-8-SB-relative-QI) 4242 (comment "m16c SB relative QI") 4243 (attrs (machine 16)) 4244 (mode QI) 4245 (args (Dsp-16-u8)) 4246 (syntax "${Dsp-16-u8}[sb]") 4247 (base-ifield f-5-3) 4248 (encoding (+ (f-5-3 5) Dsp-16-u8)) 4249 (ifield-assertion (eq f-5-3 5)) 4250 (getter (mem16 QI (add Dsp-16-u8 (reg h-sb)))) 4251 (setter (set (mem16 QI (add Dsp-16-u8 (reg h-sb))) newval)) 4252) 4253(define-derived-operand 4254 (name dst16-3-S-16-8-FB-relative-QI) 4255 (comment "m16c FB relative QI") 4256 (attrs (machine 16)) 4257 (mode QI) 4258 (args (Dsp-16-s8)) 4259 (syntax "${Dsp-16-s8}[fb]") 4260 (base-ifield f-5-3) 4261 (encoding (+ (f-5-3 6) Dsp-16-s8)) 4262 (ifield-assertion (eq f-5-3 6)) 4263 (getter (mem16 QI (add Dsp-16-s8 (reg h-fb)))) 4264 (setter (set (mem16 QI (add Dsp-16-s8 (reg h-fb))) newval)) 4265) 4266(define-derived-operand 4267 (name dst16-3-S-16-16-absolute-QI) 4268 (comment "m16c absolute address QI") 4269 (attrs (machine 16)) 4270 (mode QI) 4271 (args (Dsp-16-u16)) 4272 (syntax "${Dsp-16-u16}") 4273 (base-ifield f-5-3) 4274 (encoding (+ (f-5-3 7) Dsp-16-u16)) 4275 (ifield-assertion (eq f-5-3 7)) 4276 (getter (mem16 QI Dsp-16-u16)) 4277 (setter (set (mem16 QI Dsp-16-u16) newval)) 4278) 4279(define-derived-operand 4280 (name srcdst16-r0l-r0h-S-derived) 4281 (comment "m16c r0l/r0h operand for short format insns") 4282 (attrs (machine 16)) 4283 (mode SI) 4284 (args (SrcDst16-r0l-r0h-S-normal)) 4285 (syntax "${SrcDst16-r0l-r0h-S-normal}") 4286 (base-ifield f-6-3) 4287 (encoding (+ (f-6-2 0) SrcDst16-r0l-r0h-S-normal)) 4288 (ifield-assertion (eq f-6-2 0)) 4289 (getter (trunc SI SrcDst16-r0l-r0h-S-normal)) 4290 (setter ()) ; no setter 4291) 4292(define-derived-operand 4293 (name dst32-2-S-R0l-direct-QI) 4294 (comment "m32c R0l direct QI") 4295 (attrs (machine 32)) 4296 (mode QI) 4297 (args (R0l)) 4298 (syntax "r0l") 4299 (base-ifield f-2-2) 4300 (encoding (+ (f-2-2 0))) 4301 (ifield-assertion (eq f-2-2 0)) 4302 (getter (trunc QI R0l)) 4303 (setter (set R0l newval)) 4304) 4305(define-derived-operand 4306 (name dst32-2-S-R0-direct-HI) 4307 (comment "m32c R0 direct HI") 4308 (attrs (machine 32)) 4309 (mode HI) 4310 (args (R0)) 4311 (syntax "r0") 4312 (base-ifield f-2-2) 4313 (encoding (+ (f-2-2 0))) 4314 (ifield-assertion (eq f-2-2 0)) 4315 (getter (trunc HI R0)) 4316 (setter (set R0 newval)) 4317) 4318(define-derived-operand 4319 (name dst32-1-S-A0-direct-HI) 4320 (comment "m32c A0 direct HI") 4321 (attrs (machine 32)) 4322 (mode HI) 4323 (args (A0)) 4324 (syntax "a0") 4325 (base-ifield f-7-1) 4326 (encoding (+ (f-7-1 0))) 4327 (ifield-assertion (eq f-7-1 0)) 4328 (getter (trunc HI A0)) 4329 (setter (set A0 newval)) 4330) 4331(define-derived-operand 4332 (name dst32-1-S-A1-direct-HI) 4333 (comment "m32c A1 direct HI") 4334 (attrs (machine 32)) 4335 (mode HI) 4336 (args (A1)) 4337 (syntax "a1") 4338 (base-ifield f-7-1) 4339 (encoding (+ (f-7-1 1))) 4340 (ifield-assertion (eq f-7-1 1)) 4341 (getter (trunc HI A1)) 4342 (setter (set A1 newval)) 4343) 4344(define-pmacro (dst32-2-S-operands xmode) 4345 (begin 4346 (define-derived-operand 4347 (name (.sym dst32-2-S-8-SB-relative- xmode)) 4348 (comment "m32c SB relative for short binary insns") 4349 (attrs (machine 32)) 4350 (mode xmode) 4351 (args (Dsp-8-u8)) 4352 (syntax "${Dsp-8-u8}[sb]") 4353 (base-ifield f-2-2) 4354 (encoding (+ (f-2-2 2) Dsp-8-u8)) 4355 (ifield-assertion (eq f-2-2 2)) 4356 (getter (c-call xmode (.str "operand_getter_" xmode) sb Dsp-8-u8)) 4357 (setter (c-call DFLT (.str "operand_setter_" xmode) newval sb Dsp-8-u8)) 4358; (getter (mem32 xmode (add Dsp-8-u8 (reg h-sb)))) 4359; (setter (set (mem32 xmode (add Dsp-8-u8 (reg h-sb))) newval)) 4360 ) 4361 (define-derived-operand 4362 (name (.sym dst32-2-S-8-FB-relative- xmode)) 4363 (comment "m32c FB relative for short binary insns") 4364 (attrs (machine 32)) 4365 (mode xmode) 4366 (args (Dsp-8-s8)) 4367 (syntax "${Dsp-8-s8}[fb]") 4368 (base-ifield f-2-2) 4369 (encoding (+ (f-2-2 3) Dsp-8-s8)) 4370 (ifield-assertion (eq f-2-2 3)) 4371 (getter (c-call xmode (.str "operand_getter_" xmode) fb Dsp-8-s8)) 4372 (setter (c-call DFLT (.str "operand_setter_" xmode) newval fb Dsp-8-s8)) 4373; (getter (mem32 xmode (add Dsp-8-s8 (reg h-fb)))) 4374; (setter (set (mem32 xmode (add Dsp-8-s8 (reg h-fb))) newval)) 4375 ) 4376 (define-derived-operand 4377 (name (.sym dst32-2-S-16-absolute- xmode)) 4378 (comment "m32c absolute address for short binary insns") 4379 (attrs (machine 32)) 4380 (mode xmode) 4381 (args (Dsp-8-u16)) 4382 (syntax "${Dsp-8-u16}") 4383 (base-ifield f-2-2) 4384 (encoding (+ (f-2-2 1) Dsp-8-u16)) 4385 (ifield-assertion (eq f-2-2 1)) 4386 (getter (c-call xmode (.str "operand_getter_" xmode) (const 0) Dsp-8-u16)) 4387 (setter (c-call DFLT (.str "operand_setter_" xmode) newval (const 0) Dsp-8-u16)) 4388; (getter (mem32 xmode Dsp-8-u16)) 4389; (setter (set (mem32 xmode Dsp-8-u16) newval)) 4390 ) 4391; (define-derived-operand 4392; (name (.sym dst32-2-S-8-SB-relative-indirect- xmode)) 4393; (comment "m32c SB relative for short binary insns") 4394; (attrs (machine 32)) 4395; (mode xmode) 4396; (args (Dsp-16-u8)) 4397; (syntax "[${Dsp-16-u8}[sb]]") 4398; (base-ifield f-10-2) 4399; (encoding (+ (f-10-2 2) Dsp-16-u8)) 4400; (ifield-assertion (eq f-10-2 2)) 4401; (getter (mem32 xmode (indirect-addr (add Dsp-16-u8 (reg h-sb))))) 4402; (setter (set (mem32 xmode (indirect-addr (add Dsp-16-u8 (reg h-sb)))) newval)) 4403; ) 4404; (define-derived-operand 4405; (name (.sym dst32-2-S-8-FB-relative-indirect- xmode)) 4406; (comment "m32c FB relative for short binary insns") 4407; (attrs (machine 32)) 4408; (mode xmode) 4409; (args (Dsp-16-s8)) 4410; (syntax "[${Dsp-16-s8}[fb]]") 4411; (base-ifield f-10-2) 4412; (encoding (+ (f-10-2 3) Dsp-16-s8)) 4413; (ifield-assertion (eq f-10-2 3)) 4414; (getter (mem32 xmode (indirect-addr (add Dsp-16-s8 (reg h-fb))))) 4415; (setter (set (mem32 xmode (indirect-addr (add Dsp-16-s8 (reg h-fb)))) newval)) 4416; ) 4417; (define-derived-operand 4418; (name (.sym dst32-2-S-16-absolute-indirect- xmode)) 4419; (comment "m32c absolute address for short binary insns") 4420; (attrs (machine 32)) 4421; (mode xmode) 4422; (args (Dsp-16-u16)) 4423; (syntax "[${Dsp-16-u16}]") 4424; (base-ifield f-10-2) 4425; (encoding (+ (f-10-2 1) Dsp-16-u16)) 4426; (ifield-assertion (eq f-10-2 1)) 4427; (getter (mem32 xmode (indirect-addr Dsp-16-u16))) 4428; (setter (set (mem32 xmode (indirect-addr Dsp-16-u16)) newval)) 4429; ) 4430 ) 4431) 4432 4433(dst32-2-S-operands QI) 4434(dst32-2-S-operands HI) 4435(dst32-2-S-operands SI) 4436 4437;============================================================= 4438; Anyof operands 4439;------------------------------------------------------------- 4440; Source operands with no additional fields 4441;------------------------------------------------------------- 4442 4443(define-pmacro (src16-basic-operand xmode) 4444 (begin 4445 (define-anyof-operand 4446 (name (.sym src16-basic- xmode)) 4447 (comment (.str "m16c source operand of size " xmode " with no additional fields")) 4448 (attrs (machine 16)) 4449 (mode xmode) 4450 (choices 4451 (.sym src16-Rn-direct- xmode) 4452 (.sym src16-An-direct- xmode) 4453 (.sym src16-An-indirect- xmode) 4454 ) 4455 ) 4456 ) 4457) 4458(src16-basic-operand QI) 4459(src16-basic-operand HI) 4460 4461(define-pmacro (src32-basic-operand xmode) 4462 (begin 4463 (define-anyof-operand 4464 (name (.sym src32-basic-Unprefixed- xmode)) 4465 (comment (.str "m32c destination operand of size " xmode " with no additional fields")) 4466 (attrs (machine 32)) 4467 (mode xmode) 4468 (choices 4469 (.sym src32-Rn-direct-Unprefixed- xmode) 4470 (.sym src32-An-direct-Unprefixed- xmode) 4471 (.sym src32-An-indirect-Unprefixed- xmode) 4472 ) 4473 ) 4474 (define-anyof-operand 4475 (name (.sym src32-basic-Prefixed- xmode)) 4476 (comment (.str "m32c destination operand of size " xmode " with no additional fields")) 4477 (attrs (machine 32)) 4478 (mode xmode) 4479 (choices 4480 (.sym src32-Rn-direct-Prefixed- xmode) 4481 (.sym src32-An-direct-Prefixed- xmode) 4482 (.sym src32-An-indirect-Prefixed- xmode) 4483 ) 4484 ) 4485; (define-anyof-operand 4486; (name (.sym src32-basic-indirect- xmode)) 4487; (comment (.str "m32c destination operand of size " xmode " indirect with no additional fields")) 4488; (attrs (machine 32)) 4489; (mode xmode) 4490; (choices 4491; (.sym src32-An-indirect-indirect- xmode) 4492; ) 4493; ) 4494 ) 4495) 4496 4497(src32-basic-operand QI) 4498(src32-basic-operand HI) 4499(src32-basic-operand SI) 4500 4501(define-anyof-operand 4502 (name src32-basic-ExtPrefixed-QI) 4503 (comment "m32c source operand of size QI with no additional fields") 4504 (attrs (machine 32)) 4505 (mode QI) 4506 (choices 4507 src32-Rn-direct-Prefixed-QI 4508 src32-An-indirect-Prefixed-QI 4509 ) 4510) 4511 4512;------------------------------------------------------------- 4513; Source operands with additional fields at offset 16 bits 4514;------------------------------------------------------------- 4515 4516(define-pmacro (src16-16-operand xmode) 4517 (begin 4518 (define-anyof-operand 4519 (name (.sym src16-16-8- xmode)) 4520 (comment (.str "m16c source operand of size " xmode " with additional 8 bit fields at offset 16")) 4521 (attrs (machine 16)) 4522 (mode xmode) 4523 (choices 4524 (.sym src16-16-8-An-relative- xmode) 4525 (.sym src16-16-8-SB-relative- xmode) 4526 (.sym src16-16-8-FB-relative- xmode) 4527 ) 4528 ) 4529 (define-anyof-operand 4530 (name (.sym src16-16-16- xmode)) 4531 (comment (.str "m16c source operand of size " xmode " with additional 16 bit fields at offset 16")) 4532 (attrs (machine 16)) 4533 (mode xmode) 4534 (choices 4535 (.sym src16-16-16-An-relative- xmode) 4536 (.sym src16-16-16-SB-relative- xmode) 4537 (.sym src16-16-16-absolute- xmode) 4538 ) 4539 ) 4540 ) 4541) 4542(src16-16-operand QI) 4543(src16-16-operand HI) 4544 4545(define-pmacro (src32-16-operand xmode) 4546 (begin 4547 (define-anyof-operand 4548 (name (.sym src32-16-8-Unprefixed- xmode)) 4549 (comment (.str "m32c source operand of size " xmode " with additional 8 bit fields at offset 16")) 4550 (attrs (machine 32)) 4551 (mode xmode) 4552 (choices 4553 (.sym src32-16-8-An-relative-Unprefixed- xmode) 4554 (.sym src32-16-8-SB-relative-Unprefixed- xmode) 4555 (.sym src32-16-8-FB-relative-Unprefixed- xmode) 4556 ) 4557 ) 4558 (define-anyof-operand 4559 (name (.sym src32-16-16-Unprefixed- xmode)) 4560 (comment (.str "m32c source operand of size " xmode " with additional 16 bit fields at offset 16")) 4561 (attrs (machine 32)) 4562 (mode xmode) 4563 (choices 4564 (.sym src32-16-16-An-relative-Unprefixed- xmode) 4565 (.sym src32-16-16-SB-relative-Unprefixed- xmode) 4566 (.sym src32-16-16-FB-relative-Unprefixed- xmode) 4567 (.sym src32-16-16-absolute-Unprefixed- xmode) 4568 ) 4569 ) 4570 (define-anyof-operand 4571 (name (.sym src32-16-24-Unprefixed- xmode)) 4572 (comment (.str "m32c source operand of size " xmode " with additional 24 bit fields at offset 16")) 4573 (attrs (machine 32)) 4574 (mode xmode) 4575 (choices 4576 (.sym src32-16-24-An-relative-Unprefixed- xmode) 4577 (.sym src32-16-24-absolute-Unprefixed- xmode) 4578 ) 4579 ) 4580 ) 4581) 4582 4583(src32-16-operand QI) 4584(src32-16-operand HI) 4585(src32-16-operand SI) 4586 4587;------------------------------------------------------------- 4588; Source operands with additional fields at offset 24 bits 4589;------------------------------------------------------------- 4590 4591(define-pmacro (src-24-operand group xmode) 4592 (begin 4593 (define-anyof-operand 4594 (name (.sym src32-24-8- group - xmode)) 4595 (comment (.str "m32c source operand of size " xmode " with additional 8 bit fields at offset 24")) 4596 (attrs (machine 32)) 4597 (mode xmode) 4598 (choices 4599 (.sym src32-24-8-An-relative- group - xmode) 4600 (.sym src32-24-8-SB-relative- group - xmode) 4601 (.sym src32-24-8-FB-relative- group - xmode) 4602 ) 4603 ) 4604 (define-anyof-operand 4605 (name (.sym src32-24-16- group - xmode)) 4606 (comment (.str "m32c source operand of size " xmode " with additional 16 bit fields at offset 16")) 4607 (attrs (machine 32)) 4608 (mode xmode) 4609 (choices 4610 (.sym src32-24-16-An-relative- group - xmode) 4611 (.sym src32-24-16-SB-relative- group - xmode) 4612 (.sym src32-24-16-FB-relative- group - xmode) 4613 (.sym src32-24-16-absolute- group - xmode) 4614 ) 4615 ) 4616 (define-anyof-operand 4617 (name (.sym src32-24-24- group - xmode)) 4618 (comment (.str "m32c source operand of size " xmode " with additional 24 bit fields at offset 16")) 4619 (attrs (machine 32)) 4620 (mode xmode) 4621 (choices 4622 (.sym src32-24-24-An-relative- group - xmode) 4623 (.sym src32-24-24-absolute- group - xmode) 4624 ) 4625 ) 4626 ) 4627) 4628 4629(src-24-operand Prefixed QI) 4630(src-24-operand Prefixed HI) 4631(src-24-operand Prefixed SI) 4632 4633(define-pmacro (src-24-indirect-operand xmode) 4634 (begin 4635; (define-anyof-operand 4636; (name (.sym src32-24-8-indirect- xmode)) 4637; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) 4638; (attrs (machine 32)) 4639; (mode xmode) 4640; (choices 4641; (.sym src32-24-8-An-relative-indirect- xmode) 4642; (.sym src32-24-8-SB-relative-indirect- xmode) 4643; (.sym src32-24-8-FB-relative-indirect- xmode) 4644; ) 4645; ) 4646; (define-anyof-operand 4647; (name (.sym src32-24-16-indirect- xmode)) 4648; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) 4649; (attrs (machine 32)) 4650; (mode xmode) 4651; (choices 4652; (.sym src32-24-16-An-relative-indirect- xmode) 4653; (.sym src32-24-16-SB-relative-indirect- xmode) 4654; (.sym src32-24-16-FB-relative-indirect- xmode) 4655; ) 4656; ) 4657; (define-anyof-operand 4658; (name (.sym src32-24-24-indirect- xmode)) 4659; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) 4660; (attrs (machine 32)) 4661; (mode xmode) 4662; (choices 4663; (.sym src32-24-24-An-relative-indirect- xmode) 4664; ) 4665; ) 4666; (define-anyof-operand 4667; (name (.sym src32-24-16-absolute-indirect- xmode)) 4668; (comment (.str "m32c source operand of size " xmode " 16 bit absolute indirect")) 4669; (attrs (machine 32)) 4670; (mode xmode) 4671; (choices 4672; (.sym src32-24-16-absolute-indirect-derived- xmode) 4673; ) 4674; ) 4675; (define-anyof-operand 4676; (name (.sym src32-24-24-absolute-indirect- xmode)) 4677; (comment (.str "m32c source operand of size " xmode " 24 bit absolute indirect")) 4678; (attrs (machine 32)) 4679; (mode xmode) 4680; (choices 4681; (.sym src32-24-24-absolute-indirect-derived- xmode) 4682; ) 4683; ) 4684 ) 4685) 4686 4687; (src-24-indirect-operand QI) 4688; (src-24-indirect-operand HI) 4689; (src-24-indirect-operand SI) 4690 4691;------------------------------------------------------------- 4692; Destination operands with no additional fields 4693;------------------------------------------------------------- 4694 4695(define-pmacro (dst16-basic-operand xmode) 4696 (begin 4697 (define-anyof-operand 4698 (name (.sym dst16-basic- xmode)) 4699 (comment (.str "m16c destination operand of size " xmode " with no additional fields")) 4700 (attrs (machine 16)) 4701 (mode xmode) 4702 (choices 4703 (.sym dst16-Rn-direct- xmode) 4704 (.sym dst16-An-direct- xmode) 4705 (.sym dst16-An-indirect- xmode) 4706 ) 4707 ) 4708 ) 4709) 4710 4711(dst16-basic-operand QI) 4712(dst16-basic-operand HI) 4713(dst16-basic-operand SI) 4714 4715(define-pmacro (dst32-basic-operand xmode) 4716 (begin 4717 (define-anyof-operand 4718 (name (.sym dst32-basic-Unprefixed- xmode)) 4719 (comment (.str "m32c destination operand of size " xmode " with no additional fields")) 4720 (attrs (machine 32)) 4721 (mode xmode) 4722 (choices 4723 (.sym dst32-Rn-direct-Unprefixed- xmode) 4724 (.sym dst32-An-direct-Unprefixed- xmode) 4725 (.sym dst32-An-indirect-Unprefixed- xmode) 4726 ) 4727 ) 4728 (define-anyof-operand 4729 (name (.sym dst32-basic-Prefixed- xmode)) 4730 (comment (.str "m32c destination operand of size " xmode " with no additional fields")) 4731 (attrs (machine 32)) 4732 (mode xmode) 4733 (choices 4734 (.sym dst32-Rn-direct-Prefixed- xmode) 4735 (.sym dst32-An-direct-Prefixed- xmode) 4736 (.sym dst32-An-indirect-Prefixed- xmode) 4737 ) 4738 ) 4739 ) 4740) 4741 4742(dst32-basic-operand QI) 4743(dst32-basic-operand HI) 4744(dst32-basic-operand SI) 4745 4746;------------------------------------------------------------- 4747; Destination operands with possible additional fields at offset 16 bits 4748;------------------------------------------------------------- 4749 4750(define-pmacro (dst16-16-operand xmode) 4751 (begin 4752 (define-anyof-operand 4753 (name (.sym dst16-16- xmode)) 4754 (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16")) 4755 (attrs (machine 16)) 4756 (mode xmode) 4757 (choices 4758 (.sym dst16-Rn-direct- xmode) 4759 (.sym dst16-An-direct- xmode) 4760 (.sym dst16-An-indirect- xmode) 4761 (.sym dst16-16-8-An-relative- xmode) 4762 (.sym dst16-16-16-An-relative- xmode) 4763 (.sym dst16-16-8-SB-relative- xmode) 4764 (.sym dst16-16-16-SB-relative- xmode) 4765 (.sym dst16-16-8-FB-relative- xmode) 4766 (.sym dst16-16-16-absolute- xmode) 4767 ) 4768 ) 4769 (define-anyof-operand 4770 (name (.sym dst16-16-8- xmode)) 4771 (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16")) 4772 (attrs (machine 16)) 4773 (mode xmode) 4774 (choices 4775 (.sym dst16-16-8-An-relative- xmode) 4776 (.sym dst16-16-8-SB-relative- xmode) 4777 (.sym dst16-16-8-FB-relative- xmode) 4778 ) 4779 ) 4780 (define-anyof-operand 4781 (name (.sym dst16-16-16- xmode)) 4782 (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16")) 4783 (attrs (machine 16)) 4784 (mode xmode) 4785 (choices 4786 (.sym dst16-16-16-An-relative- xmode) 4787 (.sym dst16-16-16-SB-relative- xmode) 4788 (.sym dst16-16-16-absolute- xmode) 4789 ) 4790 ) 4791 (define-anyof-operand 4792 (name (.sym dst16-16-16sa- xmode)) 4793 (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16")) 4794 (attrs (machine 16)) 4795 (mode xmode) 4796 (choices 4797 (.sym dst16-16-16-SB-relative- xmode) 4798 (.sym dst16-16-16-absolute- xmode) 4799 ) 4800 ) 4801 (define-anyof-operand 4802 (name (.sym dst16-16-20ar- xmode)) 4803 (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16")) 4804 (attrs (machine 16)) 4805 (mode xmode) 4806 (choices 4807 (.sym dst16-16-20-An-relative- xmode) 4808 ) 4809 ) 4810 ) 4811) 4812 4813(dst16-16-operand QI) 4814(dst16-16-operand HI) 4815(dst16-16-operand SI) 4816 4817(define-anyof-operand 4818 (name dst16-16-Ext-QI) 4819 (comment "m16c destination operand of size QI for 'ext' insns with additional fields at offset 16") 4820 (attrs (machine 16)) 4821 (mode QI) 4822 (choices 4823 dst16-Rn-direct-Ext-QI 4824 dst16-An-indirect-Ext-QI 4825 dst16-16-8-An-relative-Ext-QI 4826 dst16-16-16-An-relative-Ext-QI 4827 dst16-16-8-SB-relative-Ext-QI 4828 dst16-16-16-SB-relative-Ext-QI 4829 dst16-16-8-FB-relative-Ext-QI 4830 dst16-16-16-absolute-Ext-QI 4831 ) 4832) 4833 4834(define-derived-operand 4835 (name dst16-An-indirect-Mova-HI) 4836 (comment "m16c addressof An indirect destination HI") 4837 (attrs (ISA m16c)) 4838 (mode HI) 4839 (args (Dst16An)) 4840 (syntax "[$Dst16An]") 4841 (base-ifield f-12-4) 4842 (encoding (+ (f-12-2 1) (f-14-1 1) Dst16An)) 4843 (ifield-assertion 4844 (andif (eq f-12-2 1) (eq f-14-1 1))) 4845 (getter Dst16An) 4846 (setter (nop)) 4847 ) 4848 4849(define-derived-operand 4850 (name dst16-16-8-An-relative-Mova-HI) 4851 (comment 4852 "m16c addressof dsp:8[An] relative destination HI") 4853 (attrs (ISA m16c)) 4854 (mode HI) 4855 (args (Dst16An Dsp-16-u8)) 4856 (syntax "${Dsp-16-u8}[$Dst16An]") 4857 (base-ifield f-12-4) 4858 (encoding 4859 (+ (f-12-2 2) (f-14-1 0) Dsp-16-u8 Dst16An)) 4860 (ifield-assertion 4861 (andif (eq f-12-2 2) (eq f-14-1 0))) 4862 (getter (add Dsp-16-u8 Dst16An)) 4863 (setter (nop)) 4864) 4865(define-derived-operand 4866 (name dst16-16-16-An-relative-Mova-HI) 4867 (comment 4868 "m16c addressof dsp:16[An] relative destination HI") 4869 (attrs (ISA m16c)) 4870 (mode HI) 4871 (args (Dst16An Dsp-16-u16)) 4872 (syntax "${Dsp-16-u16}[$Dst16An]") 4873 (base-ifield f-12-4) 4874 (encoding 4875 (+ (f-12-2 3) (f-14-1 0) Dsp-16-u16 Dst16An)) 4876 (ifield-assertion 4877 (andif (eq f-12-2 3) (eq f-14-1 0))) 4878 (getter (add Dsp-16-u16 Dst16An)) 4879 (setter (nop)) 4880 ) 4881(define-derived-operand 4882 (name dst16-16-8-SB-relative-Mova-HI) 4883 (comment 4884 "m16c addressof dsp:8[sb] relative destination HI") 4885 (attrs (ISA m16c)) 4886 (mode HI) 4887 (args (Dsp-16-u8)) 4888 (syntax "${Dsp-16-u8}[sb]") 4889 (base-ifield f-12-4) 4890 (encoding (+ (f-12-4 10) Dsp-16-u8)) 4891 (ifield-assertion (eq f-12-4 10)) 4892 (getter (add Dsp-16-u8 (reg h-sb))) 4893 (setter (nop)) 4894) 4895(define-derived-operand 4896 (name dst16-16-16-SB-relative-Mova-HI) 4897 (comment 4898 "m16c addressof dsp:16[sb] relative destination HI") 4899 (attrs (ISA m16c)) 4900 (mode HI) 4901 (args (Dsp-16-u16)) 4902 (syntax "${Dsp-16-u16}[sb]") 4903 (base-ifield f-12-4) 4904 (encoding (+ (f-12-4 14) Dsp-16-u16)) 4905 (ifield-assertion (eq f-12-4 14)) 4906 (getter (add Dsp-16-u16 (reg h-sb))) 4907 (setter (nop)) 4908 ) 4909(define-derived-operand 4910 (name dst16-16-8-FB-relative-Mova-HI) 4911 (comment 4912 "m16c addressof dsp:8[fb] relative destination HI") 4913 (attrs (ISA m16c)) 4914 (mode HI) 4915 (args (Dsp-16-s8)) 4916 (syntax "${Dsp-16-s8}[fb]") 4917 (base-ifield f-12-4) 4918 (encoding (+ (f-12-4 11) Dsp-16-s8)) 4919 (ifield-assertion (eq f-12-4 11)) 4920 (getter (add Dsp-16-s8 (reg h-fb))) 4921 (setter (nop)) 4922 ) 4923(define-derived-operand 4924 (name dst16-16-16-absolute-Mova-HI) 4925 (comment "m16c addressof absolute address HI") 4926 (attrs (ISA m16c)) 4927 (mode HI) 4928 (args (Dsp-16-u16)) 4929 (syntax "${Dsp-16-u16}") 4930 (base-ifield f-12-4) 4931 (encoding (+ (f-12-4 15) Dsp-16-u16)) 4932 (ifield-assertion (eq f-12-4 15)) 4933 (getter Dsp-16-u16) 4934 (setter (nop)) 4935 ) 4936 4937(define-anyof-operand 4938 (name dst16-16-Mova-HI) 4939 (comment "m16c addressof destination operand of size HI with additional fields at offset 16") 4940 (attrs (machine 16)) 4941 (mode HI) 4942 (choices 4943 dst16-An-indirect-Mova-HI 4944 dst16-16-8-An-relative-Mova-HI 4945 dst16-16-16-An-relative-Mova-HI 4946 dst16-16-8-SB-relative-Mova-HI 4947 dst16-16-16-SB-relative-Mova-HI 4948 dst16-16-8-FB-relative-Mova-HI 4949 dst16-16-16-absolute-Mova-HI 4950 ) 4951) 4952 4953(define-derived-operand 4954 (name dst32-An-indirect-Unprefixed-Mova-SI) 4955 (comment "m32c addressof An indirect destination SI") 4956 (attrs (ISA m32c)) 4957 (mode SI) 4958 (args (Dst32AnUnprefixed)) 4959 (syntax "[$Dst32AnUnprefixed]") 4960 (base-ifield f-4-6) 4961 (encoding 4962 (+ (f-4-3 0) (f-8-1 0) Dst32AnUnprefixed)) 4963 (ifield-assertion 4964 (andif (eq f-4-3 0) (eq f-8-1 0))) 4965 (getter Dst32AnUnprefixed) 4966 (setter (nop)) 4967 ) 4968 4969(define-derived-operand 4970 (name dst32-16-8-An-relative-Unprefixed-Mova-SI) 4971 (comment "m32c addressof dsp:8[An] relative destination SI") 4972 (attrs (ISA m32c)) 4973 (mode SI) 4974 (args (Dst32AnUnprefixed Dsp-16-u8)) 4975 (syntax "${Dsp-16-u8}[$Dst32AnUnprefixed]") 4976 (base-ifield f-4-6) 4977 (encoding 4978 (+ (f-4-3 1) 4979 (f-8-1 0) 4980 Dsp-16-u8 4981 Dst32AnUnprefixed)) 4982 (ifield-assertion 4983 (andif (eq f-4-3 1) (eq f-8-1 0))) 4984 (getter (add Dsp-16-u8 Dst32AnUnprefixed)) 4985 (setter (nop)) 4986) 4987 4988(define-derived-operand 4989 (name dst32-16-16-An-relative-Unprefixed-Mova-SI) 4990 (comment 4991 "m32c addressof dsp:16[An] relative destination SI") 4992 (attrs (ISA m32c)) 4993 (mode SI) 4994 (args (Dst32AnUnprefixed Dsp-16-u16)) 4995 (syntax "${Dsp-16-u16}[$Dst32AnUnprefixed]") 4996 (base-ifield f-4-6) 4997 (encoding 4998 (+ (f-4-3 2) 4999 (f-8-1 0) 5000 Dsp-16-u16 5001 Dst32AnUnprefixed)) 5002 (ifield-assertion 5003 (andif (eq f-4-3 2) (eq f-8-1 0))) 5004 (getter (add Dsp-16-u16 Dst32AnUnprefixed)) 5005 (setter (nop)) 5006 ) 5007 5008(define-derived-operand 5009 (name dst32-16-24-An-relative-Unprefixed-Mova-SI) 5010 (comment "addressof m32c dsp:16[An] relative destination SI") 5011 (attrs (ISA m32c)) 5012 (mode SI) 5013 (args (Dst32AnUnprefixed Dsp-16-u24)) 5014 (syntax "${Dsp-16-u24}[$Dst32AnUnprefixed]") 5015 (base-ifield f-4-6) 5016 (encoding 5017 (+ (f-4-3 3) 5018 (f-8-1 0) 5019 Dsp-16-u24 5020 Dst32AnUnprefixed)) 5021 (ifield-assertion 5022 (andif (eq f-4-3 3) (eq f-8-1 0))) 5023 (getter (add Dsp-16-u24 Dst32AnUnprefixed)) 5024 (setter (nop)) 5025 ) 5026 5027(define-derived-operand 5028 (name dst32-16-8-SB-relative-Unprefixed-Mova-SI) 5029 (comment "m32c addressof dsp:8[sb] relative destination SI") 5030 (attrs (ISA m32c)) 5031 (mode SI) 5032 (args (Dsp-16-u8)) 5033 (syntax "${Dsp-16-u8}[sb]") 5034 (base-ifield f-4-6) 5035 (encoding (+ (f-4-3 1) (f-8-2 2) Dsp-16-u8)) 5036 (ifield-assertion 5037 (andif (eq f-4-3 1) (eq f-8-2 2))) 5038 (getter (add Dsp-16-u8 (reg h-sb))) 5039 (setter (nop)) 5040 ) 5041 5042(define-derived-operand 5043 (name dst32-16-16-SB-relative-Unprefixed-Mova-SI) 5044 (comment "m32c addressof dsp:16[sb] relative destination SI") 5045 (attrs (ISA m32c)) 5046 (mode SI) 5047 (args (Dsp-16-u16)) 5048 (syntax "${Dsp-16-u16}[sb]") 5049 (base-ifield f-4-6) 5050 (encoding (+ (f-4-3 2) (f-8-2 2) Dsp-16-u16)) 5051 (ifield-assertion 5052 (andif (eq f-4-3 2) (eq f-8-2 2))) 5053 (getter (add Dsp-16-u16 (reg h-sb))) 5054 (setter (nop)) 5055 ) 5056 5057(define-derived-operand 5058 (name dst32-16-8-FB-relative-Unprefixed-Mova-SI) 5059 (comment "m32c addressof dsp:8[fb] relative destination SI") 5060 (attrs (ISA m32c)) 5061 (mode SI) 5062 (args (Dsp-16-s8)) 5063 (syntax "${Dsp-16-s8}[fb]") 5064 (base-ifield f-4-6) 5065 (encoding (+ (f-4-3 1) (f-8-2 3) Dsp-16-s8)) 5066 (ifield-assertion 5067 (andif (eq f-4-3 1) (eq f-8-2 3))) 5068 (getter (add Dsp-16-s8 (reg h-fb))) 5069 (setter (nop)) 5070 ) 5071 5072(define-derived-operand 5073 (name dst32-16-16-FB-relative-Unprefixed-Mova-SI) 5074 (comment "m32c addressof dsp:16[fb] relative destination SI") 5075 (attrs (ISA m32c)) 5076 (mode SI) 5077 (args (Dsp-16-s16)) 5078 (syntax "${Dsp-16-s16}[fb]") 5079 (base-ifield f-4-6) 5080 (encoding (+ (f-4-3 2) (f-8-2 3) Dsp-16-s16)) 5081 (ifield-assertion 5082 (andif (eq f-4-3 2) (eq f-8-2 3))) 5083 (getter (add Dsp-16-s16 (reg h-fb))) 5084 (setter (nop)) 5085 ) 5086 5087(define-derived-operand 5088 (name dst32-16-16-absolute-Unprefixed-Mova-SI) 5089 (comment "m32c addressof absolute address SI") (attrs (ISA m32c)) 5090 (mode SI) 5091 (args (Dsp-16-u16)) 5092 (syntax "${Dsp-16-u16}") 5093 (base-ifield f-4-6) 5094 (encoding (+ (f-4-3 3) (f-8-2 3) Dsp-16-u16)) 5095 (ifield-assertion 5096 (andif (eq f-4-3 3) (eq f-8-2 3))) 5097 (getter Dsp-16-u16) 5098 (setter (nop)) 5099 ) 5100 5101(define-derived-operand 5102 (name dst32-16-24-absolute-Unprefixed-Mova-SI) 5103 (comment "m32c addressof absolute address SI") (attrs (ISA m32c)) 5104 (mode SI) 5105 (args (Dsp-16-u24)) 5106 (syntax "${Dsp-16-u24}") 5107 (base-ifield f-4-6) 5108 (encoding (+ (f-4-3 3) (f-8-2 2) Dsp-16-u24)) 5109 (ifield-assertion 5110 (andif (eq f-4-3 3) (eq f-8-2 2))) 5111 (getter Dsp-16-u24) 5112 (setter (nop)) 5113 ) 5114 5115(define-anyof-operand 5116 (name dst32-16-Unprefixed-Mova-SI) 5117 (comment 5118 "m32c addressof destination operand of size SI with additional fields at offset 16") 5119 (attrs (ISA m32c)) 5120 (mode SI) 5121 (choices 5122 dst32-An-indirect-Unprefixed-Mova-SI 5123 dst32-16-8-An-relative-Unprefixed-Mova-SI 5124 dst32-16-16-An-relative-Unprefixed-Mova-SI 5125 dst32-16-24-An-relative-Unprefixed-Mova-SI 5126 dst32-16-8-SB-relative-Unprefixed-Mova-SI 5127 dst32-16-16-SB-relative-Unprefixed-Mova-SI 5128 dst32-16-8-FB-relative-Unprefixed-Mova-SI 5129 dst32-16-16-FB-relative-Unprefixed-Mova-SI 5130 dst32-16-16-absolute-Unprefixed-Mova-SI 5131 dst32-16-24-absolute-Unprefixed-Mova-SI)) 5132 5133(define-pmacro (dst32-16-operand xmode) 5134 (begin 5135 (define-anyof-operand 5136 (name (.sym dst32-16-Unprefixed- xmode)) 5137 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16")) 5138 (attrs (machine 32)) 5139 (mode xmode) 5140 (choices 5141 (.sym dst32-Rn-direct-Unprefixed- xmode) 5142 (.sym dst32-An-direct-Unprefixed- xmode) 5143 (.sym dst32-An-indirect-Unprefixed- xmode) 5144 (.sym dst32-16-8-An-relative-Unprefixed- xmode) 5145 (.sym dst32-16-16-An-relative-Unprefixed- xmode) 5146 (.sym dst32-16-24-An-relative-Unprefixed- xmode) 5147 (.sym dst32-16-8-SB-relative-Unprefixed- xmode) 5148 (.sym dst32-16-16-SB-relative-Unprefixed- xmode) 5149 (.sym dst32-16-8-FB-relative-Unprefixed- xmode) 5150 (.sym dst32-16-16-FB-relative-Unprefixed- xmode) 5151 (.sym dst32-16-16-absolute-Unprefixed- xmode) 5152 (.sym dst32-16-24-absolute-Unprefixed- xmode) 5153 ) 5154 ) 5155 (define-anyof-operand 5156 (name (.sym dst32-16-8-Unprefixed- xmode)) 5157 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16")) 5158 (attrs (machine 32)) 5159 (mode xmode) 5160 (choices 5161 (.sym dst32-16-8-An-relative-Unprefixed- xmode) 5162 (.sym dst32-16-8-SB-relative-Unprefixed- xmode) 5163 (.sym dst32-16-8-FB-relative-Unprefixed- xmode) 5164 ) 5165 ) 5166 (define-anyof-operand 5167 (name (.sym dst32-16-16-Unprefixed- xmode)) 5168 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16")) 5169 (attrs (machine 32)) 5170 (mode xmode) 5171 (choices 5172 (.sym dst32-16-16-An-relative-Unprefixed- xmode) 5173 (.sym dst32-16-16-SB-relative-Unprefixed- xmode) 5174 (.sym dst32-16-16-FB-relative-Unprefixed- xmode) 5175 (.sym dst32-16-16-absolute-Unprefixed- xmode) 5176 ) 5177 ) 5178 (define-anyof-operand 5179 (name (.sym dst32-16-16sa-Unprefixed- xmode)) 5180 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16")) 5181 (attrs (machine 32)) 5182 (mode xmode) 5183 (choices 5184 (.sym dst32-16-16-SB-relative-Unprefixed- xmode) 5185 (.sym dst32-16-16-FB-relative-Unprefixed- xmode) 5186 (.sym dst32-16-16-absolute-Unprefixed- xmode) 5187 ) 5188 ) 5189 (define-anyof-operand 5190 (name (.sym dst32-16-24-Unprefixed- xmode)) 5191 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16")) 5192 (attrs (machine 32)) 5193 (mode xmode) 5194 (choices 5195 (.sym dst32-16-24-An-relative-Unprefixed- xmode) 5196 (.sym dst32-16-24-absolute-Unprefixed- xmode) 5197 ) 5198 ) 5199 ) 5200) 5201 5202(dst32-16-operand QI) 5203(dst32-16-operand HI) 5204(dst32-16-operand SI) 5205 5206(define-pmacro (dst32-16-Ext-operand smode dmode) 5207 (begin 5208 (define-anyof-operand 5209 (name (.sym dst32-16-ExtUnprefixed- smode)) 5210 (comment (.str "m32c destination operand of size " smode " with additional fields at offset 16")) 5211 (attrs (machine 32)) 5212 (mode dmode) 5213 (choices 5214 (.sym dst32-Rn-direct-ExtUnprefixed- smode) 5215 (.sym dst32-An-direct-Unprefixed- dmode) ; ExtUnprefixed mode not required for this operand -- use the normal dmode version 5216 (.sym dst32-An-indirect-ExtUnprefixed- smode) 5217 (.sym dst32-16-8-An-relative-ExtUnprefixed- smode) 5218 (.sym dst32-16-16-An-relative-ExtUnprefixed- smode) 5219 (.sym dst32-16-24-An-relative-ExtUnprefixed- smode) 5220 (.sym dst32-16-8-SB-relative-ExtUnprefixed- smode) 5221 (.sym dst32-16-16-SB-relative-ExtUnprefixed- smode) 5222 (.sym dst32-16-8-FB-relative-ExtUnprefixed- smode) 5223 (.sym dst32-16-16-FB-relative-ExtUnprefixed- smode) 5224 (.sym dst32-16-16-absolute-ExtUnprefixed- smode) 5225 (.sym dst32-16-24-absolute-ExtUnprefixed- smode) 5226 ) 5227 ) 5228 ) 5229) 5230 5231(dst32-16-Ext-operand QI HI) 5232(dst32-16-Ext-operand HI SI) 5233 5234(define-anyof-operand 5235 (name dst32-16-Unprefixed-Mulex-HI) 5236 (comment "m32c destination operand of size HI with additional fields at offset 16") 5237 (attrs (machine 32)) 5238 (mode HI) 5239 (choices 5240 dst32-R3-direct-Unprefixed-HI 5241 dst32-An-direct-Unprefixed-HI 5242 dst32-An-indirect-Unprefixed-HI 5243 dst32-16-8-An-relative-Unprefixed-HI 5244 dst32-16-16-An-relative-Unprefixed-HI 5245 dst32-16-24-An-relative-Unprefixed-HI 5246 dst32-16-8-SB-relative-Unprefixed-HI 5247 dst32-16-16-SB-relative-Unprefixed-HI 5248 dst32-16-8-FB-relative-Unprefixed-HI 5249 dst32-16-16-FB-relative-Unprefixed-HI 5250 dst32-16-16-absolute-Unprefixed-HI 5251 dst32-16-24-absolute-Unprefixed-HI 5252 ) 5253) 5254;------------------------------------------------------------- 5255; Destination operands with possible additional fields at offset 24 bits 5256;------------------------------------------------------------- 5257 5258(define-pmacro (dst16-24-operand xmode) 5259 (begin 5260 (define-anyof-operand 5261 (name (.sym dst16-24- xmode)) 5262 (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 24")) 5263 (attrs (machine 16)) 5264 (mode xmode) 5265 (choices 5266 (.sym dst16-Rn-direct- xmode) 5267 (.sym dst16-An-direct- xmode) 5268 (.sym dst16-An-indirect- xmode) 5269 (.sym dst16-24-8-An-relative- xmode) 5270 (.sym dst16-24-16-An-relative- xmode) 5271 (.sym dst16-24-8-SB-relative- xmode) 5272 (.sym dst16-24-16-SB-relative- xmode) 5273 (.sym dst16-24-8-FB-relative- xmode) 5274 (.sym dst16-24-16-absolute- xmode) 5275 ) 5276 ) 5277 ) 5278) 5279 5280(dst16-24-operand QI) 5281(dst16-24-operand HI) 5282 5283(define-pmacro (dst32-24-operand xmode) 5284 (begin 5285 (define-anyof-operand 5286 (name (.sym dst32-24-Unprefixed- xmode)) 5287 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) 5288 (attrs (machine 32)) 5289 (mode xmode) 5290 (choices 5291 (.sym dst32-Rn-direct-Unprefixed- xmode) 5292 (.sym dst32-An-direct-Unprefixed- xmode) 5293 (.sym dst32-An-indirect-Unprefixed- xmode) 5294 (.sym dst32-24-8-An-relative-Unprefixed- xmode) 5295 (.sym dst32-24-16-An-relative-Unprefixed- xmode) 5296 (.sym dst32-24-24-An-relative-Unprefixed- xmode) 5297 (.sym dst32-24-8-SB-relative-Unprefixed- xmode) 5298 (.sym dst32-24-16-SB-relative-Unprefixed- xmode) 5299 (.sym dst32-24-8-FB-relative-Unprefixed- xmode) 5300 (.sym dst32-24-16-FB-relative-Unprefixed- xmode) 5301 (.sym dst32-24-16-absolute-Unprefixed- xmode) 5302 (.sym dst32-24-24-absolute-Unprefixed- xmode) 5303 ) 5304 ) 5305 (define-anyof-operand 5306 (name (.sym dst32-24-Prefixed- xmode)) 5307 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) 5308 (attrs (machine 32)) 5309 (mode xmode) 5310 (choices 5311 (.sym dst32-Rn-direct-Prefixed- xmode) 5312 (.sym dst32-An-direct-Prefixed- xmode) 5313 (.sym dst32-An-indirect-Prefixed- xmode) 5314 (.sym dst32-24-8-An-relative-Prefixed- xmode) 5315 (.sym dst32-24-16-An-relative-Prefixed- xmode) 5316 (.sym dst32-24-24-An-relative-Prefixed- xmode) 5317 (.sym dst32-24-8-SB-relative-Prefixed- xmode) 5318 (.sym dst32-24-16-SB-relative-Prefixed- xmode) 5319 (.sym dst32-24-8-FB-relative-Prefixed- xmode) 5320 (.sym dst32-24-16-FB-relative-Prefixed- xmode) 5321 (.sym dst32-24-16-absolute-Prefixed- xmode) 5322 (.sym dst32-24-24-absolute-Prefixed- xmode) 5323 ) 5324 ) 5325 (define-anyof-operand 5326 (name (.sym dst32-24-8-Prefixed- xmode)) 5327 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) 5328 (attrs (machine 32)) 5329 (mode xmode) 5330 (choices 5331 (.sym dst32-24-8-An-relative-Prefixed- xmode) 5332 (.sym dst32-24-8-SB-relative-Prefixed- xmode) 5333 (.sym dst32-24-8-FB-relative-Prefixed- xmode) 5334 ) 5335 ) 5336 (define-anyof-operand 5337 (name (.sym dst32-24-16-Prefixed- xmode)) 5338 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) 5339 (attrs (machine 32)) 5340 (mode xmode) 5341 (choices 5342 (.sym dst32-24-16-An-relative-Prefixed- xmode) 5343 (.sym dst32-24-16-SB-relative-Prefixed- xmode) 5344 (.sym dst32-24-16-FB-relative-Prefixed- xmode) 5345 (.sym dst32-24-16-absolute-Prefixed- xmode) 5346 ) 5347 ) 5348 (define-anyof-operand 5349 (name (.sym dst32-24-24-Prefixed- xmode)) 5350 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) 5351 (attrs (machine 32)) 5352 (mode xmode) 5353 (choices 5354 (.sym dst32-24-24-An-relative-Prefixed- xmode) 5355 (.sym dst32-24-24-absolute-Prefixed- xmode) 5356 ) 5357 ) 5358; (define-anyof-operand 5359; (name (.sym dst32-24-indirect- xmode)) 5360; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) 5361; (attrs (machine 32)) 5362; (mode xmode) 5363; (choices 5364; (.sym dst32-An-indirect-indirect- xmode) 5365; (.sym dst32-24-8-An-relative-indirect- xmode) 5366; (.sym dst32-24-16-An-relative-indirect- xmode) 5367; (.sym dst32-24-24-An-relative-indirect- xmode) 5368; (.sym dst32-24-8-SB-relative-indirect- xmode) 5369; (.sym dst32-24-16-SB-relative-indirect- xmode) 5370; (.sym dst32-24-8-FB-relative-indirect- xmode) 5371; (.sym dst32-24-16-FB-relative-indirect- xmode) 5372; ) 5373; ) 5374; (define-anyof-operand 5375; (name (.sym dst32-basic-indirect- xmode)) 5376; (comment (.str "m32c destination operand of size " xmode " with no additional fields")) 5377; (attrs (machine 32)) 5378; (mode xmode) 5379; (choices 5380; (.sym dst32-An-indirect-indirect- xmode) 5381; ) 5382; ) 5383; (define-anyof-operand 5384; (name (.sym dst32-24-8-indirect- xmode)) 5385; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) 5386; (attrs (machine 32)) 5387; (mode xmode) 5388; (choices 5389; (.sym dst32-24-8-An-relative-indirect- xmode) 5390; (.sym dst32-24-8-SB-relative-indirect- xmode) 5391; (.sym dst32-24-8-FB-relative-indirect- xmode) 5392; ) 5393; ) 5394; (define-anyof-operand 5395; (name (.sym dst32-24-16-indirect- xmode)) 5396; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) 5397; (attrs (machine 32)) 5398; (mode xmode) 5399; (choices 5400; (.sym dst32-24-16-An-relative-indirect- xmode) 5401; (.sym dst32-24-16-SB-relative-indirect- xmode) 5402; (.sym dst32-24-16-FB-relative-indirect- xmode) 5403; ) 5404; ) 5405; (define-anyof-operand 5406; (name (.sym dst32-24-24-indirect- xmode)) 5407; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) 5408; (attrs (machine 32)) 5409; (mode xmode) 5410; (choices 5411; (.sym dst32-24-24-An-relative-indirect- xmode) 5412; ) 5413; ) 5414; (define-anyof-operand 5415; (name (.sym dst32-24-absolute-indirect- xmode)) 5416; (comment (.str "m32c destination operand of size " xmode " absolute indirect")) 5417; (attrs (machine 32)) 5418; (mode xmode) 5419; (choices 5420; (.sym dst32-24-16-absolute-indirect-derived- xmode) 5421; (.sym dst32-24-24-absolute-indirect-derived- xmode) 5422; ) 5423; ) 5424; (define-anyof-operand 5425; (name (.sym dst32-24-16-absolute-indirect- xmode)) 5426; (comment (.str "m32c destination operand of size " xmode " absolute indirect")) 5427; (attrs (machine 32)) 5428; (mode xmode) 5429; (choices 5430; (.sym dst32-24-16-absolute-indirect-derived- xmode) 5431; ) 5432; ) 5433; (define-anyof-operand 5434; (name (.sym dst32-24-24-absolute-indirect- xmode)) 5435; (comment (.str "m32c destination operand of size " xmode " absolute indirect")) 5436; (attrs (machine 32)) 5437; (mode xmode) 5438; (choices 5439; (.sym dst32-24-24-absolute-indirect-derived- xmode) 5440; ) 5441; ) 5442 ) 5443) 5444 5445(dst32-24-operand QI) 5446(dst32-24-operand HI) 5447(dst32-24-operand SI) 5448 5449;------------------------------------------------------------- 5450; Destination operands with possible additional fields at offset 32 bits 5451;------------------------------------------------------------- 5452 5453(define-pmacro (dst16-32-operand xmode) 5454 (begin 5455 (define-anyof-operand 5456 (name (.sym dst16-32- xmode)) 5457 (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 32")) 5458 (attrs (machine 16)) 5459 (mode xmode) 5460 (choices 5461 (.sym dst16-Rn-direct- xmode) 5462 (.sym dst16-An-direct- xmode) 5463 (.sym dst16-An-indirect- xmode) 5464 (.sym dst16-32-8-An-relative- xmode) 5465 (.sym dst16-32-16-An-relative- xmode) 5466 (.sym dst16-32-8-SB-relative- xmode) 5467 (.sym dst16-32-16-SB-relative- xmode) 5468 (.sym dst16-32-8-FB-relative- xmode) 5469 (.sym dst16-32-16-absolute- xmode) 5470 ) 5471 ) 5472 ) 5473) 5474(dst16-32-operand QI) 5475(dst16-32-operand HI) 5476 5477; This macro actually handles operands at offset 32, 40 and 48 bits 5478(define-pmacro (dst32-32plus-operand offset xmode) 5479 (begin 5480 (define-anyof-operand 5481 (name (.sym dst32- offset -Unprefixed- xmode)) 5482 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32")) 5483 (attrs (machine 32)) 5484 (mode xmode) 5485 (choices 5486 (.sym dst32-Rn-direct-Unprefixed- xmode) 5487 (.sym dst32-An-direct-Unprefixed- xmode) 5488 (.sym dst32-An-indirect-Unprefixed- xmode) 5489 (.sym dst32- offset -8-An-relative-Unprefixed- xmode) 5490 (.sym dst32- offset -16-An-relative-Unprefixed- xmode) 5491 (.sym dst32- offset -24-An-relative-Unprefixed- xmode) 5492 (.sym dst32- offset -8-SB-relative-Unprefixed- xmode) 5493 (.sym dst32- offset -16-SB-relative-Unprefixed- xmode) 5494 (.sym dst32- offset -8-FB-relative-Unprefixed- xmode) 5495 (.sym dst32- offset -16-FB-relative-Unprefixed- xmode) 5496 (.sym dst32- offset -16-absolute-Unprefixed- xmode) 5497 (.sym dst32- offset -24-absolute-Unprefixed- xmode) 5498 ) 5499 ) 5500 (define-anyof-operand 5501 (name (.sym dst32- offset -Prefixed- xmode)) 5502 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32")) 5503 (attrs (machine 32)) 5504 (mode xmode) 5505 (choices 5506 (.sym dst32-Rn-direct-Prefixed- xmode) 5507 (.sym dst32-An-direct-Prefixed- xmode) 5508 (.sym dst32-An-indirect-Prefixed- xmode) 5509 (.sym dst32- offset -8-An-relative-Prefixed- xmode) 5510 (.sym dst32- offset -16-An-relative-Prefixed- xmode) 5511 (.sym dst32- offset -24-An-relative-Prefixed- xmode) 5512 (.sym dst32- offset -8-SB-relative-Prefixed- xmode) 5513 (.sym dst32- offset -16-SB-relative-Prefixed- xmode) 5514 (.sym dst32- offset -8-FB-relative-Prefixed- xmode) 5515 (.sym dst32- offset -16-FB-relative-Prefixed- xmode) 5516 (.sym dst32- offset -16-absolute-Prefixed- xmode) 5517 (.sym dst32- offset -24-absolute-Prefixed- xmode) 5518 ) 5519 ) 5520; (define-anyof-operand 5521; (name (.sym dst32- offset -indirect- xmode)) 5522; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32")) 5523; (attrs (machine 32)) 5524; (mode xmode) 5525; (choices 5526; (.sym dst32-An-indirect-indirect- xmode) 5527; (.sym dst32- offset -8-An-relative-indirect- xmode) 5528; (.sym dst32- offset -16-An-relative-indirect- xmode) 5529; (.sym dst32- offset -24-An-relative-indirect- xmode) 5530; (.sym dst32- offset -8-SB-relative-indirect- xmode) 5531; (.sym dst32- offset -16-SB-relative-indirect- xmode) 5532; (.sym dst32- offset -8-FB-relative-indirect- xmode) 5533; (.sym dst32- offset -16-FB-relative-indirect- xmode) 5534; ) 5535; ) 5536; (define-anyof-operand 5537; (name (.sym dst32- offset -absolute-indirect- xmode)) 5538; (comment (.str "m32c destination operand of size " xmode " absolute indirect")) 5539; (attrs (machine 32)) 5540; (mode xmode) 5541; (choices 5542; (.sym dst32- offset -16-absolute-indirect-derived- xmode) 5543; (.sym dst32- offset -24-absolute-indirect-derived- xmode) 5544; ) 5545; ) 5546 ) 5547) 5548 5549(dst32-32plus-operand 32 QI) 5550(dst32-32plus-operand 32 HI) 5551(dst32-32plus-operand 32 SI) 5552(dst32-32plus-operand 40 QI) 5553(dst32-32plus-operand 40 HI) 5554(dst32-32plus-operand 40 SI) 5555 5556;------------------------------------------------------------- 5557; Destination operands with possible additional fields at offset 48 bits 5558;------------------------------------------------------------- 5559 5560(define-pmacro (dst32-48-operand offset xmode) 5561 (begin 5562 (define-anyof-operand 5563 (name (.sym dst32- offset -Prefixed- xmode)) 5564 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32")) 5565 (attrs (machine 32)) 5566 (mode xmode) 5567 (choices 5568 (.sym dst32-Rn-direct-Prefixed- xmode) 5569 (.sym dst32-An-direct-Prefixed- xmode) 5570 (.sym dst32-An-indirect-Prefixed- xmode) 5571 (.sym dst32- offset -8-An-relative-Prefixed- xmode) 5572 (.sym dst32- offset -16-An-relative-Prefixed- xmode) 5573 (.sym dst32- offset -24-An-relative-Prefixed- xmode) 5574 (.sym dst32- offset -8-SB-relative-Prefixed- xmode) 5575 (.sym dst32- offset -16-SB-relative-Prefixed- xmode) 5576 (.sym dst32- offset -8-FB-relative-Prefixed- xmode) 5577 (.sym dst32- offset -16-FB-relative-Prefixed- xmode) 5578 (.sym dst32- offset -16-absolute-Prefixed- xmode) 5579 (.sym dst32- offset -24-absolute-Prefixed- xmode) 5580 ) 5581 ) 5582; (define-anyof-operand 5583; (name (.sym dst32- offset -indirect- xmode)) 5584; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32")) 5585; (attrs (machine 32)) 5586; (mode xmode) 5587; (choices 5588; (.sym dst32-An-indirect-indirect- xmode) 5589; (.sym dst32- offset -8-An-relative-indirect- xmode) 5590; (.sym dst32- offset -16-An-relative-indirect- xmode) 5591; (.sym dst32- offset -24-An-relative-indirect- xmode) 5592; (.sym dst32- offset -8-SB-relative-indirect- xmode) 5593; (.sym dst32- offset -16-SB-relative-indirect- xmode) 5594; (.sym dst32- offset -8-FB-relative-indirect- xmode) 5595; (.sym dst32- offset -16-FB-relative-indirect- xmode) 5596; ) 5597; ) 5598; (define-anyof-operand 5599; (name (.sym dst32- offset -absolute-indirect- xmode)) 5600; (comment (.str "m32c destination operand of size " xmode " absolute indirect")) 5601; (attrs (machine 32)) 5602; (mode xmode) 5603; (choices 5604; (.sym dst32- offset -16-absolute-indirect-derived- xmode) 5605; (.sym dst32- offset -24-absolute-indirect-derived- xmode) 5606; ) 5607; ) 5608 ) 5609) 5610 5611(dst32-48-operand 48 QI) 5612(dst32-48-operand 48 HI) 5613(dst32-48-operand 48 SI) 5614 5615;------------------------------------------------------------- 5616; Bit operands for m16c 5617;------------------------------------------------------------- 5618 5619(define-pmacro (bit16-operand offset) 5620 (begin 5621 (define-anyof-operand 5622 (name (.sym bit16- offset)) 5623 (comment (.str "m16c bit operand with possible additional fields at offset 24")) 5624 (attrs (machine 16)) 5625 (mode BI) 5626 (choices 5627 bit16-Rn-direct 5628 bit16-An-direct 5629 bit16-An-indirect 5630 (.sym bit16- offset -8-An-relative) 5631 (.sym bit16- offset -16-An-relative) 5632 (.sym bit16- offset -8-SB-relative) 5633 (.sym bit16- offset -16-SB-relative) 5634 (.sym bit16- offset -8-FB-relative) 5635 (.sym bit16- offset -16-absolute) 5636 ) 5637 ) 5638 (define-anyof-operand 5639 (name (.sym bit16- offset -basic)) 5640 (comment (.str "m16c bit operand with no additional fields")) 5641 (attrs (machine 16)) 5642 (mode BI) 5643 (choices 5644 bit16-An-indirect 5645 ) 5646 ) 5647 (define-anyof-operand 5648 (name (.sym bit16- offset -8)) 5649 (comment (.str "m16c bit operand with possible additional fields at offset 24")) 5650 (attrs (machine 16)) 5651 (mode BI) 5652 (choices 5653 bit16-Rn-direct 5654 bit16-An-direct 5655 (.sym bit16- offset -8-An-relative) 5656 (.sym bit16- offset -8-SB-relative) 5657 (.sym bit16- offset -8-FB-relative) 5658 ) 5659 ) 5660 (define-anyof-operand 5661 (name (.sym bit16- offset -16)) 5662 (comment (.str "m16c bit operand with possible additional fields at offset 24")) 5663 (attrs (machine 16)) 5664 (mode BI) 5665 (choices 5666 (.sym bit16- offset -16-An-relative) 5667 (.sym bit16- offset -16-SB-relative) 5668 (.sym bit16- offset -16-absolute) 5669 ) 5670 ) 5671 ) 5672) 5673 5674(bit16-operand 16) 5675 5676;------------------------------------------------------------- 5677; Bit operands for m32c 5678;------------------------------------------------------------- 5679 5680(define-pmacro (bit32-operand offset group) 5681 (begin 5682 (define-anyof-operand 5683 (name (.sym bit32- offset - group)) 5684 (comment (.str "m32c bit operand with possible additional fields at offset 24")) 5685 (attrs (machine 32)) 5686 (mode BI) 5687 (choices 5688 (.sym bit32-Rn-direct- group) 5689 (.sym bit32-An-direct- group) 5690 (.sym bit32-An-indirect- group) 5691 (.sym bit32- offset -11-An-relative- group) 5692 (.sym bit32- offset -19-An-relative- group) 5693 (.sym bit32- offset -27-An-relative- group) 5694 (.sym bit32- offset -11-SB-relative- group) 5695 (.sym bit32- offset -19-SB-relative- group) 5696 (.sym bit32- offset -11-FB-relative- group) 5697 (.sym bit32- offset -19-FB-relative- group) 5698 (.sym bit32- offset -19-absolute- group) 5699 (.sym bit32- offset -27-absolute- group) 5700 ) 5701 ) 5702 ) 5703) 5704 5705(bit32-operand 16 Unprefixed) 5706(bit32-operand 24 Prefixed) 5707 5708(define-anyof-operand 5709 (name bit32-basic-Unprefixed) 5710 (comment "m32c bit operand with no additional fields") 5711 (attrs (machine 32)) 5712 (mode BI) 5713 (choices 5714 bit32-Rn-direct-Unprefixed 5715 bit32-An-direct-Unprefixed 5716 bit32-An-indirect-Unprefixed 5717 ) 5718) 5719 5720(define-anyof-operand 5721 (name bit32-16-8-Unprefixed) 5722 (comment "m32c bit operand with 8 bit additional fields") 5723 (attrs (machine 32)) 5724 (mode BI) 5725 (choices 5726 bit32-16-11-An-relative-Unprefixed 5727 bit32-16-11-SB-relative-Unprefixed 5728 bit32-16-11-FB-relative-Unprefixed 5729 ) 5730) 5731 5732(define-anyof-operand 5733 (name bit32-16-16-Unprefixed) 5734 (comment "m32c bit operand with 16 bit additional fields") 5735 (attrs (machine 32)) 5736 (mode BI) 5737 (choices 5738 bit32-16-19-An-relative-Unprefixed 5739 bit32-16-19-SB-relative-Unprefixed 5740 bit32-16-19-FB-relative-Unprefixed 5741 bit32-16-19-absolute-Unprefixed 5742 ) 5743) 5744 5745(define-anyof-operand 5746 (name bit32-16-24-Unprefixed) 5747 (comment "m32c bit operand with 24 bit additional fields") 5748 (attrs (machine 32)) 5749 (mode BI) 5750 (choices 5751 bit32-16-27-An-relative-Unprefixed 5752 bit32-16-27-absolute-Unprefixed 5753 ) 5754) 5755 5756;------------------------------------------------------------- 5757; Operands for short format binary insns 5758;------------------------------------------------------------- 5759 5760(define-anyof-operand 5761 (name src16-2-S) 5762 (comment "m16c source operand of size QI for short format insns") 5763 (attrs (machine 16)) 5764 (mode QI) 5765 (choices 5766 src16-2-S-8-SB-relative-QI 5767 src16-2-S-8-FB-relative-QI 5768 src16-2-S-16-absolute-QI 5769 ) 5770) 5771 5772(define-anyof-operand 5773 (name src32-2-S-QI) 5774 (comment "m32c source operand of size QI for short format insns") 5775 (attrs (machine 32)) 5776 (mode QI) 5777 (choices 5778 src32-2-S-8-SB-relative-QI 5779 src32-2-S-8-FB-relative-QI 5780 src32-2-S-16-absolute-QI 5781 ) 5782) 5783 5784(define-anyof-operand 5785 (name src32-2-S-HI) 5786 (comment "m32c source operand of size QI for short format insns") 5787 (attrs (machine 32)) 5788 (mode HI) 5789 (choices 5790 src32-2-S-8-SB-relative-HI 5791 src32-2-S-8-FB-relative-HI 5792 src32-2-S-16-absolute-HI 5793 ) 5794) 5795 5796(define-anyof-operand 5797 (name Dst16-3-S-8) 5798 (comment "m16c destination operand of size QI for short format insns") 5799 (attrs (machine 16)) 5800 (mode QI) 5801 (choices 5802 dst16-3-S-R0l-direct-QI 5803 dst16-3-S-R0h-direct-QI 5804 dst16-3-S-8-8-SB-relative-QI 5805 dst16-3-S-8-8-FB-relative-QI 5806 dst16-3-S-8-16-absolute-QI 5807 ) 5808) 5809 5810(define-anyof-operand 5811 (name Dst16-3-S-16) 5812 (comment "m16c destination operand of size QI for short format insns") 5813 (attrs (machine 16)) 5814 (mode QI) 5815 (choices 5816 dst16-3-S-R0l-direct-QI 5817 dst16-3-S-R0h-direct-QI 5818 dst16-3-S-16-8-SB-relative-QI 5819 dst16-3-S-16-8-FB-relative-QI 5820 dst16-3-S-16-16-absolute-QI 5821 ) 5822) 5823 5824(define-anyof-operand 5825 (name srcdst16-r0l-r0h-S) 5826 (comment "m16c r0l/r0h operand of size QI for short format insns") 5827 (attrs (machine 16)) 5828 (mode SI) 5829 (choices 5830 srcdst16-r0l-r0h-S-derived 5831 ) 5832) 5833 5834(define-anyof-operand 5835 (name dst32-2-S-basic-QI) 5836 (comment "m32c r0l operand of size QI for short format binary insns") 5837 (attrs (machine 32)) 5838 (mode QI) 5839 (choices 5840 dst32-2-S-R0l-direct-QI 5841 ) 5842) 5843 5844(define-anyof-operand 5845 (name dst32-2-S-basic-HI) 5846 (comment "m32c r0 operand of size HI for short format binary insns") 5847 (attrs (machine 32)) 5848 (mode HI) 5849 (choices 5850 dst32-2-S-R0-direct-HI 5851 ) 5852) 5853 5854(define-pmacro (dst32-2-S-operands xmode) 5855 (begin 5856 (define-anyof-operand 5857 (name (.sym dst32-2-S-8- xmode)) 5858 (comment "m32c operand of size " xmode " for short format binary insns") 5859 (attrs (machine 32)) 5860 (mode xmode) 5861 (choices 5862 (.sym dst32-2-S-8-SB-relative- xmode) 5863 (.sym dst32-2-S-8-FB-relative- xmode) 5864 ) 5865 ) 5866 (define-anyof-operand 5867 (name (.sym dst32-2-S-16- xmode)) 5868 (comment "m32c operand of size " xmode " for short format binary insns") 5869 (attrs (machine 32)) 5870 (mode xmode) 5871 (choices 5872 (.sym dst32-2-S-16-absolute- xmode) 5873 ) 5874 ) 5875; (define-anyof-operand 5876; (name (.sym dst32-2-S-8-indirect- xmode)) 5877; (comment "m32c operand of size " xmode " for short format binary insns") 5878; (attrs (machine 32)) 5879; (mode xmode) 5880; (choices 5881; (.sym dst32-2-S-8-SB-relative-indirect- xmode) 5882; (.sym dst32-2-S-8-FB-relative-indirect- xmode) 5883; ) 5884; ) 5885; (define-anyof-operand 5886; (name (.sym dst32-2-S-absolute-indirect- xmode)) 5887; (comment "m32c operand of size " xmode " for short format binary insns") 5888; (attrs (machine 32)) 5889; (mode xmode) 5890; (choices 5891; (.sym dst32-2-S-16-absolute-indirect- xmode) 5892; ) 5893; ) 5894 ) 5895) 5896 5897(dst32-2-S-operands QI) 5898(dst32-2-S-operands HI) 5899(dst32-2-S-operands SI) 5900 5901(define-anyof-operand 5902 (name dst32-an-S) 5903 (comment "m32c An operand for short format binary insns") 5904 (attrs (machine 32)) 5905 (mode HI) 5906 (choices 5907 dst32-1-S-A0-direct-HI 5908 dst32-1-S-A1-direct-HI 5909 ) 5910) 5911 5912(define-anyof-operand 5913 (name bit16-11-S) 5914 (comment "m16c bit operand for short format insns") 5915 (attrs (machine 16)) 5916 (mode BI) 5917 (choices 5918 bit16-11-SB-relative-S 5919 ) 5920) 5921 5922(define-anyof-operand 5923 (name Rn16-push-S-anyof) 5924 (comment "m16c bit operand for short format insns") 5925 (attrs (machine 16)) 5926 (mode QI) 5927 (choices 5928 Rn16-push-S-derived 5929 ) 5930) 5931 5932(define-anyof-operand 5933 (name An16-push-S-anyof) 5934 (comment "m16c bit operand for short format insns") 5935 (attrs (machine 16)) 5936 (mode HI) 5937 (choices 5938 An16-push-S-derived 5939 ) 5940) 5941 5942;============================================================= 5943; Common macros for instruction definitions 5944; 5945(define-pmacro (set-z x) 5946 (sequence () 5947 (set zbit (zflag x))) 5948 5949) 5950 5951(define-pmacro (set-s x) 5952 (sequence () 5953 (set sbit (nflag x))) 5954) 5955 5956(define-pmacro (set-z-and-s x) 5957 (sequence () 5958 (set-z x) 5959 (set-s x)) 5960) 5961 5962;============================================================= 5963; Unary insn macros 5964;------------------------------------------------------------- 5965 5966(define-pmacro (unary-insn-defn-g mach group mode wstr op encoding sem opg) 5967 (dni (.sym op mach wstr - group) 5968 (.str op wstr opg " dst" mach "-" group "-" mode) 5969 ((machine mach) RL_1ADDR) 5970 (.str op wstr opg " ${dst" mach "-" group "-" mode "}") 5971 encoding 5972 (sem mode (.sym dst mach - group - mode)) 5973 ()) 5974) 5975 5976(define-pmacro (unary-insn-defn mach group mode wstr op encoding sem) 5977 (unary-insn-defn-g mach group mode wstr op encoding sem "") 5978) 5979 5980 5981(define-pmacro (unary16-defn-g mode wstr wbit op opc1 opc2 opc3 sem opg) 5982 (unary-insn-defn-g 16 16 mode wstr op 5983 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16- mode)) 5984 sem opg) 5985) 5986(define-pmacro (unary16-defn mode wstr wbit op opc1 opc2 opc3 sem) 5987 (unary-16-defn-g mode wstr wbit op opc1 opc2 opc3 sem "") 5988) 5989 5990(define-pmacro (unary32-defn-g mode wstr wbit op opc1 opc2 opc3 sem opg) 5991 (begin 5992 ; Multi insns are tried for assembly in the reverse order in which they appear here, so 5993 ; define the absolute-indirect insns first in order to prevent them from being selected 5994 ; when the mode is register-indirect 5995; (unary-insn-defn 32 24-absolute-indirect mode wstr op 5996; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (.sym dst32-24-absolute-indirect- mode) (f-18-2 opc2) (f-20-4 opc3)) 5997; sem) 5998 (unary-insn-defn-g 32 16-Unprefixed mode wstr op 5999 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3)) 6000 sem opg) 6001; (unary-insn-defn 32 24-indirect mode wstr op 6002; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (.sym dst32-24-indirect- mode) (f-18-2 opc2) (f-20-4 opc3)) 6003; sem) 6004 ) 6005) 6006(define-pmacro (unary32-defn mode wstr wbit op opc1 opc2 opc3 sem) 6007 (unary32-defn-g mode wstr wbit op opc1 opc2 opc3 sem "") 6008) 6009 6010(define-pmacro (unary-insn-mach-g mach op opc1 opc2 opc3 sem opg) 6011 (begin 6012 (.apply (.sym unary mach -defn-g) (QI .b 0 op opc1 opc2 opc3 sem opg)) 6013 (.apply (.sym unary mach -defn-g) (HI .w 1 op opc1 opc2 opc3 sem opg)) 6014 ) 6015) 6016(define-pmacro (unary-insn-mach mach op opc1 opc2 opc3 sem) 6017 (unary-insn-mach-g mach op opc1 opc2 opc3 sem "") 6018) 6019 6020(define-pmacro (unary-insn op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem) 6021 (begin 6022 (unary-insn-mach-g 16 op opc16-1 opc16-2 opc16-3 sem "") 6023 (unary-insn-mach-g 32 op opc32-1 opc32-2 opc32-3 sem "") 6024 ) 6025) 6026 6027(define-pmacro (unary-insn-g op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem) 6028 (begin 6029 (unary-insn-mach-g 16 op opc16-1 opc16-2 opc16-3 sem "$G") 6030 (unary-insn-mach-g 32 op opc32-1 opc32-2 opc32-3 sem "$G") 6031 ) 6032) 6033 6034;------------------------------------------------------------- 6035; Sign/zero extension macros 6036;------------------------------------------------------------- 6037 6038(define-pmacro (ext-insn-defn mach group smode dmode wstr op encoding sem) 6039 (dni (.sym op mach wstr - group) 6040 (.str op wstr " dst" mach "-" group "-" smode) 6041 ((machine mach)) 6042 (.str op wstr " ${dst" mach "-" group "-" smode "}") 6043 encoding 6044 (sem smode dmode (.sym dst mach - group - smode) (.sym dst mach - group - smode)) 6045 ()) 6046) 6047 6048(define-pmacro (ext16-defn smode dmode wstr wbit op opc1 opc2 opc3 sem) 6049 (ext-insn-defn 16 16-Ext smode dmode wstr op 6050 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-Ext- smode)) 6051 sem) 6052) 6053 6054(define-pmacro (ext32-defn smode dmode wstr wbit op opc1 opc2 opc3 sem) 6055 (ext-insn-defn 32 16-ExtUnprefixed smode dmode wstr op 6056 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst32-16-ExtUnprefixed- smode)) 6057 sem) 6058) 6059 6060(define-pmacro (ext32-binary-insn src-group dst-group op wstr encoding sem) 6061 (dni (.sym op 32 wstr - src-group - dst-group) 6062 (.str op 32 wstr " src32-" src-group "-QI,dst32-" dst-group "-HI") 6063 ((machine 32)) 6064 (.str op wstr " ${src32-" src-group "-QI},${dst32-" dst-group "-HI}") 6065 encoding 6066 (sem QI HI (.sym src32- src-group -QI) (.sym dst32 - dst-group -HI)) 6067 ()) 6068) 6069 6070(define-pmacro (ext32-binary-defn op wstr opc1 opc2 sem) 6071 (begin 6072 (ext32-binary-insn basic-ExtPrefixed 24-Prefixed op wstr 6073 (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 0) src32-basic-ExtPrefixed-QI dst32-24-Prefixed-HI (f-20-4 opc2)) 6074 sem) 6075 (ext32-binary-insn 24-24-Prefixed 48-Prefixed op wstr 6076 (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 0) src32-24-24-Prefixed-QI dst32-48-Prefixed-HI (f-20-4 opc2)) 6077 sem) 6078 (ext32-binary-insn 24-16-Prefixed 40-Prefixed op wstr 6079 (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 0) src32-24-16-Prefixed-QI dst32-40-Prefixed-HI (f-20-4 opc2)) 6080 sem) 6081 (ext32-binary-insn 24-8-Prefixed 32-Prefixed op wstr 6082 (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 0) src32-24-8-Prefixed-QI dst32-32-Prefixed-HI (f-20-4 opc2)) 6083 sem) 6084 ) 6085) 6086 6087;============================================================= 6088; Binary Arithmetic macros 6089; 6090;------------------------------------------------------------- 6091;<arith>.size:S src2,r0[l] -- for m32c 6092;------------------------------------------------------------- 6093 6094(define-pmacro (binary-arith32-S-src2 op xmode wstr wbit opc1 opc2 sem) 6095 (dni (.sym op 32 wstr .S-src2-r0- xmode) 6096 (.str op 32 wstr ":S src2,r0[l]") 6097 ((machine 32)) 6098 (.str op wstr"$S ${src32-2-S-" xmode "},${Dst32R0" xmode "-S}") 6099 (+ opc1 opc2 (.sym src32-2-S- xmode) (f-7-1 wbit)) 6100 (sem xmode (.sym src32-2-S- xmode) (.sym Dst32R0 xmode -S)) 6101 ()) 6102) 6103 6104;------------------------------------------------------------- 6105;<arith>.b:S src2,r0l/r0h -- for m16c 6106;------------------------------------------------------------- 6107 6108(define-pmacro (binary-arith16-b-S-src2 op opc1 opc2 sem) 6109 (begin 6110 (dni (.sym op 16 .b.S-src2) 6111 (.str op ".b:S src2,r0[lh]") 6112 ((machine 16)) 6113 (.str op ".b$S ${src16-2-S},${Dst16RnQI-S}") 6114 (+ opc1 opc2 Dst16RnQI-S src16-2-S) 6115 (sem QI src16-2-S Dst16RnQI-S) 6116 ()) 6117 (dni (.sym op 16 .b.S-r0l-r0h) 6118 (.str op ".b:S r0l/r0h") 6119 ((machine 16)) 6120 (.str op ".b$S ${srcdst16-r0l-r0h-S}") 6121 (+ opc1 opc2 srcdst16-r0l-r0h-S) 6122 (if (eq srcdst16-r0l-r0h-S 0) 6123 (sem QI R0h R0l) 6124 (sem QI R0l R0h)) 6125 ()) 6126 ) 6127) 6128 6129;------------------------------------------------------------- 6130;<arith>.b:S #imm8,dst3 -- for m16c 6131;------------------------------------------------------------- 6132 6133(define-pmacro (binary-arith16-b-S-imm8-dst3 op sz opc1 opc2 sem) 6134 (dni (.sym op 16 .b.S-imm8-dst3) 6135 (.str op sz ":S imm8,dst3") 6136 ((machine 16)) 6137 (.str op sz "$S #${Imm-8-QI},${Dst16-3-S-16}") 6138 (+ opc1 opc2 Dst16-3-S-16 Imm-8-QI) 6139 (sem QI Imm-8-QI Dst16-3-S-16) 6140 ()) 6141) 6142 6143;------------------------------------------------------------- 6144;<arith>.size:Q #imm4,sp -- for m16c 6145;------------------------------------------------------------- 6146 6147(define-pmacro (binary-arith16-Q-sp op opc1 opc2 opc3 sem) 6148 (dni (.sym op 16 -wQ-sp) 6149 (.str op ".w:q #imm4,sp") 6150 ((machine 16)) 6151 (.str op ".w$Q #${Imm-12-s4},sp") 6152 (+ opc1 opc2 opc3 Imm-12-s4) 6153 (sem QI Imm-12-s4 sp) 6154 ()) 6155) 6156 6157;------------------------------------------------------------- 6158;<arith>.size:G #imm,sp -- for m16c 6159;------------------------------------------------------------- 6160 6161(define-pmacro (binary-arith16-G-sp-defn mode wstr wbit op opc1 opc2 opc3 opc4 sem) 6162 (dni (.sym op 16 wstr - G-sp) 6163 (.str op wstr " imm-sp " mode) 6164 ((machine 16)) 6165 (.str op wstr "$G #${Imm-16-" mode "},sp") 6166 (+ opc1 opc2 (f-7-1 wbit) opc3 opc4 (.sym Imm-16- mode)) 6167 (sem mode (.sym Imm-16- mode) sp) 6168 ()) 6169) 6170 6171(define-pmacro (binary-arith16-G-sp op opc1 opc2 opc3 opc4 sem) 6172 (begin 6173 (binary-arith16-G-sp-defn QI .b 0 op opc1 opc2 opc3 opc4 sem) 6174 (binary-arith16-G-sp-defn HI .w 1 op opc1 opc2 opc3 opc4 sem) 6175 ) 6176) 6177 6178;------------------------------------------------------------- 6179;<arith>.size:G #imm,dst -- for m16c and m32c 6180;------------------------------------------------------------- 6181 6182(define-pmacro (binary-arith-imm-dst-defn mach src dstgroup dmode wstr op suffix encoding sem) 6183 (dni (.sym op mach wstr - imm-G - dstgroup) 6184 (.str op wstr " " mach "-imm-G-" dstgroup "-" dmode) 6185 ((machine mach) RL_1ADDR) 6186 (.str op wstr "$"suffix " #${" src "},${dst" mach "-" dstgroup "-" dmode "}") 6187 encoding 6188 (sem dmode src (.sym dst mach - dstgroup - dmode)) 6189 ()) 6190) 6191 6192; m16c variants 6193(define-pmacro (binary-arith16-imm-dst-defn smode dmode wstr wbit op suffix opc1 opc2 opc3 sem) 6194 (begin 6195 (binary-arith-imm-dst-defn 16 (.sym Imm-32- smode) 16-16 dmode wstr op suffix 6196 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- dmode) (.sym Imm-32- smode)) 6197 sem) 6198 (binary-arith-imm-dst-defn 16 (.sym Imm-24- smode) 16-8 dmode wstr op suffix 6199 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- dmode) (.sym Imm-24- smode)) 6200 sem) 6201 (binary-arith-imm-dst-defn 16 (.sym Imm-16- smode) basic dmode wstr op suffix 6202 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- dmode) (.sym Imm-16- smode)) 6203 sem) 6204 ) 6205) 6206 6207; m32c Unprefixed variants 6208(define-pmacro (binary-arith32-imm-dst-Unprefixed smode dmode wstr wbit op suffix opc1 opc2 opc3 sem) 6209 (begin 6210 (binary-arith-imm-dst-defn 32 (.sym Imm-40- smode) 16-24-Unprefixed dmode wstr op suffix 6211 (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) (.sym dst32-16-24-Unprefixed- dmode) (.sym Imm-40- smode)) 6212 sem) 6213 (binary-arith-imm-dst-defn 32 (.sym Imm-32- smode) 16-16-Unprefixed dmode wstr op suffix 6214 (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) (.sym dst32-16-16-Unprefixed- dmode) (.sym Imm-32- smode)) 6215 sem) 6216 (binary-arith-imm-dst-defn 32 (.sym Imm-24- smode) 16-8-Unprefixed dmode wstr op suffix 6217 (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) (.sym dst32-16-8-Unprefixed- dmode) (.sym Imm-24- smode)) 6218 sem) 6219 (binary-arith-imm-dst-defn 32 (.sym Imm-16- smode) basic-Unprefixed dmode wstr op suffix 6220 (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) (.sym dst32-basic-Unprefixed- dmode) (.sym Imm-16- smode)) 6221 sem) 6222 ) 6223) 6224 6225; m32c Prefixed variants 6226(define-pmacro (binary-arith32-imm-dst-Prefixed smode dmode wstr wbit op suffix opc1 opc2 opc3 sem) 6227 (begin 6228 (binary-arith-imm-dst-defn 32 (.sym Imm-48- smode) 24-24-Prefixed dmode wstr op suffix 6229 (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-24-Prefixed- dmode) (.sym Imm-48- smode)) 6230 sem) 6231 (binary-arith-imm-dst-defn 32 (.sym Imm-40- smode) 24-16-Prefixed dmode wstr op suffix 6232 (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-16-Prefixed- dmode) (.sym Imm-40- smode)) 6233 sem) 6234 (binary-arith-imm-dst-defn 32 (.sym Imm-32- smode) 24-8-Prefixed dmode wstr op suffix 6235 (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-8-Prefixed- dmode) (.sym Imm-32- smode)) 6236 sem) 6237 (binary-arith-imm-dst-defn 32 (.sym Imm-24- smode) basic-Prefixed dmode wstr op suffix 6238 (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-basic-Prefixed- dmode) (.sym Imm-24- smode)) 6239 sem) 6240 ) 6241) 6242 6243; All m32c variants 6244(define-pmacro (binary-arith32-imm-dst-defn smode dmode wstr wbit op suffix opc1 opc2 opc3 sem) 6245 (begin 6246 ; Multi insns are tried for assembly in the reverse order in which they appear here, so 6247 ; define the absolute-indirect insns first in order to prevent them from being selected 6248 ; when the mode is register-indirect 6249; (binary-arith-imm-dst-defn 32 (.sym Imm-48- smode) 24-24-absolute-indirect dmode wstr op suffix 6250; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-24-absolute-indirect- dmode) (.sym Imm-48- smode)) 6251; sem) 6252; (binary-arith-imm-dst-defn 32 (.sym Imm-40- smode) 24-16-absolute-indirect dmode wstr op suffix 6253; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-16-absolute-indirect- dmode) (.sym Imm-40- smode)) 6254; sem) 6255 ; Unprefixed modes next 6256 (binary-arith32-imm-dst-Unprefixed smode dmode wstr wbit op suffix opc1 opc2 opc3 sem) 6257 6258 ; Remaining indirect modes 6259; (binary-arith-imm-dst-defn 32 (.sym Imm-24- smode) basic-indirect dmode wstr op suffix 6260; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-basic-indirect- dmode) (.sym Imm-24- smode)) 6261; sem) 6262; (binary-arith-imm-dst-defn 32 (.sym Imm-48- smode) 24-24-indirect dmode wstr op suffix 6263; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-24-indirect- dmode) (.sym Imm-48- smode)) 6264; sem) 6265; (binary-arith-imm-dst-defn 32 (.sym Imm-40- smode) 24-16-indirect dmode wstr op suffix 6266; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-16-indirect- dmode) (.sym Imm-40- smode)) 6267; sem) 6268; (binary-arith-imm-dst-defn 32 (.sym Imm-32- smode) 24-8-indirect dmode wstr op suffix 6269; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-8-indirect- dmode) (.sym Imm-32- smode)) 6270; sem) 6271 ) 6272) 6273 6274(define-pmacro (binary-arith-imm-dst-mach mach op suffix opc1 opc2 opc3 sem) 6275 (begin 6276 (.apply (.sym binary-arith mach -imm-dst-defn) (QI QI .b 0 op suffix opc1 opc2 opc3 sem)) 6277 (.apply (.sym binary-arith mach -imm-dst-defn) (HI HI .w 1 op suffix opc1 opc2 opc3 sem)) 6278 ) 6279) 6280 6281(define-pmacro (binary-arith-imm-dst op suffix opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem) 6282 (begin 6283 (binary-arith-imm-dst-mach 16 op suffix opc16-1 opc16-2 opc16-3 sem) 6284 (binary-arith-imm-dst-mach 32 op suffix opc32-1 opc32-2 opc32-3 sem) 6285 ) 6286) 6287 6288;------------------------------------------------------------- 6289;<arith>.size:Q #imm4,dst -- for m16c and m32c 6290;------------------------------------------------------------- 6291 6292(define-pmacro (binary-arith-imm4-dst-defn mach src dstgroup mode wstr op encoding sem) 6293 (dni (.sym op mach wstr - imm4-Q - dstgroup) 6294 (.str op wstr " " mach "-imm4-Q-" dstgroup "-" mode) 6295 ((machine mach) RL_1ADDR) 6296 (.str op wstr "$Q #${" src "},${dst" mach "-" dstgroup "-" mode "}") 6297 encoding 6298 (sem mode src (.sym dst mach - dstgroup - mode)) 6299 ()) 6300) 6301 6302; m16c variants 6303(define-pmacro (binary-arith16-imm4-dst-defn mode wstr wbit1 wbit2 op opc1 opc2 sem) 6304 (binary-arith-imm4-dst-defn 16 Imm-8-s4 16 mode wstr op 6305 (+ opc1 opc2 (f-7-1 wbit2) Imm-8-s4 (.sym dst16-16- mode)) 6306 sem) 6307) 6308 6309(define-pmacro (binary-arith16-shimm4-dst-defn mode wstr wbit1 wbit2 op opc1 opc2 sem) 6310 (binary-arith-imm4-dst-defn 16 Imm-sh-8-s4 16 mode wstr op 6311 (+ opc1 opc2 (f-7-1 wbit2) Imm-sh-8-s4 (.sym dst16-16- mode)) 6312 sem) 6313) 6314 6315; m32c variants 6316(define-pmacro (binary-arith32-imm4-dst-defn mode wstr wbit1 wbit2 op opc1 opc2 sem) 6317 (begin 6318 ; Multi insns are tried for assembly in the reverse order in which they appear here, so 6319 ; define the absolute-indirect insns first in order to prevent them from being selected 6320 ; when the mode is register-indirect 6321; (binary-arith-imm4-dst-defn 32 Imm-20-s4 24-absolute-indirect mode wstr op 6322; (+ (f-0-4 0) (f-4-4 9) (f-8-3 opc1) (f-11-1 wbit1) (f-15-1 wbit2) (.sym dst32-24-absolute-indirect- mode) (f-18-2 opc2) Imm-20-s4) 6323; sem) 6324 (binary-arith-imm4-dst-defn 32 Imm-12-s4 16-Unprefixed mode wstr op 6325 (+ (f-0-3 opc1) (f-3-1 wbit1) (f-7-1 wbit2) (.sym dst32-16-Unprefixed- mode) (f-10-2 opc2) Imm-12-s4) 6326 sem) 6327; (binary-arith-imm4-dst-defn 32 Imm-20-s4 24-indirect mode wstr op 6328; (+ (f-0-4 0) (f-4-4 9) (f-8-3 opc1) (f-11-1 wbit1) (f-15-1 wbit2) (.sym dst32-24-indirect- mode) (f-18-2 opc2) Imm-20-s4) 6329; sem) 6330 ) 6331) 6332 6333(define-pmacro (binary-arith32-shimm4-dst-defn mode wstr wbit1 wbit2 op opc1 opc2 sem) 6334 (begin 6335 ; Multi insns are tried for assembly in the reverse order in which they appear here, so 6336 ; define the absolute-indirect insns first in order to prevent them from being selected 6337 ; when the mode is register-indirect 6338; (binary-arith-imm4-dst-defn 32 Imm-sh-20-s4 24-absolute-indirect mode wstr op 6339; (+ (f-0-4 0) (f-4-4 9) (f-8-3 opc1) (f-11-1 wbit1) (f-15-1 wbit2) (.sym dst32-24-absolute-indirect- mode) (f-18-2 opc2) Imm-sh-20-s4) 6340; sem) 6341 (binary-arith-imm4-dst-defn 32 Imm-sh-12-s4 16-Unprefixed mode wstr op 6342 (+ (f-0-3 opc1) (f-3-1 wbit1) (f-7-1 wbit2) (.sym dst32-16-Unprefixed- mode) (f-10-2 opc2) Imm-sh-12-s4) 6343 sem) 6344; (binary-arith-imm4-dst-defn 32 Imm-sh-20-s4 24-indirect mode wstr op 6345; (+ (f-0-4 0) (f-4-4 9) (f-8-3 opc1) (f-11-1 wbit1) (f-15-1 wbit2) (.sym dst32-24-indirect- mode) (f-18-2 opc2) Imm-sh-20-s4) 6346; sem) 6347 ) 6348) 6349 6350(define-pmacro (binary-arith-imm4-dst-mach mach op opc1 opc2 sem) 6351 (begin 6352 (.apply (.sym binary-arith mach -imm4-dst-defn) (QI .b 0 0 op opc1 opc2 sem)) 6353 (.apply (.sym binary-arith mach -imm4-dst-defn) (HI .w 0 1 op opc1 opc2 sem)) 6354 ) 6355) 6356 6357(define-pmacro (binary-arith-imm4-dst op opc16-1 opc16-2 opc32-1 opc32-2 sem) 6358 (begin 6359 (binary-arith-imm4-dst-mach 16 op opc16-1 opc16-2 sem) 6360 (binary-arith-imm4-dst-mach 32 op opc32-1 opc32-2 sem) 6361 ) 6362) 6363 6364;------------------------------------------------------------- 6365;<arith>.size:G src,dst -- for m16c and m32c 6366;------------------------------------------------------------- 6367 6368(define-pmacro (binary-arith-src-dst-defn mach srcgroup dstgroup smode dmode wstr op suffix encoding sem) 6369 (dni (.sym op mach wstr - srcgroup - dstgroup) 6370 (.str op wstr " dst" mach "-" srcgroup "-" dstgroup "-" dmode) 6371 ((machine mach) RL_2ADDR) 6372 (.str op wstr "$" suffix " ${src" mach "-" srcgroup "-" smode "},${dst" mach "-" dstgroup "-" dmode "}") 6373 encoding 6374 (sem dmode (.sym src mach - srcgroup - smode) (.sym dst mach - dstgroup - dmode)) 6375 ()) 6376) 6377 6378; m16c variants 6379(define-pmacro (binary-arith16-src-dst-defn smode dmode wstr wbit op suffix opc1 opc2 sem) 6380 (begin 6381 (binary-arith-src-dst-defn 16 basic 16 smode dmode wstr op suffix 6382 (+ opc1 opc2 (f-7-1 wbit) (.sym src16-basic- smode) (.sym dst16-16- dmode)) 6383 sem) 6384 (binary-arith-src-dst-defn 16 16-16 32 smode dmode wstr op suffix 6385 (+ opc1 opc2 (f-7-1 wbit) (.sym src16-16-16- smode) (.sym dst16-32- dmode)) 6386 sem) 6387 (binary-arith-src-dst-defn 16 16-8 24 smode dmode wstr op suffix 6388 (+ opc1 opc2 (f-7-1 wbit) (.sym src16-16-8- smode) (.sym dst16-24- dmode)) 6389 sem) 6390 ) 6391) 6392 6393; m32c Prefixed variants 6394(define-pmacro (binary-arith32-src-dst-Prefixed smode dmode wstr wbit op suffix opc1 opc2 sem) 6395 (begin 6396 (binary-arith-src-dst-defn 32 basic-Prefixed 24-Prefixed smode dmode wstr op suffix 6397 (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) (.sym src32-basic-Prefixed- smode) (.sym dst32-24-Prefixed- dmode) (f-20-4 opc2)) 6398 sem) 6399 (binary-arith-src-dst-defn 32 24-24-Prefixed 48-Prefixed smode dmode wstr op suffix 6400 (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) (.sym src32-24-24-Prefixed- smode) (.sym dst32-48-Prefixed- dmode) (f-20-4 opc2)) 6401 sem) 6402 (binary-arith-src-dst-defn 32 24-16-Prefixed 40-Prefixed smode dmode wstr op suffix 6403 (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) (.sym src32-24-16-Prefixed- smode) (.sym dst32-40-Prefixed- dmode) (f-20-4 opc2)) 6404 sem) 6405 (binary-arith-src-dst-defn 32 24-8-Prefixed 32-Prefixed smode dmode wstr op suffix 6406 (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) (.sym src32-24-8-Prefixed- smode) (.sym dst32-32-Prefixed- dmode) (f-20-4 opc2)) 6407 sem) 6408 ) 6409) 6410 6411; all m32c variants 6412(define-pmacro (binary-arith32-src-dst-defn smode dmode wstr wbit op suffix opc1 opc2 sem) 6413 (begin 6414 ; Multi insns are tried for assembly in the reverse order in which they appear here, so 6415 ; define the absolute-indirect insns first in order to prevent them from being selected 6416 ; when the mode is register-indirect 6417; (binary-arith-src-dst-defn 32 24-24-absolute-indirect 48-absolute-indirect smode dmode wstr op suffix 6418; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6419; (.sym src32-24-24-absolute-indirect- smode) (.sym dst32-48-absolute-indirect- dmode) (f-20-4 opc2)) 6420; sem) 6421; (binary-arith-src-dst-defn 32 24-16-absolute-indirect 40-absolute-indirect smode dmode wstr op suffix 6422; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6423; (.sym src32-24-16-absolute-indirect- smode) (.sym dst32-40-absolute-indirect- dmode) (f-20-4 opc2)) 6424; sem) 6425; (binary-arith-src-dst-defn 32 24-24-absolute-indirect 48-Prefixed smode dmode wstr op suffix 6426; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) 6427; (.sym src32-24-24-absolute-indirect- smode) (.sym dst32-48-Prefixed- dmode) (f-20-4 opc2)) 6428; sem) 6429; (binary-arith-src-dst-defn 32 24-16-absolute-indirect 40-Prefixed smode dmode wstr op suffix 6430; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) 6431; (.sym src32-24-16-absolute-indirect- smode) (.sym dst32-40-Prefixed- dmode) (f-20-4 opc2)) 6432; sem) 6433; (binary-arith-src-dst-defn 32 24-24-absolute-indirect 48-indirect smode dmode wstr op suffix 6434; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6435; (.sym src32-24-24-absolute-indirect- smode) (.sym dst32-48-indirect- dmode) (f-20-4 opc2)) 6436; sem) 6437; (binary-arith-src-dst-defn 32 24-16-absolute-indirect 40-indirect smode dmode wstr op suffix 6438; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6439; (.sym src32-24-16-absolute-indirect- smode) (.sym dst32-40-indirect- dmode) (f-20-4 opc2)) 6440; sem) 6441; (binary-arith-src-dst-defn 32 basic-Prefixed 24-absolute-indirect smode dmode wstr op suffix 6442; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6443; (.sym src32-basic-Prefixed- smode) (.sym dst32-24-absolute-indirect- dmode) (f-20-4 opc2)) 6444; sem) 6445; (binary-arith-src-dst-defn 32 24-24-Prefixed 48-absolute-indirect smode dmode wstr op suffix 6446; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6447; (.sym src32-24-24-Prefixed- smode) (.sym dst32-48-absolute-indirect- dmode) (f-20-4 opc2)) 6448; sem) 6449; (binary-arith-src-dst-defn 32 24-16-Prefixed 40-absolute-indirect smode dmode wstr op suffix 6450; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6451; (.sym src32-24-16-Prefixed- smode) (.sym dst32-40-absolute-indirect- dmode) (f-20-4 opc2)) 6452; sem) 6453; (binary-arith-src-dst-defn 32 24-8-Prefixed 32-absolute-indirect smode dmode wstr op suffix 6454; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6455; (.sym src32-24-8-Prefixed- smode) (.sym dst32-32-absolute-indirect- dmode) (f-20-4 opc2)) 6456; sem) 6457; (binary-arith-src-dst-defn 32 basic-indirect 24-absolute-indirect smode dmode wstr op suffix 6458; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6459; (.sym src32-basic-indirect- smode) (.sym dst32-24-absolute-indirect- dmode) (f-20-4 opc2)) 6460; sem) 6461; (binary-arith-src-dst-defn 32 24-24-indirect 48-absolute-indirect smode dmode wstr op suffix 6462; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6463; (.sym src32-24-24-indirect- smode) (.sym dst32-48-absolute-indirect- dmode) (f-20-4 opc2)) 6464; sem) 6465; (binary-arith-src-dst-defn 32 24-16-indirect 40-absolute-indirect smode dmode wstr op suffix 6466; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6467; (.sym src32-24-16-indirect- smode) (.sym dst32-40-absolute-indirect- dmode) (f-20-4 opc2)) 6468; sem) 6469; (binary-arith-src-dst-defn 32 24-8-indirect 32-absolute-indirect smode dmode wstr op suffix 6470; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6471; (.sym src32-24-8-indirect- smode) (.sym dst32-32-absolute-indirect- dmode) (f-20-4 opc2)) 6472; sem) 6473 (binary-arith-src-dst-defn 32 basic-Unprefixed 16-Unprefixed smode dmode wstr op suffix 6474 (+ (f-0-1 opc1) (f-7-1 wbit) (.sym src32-basic-Unprefixed- smode) (.sym dst32-16-Unprefixed- dmode) (f-12-4 opc2)) 6475 sem) 6476 (binary-arith-src-dst-defn 32 16-24-Unprefixed 40-Unprefixed smode dmode wstr op suffix 6477 (+ (f-0-1 opc1) (f-7-1 wbit) (.sym src32-16-24-Unprefixed- smode) (.sym dst32-40-Unprefixed- dmode) (f-12-4 opc2)) 6478 sem) 6479 (binary-arith-src-dst-defn 32 16-16-Unprefixed 32-Unprefixed smode dmode wstr op suffix 6480 (+ (f-0-1 opc1) (f-7-1 wbit) (.sym src32-16-16-Unprefixed- smode) (.sym dst32-32-Unprefixed- dmode) (f-12-4 opc2)) 6481 sem) 6482 (binary-arith-src-dst-defn 32 16-8-Unprefixed 24-Unprefixed smode dmode wstr op suffix 6483 (+ (f-0-1 opc1) (f-7-1 wbit) (.sym src32-16-8-Unprefixed- smode) (.sym dst32-24-Unprefixed- dmode) (f-12-4 opc2)) 6484 sem) 6485; (binary-arith-src-dst-defn 32 basic-indirect 24-Prefixed smode dmode wstr op suffix 6486; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) 6487; (.sym src32-basic-indirect- smode) (.sym dst32-24-Prefixed- dmode) (f-20-4 opc2)) 6488; sem) 6489; (binary-arith-src-dst-defn 32 24-24-indirect 48-Prefixed smode dmode wstr op suffix 6490; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) 6491; (.sym src32-24-24-indirect- smode) (.sym dst32-48-Prefixed- dmode) (f-20-4 opc2)) 6492; sem) 6493; (binary-arith-src-dst-defn 32 24-16-indirect 40-Prefixed smode dmode wstr op suffix 6494; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) 6495; (.sym src32-24-16-indirect- smode) (.sym dst32-40-Prefixed- dmode) (f-20-4 opc2)) 6496; sem) 6497; (binary-arith-src-dst-defn 32 24-8-indirect 32-Prefixed smode dmode wstr op suffix 6498; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) 6499; (.sym src32-24-8-indirect- smode) (.sym dst32-32-Prefixed- dmode) (f-20-4 opc2)) 6500; sem) 6501; (binary-arith-src-dst-defn 32 basic-Prefixed 24-indirect smode dmode wstr op suffix 6502; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6503; (.sym src32-basic-Prefixed- smode) (.sym dst32-24-indirect- dmode) (f-20-4 opc2)) 6504; sem) 6505; (binary-arith-src-dst-defn 32 24-24-Prefixed 48-indirect smode dmode wstr op suffix 6506; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6507; (.sym src32-24-24-Prefixed- smode) (.sym dst32-48-indirect- dmode) (f-20-4 opc2)) 6508; sem) 6509; (binary-arith-src-dst-defn 32 24-16-Prefixed 40-indirect smode dmode wstr op suffix 6510; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6511; (.sym src32-24-16-Prefixed- smode) (.sym dst32-40-indirect- dmode) (f-20-4 opc2)) 6512; sem) 6513; (binary-arith-src-dst-defn 32 24-8-Prefixed 32-indirect smode dmode wstr op suffix 6514; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6515; (.sym src32-24-8-Prefixed- smode) (.sym dst32-32-indirect- dmode) (f-20-4 opc2)) 6516; sem) 6517; (binary-arith-src-dst-defn 32 basic-indirect 24-indirect smode dmode wstr op suffix 6518; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6519; (.sym src32-basic-indirect- smode) (.sym dst32-24-indirect- dmode) (f-20-4 opc2)) 6520; sem) 6521; (binary-arith-src-dst-defn 32 24-24-indirect 48-indirect smode dmode wstr op suffix 6522; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6523; (.sym src32-24-24-indirect- smode) (.sym dst32-48-indirect- dmode) (f-20-4 opc2)) 6524; sem) 6525; (binary-arith-src-dst-defn 32 24-16-indirect 40-indirect smode dmode wstr op suffix 6526; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6527; (.sym src32-24-16-indirect- smode) (.sym dst32-40-indirect- dmode) (f-20-4 opc2)) 6528; sem) 6529; (binary-arith-src-dst-defn 32 24-8-indirect 32-indirect smode dmode wstr op suffix 6530; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) 6531; (.sym src32-24-8-indirect- smode) (.sym dst32-32-indirect- dmode) (f-20-4 opc2)) 6532; sem) 6533 ) 6534) 6535 6536(define-pmacro (binary-arith-src-dst-mach mach op suffix opc1 opc2 sem) 6537 (begin 6538 (.apply (.sym binary-arith mach -src-dst-defn) (QI QI .b 0 op suffix opc1 opc2 sem)) 6539 (.apply (.sym binary-arith mach -src-dst-defn) (HI HI .w 1 op suffix opc1 opc2 sem)) 6540 ) 6541) 6542 6543(define-pmacro (binary-arith-src-dst op suffix opc16-1 opc16-2 opc32-1 opc32-2 sem) 6544 (begin 6545 (binary-arith-src-dst-mach 16 op suffix opc16-1 opc16-2 sem) 6546 (binary-arith-src-dst-mach 32 op suffix opc32-1 opc32-2 sem) 6547 ) 6548) 6549 6550;------------------------------------------------------------- 6551;<arith>.size:S #imm,dst -- for m32c 6552;------------------------------------------------------------- 6553 6554(define-pmacro (binary-arith32-s-imm-dst-defn src dstgroup mode wstr op encoding sem) 6555 (dni (.sym op 32 wstr - imm-S - dstgroup) 6556 (.str op wstr " 32-imm-S-" dstgroup "-" mode) 6557 ((machine 32)) 6558 (.str op wstr "$S #${" src "},${dst32-" dstgroup "-" mode "}") 6559 encoding 6560 (sem mode src (.sym dst32- dstgroup - mode)) 6561 ()) 6562) 6563 6564(define-pmacro (binary-arith32-z-imm-dst-defn src dstgroup mode wstr op encoding sem) 6565 (dni (.sym op 32 wstr - imm-Z - dstgroup) 6566 (.str op wstr " 32-imm-Z-" dstgroup "-" mode) 6567 ((machine 32)) 6568 (.str op wstr "$Z #0,${dst32-" dstgroup "-" mode "}") 6569 encoding 6570 (sem mode (const 0) (.sym dst32- dstgroup - mode)) 6571 ()) 6572) 6573 6574(define-pmacro (binary-arith32-s-imm-dst mode wstr wbit op opc1 opc2 sem) 6575 (begin 6576; (binary-arith32-s-imm-dst-defn (.sym Imm-32- mode) 2-S-absolute-indirect mode wstr op 6577; (+ (f-0-4 0) (f-4-4 9) (f-8-2 opc1) (.sym dst32-2-S-absolute-indirect- mode) (f-12-3 opc2) (f-15-1 wbit) (.sym Imm-32- mode)) 6578; sem) 6579 (binary-arith32-s-imm-dst-defn (.sym Imm-8- mode) 2-S-basic mode wstr op 6580 (+ (f-0-2 opc1) (.sym dst32-2-S-basic- mode) (f-4-3 opc2) (f-7-1 wbit) (.sym Imm-8- mode)) 6581 sem) 6582 (binary-arith32-s-imm-dst-defn (.sym Imm-24- mode) 2-S-16 mode wstr op 6583 (+ (f-0-2 opc1) (.sym dst32-2-S-16- mode) (f-4-3 opc2) (f-7-1 wbit) (.sym Imm-24- mode)) 6584 sem) 6585 (binary-arith32-s-imm-dst-defn (.sym Imm-16- mode) 2-S-8 mode wstr op 6586 (+ (f-0-2 opc1) (.sym dst32-2-S-8- mode) (f-4-3 opc2) (f-7-1 wbit) (.sym Imm-16- mode)) 6587 sem) 6588; (binary-arith32-s-imm-dst-defn (.sym Imm-24- mode) 2-S-8-indirect mode wstr op 6589; (+ (f-0-4 0) (f-4-4 9) (f-8-2 opc1) (.sym dst32-2-S-8-indirect- mode) (f-12-3 opc2) (f-15-1 wbit) (.sym Imm-24- mode)) 6590; sem) 6591 ) 6592) 6593 6594(define-pmacro (binary-arith32-z-imm-dst mode wstr wbit op opc1 opc2 sem) 6595 (begin 6596; (binary-arith32-z-imm-dst-defn (.sym Imm-32- mode) 2-S-absolute-indirect mode wstr op 6597; (+ (f-0-4 0) (f-4-4 9) (f-8-2 opc1) (.sym dst32-2-S-absolute-indirect- mode) (f-12-3 opc2) (f-15-1 wbit) (.sym Imm-32- mode)) 6598; sem) 6599 (binary-arith32-z-imm-dst-defn (.sym Imm-8- mode) 2-S-basic mode wstr op 6600 (+ (f-0-2 opc1) (.sym dst32-2-S-basic- mode) (f-4-3 opc2) (f-7-1 wbit)) 6601 sem) 6602 (binary-arith32-z-imm-dst-defn (.sym Imm-24- mode) 2-S-16 mode wstr op 6603 (+ (f-0-2 opc1) (.sym dst32-2-S-16- mode) (f-4-3 opc2) (f-7-1 wbit)) 6604 sem) 6605 (binary-arith32-z-imm-dst-defn (.sym Imm-16- mode) 2-S-8 mode wstr op 6606 (+ (f-0-2 opc1) (.sym dst32-2-S-8- mode) (f-4-3 opc2) (f-7-1 wbit)) 6607 sem) 6608; (binary-arith32-z-imm-dst-defn (.sym Imm-24- mode) 2-S-8-indirect mode wstr op 6609; (+ (f-0-4 0) (f-4-4 9) (f-8-2 opc1) (.sym dst32-2-S-8-indirect- mode) (f-12-3 opc2) (f-15-1 wbit) (.sym Imm-24- mode)) 6610; sem) 6611 ) 6612) 6613 6614;------------------------------------------------------------- 6615;<arith>.L:S #imm1,An -- for m32c 6616;------------------------------------------------------------- 6617 6618(define-pmacro (binary-arith32-l-s-imm1-an op opc1 opc2 sem) 6619 (begin 6620 (dni (.sym op 32.l-s-imm1-S-an) 6621 (.str op ".l 32-imm1-S-an") 6622 ((machine 32)) 6623 (.str op ".l$S #${Imm1-S},${dst32-an-S}") 6624 (+ opc1 Imm1-S opc2 dst32-an-S) 6625 (sem SI Imm1-S dst32-an-S) 6626 ()) 6627 ) 6628) 6629 6630;------------------------------------------------------------- 6631;<arith>.L:Q #imm3,sp -- for m32c 6632;------------------------------------------------------------- 6633 6634(define-pmacro (binary-arith32-l-q-imm3-sp op opc1 opc2 sem) 6635 (begin 6636 (dni (.sym op 32.l-imm3-Q) 6637 (.str op ".l 32-imm3-Q") 6638 ((machine 32)) 6639 (.str op ".l$Q #${Imm3-S},sp") 6640 (+ opc1 Imm3-S opc2) 6641 (sem SI Imm3-S sp) 6642 ()) 6643 ) 6644) 6645 6646;------------------------------------------------------------- 6647;<arith>.L:S #imm8,sp -- for m32c 6648;------------------------------------------------------------- 6649 6650(define-pmacro (binary-arith32-l-s-imm8-sp op opc1 opc2 opc3 opc4 sem) 6651 (begin 6652 (dni (.sym op 32.l-imm8-S) 6653 (.str op ".l 32-imm8-S") 6654 ((machine 32)) 6655 (.str op ".l$S #${Imm-16-QI},sp") 6656 (+ opc1 opc2 opc3 opc4 Imm-16-QI) 6657 (sem SI Imm-16-QI sp) 6658 ()) 6659 ) 6660) 6661 6662;------------------------------------------------------------- 6663;<arith>.L:G #imm16,sp -- for m32c 6664;------------------------------------------------------------- 6665 6666(define-pmacro (binary-arith32-l-g-imm16-sp op opc1 opc2 opc3 opc4 sem) 6667 (begin 6668 (dni (.sym op 32.l-imm16-G) 6669 (.str op ".l 32-imm16-G") 6670 ((machine 32)) 6671 (.str op ".l$G #${Imm-16-HI},sp") 6672 (+ opc1 opc2 opc3 opc4 Imm-16-HI) 6673 (sem SI Imm-16-HI sp) 6674 ()) 6675 ) 6676) 6677 6678;------------------------------------------------------------- 6679;<arith>jnz.size #imm4,dst,label -- for m16c and m32c 6680;------------------------------------------------------------- 6681 6682(define-pmacro (arith-jnz-imm4-dst-defn mach src dstgroup label mode wstr op encoding sem) 6683 (dni (.sym op mach wstr - imm4 - dstgroup) 6684 (.str op wstr " " mach "-imm4-" dstgroup "-" label "-" mode) 6685 (RL_JUMP RELAXABLE (machine mach)) 6686 (.str op wstr " #${" src "},${dst" mach "-" dstgroup "-" mode "},${" label "}") 6687 encoding 6688 (sem mode src (.sym dst mach - dstgroup - mode) label) 6689 ()) 6690) 6691 6692; m16c variants 6693(define-pmacro (arith-jnz16-imm4-dst-defn mode wstr wbit op i4n opc1 opc2 sem) 6694 (begin 6695 (arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) basic Lab-16-8 mode wstr op 6696 (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-basic- mode) Lab-16-8) 6697 sem) 6698 (arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) 16-16 Lab-32-8 mode wstr op 6699 (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-16-16- mode) Lab-32-8) 6700 sem) 6701 (arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) 16-8 Lab-24-8 mode wstr op 6702 (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-16-8- mode) Lab-24-8) 6703 sem) 6704 ) 6705) 6706 6707; m32c variants 6708(define-pmacro (arith-jnz32-imm4-dst-defn mode wstr wbit op i4n opc1 opc2 sem) 6709 (begin 6710 (arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) basic-Unprefixed Lab-16-8 mode wstr op 6711 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-16-8) 6712 sem) 6713 (arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) 16-24-Unprefixed Lab-40-8 mode wstr op 6714 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-40-8) 6715 sem) 6716 (arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) 16-16-Unprefixed Lab-32-8 mode wstr op 6717 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-32-8) 6718 sem) 6719 (arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) 16-8-Unprefixed Lab-24-8 mode wstr op 6720 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-24-8) 6721 sem) 6722 ) 6723) 6724 6725(define-pmacro (arith-jnz-imm4-dst-mach mach op i4n opc1 opc2 sem) 6726 (begin 6727 (.apply (.sym arith-jnz mach -imm4-dst-defn) (QI .b 0 op i4n opc1 opc2 sem)) 6728 (.apply (.sym arith-jnz mach -imm4-dst-defn) (HI .w 1 op i4n opc1 opc2 sem)) 6729 ) 6730) 6731 6732(define-pmacro (arith-jnz-imm4-dst op i4n opc16-1 opc16-2 opc32-1 opc32-2 sem) 6733 (begin 6734 (arith-jnz-imm4-dst-mach 16 op i4n opc16-1 opc16-2 sem) 6735 (arith-jnz-imm4-dst-mach 32 op i4n opc32-1 opc32-2 sem) 6736 ) 6737) 6738 6739;------------------------------------------------------------- 6740;mov.size dsp8[sp],dst -- for m16c and m32c 6741;------------------------------------------------------------- 6742(define-pmacro (mov-dspsp-dst-defn mach dstgroup dsp mode wstr op encoding sem) 6743 (dni (.sym op mach wstr -dspsp-dst- dstgroup) 6744 (.str op wstr " " mach "-dsp[sp]-" dstgroup "-" dsp "-" mode) 6745 ((machine mach)) 6746 (.str op wstr "$G ${" dsp "}[sp],${dst" mach "-" dstgroup "-" mode "}") 6747 encoding 6748 (sem mach mode dsp (.sym dst mach - dstgroup - mode)) 6749 ()) 6750) 6751(define-pmacro (mov-src-dspsp-defn mach dstgroup dsp mode wstr op encoding sem) 6752 (dni (.sym op mach wstr -dst-dspsp- dstgroup) 6753 (.str op wstr " " mach "-dsp[sp]-" dstgroup "-" dsp "-" mode) 6754 ((machine mach)) 6755 (.str op wstr "$G ${dst" mach "-" dstgroup "-" mode "},${" dsp "}[sp]") 6756 encoding 6757 (sem mach mode (.sym dst mach - dstgroup - mode) dsp) 6758 ()) 6759) 6760 6761; m16c variants 6762(define-pmacro (mov16-dspsp-dst-defn mode wstr wbit op opc1 opc2 opc3 sem) 6763 (begin 6764 (mov-dspsp-dst-defn 16 basic Dsp-16-s8 mode wstr op 6765 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-s8) 6766 sem) 6767 (mov-dspsp-dst-defn 16 16-16 Dsp-32-s8 mode wstr op 6768 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-s8) 6769 sem) 6770 (mov-dspsp-dst-defn 16 16-8 Dsp-24-s8 mode wstr op 6771 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-s8) 6772 sem) 6773 ) 6774) 6775 6776(define-pmacro (mov16-src-dspsp-defn mode wstr wbit op opc1 opc2 opc3 sem) 6777 (begin 6778 (mov-src-dspsp-defn 16 basic Dsp-16-s8 mode wstr op 6779 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-s8) 6780 sem) 6781 (mov-src-dspsp-defn 16 16-16 Dsp-32-s8 mode wstr op 6782 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-s8) 6783 sem) 6784 (mov-src-dspsp-defn 16 16-8 Dsp-24-s8 mode wstr op 6785 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-s8) 6786 sem) 6787 ) 6788) 6789 6790; m32c variants 6791(define-pmacro (mov32-dspsp-dst-defn mode wstr wbit op opc1 opc2 opc3 sem) 6792 (begin 6793 (mov-dspsp-dst-defn 32 basic-Unprefixed Dsp-16-s8 mode wstr op 6794 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-16-s8) 6795 sem) 6796 (mov-dspsp-dst-defn 32 16-24-Unprefixed Dsp-40-s8 mode wstr op 6797 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-40-s8) 6798 sem) 6799 (mov-dspsp-dst-defn 32 16-16-Unprefixed Dsp-32-s8 mode wstr op 6800 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-32-s8) 6801 sem) 6802 (mov-dspsp-dst-defn 32 16-8-Unprefixed Dsp-24-s8 mode wstr op 6803 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-24-s8) 6804 sem) 6805 ) 6806) 6807(define-pmacro (mov32-src-dspsp-defn mode wstr wbit op opc1 opc2 opc3 sem) 6808 (begin 6809 (mov-src-dspsp-defn 32 basic-Unprefixed Dsp-16-s8 mode wstr op 6810 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-16-s8) 6811 sem) 6812 (mov-src-dspsp-defn 32 16-24-Unprefixed Dsp-40-s8 mode wstr op 6813 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-40-s8) 6814 sem) 6815 (mov-src-dspsp-defn 32 16-16-Unprefixed Dsp-32-s8 mode wstr op 6816 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-32-s8) 6817 sem) 6818 (mov-src-dspsp-defn 32 16-8-Unprefixed Dsp-24-s8 mode wstr op 6819 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-24-s8) 6820 sem) 6821 ) 6822) 6823 6824(define-pmacro (mov-src-dspsp-mach mach op opc1 opc2 opc3 sem) 6825 (begin 6826 (.apply (.sym mov mach -src-dspsp-defn) (QI .b 0 op opc1 opc2 opc3 sem)) 6827 (.apply (.sym mov mach -src-dspsp-defn) (HI .w 1 op opc1 opc2 opc3 sem)) 6828 ) 6829) 6830 6831(define-pmacro (mov-dspsp-dst-mach mach op opc1 opc2 opc3 sem) 6832 (begin 6833 (.apply (.sym mov mach -dspsp-dst-defn) (QI .b 0 op opc1 opc2 opc3 sem)) 6834 (.apply (.sym mov mach -dspsp-dst-defn) (HI .w 1 op opc1 opc2 opc3 sem)) 6835 ) 6836) 6837 6838(define-pmacro (mov-dspsp-dst op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem) 6839 (begin 6840 (mov-dspsp-dst-mach 16 op opc16-1 opc16-2 opc16-3 sem) 6841 (mov-dspsp-dst-mach 32 op opc32-1 opc32-2 opc32-3 sem) 6842 ) 6843) 6844(define-pmacro (mov-src-dspsp op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem) 6845 (begin 6846 (mov-src-dspsp-mach 16 op opc16-1 opc16-2 opc16-3 sem) 6847 (mov-src-dspsp-mach 32 op opc32-1 opc32-2 opc32-3 sem) 6848 ) 6849) 6850 6851;------------------------------------------------------------- 6852; lde dsp24,dst -- for m16c 6853;------------------------------------------------------------- 6854 6855(define-pmacro (lde-dst-dsp mode wstr wbit dstgroup srcdisp) 6856 (begin 6857 6858 (dni (.sym lde wstr - dstgroup -u20) 6859 (.str "lde" wstr "-" dstgroup "-u20") 6860 ((machine 16)) 6861 (.str "lde" wstr " ${" srcdisp "},${dst16-" dstgroup "-" mode "}") 6862 (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x8) 6863 (.sym dst16- dstgroup - mode) srcdisp) 6864 (nop) 6865 ()) 6866 6867 (dni (.sym lde wstr - dstgroup -u20a0) 6868 (.str "lde" wstr "-" dstgroup "-u20a0") 6869 ((machine 16)) 6870 (.str "lde" wstr " ${" srcdisp "}[a0],${dst16-" dstgroup "-" mode "}") 6871 (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x9) 6872 (.sym dst16- dstgroup - mode) srcdisp) 6873 (nop) 6874 ()) 6875 6876 (dni (.sym lde wstr - dstgroup -a1a0) 6877 (.str "lde" wstr "-" dstgroup "-a1a0") 6878 ((machine 16)) 6879 (.str "lde" wstr " [a1a0],${dst16-" dstgroup "-" mode "}") 6880 (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #xa) 6881 (.sym dst16- dstgroup - mode)) 6882 (nop) 6883 ()) 6884 ) 6885 ) 6886 6887(define-pmacro (lde-dst mode wstr wbit) 6888 (begin 6889 ; like: QI .b 0 6890 (lde-dst-dsp mode wstr wbit basic Dsp-16-u20) 6891 (lde-dst-dsp mode wstr wbit 16-8 Dsp-24-u20) 6892 (lde-dst-dsp mode wstr wbit 16-16 Dsp-32-u20) 6893 ) 6894) 6895 6896;------------------------------------------------------------- 6897; ste dst,dsp24 -- for m16c 6898;------------------------------------------------------------- 6899 6900(define-pmacro (ste-dst-dsp mode wstr wbit dstgroup srcdisp) 6901 (begin 6902 6903 (dni (.sym ste wstr - dstgroup -u20) 6904 (.str "ste" wstr "-" dstgroup "-u20") 6905 ((machine 16)) 6906 (.str "ste" wstr " ${dst16-" dstgroup "-" mode "},${" srcdisp "}") 6907 (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x0) 6908 (.sym dst16- dstgroup - mode) srcdisp) 6909 (nop) 6910 ()) 6911 6912 (dni (.sym ste wstr - dstgroup -u20a0) 6913 (.str "ste" wstr "-" dstgroup "-u20a0") 6914 ((machine 16)) 6915 (.str "ste" wstr " ${dst16-" dstgroup "-" mode "},${" srcdisp "}[a0]") 6916 (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x1) 6917 (.sym dst16- dstgroup - mode) srcdisp) 6918 (nop) 6919 ()) 6920 6921 (dni (.sym ste wstr - dstgroup -a1a0) 6922 (.str "ste" wstr "-" dstgroup "-a1a0") 6923 ((machine 16)) 6924 (.str "ste" wstr " ${dst16-" dstgroup "-" mode "},[a1a0]") 6925 (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x2) 6926 (.sym dst16- dstgroup - mode)) 6927 (nop) 6928 ()) 6929 ) 6930 ) 6931 6932(define-pmacro (ste-dst mode wstr wbit) 6933 (begin 6934 ; like: QI .b 0 6935 (ste-dst-dsp mode wstr wbit basic Dsp-16-u20) 6936 (ste-dst-dsp mode wstr wbit 16-8 Dsp-24-u20) 6937 (ste-dst-dsp mode wstr wbit 16-16 Dsp-32-u20) 6938 ) 6939) 6940 6941;============================================================= 6942; Division 6943;------------------------------------------------------------- 6944 6945(define-pmacro (div-sem divop modop opmode reg src quot rem max min) 6946 (sequence () 6947 (if (eq src 0) 6948 (set obit (const BI 1)) 6949 (sequence ((opmode quot-result) (opmode rem-result)) 6950 (set quot-result (divop opmode (ext opmode reg) src)) 6951 (set rem-result (modop opmode (ext opmode reg) src)) 6952 (set obit (orif (gt opmode quot-result max) 6953 (lt opmode quot-result min))) 6954 (set quot quot-result) 6955 (set rem rem-result)))) 6956) 6957 6958;<divop>.size #imm -- for m16c and m32c 6959(define-pmacro (div-imm-defn mach wstr op src encoding divop modop opmode reg quot rem max min sem) 6960 (dni (.sym op mach wstr - src) 6961 (.str op mach wstr "-" src) 6962 ((machine mach)) 6963 (.str op wstr " #${" src "}") 6964 encoding 6965 (sem divop modop opmode reg src quot rem max min) 6966 ()) 6967) 6968(define-pmacro (div16-imm-defn smode wstr wbit op divop modop opmode reg quot rem max min opc1 opc2 opc3 opc4 sem) 6969 (div-imm-defn 16 wstr op (.sym Imm-16 - smode) 6970 (+ opc1 opc2 (f-7-1 wbit) opc3 opc4 (.sym Imm-16 - smode)) 6971 divop modop opmode reg quot rem max min 6972 sem) 6973) 6974(define-pmacro (div32-imm-defn smode wstr wbit op divop modop opmode reg quot rem max min opc1 opc2 opc3 opc4 sem) 6975 (div-imm-defn 32 wstr op (.sym Imm-16 - smode) 6976 (+ (f-0-4 opc1) (f-4-4 opc2) (f-8-3 opc3) (f-11-1 wbit) (f-12-4 opc4) (.sym Imm-16 - smode)) 6977 divop modop opmode reg quot rem max min 6978 sem) 6979) 6980(define-pmacro (div-imm-mach mach op divop modop opmode max-QI min-QI max-HI min-HI opc1 opc2 opc3 opc4 sem) 6981 (begin 6982 (.apply (.sym div mach -imm-defn) (QI .b 0 op divop modop opmode R0 R0l R0h max-QI min-QI opc1 opc2 opc3 opc4 sem)) 6983 (.apply (.sym div mach -imm-defn) (HI .w 1 op divop modop opmode R2R0 R0 R2 max-HI min-HI opc1 opc2 opc3 opc4 sem)) 6984 ) 6985) 6986(define-pmacro (div-imm op divop modop opmode max-QI min-QI max-HI min-HI opc16-1 opc16-2 opc16-3 opc16-4 opc32-1 opc32-2 opc32-3 opc32-4 sem) 6987 (begin 6988 (div-imm-mach 16 op divop modop opmode max-QI min-QI max-HI min-HI opc16-1 opc16-2 opc16-3 opc16-4 sem) 6989 (div-imm-mach 32 op divop modop opmode max-QI min-QI max-HI min-HI opc32-1 opc32-2 opc32-3 opc32-4 sem) 6990 ) 6991) 6992 6993;<divop>.size src -- for m16c and m32c 6994(define-pmacro (div-src-defn mach wstr op src encoding divop modop opmode reg quot rem max min sem) 6995 (dni (.sym op mach wstr - src) 6996 (.str op mach wstr "-" src) 6997 ((machine mach)) 6998 (.str op wstr " ${" src "}") 6999 encoding 7000 (sem divop modop opmode reg src quot rem max min) 7001 ()) 7002) 7003(define-pmacro (div16-src-defn smode wstr wbit op divop modop opmode reg quot rem max min opc1 opc2 opc3 sem) 7004 (div-src-defn 16 wstr op (.sym dst16-16 - smode) 7005 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16 - smode)) 7006 divop modop opmode reg quot rem max min 7007 sem) 7008) 7009(define-pmacro (div32-src-defn smode wstr wbit op divop modop opmode reg quot rem max min opc1 opc2 opc3 sem) 7010 (begin 7011 ; Multi insns are tried for assembly in the reverse order in which they appear here, so 7012 ; define the absolute-indirect insns first in order to prevent them from being selected 7013 ; when the mode is register-indirect 7014; (div-src-defn 32 wstr op (.sym dst32-24-absolute-indirect- smode) 7015; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (f-18-2 opc2) (f-20-4 opc3) (.sym dst32-24-absolute-indirect - smode)) 7016; divop modop opmode reg quot rem max min 7017; sem) 7018 (div-src-defn 32 wstr op (.sym dst32-16-Unprefixed- smode) 7019 (+ (f-0-4 opc1) (f-7-1 wbit) (f-10-2 opc2) (f-12-4 opc3) (.sym dst32-16-Unprefixed- smode)) 7020 divop modop opmode reg quot rem max min 7021 sem) 7022; (div-src-defn 32 wstr op (.sym dst32-24-indirect- smode) 7023; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (f-18-2 opc2) (f-20-4 opc3) (.sym dst32-24-indirect - smode)) 7024; divop modop opmode reg quot rem max min 7025; sem) 7026 ) 7027) 7028(define-pmacro (div-src-mach mach op divop modop opmode max-QI min-QI max-HI min-HI opc1 opc2 opc3 sem) 7029 (begin 7030 (.apply (.sym div mach -src-defn) (QI .b 0 op divop modop opmode R0 R0l R0h max-QI min-QI opc1 opc2 opc3 sem)) 7031 (.apply (.sym div mach -src-defn) (HI .w 1 op divop modop opmode R2R0 R0 R2 max-HI min-HI opc1 opc2 opc3 sem)) 7032 ) 7033) 7034(define-pmacro (div-src op divop modop opmode max-QI min-QI max-HI min-HI opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem) 7035 (begin 7036 (div-src-mach 16 op divop modop opmode max-QI min-QI max-HI min-HI opc16-1 opc16-2 opc16-3 sem) 7037 (div-src-mach 32 op divop modop opmode max-QI min-QI max-HI min-HI opc32-1 opc32-2 opc32-3 sem) 7038 ) 7039) 7040 7041;============================================================= 7042; Bit manipulation 7043; 7044(define-pmacro (bit-insn-defn mach op suffix opnd encoding sem) 7045 (dni (.sym op mach - suffix - opnd) 7046 (.str op mach ":" suffix " " opnd) 7047 ((machine mach)) 7048 (.str op "$" suffix " ${" opnd "}") 7049 encoding 7050 (sem opnd) 7051 ()) 7052) 7053 7054(define-pmacro (bitsrc16-defn op opc1 opc2 opc3 sem) 7055 (bit-insn-defn 16 op X bit16-16 7056 (+ opc1 opc2 opc3 bit16-16) 7057 sem) 7058) 7059 7060(define-pmacro (bitsrc32-defn op opc1 opc2 opc3 sem) 7061 (begin 7062 (bit-insn-defn 32 op X bit32-24-Prefixed 7063 (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) bit32-24-Prefixed (f-15-1 opc2) (f-18-3 opc3)) 7064 sem) 7065 ) 7066) 7067 7068(define-pmacro (bitsrc-insn op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem) 7069 (begin 7070 (bitsrc16-defn op opc16-1 opc16-2 opc16-3 sem) 7071 (bitsrc32-defn op opc32-1 opc32-2 opc32-3 sem) 7072 ) 7073) 7074 7075(define-pmacro (bitdst16-defn op opc1 opc2 opc3 opc4 opc5 opc6 sem) 7076 (begin 7077 (bit-insn-defn 16 op G bit16-16-basic (+ opc1 opc2 opc3 bit16-16-basic) sem) 7078 (bit-insn-defn 16 op G bit16-16-16 (+ opc1 opc2 opc3 bit16-16-16) sem) 7079 (bit-insn-defn 16 op S bit16-11-S (+ opc4 opc5 opc6 bit16-11-S) sem) 7080 (bit-insn-defn 16 op G bit16-16-8 (+ opc1 opc2 opc3 bit16-16-8) sem) 7081 ) 7082) 7083 7084(define-pmacro (bitdst32-defn op opc1 opc2 opc3 sem) 7085 (begin 7086 (bit-insn-defn 32 op X bit32-16-Unprefixed 7087 (+ (f-0-4 opc1) bit32-16-Unprefixed (f-7-1 opc2) (f-10-3 opc3)) 7088 sem) 7089 ) 7090) 7091 7092(define-pmacro (bitdstnos-insn op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem) 7093 (begin 7094 (bitsrc16-defn op opc16-1 opc16-2 opc16-3 sem) 7095 (bitdst32-defn op opc32-1 opc32-2 opc32-3 sem) 7096 ) 7097) 7098 7099(define-pmacro (bitdst-insn op opc16-1 opc16-2 opc16-3 opc16-4 opc16-5 opc16-6 opc32-1 opc32-2 opc32-3 sem) 7100 (begin 7101 (bitdst16-defn op opc16-1 opc16-2 opc16-3 opc16-4 opc16-5 opc16-6 sem) 7102 (bitdst32-defn op opc32-1 opc32-2 opc32-3 sem) 7103 ) 7104) 7105 7106;============================================================= 7107; Bit condition 7108; 7109(define-pmacro (bitcond-insn-defn mach op bit-opnd cond-opnd encoding sem) 7110 (dni (.sym op mach - bit-opnd - cond-opnd) 7111 (.str op mach " " bit-opnd " " cond-opnd) 7112 ((machine mach)) 7113 (.str op "${" cond-opnd "} ${" bit-opnd "}") 7114 encoding 7115 (sem mach bit-opnd cond-opnd) 7116 ()) 7117) 7118 7119(define-pmacro (bitcond16-defn op opc1 opc2 opc3 sem) 7120 (begin 7121 (bitcond-insn-defn 16 op bit16-16-basic cond16-16 (+ opc1 opc2 opc3 bit16-16-basic cond16-16) sem) 7122 (bitcond-insn-defn 16 op bit16-16-16 cond16-32 (+ opc1 opc2 opc3 bit16-16-16 cond16-32) sem) 7123 (bitcond-insn-defn 16 op bit16-16-8 cond16-24 (+ opc1 opc2 opc3 bit16-16-8 cond16-24) sem) 7124 ) 7125) 7126 7127(define-pmacro (bitcond32-defn op opc1 opc2 opc3 sem) 7128 (begin 7129 (bitcond-insn-defn 32 op bit32-16-24-Unprefixed cond32-40 7130 (+ (f-0-4 opc1) bit32-16-24-Unprefixed (f-7-1 opc2) (f-10-3 opc3) cond32-40) 7131 sem) 7132 (bitcond-insn-defn 32 op bit32-16-16-Unprefixed cond32-32 7133 (+ (f-0-4 opc1) bit32-16-16-Unprefixed (f-7-1 opc2) (f-10-3 opc3) cond32-32) 7134 sem) 7135 (bitcond-insn-defn 32 op bit32-16-8-Unprefixed cond32-24 7136 (+ (f-0-4 opc1) bit32-16-8-Unprefixed (f-7-1 opc2) (f-10-3 opc3) cond32-24) 7137 sem) 7138 (bitcond-insn-defn 32 op bit32-basic-Unprefixed cond32-16 7139 (+ (f-0-4 opc1) bit32-basic-Unprefixed (f-7-1 opc2) (f-10-3 opc3) cond32-16) 7140 sem) 7141 ) 7142) 7143 7144(define-pmacro (bitcond-insn op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem) 7145 (begin 7146 (bitcond16-defn op opc16-1 opc16-2 opc16-3 sem) 7147 (bitcond32-defn op opc32-1 opc32-2 opc32-3 sem) 7148 ) 7149) 7150 7151;============================================================= 7152;<insn>.size #imm1,#imm2,dst -- for m32c 7153; 7154(define-pmacro (insn-imm1-imm2-dst-defn src1 src2 dstgroup xmode wstr op encoding sem) 7155 (dni (.sym op 32 wstr - src1 - src2 - dstgroup) 7156 (.str op 32 wstr "-" src1 "-" src2 "-" dstgroup "-" xmode) 7157 ((machine 32)) 7158 (.str op wstr " #${" src1 "},#${" src2 "},${dst32-" dstgroup "-" xmode "}") 7159 encoding 7160 (sem xmode src1 src2 (.sym dst32- dstgroup - xmode)) 7161 ()) 7162) 7163 7164; m32c Prefixed variants 7165(define-pmacro (insn32-imm1-imm2-dst-Prefixed-defn xmode wstr wbit base1 base2 base3 base4 op opc1 opc2 opc3 sem) 7166 (begin 7167 (insn-imm1-imm2-dst-defn (.sym Imm-48- xmode) (.sym Imm- base4 - xmode) 24-24-Prefixed xmode wstr op 7168 (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) 7169 (.sym dst32-24-24-Prefixed- xmode) (.sym Imm-48- xmode) (.sym Imm- base4 - xmode)) 7170 sem) 7171 (insn-imm1-imm2-dst-defn (.sym Imm-40- xmode) (.sym Imm- base3 - xmode) 24-16-Prefixed xmode wstr op 7172 (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) 7173 (.sym dst32-24-16-Prefixed- xmode) (.sym Imm-40- xmode) (.sym Imm- base3 - xmode)) 7174 sem) 7175 (insn-imm1-imm2-dst-defn (.sym Imm-32- xmode) (.sym Imm- base2 - xmode) 24-8-Prefixed xmode wstr op 7176 (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) 7177 (.sym dst32-24-8-Prefixed- xmode) (.sym Imm-32- xmode) (.sym Imm- base2 - xmode)) 7178 sem) 7179 (insn-imm1-imm2-dst-defn (.sym Imm-24- xmode) (.sym Imm- base1 - xmode) basic-Prefixed xmode wstr op 7180 (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) 7181 (.sym dst32-basic-Prefixed- xmode) (.sym Imm-24- xmode) (.sym Imm- base1 - xmode)) 7182 sem) 7183 ) 7184) 7185 7186; m32c Unprefixed variants 7187(define-pmacro (insn32-imm1-imm2-dst-Unprefixed-defn xmode wstr wbit base1 base2 base3 base4 op opc1 opc2 opc3 sem) 7188 (begin 7189 (insn-imm1-imm2-dst-defn (.sym Imm-40- xmode) (.sym Imm- base4 - xmode) 16-24-Unprefixed xmode wstr op 7190 (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) 7191 (.sym dst32-16-24-Unprefixed- xmode) (.sym Imm-40- xmode) (.sym Imm- base4 - xmode)) 7192 sem) 7193 (insn-imm1-imm2-dst-defn (.sym Imm-32- xmode) (.sym Imm- base3 - xmode) 16-16-Unprefixed xmode wstr op 7194 (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) 7195 (.sym dst32-16-16-Unprefixed- xmode) (.sym Imm-32- xmode) (.sym Imm- base3 - xmode)) 7196 sem) 7197 (insn-imm1-imm2-dst-defn (.sym Imm-24- xmode) (.sym Imm- base2 - xmode) 16-8-Unprefixed xmode wstr op 7198 (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) 7199 (.sym dst32-16-8-Unprefixed- xmode) (.sym Imm-24- xmode) (.sym Imm- base2 - xmode)) 7200 sem) 7201 (insn-imm1-imm2-dst-defn (.sym Imm-16- xmode) (.sym Imm- base1 - xmode) basic-Unprefixed xmode wstr op 7202 (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) 7203 (.sym dst32-basic-Unprefixed- xmode) (.sym Imm-16- xmode) (.sym Imm- base1 - xmode)) 7204 sem) 7205 ) 7206) 7207 7208(define-pmacro (insn-imm1-imm2-dst-Prefixed op opc32-1 opc32-2 opc32-3 sem) 7209 (begin 7210 (insn32-imm1-imm2-dst-Prefixed-defn QI .b 0 32 40 48 56 op opc32-1 opc32-2 opc32-3 sem) 7211 (insn32-imm1-imm2-dst-Prefixed-defn HI .w 1 40 48 56 64 op opc32-1 opc32-2 opc32-3 sem) 7212 ) 7213) 7214(define-pmacro (insn-imm1-imm2-dst-Unprefixed op opc32-1 opc32-2 opc32-3 sem) 7215 (begin 7216 (insn32-imm1-imm2-dst-Unprefixed-defn QI .b 0 24 32 40 48 op opc32-1 opc32-2 opc32-3 sem) 7217 (insn32-imm1-imm2-dst-Unprefixed-defn HI .w 1 32 40 48 56 op opc32-1 opc32-2 opc32-3 sem) 7218 ) 7219) 7220 7221;============================================================= 7222; Insn definitions 7223;------------------------------------------------------------- 7224; abs - absolute 7225;------------------------------------------------------------- 7226 7227(define-pmacro (abs-sem mode dst) 7228 (sequence ((mode result)) 7229 (set result (abs mode dst)) 7230 (set obit (eq result dst)) 7231 (set-z-and-s result) 7232 (set dst result)) 7233) 7234(unary-insn abs (f-0-4 7) (f-4-3 3) (f-8-4 #xF) #xA #x1 #xF abs-sem) 7235 7236;------------------------------------------------------------- 7237; adcf - addition carry flag 7238;------------------------------------------------------------- 7239 7240(define-pmacro (adcf-sem mode dst) 7241 (sequence ((mode result)) 7242 (set result (addc mode dst 0 cbit)) 7243 (set obit (add-oflag mode dst 0 cbit)) 7244 (set cbit (add-cflag mode dst 0 cbit)) 7245 (set-z-and-s result) 7246 (set dst result)) 7247) 7248(unary-insn adcf (f-0-4 7) (f-4-3 3) (f-8-4 #xE) #xB #x1 #xE adcf-sem) 7249 7250;------------------------------------------------------------- 7251; add - binary addition 7252;------------------------------------------------------------- 7253 7254(define-pmacro (add-sem mode src1 dst) 7255 (sequence ((mode result)) 7256 (set result (add mode src1 dst)) 7257 (set obit (add-oflag mode src1 dst 0)) 7258 (set cbit (add-cflag mode src1 dst 0)) 7259 (set-z-and-s result) 7260 (set dst result)) 7261) 7262 7263; add.L:G #imm32,dst (m32 #2) 7264(binary-arith32-imm-dst-defn SI SI .l 0 add G #x8 #x3 #x1 add-sem) 7265; add.size:G #imm,dst (m16 #1 m32 #1) 7266(binary-arith-imm-dst add G (f-0-4 7) (f-4-3 3) (f-8-4 4) #x8 #x2 #xE add-sem) 7267; add.size:Q #imm4,dst (m16 #2 m32 #3) 7268(binary-arith-imm4-dst add (f-0-4 #xC) (f-4-3 4) #x7 #x3 add-sem) 7269(binary-arith32-imm4-dst-defn SI .l 1 0 add #x7 #x3 add-sem) 7270; add.b:S #imm8,dst3 (m16 #3) 7271(binary-arith16-b-S-imm8-dst3 add ".b" (f-0-4 8) (f-4-1 0) add-sem) 7272; add.BW:Q #imm4,sp (m16 #7) 7273(binary-arith16-Q-sp add (f-0-4 7) (f-4-4 #xD) (f-8-4 #xB) add-sem) 7274(dnmi add16-bQ-sp "add16-bQ-sp" () 7275 "add.b:q #${Imm-12-s4},sp" 7276 (emit add16-wQ-sp Imm-12-s4)) 7277; add.BW:G #imm,sp (m16 #6) 7278(binary-arith16-G-sp add (f-0-4 7) (f-4-3 6) (f-8-4 #xE) (f-12-4 #xB) add-sem) 7279; add.BW:G src,dst (m16 #4 m32 #6) 7280(binary-arith-src-dst add G (f-0-4 #xA) (f-4-3 0) #x1 #x8 add-sem) 7281; add.B.S src2,r0l/r0h (m16 #5) 7282(binary-arith16-b-S-src2 add (f-0-4 2) (f-4-1 0) add-sem) 7283; add.L:G src,dst (m32 #7) 7284(binary-arith32-src-dst-defn SI SI .l 1 add G #x1 #x2 add-sem) 7285; add.L:S #imm{1,2},A0/A1 (m32 #5) 7286(binary-arith32-l-s-imm1-an add (f-0-2 2) (f-3-4 6) add-sem) 7287; add.L:Q #imm3,sp (m32 #9) 7288(binary-arith32-l-q-imm3-sp add (f-0-2 1) (f-4-3 1) add-sem) 7289; add.L:S #imm8,sp (m32 #10) 7290(binary-arith32-l-s-imm8-sp add (f-0-4 #xb) (f-4-4 6) (f-8-4 0) (f-12-4 3) add-sem) 7291; add.L:G #imm16,sp (m32 #8) 7292(binary-arith32-l-g-imm16-sp add (f-0-4 #xb) (f-4-4 6) (f-8-4 1) (f-12-4 3) add-sem) 7293; add.BW:S #imm,dst2 (m32 #4) 7294(binary-arith32-s-imm-dst QI .b 0 add #x0 #x3 add-sem) 7295(binary-arith32-s-imm-dst HI .w 1 add #x0 #x3 add-sem) 7296 7297;------------------------------------------------------------- 7298; adc - binary add with carry 7299;------------------------------------------------------------- 7300 7301(define-pmacro (addc-sem mode src dst) 7302 (sequence ((mode result)) 7303 (set result (addc mode src dst cbit)) 7304 (set obit (add-oflag mode src dst cbit)) 7305 (set cbit (add-cflag mode src dst cbit)) 7306 (set-z-and-s result) 7307 (set dst result)) 7308) 7309 7310; adc.size:G #imm,dst 7311(binary-arith16-imm-dst-defn QI QI .b 0 adc X (f-0-4 7) (f-4-3 3) (f-8-4 6) addc-sem) 7312(binary-arith16-imm-dst-defn HI HI .w 1 adc X (f-0-4 7) (f-4-3 3) (f-8-4 6) addc-sem) 7313(binary-arith32-imm-dst-Prefixed QI QI .b 0 adc X #x8 #x2 #xE addc-sem) 7314(binary-arith32-imm-dst-Prefixed HI HI .w 1 adc X #x8 #x2 #xE addc-sem) 7315 7316; adc.BW:G src,dst 7317(binary-arith16-src-dst-defn QI QI .b 0 adc X (f-0-4 #xB) (f-4-3 0) addc-sem) 7318(binary-arith16-src-dst-defn HI HI .w 1 adc X (f-0-4 #xB) (f-4-3 0) addc-sem) 7319(binary-arith32-src-dst-Prefixed QI QI .b 0 adc X #x1 #x4 addc-sem) 7320(binary-arith32-src-dst-Prefixed HI HI .w 1 adc X #x1 #x4 addc-sem) 7321 7322;------------------------------------------------------------- 7323; dadc - decimal add with carry 7324; dadd - decimal addition 7325;------------------------------------------------------------- 7326 7327(define-pmacro (dadc-sem mode src dst) 7328 (sequence ((mode result)) 7329 (set result (subc mode dst src (not cbit))) 7330 (set cbit (sub-cflag mode dst src (not cbit))) 7331 (set-z-and-s result) 7332 (set dst result)) 7333) 7334 7335(define-pmacro (decimal-subtraction16-insn op opc1 opc2) 7336 (begin 7337 ; op.b #imm8,r0l 7338 (dni (.sym op 16.b-imm8) 7339 (.str op ".b #imm8") 7340 ((machine 16)) 7341 (.str op ".b #${Imm-16-QI},r0l") 7342 (+ (f-0-4 #x7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 opc1) Imm-16-QI) 7343 ((.sym op -sem) QI Imm-16-QI R0l) 7344 ()) 7345 ; op.w #imm16,r0 7346 (dni (.sym op 16.w-imm16) 7347 (.str op ".b #imm16") 7348 ((machine 16)) 7349 (.str op ".w #${Imm-16-HI},r0") 7350 (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 opc1) Imm-16-HI) 7351 ((.sym op -sem) HI Imm-16-HI R0) 7352 ()) 7353 ; op.b #r0h,r0l 7354 (dni (.sym op 16.b-r0h-r0l) 7355 (.str op ".b r0h,r0l") 7356 ((machine 16)) 7357 (.str op ".b r0h,r0l") 7358 (+ (f-0-4 #x7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 opc2)) 7359 ((.sym op -sem) QI R0h R0l) 7360 ()) 7361 ; op.w #r1,r0 7362 (dni (.sym op 16.w-r1-r0) 7363 (.str op ".b r1,r0") 7364 ((machine 16)) 7365 (.str op ".w r1,r0") 7366 (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 opc2)) 7367 ((.sym op -sem) HI R1 R0) 7368 ()) 7369 ) 7370) 7371 7372; dadc for m16c 7373(decimal-subtraction16-insn dadc #xE #x6 ) 7374 7375; dadc.size #imm,dst 7376(binary-arith32-imm-dst-Prefixed QI QI .b 0 dadc X #x8 #x0 #xE dadc-sem) 7377(binary-arith32-imm-dst-Prefixed HI HI .w 1 dadc X #x8 #x0 #xE dadc-sem) 7378; dadc.BW src,dst 7379(binary-arith32-src-dst-Prefixed QI QI .b 0 dadc X #x1 #x8 dadc-sem) 7380(binary-arith32-src-dst-Prefixed HI HI .w 1 dadc X #x1 #x8 dadc-sem) 7381 7382(define-pmacro (dadd-sem mode src dst) 7383 (sequence ((mode result)) 7384 (set result (subc mode dst src 0)) 7385 (set cbit (sub-cflag mode dst src 0)) 7386 (set-z-and-s result) 7387 (set dst result)) 7388) 7389 7390; dadd for m16c 7391(decimal-subtraction16-insn dadd #xC #x4) 7392 7393; dadd.size #imm,dst 7394(binary-arith32-imm-dst-Prefixed QI QI .b 0 dadd X #x8 #x1 #xE dadd-sem) 7395(binary-arith32-imm-dst-Prefixed HI HI .w 1 dadd X #x8 #x1 #xE dadd-sem) 7396; dadd.BW src,dst 7397(binary-arith32-src-dst-Prefixed QI QI .b 0 dadd X #x1 #x0 dadd-sem) 7398(binary-arith32-src-dst-Prefixed HI HI .w 1 dadd X #x1 #x0 dadd-sem) 7399 7400;-------------------------------------------------------------; 7401; addx - Add extend sign with no carry 7402;-------------------------------------------------------------; 7403 7404(define-pmacro (addx-sem mode src dst) 7405 (sequence ((SI source) (SI result)) 7406 (set source (zext SI (trunc QI src))) 7407 (set result (add SI source dst)) 7408 (set obit (add-oflag SI source dst 0)) 7409 (set cbit (add-cflag SI source dst 0)) 7410 (set-z-and-s result) 7411 (set dst result)) 7412) 7413 7414; addx #imm,dst 7415(binary-arith32-imm-dst-defn QI SI "" 0 addx X #x8 #x1 #x1 addx-sem) 7416; addx src,dst 7417(binary-arith32-src-dst-defn QI SI "" 0 addx X #x1 #x2 addx-sem) 7418 7419;------------------------------------------------------------- 7420; adjnz - Add/Sub and branch if not zero 7421;------------------------------------------------------------- 7422 7423(define-pmacro (arith-jnz-sem mode src dst label) 7424 (sequence ((mode result)) 7425 (set result (add mode src dst)) 7426 (set dst result) 7427 (if (ne result 0) 7428 (set pc label))) 7429) 7430 7431; adjnz.size #imm4,dst,label 7432(arith-jnz-imm4-dst adjnz s4 (f-0-4 #xF) (f-4-3 4) #xf #x1 arith-jnz-sem) 7433 7434;------------------------------------------------------------- 7435; and - binary and 7436;------------------------------------------------------------- 7437 7438(define-pmacro (and-sem mode src1 dst) 7439 (sequence ((mode result)) 7440 (set result (and mode src1 dst)) 7441 (set-z-and-s result) 7442 (set dst result)) 7443) 7444 7445; and.size:G #imm,dst (m16 #1 m32 #1) 7446(binary-arith-imm-dst and G (f-0-4 7) (f-4-3 3) (f-8-4 2) #x8 #x3 #xF and-sem) 7447; and.b:S #imm8,dst3 (m16 #2) 7448(binary-arith16-b-S-imm8-dst3 and ".b" (f-0-4 9) (f-4-1 0) and-sem) 7449; and.BW:G src,dst (m16 #3 m32 #3) 7450(binary-arith-src-dst and G (f-0-4 #x9) (f-4-3 0) #x1 #xD and-sem) 7451; and.B.S src2,r0l/r0h (m16 #4) 7452(binary-arith16-b-S-src2 and (f-0-4 1) (f-4-1 0) and-sem) 7453; and.BW:S #imm,dst2 (m32 #2) 7454(binary-arith32-s-imm-dst QI .b 0 and #x1 #x6 and-sem) 7455(binary-arith32-s-imm-dst HI .w 1 and #x1 #x6 and-sem) 7456 7457;------------------------------------------------------------- 7458; band - bit and 7459;------------------------------------------------------------- 7460 7461(define-pmacro (band-sem src) 7462 (set cbit (and src cbit)) 7463) 7464(bitsrc-insn band (f-0-4 7) (f-4-4 #xE) (f-8-4 4) #xD #x0 #x1 band-sem) 7465 7466;------------------------------------------------------------- 7467; bclr - bit clear 7468;------------------------------------------------------------- 7469 7470(define-pmacro (bclr-sem dst) 7471 (set dst 0) 7472) 7473(bitdst-insn bclr (f-0-4 7) (f-4-4 #xE) (f-8-4 8) (f-0-2 1) (f-2-2 0) (f-4-1 0) #xD #x0 #x6 bclr-sem) 7474 7475;------------------------------------------------------------- 7476; bitindex - bit index 7477;------------------------------------------------------------- 7478 7479(define-pmacro (bitindex-sem mode dst) 7480 (set BitIndex dst) 7481) 7482(unary-insn-defn 32 16-Unprefixed QI .b bitindex 7483 (+ (f-0-4 #xC) (f-7-1 0) dst32-16-Unprefixed-QI (f-10-2 #x2) (f-12-4 #xE)) 7484 bitindex-sem) 7485(unary-insn-defn 32 16-Unprefixed HI .w bitindex 7486 (+ (f-0-4 #xC) (f-7-1 1) dst32-16-Unprefixed-HI (f-10-2 #x2) (f-12-4 #xE)) 7487 bitindex-sem) 7488 7489;------------------------------------------------------------- 7490; bmCnd - bit move condition 7491;------------------------------------------------------------- 7492 7493(define-pmacro (test-condition16 cond) 7494 (case UQI cond 7495 ((#x00) (trunc BI cbit)) 7496 ((#x01) (not (or cbit zbit))) 7497 ((#x02) (trunc BI zbit)) 7498 ((#x03) (trunc BI sbit)) 7499 ((#x04) (or zbit (xor sbit obit))) 7500 ((#x05) (trunc BI obit)) 7501 ((#x06) (xor sbit obit)) 7502 ((#xf8) (not cbit)) 7503 ((#xf9) (or cbit zbit)) 7504 ((#xfa) (not zbit)) 7505 ((#xfb) (not sbit)) 7506 ((#xfc) (not (or zbit (xor sbit obit)))) 7507 ((#xfd) (not obit)) 7508 ((#xfe) (not (xor sbit obit))) 7509 (else (const BI 0)) 7510 ) 7511) 7512 7513(define-pmacro (test-condition32 cond) 7514 (case UQI cond 7515 ((#x00) (not cbit)) 7516 ((#x01) (or cbit zbit)) 7517 ((#x02) (not zbit)) 7518 ((#x03) (not sbit)) 7519 ((#x04) (not obit)) 7520 ((#x05) (not (or zbit (xor sbit obit)))) 7521 ((#x06) (not (xor sbit obit))) 7522 ((#x08) (trunc BI cbit)) 7523 ((#x09) (not (or cbit zbit))) 7524 ((#x0a) (trunc BI zbit)) 7525 ((#x0b) (trunc BI sbit)) 7526 ((#x0c) (trunc BI obit)) 7527 ((#x0d) (or zbit (xor sbit obit))) 7528 ((#x0e) (xor sbit obit)) 7529 (else (const BI 0)) 7530 ) 7531) 7532 7533(define-pmacro (bitcond-sem mach op cond) 7534 (if ((.sym test-condition mach) cond) 7535 (set op 1) 7536 (set op 0)) 7537) 7538(bitcond-insn bm (f-0-4 7) (f-4-4 #xE) (f-8-4 2) #xD #x0 #x2 bitcond-sem) 7539 7540(dni bm16-c 7541 "bm16 C" 7542 ((machine 16)) 7543 "bm$cond16c c" 7544 (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xD) cond16c) 7545 (bitcond-sem 16 cbit cond16c) 7546 ()) 7547 7548(dni bm32-c 7549 "bm32 C" 7550 ((machine 32)) 7551 "bm$cond32 c" 7552 (+ (f-0-4 #xD) (f-4-4 #x9) (f-8-1 0) (f-10-3 5) cond32) 7553 (bitcond-sem 32 cbit cond32) 7554 ()) 7555 7556;------------------------------------------------------------- 7557; bnand 7558;------------------------------------------------------------- 7559 7560(define-pmacro (bnand-sem src) 7561 (set cbit (and (inv src) cbit)) 7562) 7563(bitsrc-insn bnand (f-0-4 7) (f-4-4 #xE) (f-8-4 5) #xD #x0 #x3 bnand-sem) 7564 7565;------------------------------------------------------------- 7566; bnor 7567;------------------------------------------------------------- 7568 7569(define-pmacro (bnor-sem src) 7570 (set cbit (or (inv src) cbit)) 7571) 7572(bitsrc-insn bnor (f-0-4 7) (f-4-4 #xE) (f-8-4 7) #xD #x0 #x6 bnor-sem) 7573 7574;------------------------------------------------------------- 7575; bnot 7576;------------------------------------------------------------- 7577 7578(define-pmacro (bnot-sem dst) 7579 (set dst (inv dst)) 7580) 7581(bitdst-insn bnot (f-0-4 7) (f-4-4 #xE) (f-8-4 #xA) (f-0-2 1) (f-2-2 1) (f-4-1 0) #xD #x0 #x3 bnot-sem) 7582 7583;------------------------------------------------------------- 7584; bntst 7585;------------------------------------------------------------- 7586 7587(define-pmacro (bntst-sem src) 7588 (set cbit (inv src)) 7589 (set zbit (inv src)) 7590) 7591(bitsrc-insn bntst (f-0-4 7) (f-4-4 #xE) (f-8-4 3) #xD #x0 #x0 bntst-sem) 7592 7593;------------------------------------------------------------- 7594; bnxor 7595;------------------------------------------------------------- 7596 7597(define-pmacro (bnxor-sem src) 7598 (set cbit (xor (inv src) cbit)) 7599) 7600(bitsrc-insn bnxor (f-0-4 7) (f-4-4 #xE) (f-8-4 #xD) #xD #x0 #x7 bnxor-sem) 7601 7602;------------------------------------------------------------- 7603; bor 7604;------------------------------------------------------------- 7605 7606(define-pmacro (bor-sem src) 7607 (set cbit (or src cbit)) 7608) 7609(bitsrc-insn bor (f-0-4 7) (f-4-4 #xE) (f-8-4 #x6) #xD #x0 #x4 bor-sem) 7610 7611;------------------------------------------------------------- 7612; brk 7613;------------------------------------------------------------- 7614 7615(dni brk16 7616 "brk" 7617 ((machine 16)) 7618 "brk" 7619 (+ (f-0-4 #x0) (f-4-4 #x0)) 7620 (nop) 7621 ()) 7622 7623(dni brk32 7624 "brk" 7625 ((machine 32)) 7626 "brk" 7627 (+ (f-0-4 #x0) (f-4-4 #x0)) 7628 (nop) 7629 ()) 7630 7631;------------------------------------------------------------- 7632; brk2 7633;------------------------------------------------------------- 7634 7635(dni brk232 7636 "brk2" 7637 ((machine 32)) 7638 "brk2" 7639 (+ (f-0-4 #x0) (f-4-4 #x8)) 7640 (nop) 7641 ()) 7642 7643;------------------------------------------------------------- 7644; bset 7645;------------------------------------------------------------- 7646 7647(define-pmacro (bset-sem dst) 7648 (set dst 1) 7649) 7650(bitdst-insn bset (f-0-4 7) (f-4-4 #xE) (f-8-4 9) (f-0-2 1) (f-2-2 0) (f-4-1 1) #xD #x0 #x7 bset-sem) 7651 7652;------------------------------------------------------------- 7653; btst 7654;------------------------------------------------------------- 7655 7656(define-pmacro (btst-sem dst) 7657 (set zbit (inv dst)) 7658 (set cbit dst) 7659) 7660(bitdst16-defn btst (f-0-4 7) (f-4-4 #xE) (f-8-4 #xB) (f-0-2 1) (f-2-2 1) (f-4-1 1) btst-sem) 7661 7662(bit-insn-defn 32 btst G bit32-16-Unprefixed 7663 (+ (f-0-4 #xD) bit32-16-Unprefixed (f-7-1 #x0) (f-10-3 #x0)) 7664 btst-sem) 7665 7666(dni btst.s "btst:s" ((machine 32)) 7667 "btst:s ${Bit3-S},${Dsp-8-u16}" 7668 (+ (f-0-2 #x0) (f-4-3 #x5) Bit3-S Dsp-8-u16) 7669 () ()) 7670 7671;------------------------------------------------------------- 7672; btstc 7673;------------------------------------------------------------- 7674 7675(define-pmacro (btstc-sem dst) 7676 (set zbit (inv dst)) 7677 (set cbit dst) 7678 (set dst (const 0)) 7679) 7680(bitdstnos-insn btstc (f-0-4 7) (f-4-4 #xE) (f-8-4 #x0) #xD #x0 #x4 btstc-sem) 7681 7682;------------------------------------------------------------- 7683; btsts 7684;------------------------------------------------------------- 7685 7686(define-pmacro (btsts-sem dst) 7687 (set zbit (inv dst)) 7688 (set cbit dst) 7689 (set dst (const 0)) 7690) 7691(bitdstnos-insn btsts (f-0-4 7) (f-4-4 #xE) (f-8-4 #x1) #xD #x0 #x5 btsts-sem) 7692 7693;------------------------------------------------------------- 7694; bxor 7695;------------------------------------------------------------- 7696 7697(define-pmacro (bxor-sem src) 7698 (set cbit (xor src cbit)) 7699) 7700(bitsrc-insn bxor (f-0-4 7) (f-4-4 #xE) (f-8-4 #xC) #xD #x0 #x5 bxor-sem) 7701 7702;------------------------------------------------------------- 7703; clip 7704;------------------------------------------------------------- 7705 7706(define-pmacro (clip-sem mode imm1 imm2 dest) 7707 (sequence () 7708 (if (gt mode imm1 dest) 7709 (set dest imm1)) 7710 (if (lt mode imm2 dest) 7711 (set dest imm2))) 7712) 7713 7714(insn-imm1-imm2-dst-Prefixed clip #x8 #x3 #xE clip-sem) 7715 7716;------------------------------------------------------------- 7717; cmp - binary compare 7718;------------------------------------------------------------- 7719 7720(define-pmacro (cmp-sem mode src1 dst) 7721 (sequence ((mode result)) 7722 (set result (sub mode dst src1)) 7723 (set obit (sub-oflag mode dst src1 0)) 7724 (set cbit (not (sub-cflag mode dst src1 0))) 7725 (set-z-and-s result)) 7726) 7727 7728; cmp.L:G #imm32,dst (m32 #2) 7729(binary-arith32-imm-dst-defn SI SI .l 0 cmp G #xA #x3 #x1 cmp-sem) 7730; cmp.size:G #imm,dst (m16 #1 m32 #1) 7731(binary-arith-imm-dst cmp G (f-0-4 7) (f-4-3 3) (f-8-4 8) #x9 #x2 #xE cmp-sem) 7732; cmp.size:Q #imm4,dst (m16 #2 m32 #3) 7733(binary-arith-imm4-dst cmp (f-0-4 #xD) (f-4-3 0) #x7 #x1 cmp-sem) 7734; cmp.b:S #imm8,dst3 (m16 #3) 7735(binary-arith16-b-S-imm8-dst3 cmp ".b" (f-0-4 #xE) (f-4-1 0) cmp-sem) 7736; cmp.BW:G src,dst (m16 #4 m32 #5) 7737(binary-arith-src-dst cmp G (f-0-4 #xC) (f-4-3 0) #x1 #x6 cmp-sem) 7738; cmp.B.S src2,r0l/r0h (m16 #5) 7739(binary-arith16-b-S-src2 cmp (f-0-4 3) (f-4-1 1) cmp-sem) 7740; cmp.L:G src,dst (m32 #6) 7741(binary-arith32-src-dst-defn SI SI .l 1 cmp G #x1 #x1 cmp-sem) 7742; cmp.BW:S #imm,dst2 (m32 #4) 7743(binary-arith32-s-imm-dst QI .b 0 cmp #x1 #x3 cmp-sem) 7744(binary-arith32-s-imm-dst HI .w 1 cmp #x1 #x3 cmp-sem) 7745; cmp.BW:s src2,r0[l] (m32 #7) 7746(binary-arith32-S-src2 cmp QI .b 0 (f-0-2 1) (f-4-3 0) cmp-sem) 7747(binary-arith32-S-src2 cmp HI .w 1 (f-0-2 1) (f-4-3 0) cmp-sem) 7748 7749;------------------------------------------------------------- 7750; cmpx - binary compare extend sign 7751;------------------------------------------------------------- 7752 7753(define-pmacro (cmpx-sem mode src1 dst) 7754 (sequence ((mode result)) 7755 (set result (sub mode dst (ext mode src1))) 7756 (set obit (sub-oflag mode dst (ext mode src1) 0)) 7757 (set cbit (sub-cflag mode dst (ext mode src1) 0)) 7758 (set-z-and-s result)) 7759) 7760 7761(binary-arith32-imm-dst-defn QI SI "" 0 cmpx X #xA #x1 #x1 cmpx-sem) 7762 7763;------------------------------------------------------------- 7764; dec - decrement 7765;------------------------------------------------------------- 7766 7767(define-pmacro (dec-sem mode dest) 7768 (sequence ((mode result)) 7769 (set result (sub mode dest 1)) 7770 (set-z-and-s result) 7771 (set dest result)) 7772) 7773 7774(dni dec16.b 7775 "dec.b Dst16-3-S-8" 7776 ((machine 16)) 7777 "dec.b ${Dst16-3-S-8}" 7778 (+ (f-0-4 #xA) (f-4-1 #x1) Dst16-3-S-8) 7779 (dec-sem QI Dst16-3-S-8) 7780 ()) 7781 7782(dni dec16.w 7783 "dec.w Dst16An-S" 7784 ((machine 16)) 7785 "dec.w ${Dst16An-S}" 7786 (+ (f-0-4 #xF) (f-5-3 #x2) Dst16An-S) 7787 (dec-sem HI Dst16An-S) 7788 ()) 7789 7790(unary32-defn QI .b 0 dec #xB #x0 #xE dec-sem) 7791(unary32-defn HI .w 1 dec #xB #x0 #xE dec-sem) 7792 7793;------------------------------------------------------------- 7794; div - divide 7795; divu - divide unsigned 7796; divx - divide extension 7797;------------------------------------------------------------- 7798 7799; div.BW #imm 7800(div-imm div div mod SI 127 -128 32767 -32768 (f-0-4 #x7) (f-4-3 6) (f-8-4 #xE) (f-12-4 #x1) #xB #x0 #x2 #x3 div-sem) 7801(div-imm divu udiv umod USI 255 0 65535 0 (f-0-4 #x7) (f-4-3 6) (f-8-4 #xE) (f-12-4 #x0) #xB #x0 #x0 #x3 div-sem) 7802(div-imm divx div mod SI 127 -128 32767 -32768 (f-0-4 #x7) (f-4-3 6) (f-8-4 #xE) (f-12-4 #x3) #xB #x2 #x2 #x3 div-sem) 7803; div.BW src 7804(div-src div div mod SI 127 -128 32767 -32768 (f-0-4 #x7) (f-4-3 3) (f-8-4 #xD) #x8 #x1 #xE div-sem) 7805(div-src divu udiv umod USI 255 0 65535 0 (f-0-4 #x7) (f-4-3 3) (f-8-4 #xC) #x8 #x0 #xE div-sem) 7806(div-src divx div mod SI 127 -128 32767 -32768 (f-0-4 #x7) (f-4-3 3) (f-8-4 #x9) #x9 #x1 #xE div-sem) 7807 7808(div-src-defn 32 .l div dst32-24-Prefixed-SI 7809 (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xA) (f-15-1 1) (f-18-2 #x1) (f-20-4 #xf) dst32-24-Prefixed-SI) 7810 div mod SI R2R0 R2R0 NoRemainder #x7fffffff (neg SI #x80000000) 7811 div-sem) 7812(div-src-defn 32 .l divu dst32-24-Prefixed-SI 7813 (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xA) (f-15-1 1) (f-18-2 #x0) (f-20-4 #xf) dst32-24-Prefixed-SI) 7814 udiv umod USI R2R0 R2R0 NoRemainder #x80000000 0 7815 div-sem) 7816(div-src-defn 32 .l divx dst32-24-Prefixed-SI 7817 (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xA) (f-15-1 1) (f-18-2 #x2) (f-20-4 #xf) dst32-24-Prefixed-SI) 7818 div mod SI R2R0 R2R0 NoRemainder #x7fffffff (neg SI #x80000000) 7819 div-sem) 7820 7821;------------------------------------------------------------- 7822; dsbb - decimal subtraction with borrow 7823; dsub - decimal subtraction 7824;------------------------------------------------------------- 7825 7826(define-pmacro (dsbb-sem mode src dst) 7827 (sequence ((mode result)) 7828 (set result (subc mode dst src (not cbit))) 7829 (set cbit (sub-cflag mode dst src (not cbit))) 7830 (set-z-and-s result) 7831 (set dst result)) 7832) 7833 7834; dsbb for m16c 7835(decimal-subtraction16-insn dsbb #xF #x7) 7836 7837; dsbb.size #imm,dst 7838(binary-arith32-imm-dst-Prefixed QI QI .b 0 dsbb X #x9 #x0 #xE dsbb-sem) 7839(binary-arith32-imm-dst-Prefixed HI HI .w 1 dsbb X #x9 #x0 #xE dsbb-sem) 7840; dsbb.BW src,dst 7841(binary-arith32-src-dst-Prefixed QI QI .b 0 dsbb X #x1 #xA dsbb-sem) 7842(binary-arith32-src-dst-Prefixed HI HI .w 1 dsbb X #x1 #xA dsbb-sem) 7843 7844(define-pmacro (dsub-sem mode src dst) 7845 (sequence ((mode result)) 7846 (set result (subc mode dst src 0)) 7847 (set cbit (sub-cflag mode dst src 0)) 7848 (set-z-and-s result) 7849 (set dst result)) 7850) 7851 7852; dsub for m16c 7853(decimal-subtraction16-insn dsub #xD #x5) 7854 7855; dsub.size #imm,dst 7856(binary-arith32-imm-dst-Prefixed QI QI .b 0 dsub X #x9 #x1 #xE dsub-sem) 7857(binary-arith32-imm-dst-Prefixed HI HI .w 1 dsub X #x9 #x1 #xE dsub-sem) 7858; dsub.BW src,dst 7859(binary-arith32-src-dst-Prefixed QI QI .b 0 dsub X #x1 #x2 dsub-sem) 7860(binary-arith32-src-dst-Prefixed HI HI .w 1 dsub X #x1 #x2 dsub-sem) 7861 7862;------------------------------------------------------------- 7863; sub - binary subtraction 7864;------------------------------------------------------------- 7865 7866(define-pmacro (sub-sem mode src1 dst) 7867 (sequence ((mode result)) 7868 (set result (sub mode dst src1)) 7869 (set obit (sub-oflag mode dst src1 0)) 7870 (set cbit (sub-cflag mode dst src1 0)) 7871 (set dst result) 7872 (set-z-and-s result))) 7873 7874; sub.size:G #imm,dst (m16 #1 m32 #1) 7875(binary-arith-imm-dst sub G (f-0-4 7) (f-4-3 3) (f-8-4 5) #x8 #x3 #xE sub-sem) 7876; sub.b:S #imm8,dst3 (m16 #2) 7877(binary-arith16-b-S-imm8-dst3 sub ".b" (f-0-4 8) (f-4-1 1) sub-sem) 7878; sub.BW:G src,dst (m16 #3 m32 #4) 7879(binary-arith-src-dst sub G (f-0-4 #xA) (f-4-3 4) #x1 #xA sub-sem) 7880; sub.B.S src2,r0l/r0h (m16 #4) 7881(binary-arith16-b-S-src2 sub (f-0-4 2) (f-4-1 1) sub-sem) 7882; sub.L:G #imm32,dst (m32 #2) 7883(binary-arith32-imm-dst-defn SI SI .l 0 sub G #x9 #x3 #x1 sub-sem) 7884; sub.BW:S #imm,dst2 (m32 #3) 7885(binary-arith32-s-imm-dst QI .b 0 sub #x0 #x7 sub-sem) 7886(binary-arith32-s-imm-dst HI .w 1 sub #x0 #x7 sub-sem) 7887; sub.L:G src,dst (m32 #5) 7888(binary-arith32-src-dst-defn SI SI .l 1 sub G #x1 #x0 sub-sem) 7889 7890;------------------------------------------------------------- 7891; enter - enter function 7892; exitd - exit and deallocate stack frame 7893;------------------------------------------------------------- 7894 7895(define-pmacro (enter16-sem mach amt) 7896 (sequence () 7897 (set (reg h-sp) (sub (reg h-sp) 2)) 7898 (set (mem16 HI (reg h-sp)) (reg h-fb)) 7899 (set (reg h-fb) (reg h-sp)) 7900 (set (reg h-sp) (sub (reg h-sp) amt)))) 7901 7902(define-pmacro (exit16-sem mach) 7903 (sequence ((SI newpc)) 7904 (set (reg h-sp) (reg h-fb)) 7905 (set (reg h-fb) (mem16 HI (reg h-sp))) 7906 (set (reg h-sp) (add (reg h-sp) 2)) 7907 (set newpc (mem16 HI (reg h-sp))) 7908 (set (reg h-sp) (add (reg h-sp) 2)) 7909 (set newpc (or newpc (sll (mem16 QI (reg h-sp)) (const 16)))) 7910 (set (reg h-sp) (add (reg h-sp) 1)) 7911 (set pc newpc))) 7912 7913(define-pmacro (enter32-sem mach amt) 7914 (sequence () 7915 (set (reg h-sp) (sub (reg h-sp) 4)) 7916 (set (mem32 SI (reg h-sp)) (reg h-fb)) 7917 (set (reg h-fb) (reg h-sp)) 7918 (set (reg h-sp) (sub (reg h-sp) amt)))) 7919 7920(define-pmacro (exit32-sem mach) 7921 (sequence ((SI newpc)) 7922 (set (reg h-sp) (reg h-fb)) 7923 (set (reg h-fb) (mem32 SI (reg h-sp))) 7924 (set (reg h-sp) (add (reg h-sp) 4)) 7925 (set newpc (mem32 SI (reg h-sp))) 7926 (set (reg h-sp) (add (reg h-sp) 4)) 7927 (set pc newpc))) 7928 7929(dni enter16 "enter #Imm-16-QI" ((machine 16)) 7930 ("enter #${Dsp-16-u8}") 7931 (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xF) (f-12-4 2) Dsp-16-u8) 7932 (enter16-sem 16 Dsp-16-u8) 7933 ()) 7934 7935(dni exitd16 "exitd" ((machine 16)) 7936 ("exitd") 7937 (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xF) (f-12-4 2)) 7938 (exit16-sem 16) 7939 ()) 7940 7941(dni enter32 "enter #Imm-8-QI" ((machine 32)) 7942 ("enter #${Dsp-8-u8}") 7943 (+ (f-0-4 #xE) (f-4-4 #xC) Dsp-8-u8) 7944 (enter32-sem 32 Dsp-8-u8) 7945 ()) 7946 7947(dni exitd32 "exitd" ((machine 32)) 7948 ("exitd") 7949 (+ (f-0-4 #xF) (f-4-4 #xC)) 7950 (exit32-sem 32) 7951 ()) 7952 7953;------------------------------------------------------------- 7954; fclr - flag register clear 7955; fset - flag register set 7956;------------------------------------------------------------- 7957 7958(define-pmacro (set-flags-sem flag) 7959 (sequence ((SI tmp)) 7960 (case DFLT flag 7961 ((#x0) (set cbit 1)) 7962 ((#x1) (set dbit 1)) 7963 ((#x2) (set zbit 1)) 7964 ((#x3) (set sbit 1)) 7965 ((#x4) (set bbit 1)) 7966 ((#x5) (set obit 1)) 7967 ((#x6) (set ibit 1)) 7968 ((#x7) (set ubit 1))) 7969 ) 7970 ) 7971 7972(define-pmacro (clear-flags-sem flag) 7973 (sequence ((SI tmp)) 7974 (case DFLT flag 7975 ((#x0) (set cbit 0)) 7976 ((#x1) (set dbit 0)) 7977 ((#x2) (set zbit 0)) 7978 ((#x3) (set sbit 0)) 7979 ((#x4) (set bbit 0)) 7980 ((#x5) (set obit 0)) 7981 ((#x6) (set ibit 0)) 7982 ((#x7) (set ubit 0))) 7983 ) 7984 ) 7985 7986(dni fclr16 "fclr flag" ((machine 16)) 7987 ("fclr ${flags16}") 7988 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) flags16 (f-12-4 5)) 7989 (clear-flags-sem flags16) 7990 ()) 7991 7992(dni fset16 "fset flag" ((machine 16)) 7993 ("fset ${flags16}") 7994 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) flags16 (f-12-4 4)) 7995 (set-flags-sem flags16) 7996 ()) 7997 7998(dni fclr "fclr" ((machine 32)) 7999 ("fclr ${flags32}") 8000 (+ (f-0-4 #xD) (f-4-4 3) (f-8-4 #xE) (f-12-1 1) flags32) 8001 (clear-flags-sem flags32) 8002 ()) 8003 8004(dni fset "fset" ((machine 32)) 8005 ("fset ${flags32}") 8006 (+ (f-0-4 #xD) (f-4-4 1) (f-8-4 #xE) (f-12-1 1) flags32) 8007 (set-flags-sem flags32) 8008 ()) 8009 8010;------------------------------------------------------------- 8011; inc - increment 8012;------------------------------------------------------------- 8013 8014(define-pmacro (inc-sem mode dest) 8015 (sequence ((mode result)) 8016 (set result (add mode dest 1)) 8017 (set-z-and-s result) 8018 (set dest result)) 8019) 8020 8021(dni inc16.b 8022 "inc.b Dst16-3-S-8" 8023 ((machine 16)) 8024 "inc.b ${Dst16-3-S-8}" 8025 (+ (f-0-4 #xA) (f-4-1 #x0) Dst16-3-S-8) 8026 (inc-sem QI Dst16-3-S-8) 8027 ()) 8028 8029(dni inc16.w 8030 "inc.w Dst16An-S" 8031 ((machine 16)) 8032 "inc.w ${Dst16An-S}" 8033 (+ (f-0-4 #xB) (f-5-3 #x2) Dst16An-S) 8034 (inc-sem HI Dst16An-S) 8035 ()) 8036 8037(unary32-defn QI .b 0 inc #xA #x0 #xE inc-sem) 8038(unary32-defn HI .w 1 inc #xA #x0 #xE inc-sem) 8039 8040;------------------------------------------------------------- 8041; freit - fast return from interrupt (m32) 8042; int - interrupt 8043; into - interrupt on overflow 8044;------------------------------------------------------------- 8045 8046; ??? semantics 8047(dni freit32 "FREIT" ((machine 32)) 8048 ("freit") 8049 (+ (f-0-4 9) (f-4-4 #xF)) 8050 (nop) 8051 ()) 8052 8053(dni int16 "int Dsp-10-u6" ((machine 16)) 8054 ("int #${Dsp-10-u6}") 8055 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-2 3) Dsp-10-u6) 8056 (c-call VOID "do_int" pc Dsp-10-u6) 8057 ()) 8058 8059(dni into16 "into" ((machine 16)) 8060 ("into") 8061 (+ (f-0-4 #xF) (f-4-4 6)) 8062 (nop) 8063 ()) 8064 8065(dni int32 "int Dsp-8-u6" ((machine 32)) 8066 ("int #${Dsp-8-u6}") 8067 (+ (f-0-4 #xB) (f-4-4 #xE) Dsp-8-u6 (f-14-2 0)) 8068 (c-call VOID "do_int" pc Dsp-8-u6) 8069 ()) 8070 8071(dni into32 "into" ((machine 32)) 8072 ("into") 8073 (+ (f-0-4 #xB) (f-4-4 #xF)) 8074 (nop) 8075 ()) 8076 8077;------------------------------------------------------------- 8078; index (m32c) 8079;------------------------------------------------------------- 8080 8081; TODO add support to insns allowing index 8082(define-pmacro (indexb-sem mode d) (set SrcIndex d) (set DstIndex d)) 8083(define-pmacro (indexbd-sem mode d) (set SrcIndex (const 0)) (set DstIndex d)) 8084(define-pmacro (indexbs-sem mode d) (set SrcIndex d) (set DstIndex (const 0))) 8085(define-pmacro (indexw-sem mode d) 8086 (set SrcIndex (sll d (const 2))) (set DstIndex (sll d (const 2)))) 8087(define-pmacro (indexwd-sem mode d) 8088 (set SrcIndex (const 0)) (set DstIndex (sll d (const 2)))) 8089(define-pmacro (indexws-sem mode d) 8090 (set SrcIndex (sll d (const 2))) (set DstIndex (const 0))) 8091(define-pmacro (indexl-sem mode d) 8092 (set SrcIndex d) (set DstIndex (sll d (const 2)))) 8093(define-pmacro (indexld-sem mode d) 8094 (set SrcIndex (const 0)) (set DstIndex (sll d (const 2)))) 8095(define-pmacro (indexls-sem mode d) 8096 (set SrcIndex (sll d (const 2))) (set DstIndex (const 0))) 8097 8098; Note that "wbit" not where the size bit goes here, hence, it's 8099; always 0 in these calls but op2 differs instead. 8100 8101; indexb src (index byte) 8102(unary32-defn QI .b 0 indexb #x8 0 #x3 indexb-sem) 8103(unary32-defn HI .w 0 indexb #x8 1 #x3 indexb-sem) 8104; indexbd src (index byte dest) 8105(unary32-defn QI .b 0 indexbd #xA 0 3 indexbd-sem) 8106(unary32-defn HI .w 0 indexbd #xA 1 3 indexbd-sem) 8107; indexbs src (index byte src) 8108(unary32-defn QI .b 0 indexbs #xC 0 3 indexbs-sem) 8109(unary32-defn HI .w 0 indexbs #xC 1 3 indexbs-sem) 8110; indexl src (index long) 8111(unary32-defn QI .b 0 indexl 9 2 3 indexl-sem) 8112(unary32-defn HI .w 0 indexl 9 3 3 indexl-sem) 8113; indexld src (index long dest) 8114(unary32-defn QI .b 0 indexld #xB 2 3 indexld-sem) 8115(unary32-defn HI .w 0 indexld #xB 3 3 indexld-sem) 8116; indexls src (index long src) 8117(unary32-defn QI .b 0 indexls 9 0 3 indexls-sem) 8118(unary32-defn HI .w 0 indexls 9 1 3 indexls-sem) 8119; indexw src (index word) 8120(unary32-defn QI .b 0 indexw 8 2 3 indexw-sem) 8121(unary32-defn HI .w 0 indexw 8 3 3 indexw-sem) 8122; indexwd src (index word dest) 8123(unary32-defn QI .b 0 indexwd #xA 2 3 indexwd-sem) 8124(unary32-defn HI .w 0 indexwd #xA 3 3 indexwd-sem) 8125; indexws (index word src) 8126(unary32-defn QI .b 0 indexws #xC 2 3 indexws-sem) 8127(unary32-defn HI .w 0 indexws #xC 3 3 indexws-sem) 8128 8129;------------------------------------------------------------- 8130; jcc - jump on condition 8131;------------------------------------------------------------- 8132 8133(define-pmacro (jcnd32-sem cnd label) 8134 (sequence () 8135 (case DFLT cnd 8136 ((#x00) (if (not cbit) (set pc label))) ;ltu nc 8137 ((#x01) (if (not (and cbit (not zbit))) (set pc label))) ;leu 8138 ((#x02) (if (not zbit) (set pc label))) ;ne nz 8139 ((#x03) (if (not sbit) (set pc label))) ;pz 8140 ((#x04) (if (not obit) (set pc label))) ;no 8141 ((#x05) (if (not (or zbit (xor sbit obit))) (set pc label))) ;gt 8142 ((#x06) (if (not (xor sbit obit)) (set pc label))) ;ge 8143 ((#x08) (if (trunc BI cbit) (set pc label))) ;geu c 8144 ((#x09) (if (and cbit (not zbit)) (set pc label))) ;gtu 8145 ((#x0a) (if (trunc BI zbit) (set pc label))) ;eq z 8146 ((#x0b) (if (trunc BI sbit) (set pc label))) ;n 8147 ((#x0c) (if (trunc BI obit) (set pc label))) ;o 8148 ((#x0d) (if (or zbit (xor sbit obit)) (set pc label))) ;le 8149 ((#x0e) (if (xor sbit obit) (set pc label))) ;lt 8150 ) 8151 ) 8152 ) 8153 8154(define-pmacro (jcnd16-sem cnd label) 8155 (sequence () 8156 (case DFLT cnd 8157 ((#x00) (if (trunc BI cbit) (set pc label))) ;geu c 8158 ((#x01) (if (and cbit (not zbit)) (set pc label))) ;gtu 8159 ((#x02) (if (trunc BI zbit) (set pc label))) ;eq z 8160 ((#x03) (if (trunc BI sbit) (set pc label))) ;n 8161 ((#x04) (if (not cbit) (set pc label))) ;ltu nc 8162 ((#x05) (if (not (and cbit (not zbit))) (set pc label))) ;leu 8163 ((#x06) (if (not zbit) (set pc label))) ;ne nz 8164 ((#x07) (if (not sbit) (set pc label))) ;pz 8165 ((#x08) (if (or zbit (xor sbit obit)) (set pc label))) ;le 8166 ((#x09) (if (trunc BI obit) (set pc label))) ;o 8167 ((#x0a) (if (not (xor sbit obit)) (set pc label))) ;ge 8168 ((#x0c) (if (not (or zbit (xor sbit obit))) (set pc label))) ;gt 8169 ((#x0d) (if (not obit) (set pc label))) ;no 8170 ((#x0e) (if (xor sbit obit) (set pc label))) ;lt 8171 ) 8172 ) 8173 ) 8174 8175(dni jcnd16-5 8176 "jCnd label" 8177 (RL_JUMP RELAXABLE (machine 16)) 8178 "j$cond16j5 ${Lab-8-8}" 8179 (+ (f-0-4 #x6) (f-4-1 1) cond16j5 Lab-8-8) 8180 (jcnd16-sem cond16j5 Lab-8-8) 8181 () 8182) 8183 8184(dni jcnd16 8185 "jCnd label" 8186 (RL_JUMP RELAXABLE (machine 16)) 8187 "j$cond16j ${Lab-16-8}" 8188 (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xC) cond16j Lab-16-8) 8189 (jcnd16-sem cond16j Lab-16-8) 8190 () 8191) 8192 8193(dni jcnd32 8194 "jCnd label" 8195 (RL_JUMP RELAXABLE (machine 32)) 8196 "j$cond32j ${Lab-8-8}" 8197 (+ (f-0-1 1) (f-4-3 5) cond32j Lab-8-8) 8198 (jcnd32-sem cond32j Lab-8-8) 8199 () 8200) 8201 8202;------------------------------------------------------------- 8203; jmp - jump 8204;------------------------------------------------------------- 8205 8206; jmp.s label3 (m16 #1) 8207(dni jmp16.s "jmp.s Lab-5-3" (RL_JUMP RELAXABLE (machine 16)) 8208 ("jmp.s ${Lab-5-3}") 8209 (+ (f-0-4 6) (f-4-1 0) Lab-5-3) 8210 (sequence () (set pc Lab-5-3)) 8211 ()) 8212; jmp.b label8 (m16 #2) 8213(dni jmp16.b "jmp.b Lab-8-8" (RL_JUMP RELAXABLE (machine 16)) 8214 ("jmp.b ${Lab-8-8}") 8215 (+ (f-0-4 #xF) (f-4-4 #xE) Lab-8-8) 8216 (sequence () (set pc Lab-8-8)) 8217 ()) 8218; jmp.w label16 (m16 #3) 8219(dni jmp16.w "jmp.w Lab-8-16" (RL_JUMP RELAXABLE (machine 16)) 8220 ("jmp.w ${Lab-8-16}") 8221 (+ (f-0-4 #xF) (f-4-4 4) Lab-8-16) 8222 (sequence () (set pc Lab-8-16)) 8223 ()) 8224; jmp.a label24 (m16 #4) 8225(dni jmp16.a "jmp.a Lab-8-24" (RL_JUMP RELAXABLE (machine 16)) 8226 ("jmp.a ${Lab-8-24}") 8227 (+ (f-0-4 #xF) (f-4-4 #xC) Lab-8-24) 8228 (sequence () (set pc Lab-8-24)) 8229 ()) 8230 8231(define-pmacro (jmp16-sem mode dst) 8232 (set pc (and dst #xfffff)) 8233) 8234(define-pmacro (jmp32-sem mode dst) 8235 (set pc dst) 8236) 8237; jmpi.w dst (m16 #1 m32 #2) 8238(unary-insn-defn 16 16 HI .w jmpi (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 2) dst16-16-HI) jmp16-sem) 8239(unary-insn-defn 32 16-Unprefixed HI .w jmpi (+ (f-0-4 #xC) (f-7-1 1) dst32-16-Unprefixed-HI (f-10-2 #x0) (f-12-4 #xF)) jmp32-sem) 8240; jmpi.a dst (m16 #2 m32 #2) 8241(unary-insn-defn 16 16 SI .a jmpi (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 0) dst16-16-SI) jmp16-sem) 8242(unary-insn-defn 32 16-Unprefixed SI .a jmpi (+ (f-0-4 #x8) (f-7-1 0) dst32-16-Unprefixed-SI (f-10-2 #x0) (f-12-4 1)) jmp32-sem) 8243; jmps imm8 (m16 #1) 8244(dni jmps16 "jmps Imm-8-QI" ((machine 16)) 8245 ("jmps #${Imm-8-QI}") 8246 (+ (f-0-4 #xE) (f-4-4 #xE) Imm-8-QI) 8247 (sequence () (set pc Imm-8-QI)) 8248 ()) 8249; jmp.s label3 (m32 #1) 8250(dni jmp32.s 8251 "jmp.s label" 8252 (RL_JUMP RELAXABLE (machine 32)) 8253 "jmp.s ${Lab32-jmp-s}" 8254 (+ (f-0-2 1) (f-4-3 5) Lab32-jmp-s) 8255 (set pc Lab32-jmp-s) 8256 () 8257) 8258; jmp.b label8 (m32 #2) 8259(dni jmp32.b "jmp.b Lab-8-8" (RL_JUMP RELAXABLE (machine 32)) 8260 ("jmp.b ${Lab-8-8}") 8261 (+ (f-0-4 #xB) (f-4-4 #xB) Lab-8-8) 8262 (set pc Lab-8-8) 8263 ()) 8264; jmp.w label16 (m32 #3) 8265(dni jmp32.w "jmp.w Lab-8-16" (RL_JUMP RELAXABLE (machine 32)) 8266 ("jmp.w ${Lab-8-16}") 8267 (+ (f-0-4 #xC) (f-4-4 #xE) Lab-8-16) 8268 (set pc Lab-8-16) 8269 ()) 8270; jmp.a label24 (m32 #4) 8271(dni jmp32.a "jmp.a Lab-8-24" (RL_JUMP RELAXABLE (machine 32)) 8272 ("jmp.a ${Lab-8-24}") 8273 (+ (f-0-4 #xC) (f-4-4 #xC) Lab-8-24) 8274 (set pc Lab-8-24) 8275 ()) 8276; jmp.s imm8 (m32 #1) 8277(dni jmps32 "jmps Imm-8-QI" (RL_JUMP (machine 32)) 8278 ("jmps #${Imm-8-QI}") 8279 (+ (f-0-4 #xD) (f-4-4 #xC) Imm-8-QI) 8280 (set pc Imm-8-QI) 8281 ()) 8282 8283;------------------------------------------------------------- 8284; jsr jump subroutine 8285;------------------------------------------------------------- 8286 8287(define-pmacro (jsr16-sem length dst) 8288 (sequence ((SI tpc)) 8289 (set tpc (add pc length)) 8290 (set (reg h-sp) (sub (reg h-sp) 2)) 8291 (set (mem16 HI (reg h-sp)) (srl (and tpc #xffff00) 8)) 8292 (set (reg h-sp) (sub (reg h-sp) 1)) 8293 (set (mem16 QI (reg h-sp)) (and tpc #xff)) 8294 (set pc dst) 8295 ) 8296) 8297(define-pmacro (jsr32-sem length dst) 8298 (sequence ((SI tpc)) 8299 (set tpc (add pc length)) 8300 (set (reg h-sp) (sub (reg h-sp) 2)) 8301 (set (mem32 HI (reg h-sp)) (srl (and tpc #xffff0000) 16)) 8302 (set (reg h-sp) (sub (reg h-sp) 2)) 8303 (set (mem32 HI (reg h-sp)) (and tpc #xffff)) 8304 (set pc dst) 8305 ) 8306) 8307 8308; jsr.w label16 (m16 #1) 8309(dni jsr16.w "jsr.w Lab-8-16" (RL_JUMP RELAXABLE (machine 16)) 8310 ("jsr.w ${Lab-8-16}") 8311 (+ (f-0-4 #xF) (f-4-4 5) Lab-8-16) 8312 (jsr16-sem 3 Lab-8-16) 8313 ()) 8314; jsr.a label24 (m16 #2) 8315(dni jsr16.a "jsr.a Lab-8-24" (RL_JUMP RELAXABLE (machine 16)) 8316 ("jsr.a ${Lab-8-24}") 8317 (+ (f-0-4 #xF) (f-4-4 #xD) Lab-8-24) 8318 (jsr16-sem 4 Lab-8-24) 8319 ()) 8320(define-pmacro (jsri-defn mode op16 op16-1 op16-2 op16-3 op16-sem 8321 op32 op32-1 op32-2 op32-3 op32-4 op32-sem len) 8322 (begin 8323 (dni (.sym jsri16 mode - op16) 8324 (.str "jsri." mode " " op16) 8325 (RL_1ADDR (machine 16)) 8326 (.str "jsri." mode " ${" op16 "}") 8327 (+ op16-1 op16-2 op16-3 op16) 8328 (op16-sem len op16) 8329 ()) 8330 (dni (.sym jsri32 mode - op32) 8331 (.str "jsri." mode " " op32) 8332 (RL_1ADDR (machine 32)) 8333 (.str "jsri." mode " ${" op32 "}") 8334 (+ op32-1 op32-2 op32-3 op32-4 op32) 8335 (op32-sem len op32) 8336 ()) 8337 ) 8338 ) 8339; jsri.w dst (m16 #1 m32 #1)) 8340(jsri-defn w dst16-16-20ar-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem 8341 dst32-16-24-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 4) 8342(jsri-defn w dst16-16-16sa-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem 8343 dst32-16-16sa-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 4) 8344(jsri-defn w dst16-16-8-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem 8345 dst32-16-8-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 3) 8346(jsri-defn w dst16-basic-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem 8347 dst32-basic-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 2) 8348 8349; jsri.a (m16 #2 m32 #2) 8350(jsri-defn a dst16-16-20ar-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem 8351 dst32-16-24-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 4) 8352(jsri-defn a dst16-16-8-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem 8353 dst32-16-8-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 3) 8354(jsri-defn a dst16-16-16sa-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem 8355 dst32-16-16sa-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 4) 8356(jsri-defn a dst16-basic-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem 8357 dst32-basic-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 2) 8358 8359(dni jsri32.a "jsr.w dst32-16-24-Unprefixed-HI" (RL_1ADDR (machine 32)) 8360 ("jsri.a ${dst32-16-24-Unprefixed-SI}") 8361 (+ (f-0-4 #x9) (f-7-1 0) dst32-16-24-Unprefixed-SI (f-10-2 #x0) (f-12-4 #x1)) 8362 (jsr32-sem 6 dst32-16-24-Unprefixed-SI) 8363 ()) 8364; jsr.w label16 (m32 #1) 8365(dni jsr32.w "jsr.w label" (RL_JUMP RELAXABLE (machine 32)) 8366 ("jsr.w ${Lab-8-16}") 8367 (+ (f-0-4 #xC) (f-4-4 #xF) Lab-8-16) 8368 (jsr32-sem 3 Lab-8-16) 8369 ()) 8370; jsr.a label16 (m32 #2) 8371(dni jsr32.a "jsr.a label" (RL_JUMP (machine 32)) 8372 ("jsr.a ${Lab-8-24}") 8373 (+ (f-0-4 #xC) (f-4-4 #xD) Lab-8-24) 8374 (jsr32-sem 4 Lab-8-24) 8375 ()) 8376; jsrs imm8 (m16 #1) 8377(dni jsrs16 "jsrs Imm-8-QI" ((machine 16)) 8378 ("jsrs #${Imm-8-QI}") 8379 (+ (f-0-4 #xE) (f-4-4 #xF) Imm-8-QI) 8380 (jsr16-sem 2 Imm-8-QI) 8381 ()) 8382; jsrs imm8 (m32 #1) 8383(dni jsrs "jsrs #Imm-8-QI" ((machine 32)) 8384 ("jsrs #${Imm-8-QI}") 8385 (+ (f-0-4 #xD) (f-4-4 #xD) Imm-8-QI) 8386 (jsr32-sem 2 Imm-8-QI) 8387 ()) 8388 8389;------------------------------------------------------------- 8390; ldc - load control register 8391; stc - store control register 8392;------------------------------------------------------------- 8393 8394(define-pmacro (ldc32-cr1-sem src dst) 8395 (sequence () 8396 (case DFLT dst 8397 ((#x0) (set (reg h-dct0) src)) 8398 ((#x1) (set (reg h-dct1) src)) 8399 ((#x2) (sequence ((HI tflag)) 8400 (set tflag src) 8401 (if (and tflag #x1) (set cbit 1)) 8402 (if (and tflag #x2) (set dbit 1)) 8403 (if (and tflag #x4) (set zbit 1)) 8404 (if (and tflag #x8) (set sbit 1)) 8405 (if (and tflag #x10) (set bbit 1)) 8406 (if (and tflag #x20) (set obit 1)) 8407 (if (and tflag #x40) (set ibit 1)) 8408 (if (and tflag #x80) (set ubit 1)))) 8409 ((#x3) (set (reg h-svf) src)) 8410 ((#x4) (set (reg h-drc0) src)) 8411 ((#x5) (set (reg h-drc1) src)) 8412 ((#x6) (set (reg h-dmd0) src)) 8413 ((#x7) (set (reg h-dmd1) src)) 8414 ) 8415 ) 8416) 8417(define-pmacro (ldc32-cr2-sem src dst) 8418 (sequence () 8419 (case DFLT dst 8420 ((#x0) (set (reg h-intb) src)) 8421 ((#x1) (set (reg h-sp) src)) 8422 ((#x2) (set (reg h-sb) src)) 8423 ((#x3) (set (reg h-fb) src)) 8424 ((#x4) (set (reg h-svp) src)) 8425 ((#x5) (set (reg h-vct) src)) 8426 ((#x7) (set (reg h-isp) src)) 8427 ) 8428 ) 8429) 8430(define-pmacro (ldc32-cr3-sem src dst) 8431 (sequence () 8432 (case DFLT dst 8433 ((#x2) (set (reg h-dma0) src)) 8434 ((#x3) (set (reg h-dma1) src)) 8435 ((#x4) (set (reg h-dra0) src)) 8436 ((#x5) (set (reg h-dra1) src)) 8437 ((#x6) (set (reg h-dsa0) src)) 8438 ((#x7) (set (reg h-dsa1) src)) 8439 ) 8440 ) 8441) 8442(define-pmacro (ldc16-sem src dst) 8443 (sequence () 8444 (case DFLT dst 8445 ((#x1) (set (reg h-intb) src)) 8446 ((#x2) (set (reg h-intb) (or (reg h-intb) (sll src (const 16))))) 8447 ((#x3) (sequence ((HI tflag)) 8448 (set tflag src) 8449 (if (and tflag #x1) (set cbit 1)) 8450 (if (and tflag #x2) (set dbit 1)) 8451 (if (and tflag #x4) (set zbit 1)) 8452 (if (and tflag #x8) (set sbit 1)) 8453 (if (and tflag #x10) (set bbit 1)) 8454 (if (and tflag #x20) (set obit 1)) 8455 (if (and tflag #x40) (set ibit 1)) 8456 (if (and tflag #x80) (set ubit 1)))) 8457 ((#x4) (set (reg h-isp) src)) 8458 ((#x5) (set (reg h-sp) src)) 8459 ((#x6) (set (reg h-sb) src)) 8460 ((#x7) (set (reg h-fb) src)) 8461 ) 8462 ) 8463) 8464 8465(define-pmacro (stc32-cr1-sem src dst) 8466 (sequence () 8467 (case DFLT src 8468 ((#x0) (set dst (reg h-dct0))) 8469 ((#x1) (set dst (reg h-dct1))) 8470 ((#x2) (sequence ((HI tflag)) 8471 (set tflag 0) 8472 (if (eq cbit 1) (set tflag (or tflag #x1))) 8473 (if (eq dbit 1) (set tflag (or tflag #x2))) 8474 (if (eq zbit 1) (set tflag (or tflag #x4))) 8475 (if (eq sbit 1) (set tflag (or tflag #x8))) 8476 (if (eq bbit 1) (set tflag (or tflag #x10))) 8477 (if (eq obit 1) (set tflag (or tflag #x20))) 8478 (if (eq ibit 1) (set tflag (or tflag #x40))) 8479 (if (eq ubit 1) (set tflag (or tflag #x80))) 8480 (set dst tflag))) 8481 ((#x3) (set dst (reg h-svf))) 8482 ((#x4) (set dst (reg h-drc0))) 8483 ((#x5) (set dst (reg h-drc1))) 8484 ((#x6) (set dst (reg h-dmd0))) 8485 ((#x7) (set dst (reg h-dmd1))) 8486 ) 8487 ) 8488) 8489(define-pmacro (stc32-cr2-sem src dst) 8490 (sequence () 8491 (case DFLT src 8492 ((#x0) (set dst (reg h-intb))) 8493 ((#x1) (set dst (reg h-sp))) 8494 ((#x2) (set dst (reg h-sb))) 8495 ((#x3) (set dst (reg h-fb))) 8496 ((#x4) (set dst (reg h-svp))) 8497 ((#x5) (set dst (reg h-vct))) 8498 ((#x7) (set dst (reg h-isp))) 8499 ) 8500 ) 8501) 8502(define-pmacro (stc32-cr3-sem src dst) 8503 (sequence () 8504 (case DFLT src 8505 ((#x2) (set dst (reg h-dma0))) 8506 ((#x3) (set dst (reg h-dma1))) 8507 ((#x4) (set dst (reg h-dra0))) 8508 ((#x5) (set dst (reg h-dra1))) 8509 ((#x6) (set dst (reg h-dsa0))) 8510 ((#x7) (set dst (reg h-dsa1))) 8511 ) 8512 ) 8513) 8514(define-pmacro (stc16-sem src dst) 8515 (sequence () 8516 (case DFLT src 8517 ((#x1) (set dst (and (reg h-intb) (const #xffff)))) 8518 ((#x2) (set dst (srl (reg h-intb) (const 16)))) 8519 ((#x3) (sequence ((HI tflag)) 8520 (set tflag 0) 8521 (if (eq cbit 1) (set tflag (or tflag #x1))) 8522 (if (eq dbit 1) (set tflag (or tflag #x2))) 8523 (if (eq zbit 1) (set tflag (or tflag #x4))) 8524 (if (eq sbit 1) (set tflag (or tflag #x8))) 8525 (if (eq bbit 1) (set tflag (or tflag #x10))) 8526 (if (eq obit 1) (set tflag (or tflag #x20))) 8527 (if (eq ibit 1) (set tflag (or tflag #x40))) 8528 (if (eq ubit 1) (set tflag (or tflag #x80))) 8529 (set dst tflag))) 8530 ((#x4) (set dst (reg h-isp))) 8531 ((#x5) (set dst (reg h-sp))) 8532 ((#x6) (set dst (reg h-sb))) 8533 ((#x7) (set dst (reg h-fb))) 8534 ) 8535 ) 8536) 8537 8538(dni ldc16.imm16 "ldc #imm,dst" ((machine 16)) 8539 ("ldc #${Imm-16-HI},${cr16}") 8540 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) (f-12-4 0) cr16 Imm-16-HI) 8541 (ldc16-sem Imm-16-HI cr16) 8542 ()) 8543 8544(dni ldc16.dst "ldc src,dest" ((machine 16)) 8545 ("ldc ${dst16-16-HI},${cr16}") 8546 (+ (f-0-4 7) (f-4-4 #xA) (f-8-1 1) cr16 dst16-16-HI) 8547 (ldc16-sem dst16-16-HI cr16) 8548 ()) 8549; ldc src,dest (m32c #4) 8550(dni ldc32.src-cr1 "ldc src,dst" ((machine 32)) 8551 ("ldc ${dst32-24-Prefixed-HI},${cr1-Prefixed-32}") 8552 (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xD) dst32-24-Prefixed-HI (f-15-1 1) (f-18-2 0) (f-20-1 1) cr1-Prefixed-32) 8553 (ldc32-cr1-sem dst32-24-Prefixed-HI cr1-Prefixed-32) 8554 ()) 8555; ldc src,dest (m32c #5) 8556(dni ldc32.src-cr2 "ldc src,dest" ((machine 32)) 8557 ("ldc ${dst32-16-Unprefixed-SI},${cr2-32}") 8558 (+ (f-0-4 #xD) dst32-16-Unprefixed-SI (f-7-1 1) (f-10-2 0) (f-12-1 0) cr2-32) 8559 (ldc32-cr2-sem dst32-16-Unprefixed-SI cr2-32) 8560 ()) 8561; ldc src,dest (m32c #6) 8562(dni ldc32.src-cr3 "ldc src,dst" ((machine 32)) 8563 ("ldc ${dst32-24-Prefixed-SI},${cr3-Prefixed-32}") 8564 (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xD) dst32-24-Prefixed-SI (f-15-1 1) (f-18-2 0) (f-20-1 0) cr3-Prefixed-32) 8565 (ldc32-cr3-sem dst32-24-Prefixed-SI cr3-Prefixed-32) 8566 ()) 8567; ldc src,dest (m32c #1) 8568(dni ldc32.imm16-cr1 "ldc #imm,dst" ((machine 32)) 8569 ("ldc #${Imm-16-HI},${cr1-Unprefixed-32}") 8570 (+ (f-0-4 #xD) (f-4-4 5) (f-8-4 #xA) (f-12-1 1) cr1-Unprefixed-32 Imm-16-HI) 8571 (ldc32-cr1-sem Imm-16-HI cr1-Unprefixed-32) 8572 ()) 8573; ldc src,dest (m32c #2) 8574(dni ldc32.imm16-cr2 "ldc #imm,dst" ((machine 32)) 8575 ("ldc #${Dsp-16-u24},${cr2-32}") 8576 (+ (f-0-4 #xD) (f-4-4 5) (f-8-4 2) (f-12-1 1) cr2-32 Dsp-16-u24) 8577 (ldc32-cr2-sem Dsp-16-u24 cr2-32) 8578 ()) 8579; ldc src,dest (m32c #3) 8580(dni ldc32.imm16-cr3 "ldc #imm,dst" ((machine 32)) 8581 ("ldc #${Dsp-16-u24},${cr3-Unprefixed-32}") 8582 (+ (f-0-4 #xD) (f-4-4 5) (f-8-4 6) (f-12-1 1) cr3-Unprefixed-32 Dsp-16-u24) 8583 (ldc32-cr3-sem Dsp-16-u24 cr3-Unprefixed-32) 8584 ()) 8585 8586(dni stc16.src "stc src,dest" ((machine 16)) 8587 ("stc ${cr16},${dst16-16-HI}") 8588 (+ (f-0-4 7) (f-4-4 #xB) (f-8-1 1) cr16 dst16-16-HI) 8589 (stc16-sem cr16 dst16-16-HI ) 8590 ()) 8591 8592(dni stc16.pc "stc pc,dest" ((machine 16)) 8593 ("stc pc,${dst16-16-HI}") 8594 (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xC) dst16-16-HI) 8595 (sequence () (set dst16-16-HI (reg h-pc))) 8596 ()) 8597 8598(dni stc32.src-cr1 "stc src,dst" ((machine 32)) 8599 ("stc ${cr1-Prefixed-32},${dst32-24-Prefixed-HI}") 8600 (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xD) dst32-24-Prefixed-HI (f-15-1 1) (f-18-2 1) (f-20-1 1) cr1-Prefixed-32) 8601 (stc32-cr1-sem cr1-Prefixed-32 dst32-24-Prefixed-HI ) 8602 ()) 8603 8604(dni stc32.src-cr2 "stc src,dest" ((machine 32)) 8605 ("stc ${cr2-32},${dst32-16-Unprefixed-SI}") 8606 (+ (f-0-4 #xD) dst32-16-Unprefixed-SI (f-7-1 1) (f-10-2 0) (f-12-1 2) cr2-32) 8607 (stc32-cr2-sem cr2-32 dst32-16-Unprefixed-SI ) 8608 ()) 8609 8610(dni stc32.src-cr3 "stc src,dst" ((machine 32)) 8611 ("stc ${cr3-Prefixed-32},${dst32-24-Prefixed-SI}") 8612 (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xD) dst32-24-Prefixed-SI (f-15-1 1) (f-18-2 1) (f-20-1 0) cr3-Prefixed-32) 8613 (stc32-cr3-sem cr3-Prefixed-32 dst32-24-Prefixed-SI ) 8614 ()) 8615 8616;------------------------------------------------------------- 8617; ldctx - load context 8618; stctx - store context 8619;------------------------------------------------------------- 8620 8621; ??? semantics 8622(dni ldctx16 "ldctx abs16,abs24" ((machine 16)) 8623 ("ldctx ${Dsp-16-u16},${Dsp-32-u24}") 8624 (+ (f-0-4 #x7) (f-4-4 #xC) (f-8-4 #xF) (f-12-4 #x0) Dsp-16-u16 Dsp-32-u24) 8625 (nop) 8626 ()) 8627(dni ldctx32 "ldctx abs16,abs24" ((machine 32)) 8628 ("ldctx ${Dsp-16-u16},${Dsp-32-u24}") 8629 (+ (f-0-4 #xB) (f-4-4 #x6) (f-8-4 #xC) (f-12-4 #x3) Dsp-16-u16 Dsp-32-u24) 8630 (nop) 8631 ()) 8632(dni stctx16 "stctx abs16,abs24" ((machine 16)) 8633 ("stctx ${Dsp-16-u16},${Dsp-32-u24}") 8634 (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xF) (f-12-4 #x0) Dsp-16-u16 Dsp-32-u24) 8635 (nop) 8636 ()) 8637(dni stctx32 "stctx abs16,abs24" ((machine 32)) 8638 ("stctx ${Dsp-16-u16},${Dsp-32-u24}") 8639 (+ (f-0-4 #xB) (f-4-4 #x6) (f-8-4 #xD) (f-12-4 #x3) Dsp-16-u16 Dsp-32-u24) 8640 (nop) 8641 ()) 8642 8643;------------------------------------------------------------- 8644; lde - load from extra far data area (m16) 8645; ste - store to extra far data area (m16) 8646;------------------------------------------------------------- 8647 8648(lde-dst QI .b 0) 8649(lde-dst HI .w 1) 8650 8651(ste-dst QI .b 0) 8652(ste-dst HI .w 1) 8653 8654;------------------------------------------------------------- 8655; ldipl - load interrupt permission level 8656;------------------------------------------------------------- 8657 8658; ??? semantics 8659; ldintb <==> ldc #imm,intbh ; ldc #imm,intbl 8660 8661(dni ldipl16.imm "ldipl #imm" ((machine 16)) 8662 ("ldipl #${Imm-13-u3}") 8663 (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xA) (f-12-1 0) Imm-13-u3) 8664 (nop) 8665 ()) 8666(dni ldipl32.imm "ldipl #imm" ((machine 32)) 8667 ("ldipl #${Imm-13-u3}") 8668 (+ (f-0-4 #xD) (f-4-4 5) (f-8-4 #xE) (f-12-1 1) Imm-13-u3) 8669 (nop) 8670 ()) 8671 8672 8673;------------------------------------------------------------- 8674; max - maximum value 8675;------------------------------------------------------------- 8676 8677; TODO check semantics for min -1,0 8678(define-pmacro (max-sem mode src dst) 8679 (sequence () 8680 (if (gt mode src dst) 8681 (set mode dst src))) 8682) 8683 8684; max.size:G #imm,dst 8685(binary-arith32-imm-dst-Prefixed QI QI .b 0 max X #x8 #x3 #xF max-sem) 8686(binary-arith32-imm-dst-Prefixed HI HI .w 1 max X #x8 #x3 #xF max-sem) 8687 8688; max.BW:G src,dst 8689(binary-arith32-src-dst-Prefixed QI QI .b 0 max X #x1 #xD max-sem) 8690(binary-arith32-src-dst-Prefixed HI HI .w 1 max X #x1 #xD max-sem) 8691 8692;------------------------------------------------------------- 8693; min - minimum value 8694;------------------------------------------------------------- 8695 8696(define-pmacro (min-sem mode src dst) 8697 (sequence () 8698 (if (lt mode src dst) 8699 (set mode dst src))) 8700) 8701 8702; min.size:G #imm,dst 8703(binary-arith32-imm-dst-Prefixed QI QI .b 0 min X #x8 #x2 #xF min-sem) 8704(binary-arith32-imm-dst-Prefixed HI HI .w 1 min X #x8 #x2 #xF min-sem) 8705 8706; min.BW:G src,dst 8707(binary-arith32-src-dst-Prefixed QI QI .b 0 min X #x1 #xC min-sem) 8708(binary-arith32-src-dst-Prefixed HI HI .w 1 min X #x1 #xC min-sem) 8709 8710;------------------------------------------------------------- 8711; mov - move 8712;------------------------------------------------------------- 8713 8714(define-pmacro (mov-sem mode src1 dst) 8715 (sequence ((mode result)) 8716 (set result src1) 8717 (set-z-and-s result) 8718 (set mode dst src1)) 8719) 8720 8721(define-pmacro (mov-dspsp-dst-sem mach mode src1 dst) 8722 (set dst (mem-mach mach mode (add sp src1))) 8723) 8724 8725(define-pmacro (mov-src-dspsp-sem mach mode src dst1) 8726 (set (mem-mach mach mode (add sp dst1)) src) 8727) 8728 8729(define-pmacro (mov16-imm-an-defn size mode imm regn op1 op2) 8730 (dni (.sym mov16. size .S-imm- regn) 8731 (.str "mov." size ":S " imm "," regn) 8732 ((machine 16)) 8733 (.str "mov." size "$S #${" imm "}," regn) 8734 (+ op1 op2 imm) 8735 (mov-sem mode imm (reg (.sym h- regn))) 8736 ()) 8737) 8738; mov.size:G #imm,dst (m16 #1 m32 #1) 8739(binary-arith-imm-dst mov G (f-0-4 7) (f-4-3 2) (f-8-4 #xC) #x9 #x2 #xF mov-sem) 8740; mov.L:G #imm32,dst (m32 #2) 8741(binary-arith32-imm-dst-defn SI SI .l 0 mov G #xB #x3 #x1 mov-sem) 8742; mov.BW:S #imm,dst2 (m32 #4) 8743(binary-arith32-s-imm-dst QI .b 0 mov #x0 #x2 mov-sem) 8744(binary-arith32-s-imm-dst HI .w 1 mov #x0 #x2 mov-sem) 8745; mov.b:S #imm8,dst3 (m16 #3) 8746(binary-arith16-b-S-imm8-dst3 mov ".b" (f-0-4 #xC) (f-4-1 0) mov-sem) 8747; mov.b:S #imm8,aN (m16 #4) 8748(mov16-imm-an-defn b QI Imm-8-QI a0 (f-0-4 #xE) (f-4-4 2)) 8749(mov16-imm-an-defn b QI Imm-8-QI a1 (f-0-4 #xE) (f-4-4 #xA)) 8750(mov16-imm-an-defn w HI Imm-8-HI a0 (f-0-4 #xA) (f-4-4 2)) 8751(mov16-imm-an-defn w HI Imm-8-HI a1 (f-0-4 #xA) (f-4-4 #xA)) 8752; mov.WL:S #imm,A0/A1 (m32 #5) 8753(define-pmacro (mov32-wl-s-defn mode sz op1 imm regn op2) 8754 (dni (.sym mov32- sz - regn) 8755 (.str "mov." sz ":s" imm "," regn) 8756 ((machine 32)) 8757 (.str "mov." sz "$S #${" imm "}," regn) 8758 (+ (f-0-4 op1) (f-4-4 op2) imm) 8759 (mov-sem mode imm (reg (.sym h- regn))) 8760 ()) 8761) 8762(mov32-wl-s-defn HI w #x9 Imm-8-HI a0 #xC) 8763(mov32-wl-s-defn HI w #x9 Imm-8-HI a1 #xD) 8764(mov32-wl-s-defn SI l #xB Dsp-8-s24 a0 #xC) 8765(mov32-wl-s-defn SI l #xB Dsp-8-s24 a1 #xD) 8766 8767; mov.size:Q #imm4,dst (m16 #2 m32 #3) 8768(binary-arith16-imm4-dst-defn QI .b 0 0 mov (f-0-4 #xD) (f-4-3 4) mov-sem) 8769(binary-arith16-imm4-dst-defn HI .w 0 1 mov (f-0-4 #xD) (f-4-3 4) mov-sem) 8770(binary-arith32-imm4-dst-defn QI .b 1 0 mov #x7 #x2 mov-sem) 8771(binary-arith32-imm4-dst-defn HI .w 1 1 mov #x7 #x2 mov-sem) 8772 8773; mov.BW:Z #0,dst (m16 #5 m32 #6) 8774(dni mov16.b-Z-imm8-dst3 8775 "mov.b:Z #0,Dst16-3-S-8" 8776 ((machine 16)) 8777 "mov.b$Z #0,${Dst16-3-S-8}" 8778 (+ (f-0-4 #xB) (f-4-1 #x0) Dst16-3-S-8) 8779 (mov-sem QI (const 0) Dst16-3-S-8) 8780 ()) 8781; (binary-arith16-b-Z-imm8-dst3 mov ".b" (f-0-4 #xB) (f-4-1 0) mov-sem) 8782(binary-arith32-z-imm-dst QI .b 0 mov #x0 #x1 mov-sem) 8783(binary-arith32-z-imm-dst HI .w 1 mov #x0 #x1 mov-sem) 8784; mov.BW:G src,dst (m16 #6 m32 #7) 8785(binary-arith-src-dst mov G (f-0-4 #x7) (f-4-3 1) #x1 #xB mov-sem) 8786; mov.B:S src2,a0/a1 (m16 #7) 8787(dni (.sym mov 16 .b.S-An) 8788 (.str mov ".b:S src2,a[01]") 8789 ((machine 16)) 8790 (.str mov ".b$S ${src16-2-S},${Dst16AnQI-S}") 8791 (+ (f-0-4 #x3) (f-4-1 0) Dst16AnQI-S src16-2-S) 8792 (mov-sem QI src16-2-S Dst16AnQI-S) 8793 ()) 8794(define-pmacro (mov16-b-s-an-defn op1 op2 op2c) 8795 (dni (.sym mov16.b.S- op1 - op2) 8796 (.str mov ".b:S " op1 "," op2) 8797 ((machine 16)) 8798 (.str mov ".b$S " op1 "," op2) 8799 (+ (f-0-4 #x3) op2c) 8800 (mov-sem QI (reg (.sym h- op1)) (reg (.sym h- op2))) 8801 ()) 8802 ) 8803(mov16-b-s-an-defn r0l a1 (f-4-4 #x4)) 8804(mov16-b-s-an-defn r0h a0 (f-4-4 #x0)) 8805 8806; mov.L:G src,dst (m32 #8) 8807(binary-arith32-src-dst-defn SI SI .l 1 mov G #x1 #x3 mov-sem) 8808; mov.B:S r0l/r0h,dst2 (m16 #8) 8809(dni (.sym mov 16 .b.S-Rn-An) 8810 (.str mov ".b:S r0[lh],src2") 8811 ((machine 16)) 8812 (.str mov ".b$S ${Dst16RnQI-S},${src16-2-S}") 8813 (+ (f-0-4 #x0) (f-4-1 0) Dst16RnQI-S src16-2-S) 8814 (mov-sem QI src16-2-S Dst16RnQI-S) 8815 ()) 8816 8817; mov.B.S src2,r0l/r0h (m16 #9) 8818(binary-arith16-b-S-src2 mov (f-0-4 0) (f-4-1 1) mov-sem) 8819 8820; mov.BW:S src2,r0l/r0 (m32 #9) 8821; mov.BW:S src2,r1l/r1 (m32 #10) 8822(define-pmacro (mov32-src-r sz szcode mode src dst opc1 opc2) 8823 (begin 8824 (dni (.sym mov32. sz - src - dst) 8825 (.str "mov." sz "src," dst) 8826 ((machine 32)) 8827 (.str "mov." sz "$S ${" (.sym src - mode) "}," dst) 8828 (+ (f-0-2 opc1) (.sym src - mode) (f-4-3 opc2) (f-7-1 szcode)) 8829 (mov-sem mode (.sym src - mode) (reg (.sym h- dst))) 8830 ()) 8831 ) 8832 ) 8833(mov32-src-r b 0 QI dst32-2-S-16 r0l 0 4) 8834(mov32-src-r w 1 HI dst32-2-S-16 r0 0 4) 8835(mov32-src-r b 0 QI dst32-2-S-8 r0l 0 4) 8836(mov32-src-r w 1 HI dst32-2-S-8 r0 0 4) 8837(mov32-src-r b 0 QI dst32-2-S-basic r1l 1 7) 8838(mov32-src-r w 1 HI dst32-2-S-basic r1 1 7) 8839(mov32-src-r b 0 QI dst32-2-S-16 r1l 1 7) 8840(mov32-src-r w 1 HI dst32-2-S-16 r1 1 7) 8841(mov32-src-r b 0 QI dst32-2-S-8 r1l 1 7) 8842(mov32-src-r w 1 HI dst32-2-S-8 r1 1 7) 8843 8844; mov.BW:S r0l/r0,dst2 (m32 #11) 8845(define-pmacro (mov32-r-dest sz szcode mode src dst opc1 opc2) 8846 (begin 8847 (dni (.sym mov32. sz - src - dst) 8848 (.str "mov." sz "src," dst) 8849 ((machine 32)) 8850 (.str "mov." sz "$S " src ",${" (.sym dst - mode) "}") 8851 (+ (f-0-2 opc1) (.sym dst - mode) (f-4-3 opc2) (f-7-1 szcode)) 8852 (mov-sem mode (reg (.sym h- src)) (.sym dst - mode)) 8853 ()) 8854 ) 8855 ) 8856(mov32-r-dest b 0 QI r0l dst32-2-S-16 0 0) 8857(mov32-r-dest w 1 HI r0 dst32-2-S-16 0 0) 8858(mov32-r-dest b 0 QI r0l dst32-2-S-8 0 0) 8859(mov32-r-dest w 1 HI r0 dst32-2-S-8 0 0) 8860 8861; mov.L:S src,A0/A1 (m32 #12) 8862(define-pmacro (mov32-src-a src dst dstcode opc1 opc2) 8863 (begin 8864 (dni (.sym mov32. sz - src - dst) 8865 (.str "mov." sz "src," dst) 8866 ((machine 32)) 8867 (.str "mov.l" "$S ${" (.sym src - SI) "}," dst) 8868 (+ (f-0-2 opc1) (.sym src - SI) (f-4-3 opc2) (f-7-1 dstcode)) 8869 (mov-sem SI (.sym src - SI) (reg (.sym h- dst))) 8870 ()) 8871 ) 8872 ) 8873(mov32-src-a dst32-2-S-16 a0 0 1 4) 8874(mov32-src-a dst32-2-S-16 a1 1 1 4) 8875(mov32-src-a dst32-2-S-8 a0 0 1 4) 8876(mov32-src-a dst32-2-S-8 a1 1 1 4) 8877 8878; mov.BW:G dsp8[sp],dst (m16 #10 m32 #13) 8879; mov.BW:G src,dsp8[sp] (m16 #11 m32 #14) 8880(mov-dspsp-dst mov (f-0-4 #x7) (f-4-3 2) (f-8-4 #xB) #xB #x0 #xF mov-dspsp-dst-sem) 8881(mov-src-dspsp mov (f-0-4 #x7) (f-4-3 2) (f-8-4 #x3) #xA #x0 #xF mov-src-dspsp-sem) 8882 8883;------------------------------------------------------------- 8884; mova - move effective address 8885;------------------------------------------------------------- 8886 8887(define-pmacro (mov16a-defn dst dstop dstcode) 8888 (dni (.sym mova16. src - dst) 8889 (.str "mova src," dst) 8890 ((machine 16)) 8891 (.str "mova ${dst16-16-Mova-HI}," dst) 8892 (+ (f-0-4 #xE) (f-4-4 #xB) dst16-16-Mova-HI (f-8-4 dstcode)) 8893 (sequence () (set HI (reg dstop) dst16-16-Mova-HI)) 8894 ()) 8895) 8896(mov16a-defn r0 h-r0 0) 8897(mov16a-defn r1 h-r1 1) 8898(mov16a-defn r2 h-r2 2) 8899(mov16a-defn r3 h-r3 3) 8900(mov16a-defn a0 h-a0 4) 8901(mov16a-defn a1 h-a1 5) 8902 8903(define-pmacro (mov32a-defn dst dstop dstcode) 8904 (dni (.sym mova32. src - dst) 8905 (.str "mova src," dst) 8906 ((machine 32)) 8907 (.str "mova ${dst32-16-Unprefixed-Mova-SI}," dst) 8908 (+ (f-0-4 #xD) dst32-16-Unprefixed-Mova-SI (f-7-1 1) (f-10-2 1) (f-12-1 1) (f-13-3 dstcode)) 8909 (sequence () (set SI (reg dstop) dst32-16-Unprefixed-Mova-SI)) 8910 ()) 8911) 8912(mov32a-defn r2r0 h-r2r0 0) 8913(mov32a-defn r3r1 h-r3r1 1) 8914(mov32a-defn a0 h-a0 2) 8915(mov32a-defn a1 h-a1 3) 8916 8917;------------------------------------------------------------- 8918; movDir - move nibble 8919;------------------------------------------------------------- 8920 8921(define-pmacro (movdir-sem nib src dst) 8922 (sequence ((SI tmp)) 8923 (case DFLT nib 8924 ((0) (set dst (or (and dst #xf0) (and src #xf)))) 8925 ((1) (set dst (or (and dst #x0f) (sll (and src #xf) 4)))) 8926 ((2) (set dst (or (and dst #xf0) (srl (and src #xf0) 4)))) 8927 ((3) (set dst (or (and dst #x0f) (and src #xf0)))) 8928 ) 8929 ) 8930 ) 8931; movDir src,dst 8932(define-pmacro (mov16dir-1-defn nib dircode dir) 8933 (dni (.sym mov nib 16 ".r0l-dst") 8934 (.str "mov" nib " r0l,dst") 8935 ((machine 16)) 8936 (.str "mov" nib " r0l,${dst16-16-QI}") 8937 (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 dir) dst16-16-QI) 8938 (movdir-sem dircode (reg h-r0l) dst16-16-QI) 8939 ()) 8940) 8941(mov16dir-1-defn ll 0 8) 8942(mov16dir-1-defn lh 1 #xA) 8943(mov16dir-1-defn hl 2 9) 8944(mov16dir-1-defn hh 3 #xB) 8945(define-pmacro (mov16dir-2-defn nib dircode dir) 8946 (dni (.sym mov nib 16 ".src-r0l") 8947 (.str "mov" nib " src,r0l") 8948 ((machine 16)) 8949 (.str "mov" nib " ${dst16-16-QI},r0l") 8950 (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 dir) dst16-16-QI) 8951 (movdir-sem dircode dst16-16-QI (reg h-r0l)) 8952 ()) 8953) 8954(mov16dir-2-defn ll 0 0) 8955(mov16dir-2-defn lh 1 2) 8956(mov16dir-2-defn hl 2 1) 8957(mov16dir-2-defn hh 3 3) 8958 8959(define-pmacro (mov32dir-1-defn nib o1o0) 8960 (dni (.sym mov nib 32 ".r0l-dst") 8961 (.str "mov" nib " r0l,dst") 8962 ((machine 32)) 8963 (.str "mov" nib " r0l,${dst32-24-Prefixed-QI}") 8964 (+ (f-0-4 #x0) (f-4-4 #x1) (f-8-4 #xB) dst32-24-Prefixed-QI (f-15-1 0) (f-18-2 o1o0) (f-20-4 #xE)) 8965 (movdir-sem o1o0 (reg h-r0l) dst32-24-Prefixed-QI) 8966 ()) 8967) 8968(mov32dir-1-defn ll 0) 8969(mov32dir-1-defn lh 1) 8970(mov32dir-1-defn hl 2) 8971(mov32dir-1-defn hh 3) 8972(define-pmacro (mov32dir-2-defn nib o1o0) 8973 (dni (.sym mov nib 32 ".src-r0l") 8974 (.str "mov" nib " src,r0l") 8975 ((machine 32)) 8976 (.str "mov" nib " ${dst32-24-Prefixed-QI},r0l") 8977 (+ (f-0-4 #x0) (f-4-4 #x1) (f-8-4 #xA) dst32-24-Prefixed-QI (f-15-1 0) (f-18-2 o1o0) (f-20-4 #xE)) 8978 (movdir-sem o1o0 dst32-24-Prefixed-QI (reg h-r0l)) 8979 ()) 8980) 8981(mov32dir-2-defn ll 0) 8982(mov32dir-2-defn lh 1) 8983(mov32dir-2-defn hl 2) 8984(mov32dir-2-defn hh 3) 8985 8986;------------------------------------------------------------- 8987; movx - move extend sign (m32) 8988;------------------------------------------------------------- 8989 8990(define-pmacro (movx-sem mode src dst) 8991 (sequence ((SI source) (SI result)) 8992 (set SI result src) 8993 (set-z-and-s result) 8994 (set dst result)) 8995) 8996 8997; movx #imm,dst 8998(binary-arith32-imm-dst-defn QI SI "" 0 movx X #xB #x1 #x1 movx-sem) 8999 9000;------------------------------------------------------------- 9001; mul - multiply 9002;------------------------------------------------------------- 9003 9004(define-pmacro (mul-sem mode src1 dst) 9005 (sequence ((mode result)) 9006 (set obit (add-oflag mode src1 dst 0)) 9007 (set result (mul mode src1 dst)) 9008 (set dst result)) 9009) 9010 9011; mul.BW #imm,dst 9012(binary-arith-imm-dst mul G (f-0-4 7) (f-4-3 6) (f-8-4 5) #x8 #x1 #xF mul-sem) 9013; mul.BW src,dst 9014(binary-arith-src-dst mul G (f-0-4 #x7) (f-4-3 4) #x1 #xC mul-sem) 9015 9016(dni mul_l "mul.l src,r2r0" ((machine 32)) 9017 ("mul.l ${dst32-24-Prefixed-SI},r2r0") 9018 (+ (f-0-4 #x0) (f-4-4 #x1) (f-8-4 #x8) (f-15-1 #x1) (f-18-2 #x1) (f-20-4 #xf) 9019 dst32-24-Prefixed-SI) 9020 () ()) 9021 9022(dni mulu_l "mulu.l src,r2r0" ((machine 32)) 9023 ("mulu.l ${dst32-24-Prefixed-SI},r2r0") 9024 (+ (f-0-4 #x0) (f-4-4 #x1) (f-8-4 #x8) (f-15-1 #x1) (f-18-2 #x0) (f-20-4 #xf) 9025 dst32-24-Prefixed-SI) 9026 () ()) 9027;------------------------------------------------------------- 9028; mulex - multiple extend sign (m32) 9029;------------------------------------------------------------- 9030 9031; mulex src,dst 9032; (dni mulex-absolute-indirect "mulex [src]" ((machine 32)) 9033; ("mulex ${dst32-24-absolute-indirect-HI}") 9034; (+ (f-0-4 0) (f-4-4 9) (f-8-4 #xC) dst32-24-absolute-indirect-HI (f-15-1 1) (f-18-2 3) (f-20-4 #xE)) 9035; (set R1R2R0 (mul DI (ext DI R2R0) (ext DI dst32-24-absolute-indirect-HI))) 9036; ()) 9037(dni mulex "mulex src" ((machine 32)) 9038 ("mulex ${dst32-16-Unprefixed-Mulex-HI}") 9039 (+ (f-0-4 #xC) dst32-16-Unprefixed-Mulex-HI (f-7-1 1) (f-10-2 3) (f-12-4 #xE)) 9040 (set R1R2R0 (mul DI (ext DI R2R0) (ext DI dst32-16-Unprefixed-Mulex-HI))) 9041 ()) 9042; (dni mulex-indirect "mulex [src]" ((machine 32)) 9043; ("mulex ${dst32-24-indirect-HI}") 9044; (+ (f-0-4 0) (f-4-4 9) (f-8-4 #xC) dst32-24-indirect-HI (f-15-1 1) (f-18-2 3) (f-20-4 #xE)) 9045; (set R1R2R0 (mul DI (ext DI R2R0) (ext DI dst32-24-indirect-HI))) 9046; ()) 9047 9048;------------------------------------------------------------- 9049; mulu - multiply unsigned 9050;------------------------------------------------------------- 9051 9052(define-pmacro (mulu-sem mode src1 dst) 9053 (sequence ((mode result)) 9054 (set obit (add-oflag mode src1 dst 0)) 9055 (set result (mul mode src1 dst)) 9056 (set dst result)) 9057) 9058 9059; mulu.BW #imm,dst 9060(binary-arith-imm-dst mulu G (f-0-4 7) (f-4-3 6) (f-8-4 4) #x8 #x0 #xF mulu-sem) 9061; mulu.BW src,dst 9062(binary-arith-src-dst mulu G (f-0-4 #x7) (f-4-3 0) #x1 #x4 mulu-sem) 9063 9064;------------------------------------------------------------- 9065; neg - twos complement 9066;------------------------------------------------------------- 9067 9068(define-pmacro (neg-sem mode dst) 9069 (sequence ((mode result)) 9070 (set result (neg mode dst)) 9071 (set-z-and-s result) 9072 (set dst result)) 9073) 9074 9075; neg.BW:G 9076(unary-insn neg (f-0-4 7) (f-4-3 2) (f-8-4 #x5) #xA #x2 #xF neg-sem) 9077 9078;------------------------------------------------------------- 9079; not - twos complement 9080;------------------------------------------------------------- 9081 9082(define-pmacro (not-sem mode dst) 9083 (sequence ((mode result)) 9084 (set result (not mode dst)) 9085 (set-z-and-s result) 9086 (set dst result)) 9087) 9088 9089; not.BW:G 9090(unary-insn-g not (f-0-4 7) (f-4-3 2) (f-8-4 #x7) #xA #x1 #xE not-sem) 9091 9092(dni not16.b.s 9093 "not.b:s Dst16-3-S-8" 9094 ((machine 16)) 9095 "not.b:s ${Dst16-3-S-8}" 9096 (+ (f-0-4 #xb) (f-4-1 #x1) Dst16-3-S-8) 9097 (not-sem QI Dst16-3-S-8) 9098 ()) 9099 9100;------------------------------------------------------------- 9101; nop 9102;------------------------------------------------------------- 9103 9104(dni nop16 9105 "nop" 9106 ((machine 16)) 9107 "nop" 9108 (+ (f-0-4 #x0) (f-4-4 #x4)) 9109 (nop) 9110 ()) 9111 9112(dni nop32 9113 "nop" 9114 ((machine 32)) 9115 "nop" 9116 (+ (f-0-4 #xD) (f-4-4 #xE)) 9117 (nop) 9118 ()) 9119 9120;------------------------------------------------------------- 9121; or - logical or 9122;------------------------------------------------------------- 9123 9124(define-pmacro (or-sem mode src1 dst) 9125 (sequence ((mode result)) 9126 (set result (or mode src1 dst)) 9127 (set-z-and-s result) 9128 (set dst result)) 9129) 9130 9131; or.BW #imm,dst (m16 #1 m32 #1) 9132(binary-arith-imm-dst or G (f-0-4 7) (f-4-3 3) (f-8-4 3) #x8 #x2 #xF or-sem) 9133; or.b:S #imm8,dst3 (m16 #2 m32 #2) 9134(binary-arith16-b-S-imm8-dst3 or ".b" (f-0-4 9) (f-4-1 1) or-sem) 9135(binary-arith32-s-imm-dst QI .b 0 or #x1 #x2 or-sem) 9136(binary-arith32-s-imm-dst HI .w 1 or #x1 #x2 or-sem) 9137; or.BW src,dst (m16 #3 m32 #3) 9138(binary-arith-src-dst or G (f-0-4 #x9) (f-4-3 4) #x1 #x5 or-sem) 9139; or.b:S src,r0[lh] (m16) 9140(binary-arith16-b-S-src2 or (f-0-4 1) (f-4-1 1) or-sem) 9141 9142;------------------------------------------------------------- 9143; pop - restore register/memory 9144;------------------------------------------------------------- 9145 9146; TODO future: split this into .b and .w semantics 9147(define-pmacro (pop-sem-mach mach mode dst) 9148 (sequence ((mode b_or_w) (SI length)) 9149 (set b_or_w -1) 9150 (set b_or_w (srl b_or_w #x8)) 9151 (if (eq b_or_w #x0) 9152 (set length 1) ; .b 9153 (set length 2)) ; .w 9154 9155 (case DFLT length 9156 ((1) (set dst (mem-mach mach QI (reg h-sp)))) 9157 ((2) (set dst (mem-mach mach HI (reg h-sp))))) 9158 (set (reg h-sp) (add (reg h-sp) length)) 9159 ) 9160) 9161 9162(define-pmacro (pop-sem16 mode dest) (pop-sem-mach 16 mode dest)) 9163(define-pmacro (pop-sem32 mode dest) (pop-sem-mach 32 mode dest)) 9164 9165; pop.BW:G (m16 #1) 9166(unary-insn-mach-g 16 pop (f-0-4 7) (f-4-3 2) (f-8-4 #xD) pop-sem16 $G) 9167; pop.BW:G (m32 #1) 9168(unary-insn-mach 32 pop #xB #x2 #xF pop-sem32) 9169 9170; pop.b:S r0l/r0h 9171(dni pop16.b-s-rn "pop.b:S r0[lh]" ((machine 16)) 9172 "pop.b$S ${Rn16-push-S-anyof}" 9173 (+ (f-0-4 #x9) Rn16-push-S-anyof (f-5-3 #x2)) 9174 (pop-sem16 QI Rn16-push-S-anyof) 9175 ()) 9176; pop.w:S a0/a1 9177(dni pop16.b-s-an "pop.w:S a[01]" ((machine 16)) 9178 "pop.w$S ${An16-push-S-anyof}" 9179 (+ (f-0-4 #xD) An16-push-S-anyof (f-5-3 #x2)) 9180 (pop-sem16 HI An16-push-S-anyof) 9181 ()) 9182 9183;------------------------------------------------------------- 9184; popc - pop control register 9185; pushc - push control register 9186;------------------------------------------------------------- 9187 9188(define-pmacro (popc32-cr1-sem mode dst) 9189 (sequence () 9190 (case DFLT dst 9191 ((#x0) (set (reg h-dct0) (mem32 mode (reg h-sp)))) 9192 ((#x1) (set (reg h-dct1) (mem32 mode (reg h-sp)))) 9193 ((#x2) (sequence ((HI tflag)) 9194 (set tflag (mem32 mode (reg h-sp))) 9195 (if (and tflag #x1) (set cbit 1)) 9196 (if (and tflag #x2) (set dbit 1)) 9197 (if (and tflag #x4) (set zbit 1)) 9198 (if (and tflag #x8) (set sbit 1)) 9199 (if (and tflag #x10) (set bbit 1)) 9200 (if (and tflag #x20) (set obit 1)) 9201 (if (and tflag #x40) (set ibit 1)) 9202 (if (and tflag #x80) (set ubit 1)))) 9203 ((#x3) (set (reg h-svf) (mem32 mode (reg h-sp)))) 9204 ((#x4) (set (reg h-drc0) (mem32 mode (reg h-sp)))) 9205 ((#x5) (set (reg h-drc1) (mem32 mode (reg h-sp)))) 9206 ((#x6) (set (reg h-dmd0) (mem32 mode (reg h-sp)))) 9207 ((#x7) (set (reg h-dmd1) (mem32 mode (reg h-sp)))) 9208 ) 9209 (set (reg h-sp) (add (reg h-sp) 2)) 9210 ) 9211) 9212(define-pmacro (popc32-cr2-sem mode dst) 9213 (sequence () 9214 (case DFLT dst 9215 ((#x0) (set (reg h-intb) (mem32 mode (reg h-sp)))) 9216 ((#x1) (set (reg h-sp) (mem32 mode (reg h-sp)))) 9217 ((#x2) (set (reg h-sb) (mem32 mode (reg h-sp)))) 9218 ((#x3) (set (reg h-fb) (mem32 mode (reg h-sp)))) 9219 ((#x7) (set (reg h-isp) (mem32 mode (reg h-sp)))) 9220 ) 9221 (set (reg h-sp) (add (reg h-sp) 4)) 9222 ) 9223) 9224(define-pmacro (popc16-sem mode dst) 9225 (sequence () 9226 (case DFLT dst 9227 ((#x1) (set (reg h-intb) (or (and (reg h-intb) #x0000) 9228 (mem16 mode (reg h-sp))))) 9229 ((#x2) (set (reg h-intb) (or (and (reg h-intb) #xffff0000) 9230 (mem16 mode (reg h-sp))))) 9231 ((#x3) (sequence ((HI tflag)) 9232 (set tflag (mem16 mode (reg h-sp))) 9233 (if (and tflag #x1) (set cbit 1)) 9234 (if (and tflag #x2) (set dbit 1)) 9235 (if (and tflag #x4) (set zbit 1)) 9236 (if (and tflag #x8) (set sbit 1)) 9237 (if (and tflag #x10) (set bbit 1)) 9238 (if (and tflag #x20) (set obit 1)) 9239 (if (and tflag #x40) (set ibit 1)) 9240 (if (and tflag #x80) (set ubit 1)))) 9241 ((#x4) (set (reg h-isp) (mem16 mode (reg h-sp)))) 9242 ((#x5) (set (reg h-sp) (mem16 mode (reg h-sp)))) 9243 ((#x6) (set (reg h-sb) (mem16 mode (reg h-sp)))) 9244 ((#x7) (set (reg h-fb) (mem16 mode (reg h-sp)))) 9245 ) 9246 (set (reg h-sp) (add (reg h-sp) 2)) 9247 ) 9248) 9249; popc dest (m16c #1) 9250(dni popc16.imm16 "popc dst" ((machine 16)) 9251 ("popc ${cr16}") 9252 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) (f-12-4 3) cr16) 9253 (popc16-sem HI cr16) 9254 ()) 9255; popc dest (m32c #1) 9256(dni popc32.imm16-cr1 "popc dst" ((machine 32)) 9257 ("popc ${cr1-Unprefixed-32}") 9258 (+ (f-0-4 #xD) (f-4-4 3) (f-8-4 #xA) (f-12-1 1) cr1-Unprefixed-32) 9259 (popc32-cr1-sem HI cr1-Unprefixed-32) 9260 ()) 9261; popc dest (m32c #2) 9262(dni popc32.imm16-cr2 "popc dst" ((machine 32)) 9263 ("popc ${cr2-32}") 9264 (+ (f-0-4 #xD) (f-4-4 3) (f-8-4 2) (f-12-1 1) cr2-32) 9265 (popc32-cr2-sem SI cr2-32) 9266 ()) 9267 9268(define-pmacro (pushc32-cr1-sem mode dst) 9269 (sequence () 9270 (set (reg h-sp) (sub (reg h-sp) 2)) 9271 (case DFLT dst 9272 ((#x0) (set (mem32 mode (reg h-sp)) (reg h-dct0))) 9273 ((#x1) (set (mem32 mode (reg h-sp)) (reg h-dct1))) 9274 ((#x2) (sequence ((HI tflag)) 9275 (set tflag 0) 9276 (if (eq cbit 1) (set tflag (or tflag #x1))) 9277 (if (eq dbit 1) (set tflag (or tflag #x2))) 9278 (if (eq zbit 1) (set tflag (or tflag #x4))) 9279 (if (eq sbit 1) (set tflag (or tflag #x8))) 9280 (if (eq bbit 1) (set tflag (or tflag #x10))) 9281 (if (eq obit 1) (set tflag (or tflag #x20))) 9282 (if (eq ibit 1) (set tflag (or tflag #x40))) 9283 (if (eq ubit 1) (set tflag (or tflag #x80))) 9284 (set (mem32 mode (reg h-sp)) tflag))) 9285 ((#x3) (set (mem32 mode (reg h-sp)) (reg h-svf))) 9286 ((#x4) (set (mem32 mode (reg h-sp)) (reg h-drc0))) 9287 ((#x5) (set (mem32 mode (reg h-sp)) (reg h-drc1))) 9288 ((#x6) (set (mem32 mode (reg h-sp)) (reg h-dmd0))) 9289 ((#x7) (set (mem32 mode (reg h-sp)) (reg h-dmd1))) 9290 ) 9291 ) 9292) 9293(define-pmacro (pushc32-cr2-sem mode dst) 9294 (sequence () 9295 (set (reg h-sp) (sub (reg h-sp) 4)) 9296 (case DFLT dst 9297 ((#x0) (set (mem32 mode (reg h-sp)) (reg h-intb))) 9298 ((#x1) (set (mem32 mode (reg h-sp)) (reg h-sp))) 9299 ((#x2) (set (mem32 mode (reg h-sp)) (reg h-sb))) 9300 ((#x3) (set (mem32 mode (reg h-sp)) (reg h-fb))) 9301 ((#x7) (set (mem32 mode (reg h-sp)) (reg h-isp))) 9302 ) 9303 ) 9304) 9305(define-pmacro (pushc16-sem mode dst) 9306 (sequence () 9307 (set (reg h-sp) (sub (reg h-sp) 2)) 9308 (case DFLT dst 9309 ((#x1) (set (mem16 mode (reg h-sp)) (and (reg h-intb) #xffff))) 9310 ((#x2) (set (mem16 mode (reg h-sp)) (and (reg h-intb) #xffff0000))) 9311 ((#x3) (sequence ((HI tflag)) 9312 (if (eq cbit 1) (set tflag (or tflag #x1))) 9313 (if (eq dbit 1) (set tflag (or tflag #x2))) 9314 (if (eq zbit 1) (set tflag (or tflag #x4))) 9315 (if (eq sbit 1) (set tflag (or tflag #x8))) 9316 (if (eq bbit 1) (set tflag (or tflag #x10))) 9317 (if (eq obit 1) (set tflag (or tflag #x20))) 9318 (if (eq ibit 1) (set tflag (or tflag #x40))) 9319 (if (eq ubit 1) (set tflag (or tflag #x80))) 9320 (set (mem16 mode (reg h-sp)) tflag))) 9321 9322 ((#x4) (set (mem16 mode (reg h-sp)) (reg h-isp))) 9323 ((#x5) (set (mem16 mode (reg h-sp)) (reg h-sp))) 9324 ((#x6) (set (mem16 mode (reg h-sp)) (reg h-sb))) 9325 ((#x7) (set (mem16 mode (reg h-sp)) (reg h-fb))) 9326 ) 9327 ) 9328) 9329; pushc src (m16c) 9330(dni pushc16.imm16 "pushc dst" ((machine 16)) 9331 ("pushc ${cr16}") 9332 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) (f-12-4 2) cr16) 9333 (pushc16-sem HI cr16) 9334 ()) 9335; pushc src (m32c #1) 9336(dni pushc32.imm16-cr1 "pushc dst" ((machine 32)) 9337 ("pushc ${cr1-Unprefixed-32}") 9338 (+ (f-0-4 #xD) (f-4-4 1) (f-8-4 #xA) (f-12-1 1) cr1-Unprefixed-32) 9339 (pushc32-cr1-sem HI cr1-Unprefixed-32) 9340 ()) 9341; pushc src (m32c #2) 9342(dni pushc32.imm16-cr2 "pushc dst" ((machine 32)) 9343 ("pushc ${cr2-32}") 9344 (+ (f-0-4 #xD) (f-4-4 1) (f-8-4 2) (f-12-1 1) cr2-32) 9345 (pushc32-cr2-sem SI cr2-32) 9346 ()) 9347 9348;------------------------------------------------------------- 9349; popm - pop multiple 9350; pushm - push multiple 9351;------------------------------------------------------------- 9352 9353(define-pmacro (popm-sem machine dst) 9354 (sequence ((SI addrlen)) 9355 (if (eq machine 16) 9356 (set addrlen 2) 9357 (set addrlen 4)) 9358 (if (and dst 1) 9359 (sequence () (set R0 (mem-mach machine HI (reg h-sp))) 9360 (set (reg h-sp) (add (reg h-sp) 2)))) 9361 (if (and dst 2) 9362 (sequence () (set R1 (mem-mach machine HI (reg h-sp))) 9363 (set (reg h-sp) (add (reg h-sp) 2)))) 9364 (if (and dst 4) 9365 (sequence () (set R2 (mem-mach machine HI (reg h-sp))) 9366 (set (reg h-sp) (add (reg h-sp) 2)))) 9367 (if (and dst 8) 9368 (sequence () (set R3 (mem-mach machine HI (reg h-sp))) 9369 (set (reg h-sp) (add (reg h-sp) 2)))) 9370 (if (and dst 16) 9371 (sequence () (set A0 (mem-mach machine HI (reg h-sp))) 9372 (set (reg h-sp) (add (reg h-sp) addrlen)))) 9373 (if (and dst 32) 9374 (sequence () (set A1 (mem-mach machine HI (reg h-sp))) 9375 (set (reg h-sp) (add (reg h-sp) addrlen)))) 9376 (if (and dst 64) 9377 (sequence () (set (reg h-sb) (mem-mach machine HI (reg h-sp))) 9378 (set (reg h-sp) (add (reg h-sp) addrlen)))) 9379 (if (eq dst 128) 9380 (sequence () (set (reg h-fb) (mem-mach machine HI (reg h-sp))) 9381 (set (reg h-sp) (add (reg h-sp) addrlen)))) 9382 ) 9383) 9384 9385(define-pmacro (pushm-sem machine dst) 9386 (sequence ((SI count) (SI addrlen)) 9387 (if (eq machine 16) 9388 (set addrlen 2) 9389 (set addrlen 4)) 9390 (if (eq dst 1) 9391 (sequence () (set (reg h-sp) (sub (reg h-sp) addrlen)) 9392 (set (mem-mach machine HI (reg h-sp)) (reg h-fb)))) 9393 (if (and dst 2) 9394 (sequence () (set (reg h-sp) (sub (reg h-sp) addrlen)) 9395 (set (mem-mach machine HI (reg h-sp)) (reg h-sb)))) 9396 (if (and dst 4) 9397 (sequence () (set (reg h-sp) (sub (reg h-sp) addrlen)) 9398 (set (mem-mach machine HI (reg h-sp)) A1))) 9399 (if (and dst 8) 9400 (sequence () (set (reg h-sp) (sub (reg h-sp) addrlen)) 9401 (set (mem-mach machine HI (reg h-sp)) A0))) 9402 (if (and dst 16) 9403 (sequence () (set (reg h-sp) (sub (reg h-sp) 2)) 9404 (set (mem-mach machine HI (reg h-sp)) R3))) 9405 (if (and dst 32) 9406 (sequence () (set (reg h-sp) (sub (reg h-sp) 2)) 9407 (set (mem-mach machine HI (reg h-sp)) R2))) 9408 (if (and dst 64) 9409 (sequence () (set (reg h-sp) (sub (reg h-sp) 2)) 9410 (set (mem-mach machine HI (reg h-sp)) R1))) 9411 (if (and dst 128) 9412 (sequence () (set (reg h-sp) (sub (reg h-sp) 2)) 9413 (set (mem-mach machine HI (reg h-sp)) R0))) 9414 ) 9415) 9416 9417(dni popm16 "popm regs" ((machine 16)) 9418 ("popm ${Regsetpop}") 9419 (+ (f-0-4 #xE) (f-4-4 #xD) Regsetpop) 9420 (popm-sem 16 Regsetpop) 9421 ()) 9422(dni pushm16 "pushm regs" ((machine 16)) 9423 ("pushm ${Regsetpush}") 9424 (+ (f-0-4 #xE) (f-4-4 #xC) Regsetpush) 9425 (pushm-sem 16 Regsetpush) 9426 ()) 9427(dni popm "popm regs" ((machine 32)) 9428 ("popm ${Regsetpop}") 9429 (+ (f-0-4 #x8) (f-4-4 #xE) Regsetpop) 9430 (popm-sem 32 Regsetpop) 9431 ()) 9432(dni pushm "pushm regs" ((machine 32)) 9433 ("pushm ${Regsetpush}") 9434 (+ (f-0-4 #x8) (f-4-4 #xF) Regsetpush) 9435 (pushm-sem 32 Regsetpush) 9436 ()) 9437 9438;------------------------------------------------------------- 9439; push - Save register/memory/immediate data 9440;------------------------------------------------------------- 9441 9442; TODO future: split this into .b and .w semantics 9443(define-pmacro (push-sem-mach mach mode dst) 9444 (sequence ((mode b_or_w) (SI length)) 9445 (set b_or_w -1) 9446 (set b_or_w (srl b_or_w #x8)) 9447 (if (eq b_or_w #x0) 9448 (set length 1) ; .b 9449 (if (eq b_or_w #xff) 9450 (set length 2) ; .w 9451 (set length 4))) ; .l 9452 (set (reg h-sp) (sub (reg h-sp) length)) 9453 (case DFLT length 9454 ((1) (set (mem-mach mach QI (reg h-sp)) dst)) 9455 ((2) (set (mem-mach mach HI (reg h-sp)) dst)) 9456 ((4) (set (mem-mach mach SI (reg h-sp)) dst))) 9457 ) 9458 ) 9459 9460(define-pmacro (push-sem16 mode dst) (push-sem-mach 16 mode dst)) 9461(define-pmacro (push-sem32 mode dst) (push-sem-mach 32 mode dst)) 9462 9463; push.BW:G imm (m16 #1 m32 #1) 9464(dni push16.b.G-imm "push.b:G #Imm-16-QI" ((machine 16)) 9465 ("push.b$G #${Imm-16-QI}") 9466 (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 2) Imm-16-QI) 9467 (push-sem16 QI Imm-16-QI) 9468 ()) 9469 9470(dni push16.w.G-imm "push.w:G #Imm-16-HI" ((machine 16)) 9471 ("push.w$G #${Imm-16-HI}") 9472 (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 2) Imm-16-HI) 9473 (push-sem16 HI Imm-16-HI) 9474 ()) 9475 9476(dni push32.b.imm "push.b #Imm-8-QI" ((machine 32)) 9477 ("push.b #${Imm-8-QI}") 9478 (+ (f-0-4 #xA) (f-4-4 #xE) Imm-8-QI) 9479 (push-sem32 QI Imm-8-QI) 9480 ()) 9481 9482(dni push32.w.imm "push.w #Imm-8-HI" ((machine 32)) 9483 ("push.w #${Imm-8-HI}") 9484 (+ (f-0-4 #xA) (f-4-4 #xF) Imm-8-HI) 9485 (push-sem32 HI Imm-8-HI) 9486 ()) 9487 9488; push.BW:G src (m16 #2) 9489(unary-insn-mach-g 16 push (f-0-4 7) (f-4-3 2) (f-8-4 #x4) push-sem16 $G) 9490; push.BW:G src (m32 #2) 9491(unary-insn-mach 32 push #xC #x0 #xE push-sem32) 9492 9493 9494; push.b:S r0l/r0h (m16 #3) 9495(dni push16.b-s-rn "push.b:S r0[lh]" ((machine 16)) 9496 "push.b$S ${Rn16-push-S-anyof}" 9497 (+ (f-0-4 #x8) Rn16-push-S-anyof (f-5-3 #x2)) 9498 (push-sem16 QI Rn16-push-S-anyof) 9499 ()) 9500; push.w:S a0/a1 (m16 #4) 9501(dni push16.b-s-an "push.w:S a[01]" ((machine 16)) 9502 "push.w$S ${An16-push-S-anyof}" 9503 (+ (f-0-4 #xC) An16-push-S-anyof (f-5-3 #x2)) 9504 (push-sem16 HI An16-push-S-anyof) 9505 ()) 9506 9507; push.l imm32 (m32 #3) 9508(dni push32.l.imm "push.l #Imm-16-SI" ((machine 32)) 9509 ("push.l #${Imm-16-SI}") 9510 (+ (f-0-4 #xB) (f-4-4 6) (f-8-4 5) (f-12-4 3) Imm-16-SI) 9511 (push-sem32 SI Imm-16-SI) 9512 ()) 9513; push.l src (m32 #4) 9514(unary-insn-defn 32 16-Unprefixed SI .l push (+ (f-0-4 #xA) (f-7-1 0) dst32-16-Unprefixed-SI (f-10-2 0) (f-12-4 1)) push-sem32) 9515 9516;------------------------------------------------------------- 9517; pusha - push effective address 9518;------------------------------------------------------------ 9519 9520(define-pmacro (push16a-sem mode dst) 9521 (sequence () 9522 (set (reg h-sp) (sub (reg h-sp) 2)) 9523 (set (mem16 HI (reg h-sp)) dst)) 9524) 9525(define-pmacro (push32a-sem mode dst) 9526 (sequence () 9527 (set (reg h-sp) (sub (reg h-sp) 4)) 9528 (set (mem32 SI (reg h-sp)) dst)) 9529) 9530(unary-insn-defn 16 16-Mova HI "" pusha (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 9) dst16-16-Mova-HI) push16a-sem) 9531(unary-insn-defn 32 16-Unprefixed-Mova SI "" pusha (+ (f-0-4 #xB) (f-7-1 0) dst32-16-Unprefixed-Mova-SI (f-10-2 0) (f-12-4 1)) push32a-sem) 9532 9533;------------------------------------------------------------- 9534; reit - return from interrupt 9535;------------------------------------------------------------- 9536 9537; ??? semantics 9538(dni reit16 "REIT" ((machine 16)) 9539 ("reit") 9540 (+ (f-0-4 #xF) (f-4-4 #xB)) 9541 (nop) 9542 ()) 9543(dni reit32 "REIT" ((machine 32)) 9544 ("reit") 9545 (+ (f-0-4 9) (f-4-4 #xE)) 9546 (nop) 9547 ()) 9548 9549;------------------------------------------------------------- 9550; rmpa - repeat multiple and addition 9551;------------------------------------------------------------- 9552 9553; TODO semantics 9554(dni rmpa16.b "rmpa.size" ((machine 16)) 9555 ("rmpa.b") 9556 (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xF) (f-12-4 1)) 9557 (nop) 9558 ()) 9559(dni rmpa16.w "rmpa.size" ((machine 16)) 9560 ("rmpa.w") 9561 (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xF) (f-12-4 1)) 9562 (nop) 9563 ()) 9564(dni rmpa32.b "rmpa.size" ((machine 32)) 9565 ("rmpa.b") 9566 (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 4) (f-12-4 3)) 9567 (nop) 9568 ()) 9569 9570(dni rmpa32.w "rmpa.size" ((machine 32)) 9571 ("rmpa.w") 9572 (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 5) (f-12-4 3)) 9573 (nop) 9574 ()) 9575 9576;------------------------------------------------------------- 9577; rolc - rotate left with carry 9578;------------------------------------------------------------- 9579 9580; TODO check semantics 9581; TODO future: split this into .b and .w semantics 9582(define-pmacro (rolc-sem mode dst) 9583 (sequence ((mode result) (SI ocbit) (mode b_or_w) (USI mask)) 9584 (set b_or_w -1) 9585 (set b_or_w (srl b_or_w #x8)) 9586 (if (eq b_or_w #x0) 9587 (set mask #x8000) ; .b 9588 (set mask #x80000000)) ; .w 9589 (set ocbit cbit) 9590 (set cbit (and dst mask)) 9591 (set result (sll mode dst 1)) 9592 (set result (or result ocbit)) 9593 (set-z-and-s result) 9594 (set dst result)) 9595) 9596; rolc.BW src,dst 9597(unary-insn rolc (f-0-4 7) (f-4-3 3) (f-8-4 #xA) #xB #x2 #xE rolc-sem) 9598 9599;------------------------------------------------------------- 9600; rorc - rotate right with carry 9601;------------------------------------------------------------- 9602 9603; TODO check semantics 9604; TODO future: split this into .b and .w semantics 9605(define-pmacro (rorc-sem mode dst) 9606 (sequence ((mode result) (SI ocbit) (mode b_or_w) (USI mask) (SI shamt)) 9607 (set b_or_w -1) 9608 (set b_or_w (srl b_or_w #x8)) 9609 (if (eq b_or_w #x0) 9610 (sequence () (set mask #x7fff) (set shamt 15)) ; .b 9611 (sequence () (set mask #x7fffffff) (set shamt 31))) ; .w 9612 (set ocbit cbit) 9613 (set cbit (and dst #x1)) 9614 (set result (srl mode dst (const 1))) 9615 (set result (or (and result mask) (sll ocbit shamt))) 9616 (set-z-and-s result) 9617 (set dst result)) 9618) 9619; rorc.BW src,dst 9620(unary-insn rorc (f-0-4 7) (f-4-3 3) (f-8-4 #xB) #xA #x2 #xE rorc-sem) 9621 9622;------------------------------------------------------------- 9623; rot - rotate 9624;------------------------------------------------------------- 9625 9626; TODO future: split this into .b and .w semantics 9627(define-pmacro (rot-1-sem mode src1 dst) 9628 (sequence ((mode tmp) (mode b_or_w) (USI mask) (SI shift)) 9629 (case DFLT src1 9630 ((#x0) (set shift 1)) 9631 ((#x1) (set shift 2)) 9632 ((#x2) (set shift 3)) 9633 ((#x3) (set shift 4)) 9634 ((#x4) (set shift 5)) 9635 ((#x5) (set shift 6)) 9636 ((#x6) (set shift 7)) 9637 ((#x7) (set shift 8)) 9638 ((-8) (set shift -1)) 9639 ((-7) (set shift -2)) 9640 ((-6) (set shift -3)) 9641 ((-5) (set shift -4)) 9642 ((-4) (set shift -5)) 9643 ((-3) (set shift -6)) 9644 ((-2) (set shift -7)) 9645 ((-1) (set shift -8)) 9646 (else (set shift 0)) 9647 ) 9648 (set b_or_w -1) 9649 (set b_or_w (srl b_or_w #x8)) 9650 (if (eq b_or_w #x0) 9651 (set mask #x7fff) ; .b 9652 (set mask #x7fffffff)) ; .w 9653 (set tmp dst) 9654 (if (gt mode shift 0) 9655 (sequence () 9656 (set tmp (rol mode tmp shift)) 9657 (set cbit (and tmp #x1))) 9658 (sequence () 9659 (set tmp (ror mode tmp (mul shift -1))) 9660 (set cbit (and tmp mask)))) 9661 (set-z-and-s tmp) 9662 (set dst tmp)) 9663) 9664(define-pmacro (rot-2-sem mode dst) 9665 (sequence ((mode tmp) (mode b_or_w) (USI mask)) 9666 (set b_or_w -1) 9667 (set b_or_w (srl b_or_w #x8)) 9668 (if (eq b_or_w #x0) 9669 (set mask #x7fff) ; .b 9670 (set mask #x7fffffff)) ; .w 9671 (set tmp dst) 9672 (if (gt mode (reg h-r1h) 0) 9673 (sequence () 9674 (set tmp (rol mode tmp (reg h-r1h))) 9675 (set cbit (and tmp #x1))) 9676 (sequence () 9677 (set tmp (ror mode tmp (reg h-r1h))) 9678 (set cbit (and tmp mask)))) 9679 (set-z-and-s tmp) 9680 (set dst tmp)) 9681) 9682 9683; rot.BW #imm4,dst 9684(binary-arith16-shimm4-dst-defn QI .b 0 0 rot (f-0-4 #xE) (f-4-3 0) rot-1-sem) 9685(binary-arith16-shimm4-dst-defn HI .w 0 1 rot (f-0-4 #xE) (f-4-3 0) rot-1-sem) 9686(binary-arith32-shimm4-dst-defn QI .b 0 0 rot #x7 #x2 rot-1-sem) 9687(binary-arith32-shimm4-dst-defn HI .w 0 1 rot #x7 #x2 rot-1-sem) 9688; rot.BW src,dst 9689 9690(dni rot16.b-dst "rot r1h,dest" ((machine 16)) 9691 ("rot.b r1h,${dst16-16-QI}") 9692 (+ (f-0-4 7) (f-4-4 #x4) (f-8-4 #x6) dst16-16-QI) 9693 (rot-2-sem QI dst16-16-QI) 9694 ()) 9695(dni rot16.w-dst "rot r1h,dest" ((machine 16)) 9696 ("rot.w r1h,${dst16-16-HI}") 9697 (+ (f-0-4 7) (f-4-4 #x5) (f-8-4 #x6) dst16-16-HI) 9698 (rot-2-sem HI dst16-16-HI) 9699 ()) 9700 9701(dni rot32.b-dst "rot r1h,dest" ((machine 32)) 9702 ("rot.b r1h,${dst32-16-Unprefixed-QI}") 9703 (+ (f-0-4 #xA) dst32-16-Unprefixed-QI (f-7-1 0) (f-10-2 3) (f-12-4 #xF)) 9704 (rot-2-sem QI dst32-16-Unprefixed-QI) 9705 ()) 9706(dni rot32.w-dst "rot r1h,dest" ((machine 32)) 9707 ("rot.w r1h,${dst32-16-Unprefixed-HI}") 9708 (+ (f-0-4 #xA) dst32-16-Unprefixed-HI (f-7-1 1) (f-10-2 3) (f-12-4 #xF)) 9709 (rot-2-sem HI dst32-16-Unprefixed-HI) 9710 ()) 9711 9712;------------------------------------------------------------- 9713; rts - return from subroutine 9714;------------------------------------------------------------- 9715 9716(define-pmacro (rts16-sem) 9717 (sequence ((SI tpc)) 9718 (set tpc (mem16 HI (reg h-sp))) 9719 (set (reg h-sp) (add (reg h-sp) 2)) 9720 (set tpc (or tpc (sll (mem16 QI (reg h-sp)) 16))) 9721 (set (reg h-sp) (add (reg h-sp) 1)) 9722 (set pc tpc) 9723 ) 9724) 9725(define-pmacro (rts32-sem) 9726 (sequence ((SI tpc)) 9727 (set tpc (mem32 HI (reg h-sp))) 9728 (set (reg h-sp) (add (reg h-sp) 2)) 9729 (set tpc (or tpc (sll (mem32 HI (reg h-sp)) 16))) 9730 (set (reg h-sp) (add (reg h-sp) 2)) 9731 (set pc tpc) 9732 ) 9733) 9734 9735(dni rts16 "rts" ((machine 16)) 9736 ("rts") 9737 (+ (f-0-4 #xF) (f-4-4 3)) 9738 (rts16-sem) 9739 ()) 9740 9741(dni rts32 "rts" ((machine 32)) 9742 ("rts") 9743 (+ (f-0-4 #xD) (f-4-4 #xF)) 9744 (rts32-sem) 9745 ()) 9746 9747;------------------------------------------------------------- 9748; sbb - subtract with borrow 9749;------------------------------------------------------------- 9750 9751(define-pmacro (sbb-sem mode src dst) 9752 (sequence ((mode result)) 9753 (set result (subc mode dst src cbit)) 9754 (set obit (add-oflag mode dst src cbit)) 9755 (set cbit (add-oflag mode dst src cbit)) 9756 (set-z-and-s result) 9757 (set dst result)) 9758) 9759 9760; sbb.size:G #imm,dst 9761(binary-arith16-imm-dst-defn QI QI .b 0 sbb X (f-0-4 7) (f-4-3 3) (f-8-4 7) sbb-sem) 9762(binary-arith16-imm-dst-defn HI HI .w 1 sbb X (f-0-4 7) (f-4-3 3) (f-8-4 7) sbb-sem) 9763(binary-arith32-imm-dst-Prefixed QI QI .b 0 sbb X #x9 #x2 #xE sbb-sem) 9764(binary-arith32-imm-dst-Prefixed HI HI .w 1 sbb X #x9 #x2 #xE sbb-sem) 9765 9766; sbb.BW:G src,dst 9767(binary-arith16-src-dst-defn QI QI .b 0 sbb X (f-0-4 #xB) (f-4-3 4) sbb-sem) 9768(binary-arith16-src-dst-defn HI HI .w 1 sbb X (f-0-4 #xB) (f-4-3 4) sbb-sem) 9769(binary-arith32-src-dst-Prefixed QI QI .b 0 sbb X #x1 #x6 sbb-sem) 9770(binary-arith32-src-dst-Prefixed HI HI .w 1 sbb X #x1 #x6 sbb-sem) 9771 9772;------------------------------------------------------------- 9773; sbjnz - subtract then jump on not zero 9774;------------------------------------------------------------- 9775 9776(define-pmacro (sub-jnz-sem mode src dst label) 9777 (sequence ((mode result)) 9778 (set result (sub mode dst src)) 9779 (set dst result) 9780 (if (ne result 0) 9781 (set pc label))) 9782) 9783 9784; sbjnz.size #imm4,dst,label 9785(arith-jnz-imm4-dst sbjnz s4n (f-0-4 #xF) (f-4-3 4) #xf #x1 sub-jnz-sem) 9786 9787;------------------------------------------------------------- 9788; sccnd - store condition on condition (m32) 9789;------------------------------------------------------------- 9790 9791(define-pmacro (sccnd-sem cnd dst) 9792 (sequence () 9793 (set dst 0) 9794 (case DFLT cnd 9795 ((#x00) (if (not cbit) (set dst 1))) ;ltu nc 9796 ((#x01) (if (or cbit zbit) (set dst 1))) ;leu 9797 ((#x02) (if (not zbit) (set dst 1))) ;ne nz 9798 ((#x03) (if (not sbit) (set dst 1))) ;pz 9799 ((#x04) (if (not obit) (set dst 1))) ;no 9800 ((#x05) (if (not (or zbit (xor sbit obit))) (set dst 1))) ;gt 9801 ((#x06) (if (xor sbit obit) (set dst 1))) ;ge 9802 ((#x08) (if (trunc BI cbit) (set dst 1))) ;geu c 9803 ((#x09) (if (not (or cbit zbit)) (set dst 1))) ;gtu 9804 ((#x0a) (if (trunc BI zbit) (set dst 1))) ;eq z 9805 ((#x0b) (if (trunc BI sbit) (set dst 1))) ;n 9806 ((#x0c) (if (trunc BI obit) (set dst 1))) ;o 9807 ((#x0d) (if (or zbit (xor sbit obit)) (set dst 1))) ;le 9808 ((#x0e) (if (xor sbit obit) (set dst 1))) ;lt 9809 ) 9810 ) 9811 ) 9812 9813; scCND dst 9814(dni sccnd 9815 "sccnd dst" 9816 ((machine 32)) 9817 "sc$sccond32 ${dst32-16-Unprefixed-HI}" 9818 (+ (f-0-4 #xD) dst32-16-Unprefixed-HI (f-7-1 1) (f-10-2 3) sccond32) 9819 (sccnd-sem sccond32 dst32-16-Unprefixed-HI) 9820 ()) 9821 9822;------------------------------------------------------------- 9823; scmpu - string compare unequal (m32) 9824;------------------------------------------------------------- 9825 9826; TODO semantics 9827(dni scmpu.b "scmpu.b" ((machine 32)) 9828 ("scmpu.b") 9829 (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 #xC) (f-12-4 3)) 9830 (c-call VOID "scmpu_QI_semantics") 9831 ()) 9832 9833(dni scmpu.w "scmpu.w" ((machine 32)) 9834 ("scmpu.w") 9835 (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 #xD) (f-12-4 3)) 9836 (c-call VOID "scmpu_HI_semantics") 9837 ()) 9838 9839;------------------------------------------------------------- 9840; sha - shift arithmetic 9841;------------------------------------------------------------- 9842 9843; TODO future: split this into .b and .w semantics 9844(define-pmacro (sha-sem mode src1 dst) 9845 (sequence ((mode result)(mode shift)(mode shmode)) 9846 (case DFLT src1 9847 ((#x0) (set shift 1)) 9848 ((#x1) (set shift 2)) 9849 ((#x2) (set shift 3)) 9850 ((#x3) (set shift 4)) 9851 ((#x4) (set shift 5)) 9852 ((#x5) (set shift 6)) 9853 ((#x6) (set shift 7)) 9854 ((#x7) (set shift 8)) 9855 ((-8) (set shift -1)) 9856 ((-7) (set shift -2)) 9857 ((-6) (set shift -3)) 9858 ((-5) (set shift -4)) 9859 ((-4) (set shift -5)) 9860 ((-3) (set shift -6)) 9861 ((-2) (set shift -7)) 9862 ((-1) (set shift -8)) 9863 (else (set shift 0)) 9864 ) 9865 (set shmode -1) 9866 (set shmode (srl shmode #x8)) 9867 (if (lt mode shift #x0) (set result (sra mode dst (mul shift -1)))) 9868 (if (gt mode shift 0) (set result (sll mode dst shift))) 9869 (if (eq shmode #x0) ; QI 9870 (sequence 9871 ((mode cbitamt)) 9872 (if (lt mode shift #x0) 9873 (set cbitamt (sub #x8 shift)) ; sra 9874 (set cbitamt (sub shift 1))) ; sll 9875 (set cbit (srl (and (sll dst cbitamt) #x80) #x7)) 9876 (set obit (ne (and dst #x80) (and result #x80))) 9877 )) 9878 (if (eq shmode #xff) ; HI 9879 (sequence 9880 ((mode cbitamt)) 9881 (if (lt mode shift #x0) 9882 (set cbitamt (sub 16 shift)) ; sra 9883 (set cbitamt (sub shift 1))) ; sll 9884 (set cbit (srl (and (sll dst cbitamt) #x8000) #xf)) 9885 (set obit (ne (and dst #x8000) (and result #x8000))) 9886 )) 9887 (set-z-and-s result) 9888 (set dst result)) 9889) 9890(define-pmacro (shar1h-sem mode dst) 9891 (sequence ((mode result)(mode shmode)) 9892 (set shmode -1) 9893 (set shmode (srl shmode #x8)) 9894 (if (lt mode (reg h-r1h) 0) (set result (sra mode dst (reg h-r1h)))) 9895 (if (gt mode (reg h-r1h) 0) (set result (sll mode dst (reg h-r1h)))) 9896 (if (eq shmode #x0) ; QI 9897 (sequence 9898 ((mode cbitamt)) 9899 (if (lt mode (reg h-r1h) #x0) 9900 (set cbitamt (sub #x8 (reg h-r1h))) ; sra 9901 (set cbitamt (sub (reg h-r1h) 1))) ; sll 9902 (set cbit (srl (and (sll dst cbitamt) #x80) #x7)) 9903 (set obit (ne (and dst #x80) (and result #x80))) 9904 )) 9905 (if (eq shmode #xff) ; HI 9906 (sequence 9907 ((mode cbitamt)) 9908 (if (lt mode (reg h-r1h) #x0) 9909 (set cbitamt (sub 16 (reg h-r1h))) ; sra 9910 (set cbitamt (sub (reg h-r1h) 1))) ; sll 9911 (set cbit (srl (and (sll dst cbitamt) #x8000) #xf)) 9912 (set obit (ne (and dst #x8000) (and result #x8000))) 9913 )) 9914 (set-z-and-s result) 9915 (set dst result)) 9916) 9917; sha.BW #imm4,dst (m16 #1 m32 #1) 9918(binary-arith16-shimm4-dst-defn QI .b 0 0 sha (f-0-4 #xF) (f-4-3 0) sha-sem) 9919(binary-arith16-shimm4-dst-defn HI .w 0 1 sha (f-0-4 #xF) (f-4-3 0) sha-sem) 9920(binary-arith32-shimm4-dst-defn QI .b 1 0 sha #x7 #x0 sha-sem) 9921(binary-arith32-shimm4-dst-defn HI .w 1 1 sha #x7 #x0 sha-sem) 9922; sha.BW r1h,dst (m16 #2 m32 #3) 9923(dni sha16.b-dst "sha.b r1h,dest" ((machine 16)) 9924 ("sha.b r1h,${dst16-16-QI}") 9925 (+ (f-0-4 7) (f-4-4 4) (f-8-4 #xF) dst16-16-QI) 9926 (shar1h-sem HI dst16-16-QI) 9927 ()) 9928(dni sha16.w-dst "sha.w r1h,dest" ((machine 16)) 9929 ("sha.w r1h,${dst16-16-HI}") 9930 (+ (f-0-4 7) (f-4-4 5) (f-8-4 #xF) dst16-16-HI) 9931 (shar1h-sem HI dst16-16-HI) 9932 ()) 9933(dni sha32.b-dst "sha.b r1h,dest" ((machine 32)) 9934 ("sha.b r1h,${dst32-16-Unprefixed-QI}") 9935 (+ (f-0-4 #xB) dst32-16-Unprefixed-QI (f-7-1 0) (f-10-2 3) (f-12-4 #xE)) 9936 (shar1h-sem QI dst32-16-Unprefixed-QI) 9937 ()) 9938(dni sha32.w-dst "sha.w r1h,dest" ((machine 32)) 9939 ("sha.w r1h,${dst32-16-Unprefixed-HI}") 9940 (+ (f-0-4 #xB) dst32-16-Unprefixed-HI (f-7-1 1) (f-10-2 3) (f-12-4 #xE)) 9941 (shar1h-sem HI dst32-16-Unprefixed-HI) 9942 ()) 9943; sha.L #imm,dst (m16 #3) 9944(dni sha16-L-imm-r2r0 "sha.L #Imm-sh-12-s4,r2r0" ((machine 16)) 9945 "sha.l #${Imm-sh-12-s4},r2r0" 9946 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 #xA) Imm-sh-12-s4) 9947 (sha-sem SI Imm-sh-12-s4 (reg h-r2r0)) 9948 ()) 9949(dni sha16-L-imm-r3r1 "sha.L #Imm-sh-12-s4,r3r1" ((machine 16)) 9950 "sha.l #${Imm-sh-12-s4},r3r1" 9951 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 #xB) Imm-sh-12-s4) 9952 (sha-sem SI Imm-sh-12-s4 (reg h-r3r1)) 9953 ()) 9954; sha.L r1h,dst (m16 #4) 9955(dni sha16-L-r1h-r2r0 "sha.L r1h,r2r0" ((machine 16)) 9956 "sha.l r1h,r2r0" 9957 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 2) (f-12-4 1)) 9958 (sha-sem SI (reg h-r1h) (reg h-r2r0)) 9959 ()) 9960(dni sha16-L-r1h-r3r1 "sha.L r1h,r3r1" ((machine 16)) 9961 "sha.l r1h,r3r1" 9962 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 3) (f-12-4 1)) 9963 (sha-sem SI (reg h-r1h) (reg h-r3r1)) 9964 ()) 9965; sha.L #imm8,dst (m32 #2) 9966(binary-arith32-imm-dst-defn QI SI .l 0 sha X #xA #x2 #x1 sha-sem) 9967; sha.L r1h,dst (m32 #4) 9968(dni sha32.l-dst "sha.l r1h,dest" ((machine 32)) 9969 ("sha.l r1h,${dst32-16-Unprefixed-SI}") 9970 (+ (f-0-4 #xC) dst32-16-Unprefixed-SI (f-7-1 0) (f-10-2 1) (f-12-4 1)) 9971 (shar1h-sem QI dst32-16-Unprefixed-SI) 9972 ()) 9973 9974;------------------------------------------------------------- 9975; shanc - shift arithmetic non carry (m32) 9976;------------------------------------------------------------- 9977 9978; TODO check semantics 9979; shanc.L #imm8,dst 9980(binary-arith32-imm-dst-defn QI SI .l 0 shanc X #xC #x2 #x1 sha-sem) 9981 9982;------------------------------------------------------------- 9983; shl - shift logical 9984;------------------------------------------------------------- 9985 9986; TODO future: split this into .b and .w semantics 9987(define-pmacro (shl-sem mode src1 dst) 9988 (sequence ((mode result)(mode shift)(mode shmode)) 9989 (case DFLT src1 9990 ((#x0) (set shift 1)) 9991 ((#x1) (set shift 2)) 9992 ((#x2) (set shift 3)) 9993 ((#x3) (set shift 4)) 9994 ((#x4) (set shift 5)) 9995 ((#x5) (set shift 6)) 9996 ((#x6) (set shift 7)) 9997 ((#x7) (set shift 8)) 9998 ((-8) (set shift -1)) 9999 ((-7) (set shift -2)) 10000 ((-6) (set shift -3)) 10001 ((-5) (set shift -4)) 10002 ((-4) (set shift -5)) 10003 ((-3) (set shift -6)) 10004 ((-2) (set shift -7)) 10005 ((-1) (set shift -8)) 10006 (else (set shift 0)) 10007 ) 10008 (set shmode -1) 10009 (set shmode (srl shmode #x8)) 10010 (if (lt mode shift #x0) (set result (srl mode dst (mul shift -1)))) 10011 (if (gt mode shift 0) (set result (sll mode dst shift))) 10012 (if (eq shmode #x0) ; QI 10013 (sequence 10014 ((mode cbitamt)) 10015 (if (lt mode shift #x0) 10016 (set cbitamt (sub #x8 shift)); srl 10017 (set cbitamt (sub shift 1))) ; sll 10018 (set cbit (srl (and (sll dst cbitamt) #x80) #x7)) 10019 (set obit (ne (and dst #x80) (and result #x80))) 10020 )) 10021 (if (eq shmode #xff) ; HI 10022 (sequence 10023 ((mode cbitamt)) 10024 (if (lt mode shift #x0) 10025 (set cbitamt (sub 16 shift)) ; srl 10026 (set cbitamt (sub shift 1))) ; sll 10027 (set cbit (srl (and (sll dst cbitamt) #x8000) #xf)) 10028 (set obit (ne (and dst #x8000) (and result #x8000))) 10029 )) 10030 (set-z-and-s result) 10031 (set dst result)) 10032 ) 10033(define-pmacro (shlr1h-sem mode dst) 10034 (sequence ((mode result)(mode shmode)) 10035 (set shmode -1) 10036 (set shmode (srl shmode #x8)) 10037 (if (lt mode (reg h-r1h) 0) (set result (srl mode dst (reg h-r1h)))) 10038 (if (gt mode (reg h-r1h) 0) (set result (sll mode dst (reg h-r1h)))) 10039 (if (eq shmode #x0) ; QI 10040 (sequence 10041 ((mode cbitamt)) 10042 (if (lt mode (reg h-r1h) #x0) 10043 (set cbitamt (sub #x8 (reg h-r1h))) ; srl 10044 (set cbitamt (sub (reg h-r1h) 1))) ; sll 10045 (set cbit (srl (and (sll dst cbitamt) #x80) #x7)) 10046 (set obit (ne (and dst #x80) (and result #x80))) 10047 )) 10048 (if (eq shmode #xff) ; HI 10049 (sequence 10050 ((mode cbitamt)) 10051 (if (lt mode (reg h-r1h) #x0) 10052 (set cbitamt (sub 16 (reg h-r1h))) ; srl 10053 (set cbitamt (sub (reg h-r1h) 1))) ; sll 10054 (set cbit (srl (and (sll dst cbitamt) #x8000) #xf)) 10055 (set obit (ne (and dst #x8000) (and result #x8000))) 10056 )) 10057 (set-z-and-s result) 10058 (set dst result)) 10059 ) 10060; shl.BW #imm4,dst (m16 #1 m32 #1) 10061(binary-arith16-shimm4-dst-defn QI .b 0 0 shl (f-0-4 #xE) (f-4-3 4) shl-sem) 10062(binary-arith16-shimm4-dst-defn HI .w 0 1 shl (f-0-4 #xE) (f-4-3 4) shl-sem) 10063(binary-arith32-shimm4-dst-defn QI .b 0 0 shl #x7 #x0 shl-sem) 10064(binary-arith32-shimm4-dst-defn HI .w 0 1 shl #x7 #x0 shl-sem) 10065; shl.BW r1h,dst (m16 #2 m32 #3) 10066(dni shl16.b-dst "shl.b r1h,dest" ((machine 16)) 10067 ("shl.b r1h,${dst16-16-QI}") 10068 (+ (f-0-4 7) (f-4-4 4) (f-8-4 #xE) dst16-16-QI) 10069 (shlr1h-sem HI dst16-16-QI) 10070 ()) 10071(dni shl16.w-dst "shl.w r1h,dest" ((machine 16)) 10072 ("shl.w r1h,${dst16-16-HI}") 10073 (+ (f-0-4 7) (f-4-4 5) (f-8-4 #xE) dst16-16-HI) 10074 (shlr1h-sem HI dst16-16-HI) 10075 ()) 10076(dni shl32.b-dst "shl.b r1h,dest" ((machine 32)) 10077 ("shl.b r1h,${dst32-16-Unprefixed-QI}") 10078 (+ (f-0-4 #xA) dst32-16-Unprefixed-QI (f-7-1 0) (f-10-2 3) (f-12-4 #xE)) 10079 (shlr1h-sem QI dst32-16-Unprefixed-QI) 10080 ()) 10081(dni shl32.w-dst "shl.w r1h,dest" ((machine 32)) 10082 ("shl.w r1h,${dst32-16-Unprefixed-HI}") 10083 (+ (f-0-4 #xA) dst32-16-Unprefixed-HI (f-7-1 1) (f-10-2 3) (f-12-4 #xE)) 10084 (shlr1h-sem HI dst32-16-Unprefixed-HI) 10085 ()) 10086; shl.L #imm,dst (m16 #3) 10087(dni shl16-L-imm-r2r0 "shl.L #Imm-sh-12-s4,r2r0" ((machine 16)) 10088 "shl.l #${Imm-sh-12-s4},r2r0" 10089 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 #x8) Imm-sh-12-s4) 10090 (shl-sem SI Imm-sh-12-s4 (reg h-r2r0)) 10091 ()) 10092(dni shl16-L-imm-r3r1 "shl.L #Imm-sh-12-s4,r3r1" ((machine 16)) 10093 "shl.l #${Imm-sh-12-s4},r3r1" 10094 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 #x9) Imm-sh-12-s4) 10095 (shl-sem SI Imm-sh-12-s4 (reg h-r3r1)) 10096 ()) 10097; shl.L r1h,dst (m16 #4) 10098(dni shl16-L-r1h-r2r0 "shl.L r1h,r2r0" ((machine 16)) 10099 "shl.l r1h,r2r0" 10100 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 0) (f-12-4 1)) 10101 (shl-sem SI (reg h-r1h) (reg h-r2r0)) 10102 ()) 10103(dni shl16-L-r1h-r3r1 "shl.L r1h,r3r1" ((machine 16)) 10104 "shl.l r1h,r3r1" 10105 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 1) (f-12-4 1)) 10106 (shl-sem SI (reg h-r1h) (reg h-r3r1)) 10107 ()) 10108; shl.L #imm8,dst (m32 #2) 10109(binary-arith32-imm-dst-defn QI SI .l 0 shl X #x9 #x2 #x1 shl-sem) 10110; shl.L r1h,dst (m32 #4) 10111(dni shl32.l-dst "shl.l r1h,dest" ((machine 32)) 10112 ("shl.l r1h,${dst32-16-Unprefixed-SI}") 10113 (+ (f-0-4 #xC) dst32-16-Unprefixed-SI (f-7-1 0) (f-10-2 0) (f-12-4 1)) 10114 (shlr1h-sem QI dst32-16-Unprefixed-SI) 10115 ()) 10116 10117;------------------------------------------------------------- 10118; shlnc - shift logical non carry 10119;------------------------------------------------------------- 10120 10121; TODO check semantics 10122; shlnc.L #imm8,dst 10123(binary-arith32-imm-dst-defn QI SI .l 0 shlnc X #x8 #x2 #x1 shl-sem) 10124 10125;------------------------------------------------------------- 10126; sin - string input (m32) 10127;------------------------------------------------------------- 10128 10129; TODO semantics 10130(dni sin32.b "sin" ((machine 32)) 10131 ("sin.b") 10132 (+ (f-0-4 #xB) (f-4-4 2) (f-8-4 8) (f-12-4 3)) 10133 (c-call VOID "sin_QI_semantics") 10134 ()) 10135 10136(dni sin32.w "sin" ((machine 32)) 10137 ("sin.w") 10138 (+ (f-0-4 #xB) (f-4-4 2) (f-8-4 9) (f-12-4 3)) 10139 (c-call VOID "sin_HI_semantics") 10140 ()) 10141 10142;------------------------------------------------------------- 10143; smovb - string move backward 10144;------------------------------------------------------------- 10145 10146; TODO semantics 10147(dni smovb16.b "smovb.b" ((machine 16)) 10148 ("smovb.b") 10149 (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 9)) 10150 (c-call VOID "smovb_QI_semantics") 10151 ()) 10152 10153(dni smovb16.w "smovb.w" ((machine 16)) 10154 ("smovb.w") 10155 (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 9)) 10156 (c-call VOID "smovb_HI_semantics") 10157 ()) 10158 10159(dni smovb32.b "smovb.b" ((machine 32)) 10160 ("smovb.b") 10161 (+ (f-0-4 #xB) (f-4-4 6) (f-8-4 8) (f-12-4 3)) 10162 (c-call VOID "smovb_QI_semantics") 10163 ()) 10164 10165(dni smovb32.w "smovb.w" ((machine 32)) 10166 ("smovb.w") 10167 (+ (f-0-4 #xB) (f-4-4 6) (f-8-4 9) (f-12-4 3)) 10168 (c-call VOID "smovb_HI_semantics") 10169 ()) 10170 10171;------------------------------------------------------------- 10172; smovf - string move forward (m32) 10173;------------------------------------------------------------- 10174 10175; TODO semantics 10176(dni smovf16.b "smovf.b" ((machine 16)) 10177 ("smovf.b") 10178 (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 8)) 10179 (c-call VOID "smovf_QI_semantics") 10180 ()) 10181 10182(dni smovf16.w "smovf.w" ((machine 16)) 10183 ("smovf.w") 10184 (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 8)) 10185 (c-call VOID "smovf_HI_semantics") 10186 ()) 10187 10188(dni smovf32.b "smovf.b" ((machine 32)) 10189 ("smovf.b") 10190 (+ (f-0-4 #xB) (f-4-4 0) (f-8-4 8) (f-12-4 3)) 10191 (c-call VOID "smovf_QI_semantics") 10192 ()) 10193 10194(dni smovf32.w "smovf.w" ((machine 32)) 10195 ("smovf.w") 10196 (+ (f-0-4 #xB) (f-4-4 0) (f-8-4 9) (f-12-4 3)) 10197 (c-call VOID "smovf_HI_semantics") 10198 ()) 10199 10200;------------------------------------------------------------- 10201; smovu - string move unequal (m32) 10202;------------------------------------------------------------- 10203 10204; TODO semantics 10205(dni smovu.b "smovu.b" ((machine 32)) 10206 ("smovu.b") 10207 (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 8) (f-12-4 3)) 10208 (c-call VOID "smovu_QI_semantics") 10209 ()) 10210 10211(dni smovu.w "smovu.w" ((machine 32)) 10212 ("smovu.w") 10213 (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 9) (f-12-4 3)) 10214 (c-call VOID "smovu_HI_semantics") 10215 ()) 10216 10217;------------------------------------------------------------- 10218; sout - string output (m32) 10219;------------------------------------------------------------- 10220 10221; TODO semantics 10222(dni sout.b "sout.b" ((machine 32)) 10223 ("sout.b") 10224 (+ (f-0-4 #xB) (f-4-4 4) (f-8-4 8) (f-12-4 3)) 10225 (c-call VOID "sout_QI_semantics") 10226 ()) 10227 10228(dni sout.w "sout" ((machine 32)) 10229 ("sout.w") 10230 (+ (f-0-4 #xB) (f-4-4 4) (f-8-4 9) (f-12-4 3)) 10231 (c-call VOID "sout_HI_semantics") 10232 ()) 10233 10234;------------------------------------------------------------- 10235; sstr - string store 10236;------------------------------------------------------------- 10237 10238; TODO semantics 10239(dni sstr16.b "sstr.b" ((machine 16)) 10240 ("sstr.b") 10241 (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 #xA)) 10242 (c-call VOID "sstr_QI_semantics") 10243 ()) 10244 10245(dni sstr16.w "sstr.w" ((machine 16)) 10246 ("sstr.w") 10247 (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 #xA)) 10248 (c-call VOID "sstr_HI_semantics") 10249 ()) 10250 10251(dni sstr.b "sstr" ((machine 32)) 10252 ("sstr.b") 10253 (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 0) (f-12-4 3)) 10254 (c-call VOID "sstr_QI_semantics") 10255 ()) 10256 10257(dni sstr.w "sstr" ((machine 32)) 10258 ("sstr.w") 10259 (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 1) (f-12-4 3)) 10260 (c-call VOID "sstr_HI_semantics") 10261 ()) 10262 10263;------------------------------------------------------------- 10264; stnz - store on not zero 10265;------------------------------------------------------------- 10266 10267(define-pmacro (stnz-sem mode src dst) 10268 (sequence () 10269 (if (ne zbit (const 1)) 10270 (set dst src))) 10271) 10272; stnz #imm8,dst3 (m16) 10273(binary-arith16-b-S-imm8-dst3 stnz "" (f-0-4 #xD) (f-4-1 0) stnz-sem) 10274; stnz.BW #imm,dst (m32) 10275(binary-arith32-imm-dst-defn QI QI .b 0 stnz X #x9 #x1 #xF stnz-sem) 10276(binary-arith32-imm-dst-defn HI HI .w 1 stnz X #x9 #x1 #xF stnz-sem) 10277 10278;------------------------------------------------------------- 10279; stz - store on zero 10280;------------------------------------------------------------- 10281 10282(define-pmacro (stz-sem mode src dst) 10283 (sequence () 10284 (if (eq zbit (const 1)) 10285 (set dst src))) 10286) 10287; stz #imm8,dst3 (m16) 10288(binary-arith16-b-S-imm8-dst3 stz "" (f-0-4 #xC) (f-4-1 1) stz-sem) 10289; stz.BW #imm,dst (m32) 10290(binary-arith32-imm-dst-defn QI QI .b 0 stz X #x9 #x0 #xF stz-sem) 10291(binary-arith32-imm-dst-defn HI HI .w 1 stz X #x9 #x0 #xF stz-sem) 10292 10293;------------------------------------------------------------- 10294; stzx - store on zero extention 10295;------------------------------------------------------------- 10296 10297(define-pmacro (stzx-sem mode src1 src2 dst) 10298 (sequence () 10299 (if (eq zbit (const 1)) 10300 (set dst src1) 10301 (set dst src2))) 10302 ) 10303; stzx #imm8,dst3 (m16) 10304(dni stzx16-imm8-imm8-r0h "stzx #Imm8,#Imm8,r0h" ((machine 16)) 10305 ("stzx #${Imm-8-QI},#${Imm-16-QI},r0h") 10306 (+ (f-0-4 #xD) (f-4-4 #xB) Imm-8-QI Imm-16-QI) 10307 (stzx-sem QI Imm-8-QI Imm-16-QI (reg h-r0h)) 10308 ()) 10309(dni stzx16-imm8-imm8-r0l "stzx #Imm8,#Imm8,r0l" ((machine 16)) 10310 ("stzx #${Imm-8-QI},#${Imm-16-QI},r0l") 10311 (+ (f-0-4 #xD) (f-4-4 #xC) Imm-8-QI Imm-16-QI) 10312 (stzx-sem QI Imm-8-QI Imm-16-QI (reg h-r0l)) 10313 ()) 10314(dni stzx16-imm8-imm8-dsp8sb "stzx #Imm8,#Imm8,dsp8[sb]" ((machine 16)) 10315 ("stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-u8}[sb]") 10316 (+ (f-0-4 #xD) (f-4-4 #xD) Imm-8-QI Dsp-16-u8 Imm-24-QI) 10317 (stzx-sem QI Imm-8-QI Imm-16-QI (mem16 QI (add (reg h-sb) Dsp-24-u8))) 10318 ()) 10319(dni stzx16-imm8-imm8-dsp8fb "stzx #Imm8,#Imm8,dsp8[fb]" ((machine 16)) 10320 ("stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-s8}[fb]") 10321 (+ (f-0-4 #xD) (f-4-4 #xE) Imm-8-QI Dsp-16-s8 Imm-24-QI) 10322 (stzx-sem QI Imm-8-QI Imm-24-QI (mem16 QI (add (reg h-fb) Dsp-16-s8))) 10323 ()) 10324(dni stzx16-imm8-imm8-abs16 "stzx #Imm8,#Imm8,abs16" ((machine 16)) 10325 ("stzx #${Imm-8-QI},#${Imm-32-QI},${Dsp-16-u16}") 10326 (+ (f-0-4 #xD) (f-4-4 #xF) Imm-8-QI Dsp-16-u16 Imm-32-QI) 10327 (stzx-sem QI Imm-8-QI Imm-32-QI (mem16 QI Dsp-16-u16)) 10328 ()) 10329; stzx.BW #imm,dst (m32) 10330(insn-imm1-imm2-dst-Unprefixed stzx #x9 #x3 #xF stzx-sem) 10331 10332;------------------------------------------------------------- 10333; subx - subtract extend (m32) 10334;------------------------------------------------------------- 10335 10336(define-pmacro (subx-sem mode src1 dst) 10337 (sequence ((mode result)) 10338 (set result (sub mode dst (ext mode src1))) 10339 (set obit (sub-oflag mode dst (ext mode src1) 0)) 10340 (set cbit (sub-cflag mode dst (ext mode src1) 0)) 10341 (set dst result) 10342 (set-z-and-s result))) 10343; subx #imm8,dst 10344(binary-arith32-imm-dst-defn QI SI "" 0 subx G #x9 #x1 #x1 subx-sem) 10345; subx src,dst 10346(binary-arith32-src-dst-defn QI SI "" 0 subx G #x1 #x0 subx-sem) 10347 10348;------------------------------------------------------------- 10349; tst - test 10350;------------------------------------------------------------- 10351 10352(define-pmacro (tst-sem mode src1 dst) 10353 (sequence ((mode result)) 10354 (set result (and mode dst src1)) 10355 (set-z-and-s result)) 10356) 10357 10358; tst.BW #imm,dst (m16 #1 m32 #1) 10359(binary-arith-imm-dst tst G (f-0-4 7) (f-4-3 3) (f-8-4 0) #x9 #x3 #xE tst-sem) 10360; tst.BW src,dst (m16 #2 m32 #3) 10361(binary-arith16-src-dst-defn QI QI .b 0 tst X (f-0-4 #x8) (f-4-3 0) tst-sem) 10362(binary-arith16-src-dst-defn HI HI .w 1 tst X (f-0-4 #x8) (f-4-3 0) tst-sem) 10363(binary-arith32-src-dst-Prefixed QI QI .b 0 tst G #x1 #x9 tst-sem) 10364(binary-arith32-src-dst-Prefixed HI HI .w 1 tst G #x1 #x9 tst-sem) 10365; tst.BW:S #imm,dst2 (m32 #2) 10366(binary-arith32-s-imm-dst QI .b 0 tst #x0 #x6 tst-sem) 10367(binary-arith32-s-imm-dst HI .w 1 tst #x0 #x6 tst-sem) 10368 10369;------------------------------------------------------------- 10370; und - undefined 10371;------------------------------------------------------------- 10372 10373(dni und16 "und" ((machine 16)) 10374 ("und") 10375 (+ (f-0-4 #xF) (f-4-4 #xF)) 10376 (nop) 10377 ()) 10378 10379(dni und32 "und" ((machine 32)) 10380 ("und") 10381 (+ (f-0-4 #xF) (f-4-4 #xF)) 10382 (nop) 10383 ()) 10384 10385;------------------------------------------------------------- 10386; wait 10387;------------------------------------------------------------- 10388 10389; ??? semantics 10390(dni wait16 "wait" ((machine 16)) 10391 ("wait") 10392 (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xF) (f-12-4 3)) 10393 (nop) 10394 ()) 10395 10396(dni wait "wait" ((machine 32)) 10397 ("wait") 10398 (+ (f-0-4 #xB) (f-4-4 2) (f-8-4 0) (f-12-4 3)) 10399 (nop) 10400 ()) 10401 10402;------------------------------------------------------------- 10403; xchg - exchange 10404;------------------------------------------------------------- 10405 10406(define-pmacro (xchg-sem mode src dst) 10407 (sequence ((mode result)) 10408 (set result src) 10409 (set src dst) 10410 (set dst result)) 10411 ) 10412(define-pmacro (xchg16-defn mode sz szc src srcreg) 10413 (dni (.sym xchg16 sz - srcreg) 10414 (.str "xchg" sz "-" srcreg ",dst16-16-" mode) 10415 ((machine 16)) 10416 (.str "xchg." sz " " srcreg ",${dst16-16-" mode "}") 10417 (+ (f-0-4 #x7) (f-4-3 #x5) (f-7-1 szc) (f-8-2 0) (f-10-2 src) (.sym dst16-16- mode)) 10418 (xchg-sem mode (reg (.sym h- srcreg)) (.sym dst16-16- mode)) 10419 ()) 10420) 10421(xchg16-defn QI b 0 0 r0l) 10422(xchg16-defn QI b 0 1 r0h) 10423(xchg16-defn QI b 0 2 r1l) 10424(xchg16-defn QI b 0 3 r1h) 10425(xchg16-defn HI w 1 0 r0) 10426(xchg16-defn HI w 1 1 r1) 10427(xchg16-defn HI w 1 2 r2) 10428(xchg16-defn HI w 1 3 r3) 10429(define-pmacro (xchg32-defn mode sz szc src srcreg) 10430 (dni (.sym xchg32 sz - srcreg) 10431 (.str "xchg" sz "-" srcreg ",dst32-16-Unprefixed-" mode) 10432 ((machine 32)) 10433 (.str "xchg." sz " " srcreg ",${dst32-16-Unprefixed-" mode "}") 10434 (+ (f-0-4 #xD) (.sym dst32-16-Unprefixed- mode) (f-7-1 szc) (f-10-2 0) (f-12-1 1) (f-13-3 src)) 10435 (xchg-sem mode (reg (.sym h- srcreg)) (.sym dst32-16-Unprefixed- mode)) 10436 ()) 10437) 10438(xchg32-defn QI b 0 0 r0l) 10439(xchg32-defn QI b 0 1 r1l) 10440(xchg32-defn QI b 0 2 a0) 10441(xchg32-defn QI b 0 3 a1) 10442(xchg32-defn QI b 0 4 r0h) 10443(xchg32-defn QI b 0 5 r1h) 10444(xchg32-defn HI w 1 0 r0) 10445(xchg32-defn HI w 1 1 r1) 10446(xchg32-defn HI w 1 2 a0) 10447(xchg32-defn HI w 1 3 a1) 10448(xchg32-defn HI w 1 4 r2) 10449(xchg32-defn HI w 1 5 r3) 10450 10451;------------------------------------------------------------- 10452; xor - exclusive or 10453;------------------------------------------------------------- 10454 10455(define-pmacro (xor-sem mode src1 dst) 10456 (sequence ((mode result)) 10457 (set result (xor mode src1 dst)) 10458 (set-z-and-s result) 10459 (set dst result)) 10460) 10461 10462; xor.BW #imm,dst (m16 #1 m32 #1) 10463(binary-arith-imm-dst xor G (f-0-4 7) (f-4-3 3) (f-8-4 1) #x9 #x0 #xE xor-sem) 10464; xor.BW src,dst (m16 #3 m32 #3) 10465(binary-arith-src-dst xor G (f-0-4 #x8) (f-4-3 4) #x1 #x9 xor-sem) 10466 10467;------------------------------------------------------------- 10468; Widening 10469;------------------------------------------------------------- 10470 10471(define-pmacro (exts-sem smode dmode src dst) 10472 (set dst (ext dmode (trunc smode src))) 10473) 10474(define-pmacro (extz-sem smode dmode src dst) 10475 (set dst (zext dmode (trunc smode src))) 10476) 10477 10478; exts.b dst for m16c 10479(ext16-defn QI HI .b 0 exts (f-0-4 7) (f-4-3 6) (f-8-4 6) exts-sem) 10480 10481; exts.w r0 for m16c 10482(dni exts16.w-r0 10483 "exts.w r0" 10484 ((machine 16)) 10485 "exts.w r0" 10486 (+ (f-0-4 #x7) (f-4-4 #xC) (f-8-4 #xF) (f-12-4 3)) 10487 (exts-sem HI SI R0 R2R0) 10488 ()) 10489 10490; exts.size dst for m32c 10491(ext32-defn QI HI .b 0 exts (f-0-4 #xC) (f-10-2 1) (f-12-4 #xE) exts-sem) 10492(ext32-defn HI SI .w 1 exts (f-0-4 #xC) (f-10-2 1) (f-12-4 #xE) exts-sem) 10493; exts.b src,dst for m32c 10494(ext32-binary-defn exts .b #x1 #x7 exts-sem) 10495 10496; extz.b src,dst for m32c 10497(ext32-binary-defn extz "" #x1 #xB extz-sem) 10498 10499;------------------------------------------------------------- 10500; Indirect 10501;------------------------------------------------------------- 10502 10503; TODO semantics 10504(dni srcind "SRC-INDIRECT" ((machine 32)) 10505 ("src-indirect") 10506 (+ (f-0-4 4) (f-4-4 1)) 10507 (set (reg h-src-indirect) 1) 10508 ()) 10509 10510(dni destind "DEST-INDIRECT" ((machine 32)) 10511 ("dest-indirect") 10512 (+ (f-0-4 0) (f-4-4 9)) 10513 (set (reg h-dst-indirect) 1) 10514 ()) 10515 10516(dni srcdestind "SRC-DEST-INDIRECT" ((machine 32)) 10517 ("src-dest-indirect") 10518 (+ (f-0-4 4) (f-4-4 9)) 10519 (sequence () (set (reg h-src-indirect) 1) (set (reg h-dst-indirect) 1)) 10520 ()) 10521