1; CRIS CPU description. -*- Scheme -*- 2; 3; Copyright 2003, 2004, 2007 Free Software Foundation, Inc. 4; 5; Contributed by Axis Communications AB. 6; 7; This file is part of the GNU Binutils. 8; 9; This program is free software; you can redistribute it and/or modify 10; it under the terms of the GNU General Public License as published by 11; the Free Software Foundation; either version 3 of the License, or 12; (at your option) any later version. 13; 14; This program is distributed in the hope that it will be useful, 15; but WITHOUT ANY WARRANTY; without even the implied warranty of 16; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17; GNU General Public License for more details. 18; 19; You should have received a copy of the GNU General Public License 20; along with this program; if not, write to the Free Software 21; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 22; MA 02110-1301, USA. 23 24(include "simplify.inc") 25 26;;;;;;;;;;;;;;;;;; -pmacro (generic ones) 27 28(define-pmacro (.car2 l) (.apply (.pmacro (a b) a) l)) 29(define-pmacro (.cadr2 l) (.apply (.pmacro (a b) b) l)) 30(define-pmacro (SI-ext x) "How to sign-extend a dword to dword (a nop)" x) 31(define-pmacro (HI-ext x) "How to sign-extend a word to dword" (ext SI x)) 32(define-pmacro (QI-ext x) "How to sign-extend a byte to dword" (ext SI x)) 33(define-pmacro (SI-zext x) "How to zero-extend a dword to dword (a nop)" x) 34(define-pmacro (HI-zext x) "How to zero-extend a word to dword" (zext SI x)) 35(define-pmacro (QI-zext x) "How to zero-extend a byte to dword" (zext SI x)) 36(define-pmacro 37 (define-pmacro-map x) 38 "On a list ((x0 y0) .. (xN yN)), 0 <= m <= N, (define-pmacro xm ym)" 39 (.splice 40 begin 41 (.unsplice 42 (.map 43 (.pmacro (l) (.apply (.pmacro (xm ym) (define-pmacro xm ym)) l)) x))) 44) 45 46;;;;;;;;;;;;;;;;;; -arch -isa -cpu -model 47 48(define-arch 49 (name cris) 50 (comment "Axis Communications CRIS") 51 (default-alignment unaligned) 52 (insn-lsb0? #t) 53 (machs crisv0 crisv3 crisv8 crisv10 crisv32) 54 (isas cris) 55) 56 57(define-isa 58 (name cris) 59 (base-insn-bitsize 16) 60 (liw-insns 1) 61 (parallel-insns 1) 62) 63 64(define-pmacro 65 (define-cpu-cris x-suffix x-comment) 66 "Define a CRIS CPU family" 67 (define-cpu 68 (name (.sym cris x-suffix f)) 69 (comment x-comment) 70 (endian little) 71 ; CGEN-FIXME: Should be deduced from the default? 72 (word-bitsize 32) 73 (file-transform (.str x-suffix)) 74 ) 75) 76 77; Useful when there's a need to iterate over all models. 78(define-pmacro (cris-cpu-model-numbers) 79 "List of CRIS CPU model numbers (version register contents)" 80 (0 3 8 10 32) 81) 82 83(define-pmacro (cris-cpu-models) 84 "List of CRIS CPU model names" 85 (.map (.pmacro (n) (.sym v n)) (cris-cpu-model-numbers)) 86) 87 88; Mapping from model name to number. 89(define-pmacro-map 90 (.map (.pmacro (n) ((.sym v n -number) n)) 91 (cris-cpu-model-numbers))) 92 93; FIXME: Rationalize these rules. 94; CPU names must be distinct from the architecture name and machine names. 95; The "b" suffix stands for "base" and is the convention. 96; The "f" suffix stands for "family" and is the convention. 97; We ignore the "b" convention, partly because v0 isn't really a "base", at 98; least not for some aspects of v32. 99(define-cpu-cris v0 "CRIS base family") 100(define-cpu-cris v3 "CRIS v3 family") 101(define-cpu-cris v8 "CRIS v8 family") 102(define-cpu-cris v10 "CRIS v10 family") 103(define-cpu-cris v32 "CRIS v32 family") 104 105(define-pmacro MACH-PRE-V32 (MACH crisv0,crisv3,crisv8,crisv10)) 106(define-pmacro MACH-V3-UP (MACH crisv3,crisv8,crisv10,crisv32)) 107(define-pmacro MACH-V32 (MACH crisv32)) 108(define-pmacro MACH-PC MACH-PRE-V32) 109(define-pmacro MACH-ACR MACH-V32) 110(define-pmacro MACH-BRANCH-OFFSET-AT-INSN MACH-V32) 111(define-pmacro MACH-BRANCH-OFFSET-AFTER-INSN MACH-PRE-V32) 112 113(define-pmacro 114 current-mach-is-v32 115 "Whether the generated code is for V32. See comment at h-v32." 116 (reg h-v32) 117) 118 119(define-pmacro (define-mach-cris x-suffix x-comment x-name) 120 "Define a CRIS mach" 121 (define-mach 122 (name (.sym cris x-suffix)) 123 ; They're all called "cris" in bfd. Watch out for breakages for some 124 ; uses. 125 (bfd-name x-name) 126 (comment x-comment) 127 (cpu (.sym cris x-suffix f))) 128) 129 130(define-mach-cris v0 "Generic CRIS v0 CPU, ETRAX 1 .. 3" "cris") 131(define-mach-cris v3 "Generic CRIS v3 CPU, ETRAX 4" "cris") 132(define-mach-cris v8 "Generic CRIS v8 CPU, ETRAX 100" "cris") 133(define-mach-cris v10 "Generic CRIS v10 CPU, ETRAX 100 LX" "cris") 134(define-mach-cris v32 "Generic CRIS v32 CPU, ETRAX FS" "crisv32") 135 136(define-pmacro (define-model-simplecris x-name x-comment) 137 "Define a simple CRIS model" 138 (define-model 139 (name (.sym cris x-name)) 140 (comment x-comment) 141 (mach (.sym cris x-name)) 142 143 (unit u-exec "Execution Unit" () 1 1 () () () ()) 144 (unit u-mem "Memory Unit" () 1 1 () () () ()) 145 146 (unit u-const16 "Fetch 16-bit operand" () 1 1 () () () ()) 147 (unit u-const32 "Fetch 32-bit operand" () 1 1 148 () () () ()) 149 ; Used in special-case insn, for example arithmetic with PC destination. 150 (unit u-stall "Stall unit" () 1 1 () () () ()) 151 (unit u-skip4 "Skip 4 bytes" () 1 1 () () () ()) 152 (unit u-multiply "Multiply Unit" () 1 1 ((MACH crisv10)) () () ()) 153 (unit u-movem "Movem Unit" () 1 1 () 154 ((Rd INT -1)) 155 () ())) 156) 157 158(define-model-simplecris v0 "Model of CRIS v0, ETRAX 1 .. 3") 159(define-model-simplecris v3 "Model of CRIS v3, ETRAX 4") 160(define-model-simplecris v8 "Model of CRIS v8, ETRAX 100") 161(define-model-simplecris v10 "Model of CRIS v10, ETRAX 100 LX") 162 163; For some reason, we get an error: 164; Generating arch.h ... 165; ERROR: In procedure vector-ref: 166; ERROR: Wrong type argument in position 1: () 167; if we include timings for machs that we don't generate sims for. 168; Last checked: CVS as of 2004-11-18. 169; CGEN-FIXME: Looks like another CGEN bug. When it's fixed (or when 170; generating sims for v0, v3 or v8), add 0, 3 and 8 to 171; simplecris-timing-models. But before that, simplecris-timing-x has to 172; be rewritten to work on a multiple-element-list, not assume a single 173; element. (A change which seems likely to depend on lexical scoping for 174; macros to be introduced: try the obvious implementation.) 175(define-pmacro simplecris-timing-models (10)) 176(define-pmacro (simplecris-common-timing x-units) 177 "Make timing models, using x-units for all simplecris-timing-models" 178 ; CGEN-FIXME: Another CGEN bug: the part (.unsplice (10)) will remain 179 ; unexpanded in (.sym crisv (.unsplice (10)) if we write this as 180 ; ((.splice (.sym crisv (.unsplice simplecris-timing-models)) 181 ; (.unsplice x-units))) 182 ((.splice (.sym crisv (.apply (.pmacro (x) x) simplecris-timing-models)) 183 (.unsplice x-units))) 184) 185 186(define-pmacro-map 187 ( 188 ; Timing for memory instructions running on a simple cris model. 189 ((simplecris-mem-timing) (simplecris-common-timing 190 ((unit u-mem) (unit u-exec)))) 191 ; Timing for movem instructions running on a simple cris model. 192 ((simplecris-movem-timing) (simplecris-common-timing 193 ((unit u-movem) (unit u-exec)))) 194 ; Similar, for an 8- or 16-bit constant ([PC+]) operand. 195 ((simplecris-const-timing-HI) 196 (simplecris-common-timing 197 ((unit u-const16) (unit u-exec)))) 198 ; Similar, for a 32-bit constant ([PC+]) operand. 199 ((simplecris-const-timing-SI) 200 (simplecris-common-timing 201 ((unit u-const32) (unit u-exec)))) 202 ; Similar, no particular operand. 203 ((simplecris-timing) (simplecris-common-timing 204 ((unit u-exec))))) 205) 206 207(define-model 208 (name crisv32) 209 (comment "Model of CRISv32") 210 (mach crisv32) 211 212 (state 213 ; Bitmask of h-gr register (0..15) and h-sr register (17..31) 214 ; modified by 3rd previous insn, updated by the u-exec unit. 215 ; Because there's no need to mark writes to special registers BZ and 216 ; WZ, bit 16 is for jump mark and bit 20 for memory-write mark. 217 (prev-prev-prev-modf-regs UINT) 218 219 ; Ditto for the 2nd previous insn. 220 (prev-prev-modf-regs UINT) 221 222 ; Ditto for the previous insn. 223 (prev-modf-regs UINT) 224 225 ; Bit-mask for regs modified by the current insn, propagated to 226 ; prev-modf-regs. 227 (modf-regs UINT) 228 229 ; Registers loaded by movem are not forwarded to the execution 230 ; stage, so we need to insert stall-cycles for ordinary insns 231 ; accessing such registers. In addition to the *modf-regs 232 ; above, these are set to tell *ordinary* insns which registers 233 ; are inaccessible. 234 235 (prev-prev-prev-movem-dest-regs UINT) 236 237 ; Ditto for the 2nd previous insn. 238 (prev-prev-movem-dest-regs UINT) 239 240 ; Ditto for the previous insn. 241 (prev-movem-dest-regs UINT) 242 243 ; Bit-mask for regs modified by the current insn, propagated to 244 ; prev-movem-dest-regs. 245 (movem-dest-regs UINT)) 246 247 ; It seems this pipeline description isn't used at all; this is just 248 ; for show. 249 ; Noteworthy is the placement of the memory stage before the execute stage. 250 (pipeline all "" () ((fetch) (decode) (memory) (execute) (writeback))) 251 252 ; Units that contribute only a constant pipeline delay are not included. 253 (unit u-mem "Memory Unit" () 1 1 () 254 ((Rs INT -1)) 255 () ()) 256 257 ; Artificial units for read/write-related hazard accounting. 258 (unit u-mem-r "Memory Unit Read" () 1 1 () () () ()) 259 (unit u-mem-w "Memory Unit Write" () 1 1 () () () ()) 260 261 (unit u-movem-rtom "Movem-to-memory Unit" () 1 1 () 262 ((Rs INT -1) (Rd INT -1)) 263 () ()) 264 (unit u-movem-mtor "Movem-to-register Unit" () 1 1 () 265 ((Rs INT -1) (Rd INT -1)) 266 () ()) 267 (unit u-multiply "Multiply Unit" () 1 1 () 268 ((Rs INT -1) (Rd INT -1)) 269 () ()) 270 (unit u-branch "Branch Unit" () 1 1 () 271 () 272 () ()) 273 (unit u-jump-r "Jump-to-register Unit" () 1 1 () 274 ((Rs INT -1)) 275 () ()) 276 (unit u-jump-sr "Jump-to-special-register Unit" () 1 1 () 277 ((Ps INT -1)) 278 () ()) 279 (unit u-jump "JAS/BAS Unit, saving PC" () 1 1 () 280 () 281 ((Pd INT -1)) ()) 282 283 ; To keep track of PC; not really functional units. 284 (unit u-const16 "Fetch 16-bit operand" () 1 1 () () () ()) 285 (unit u-const32 "Fetch 32-bit operand" () 1 1 () () () ()) 286 (unit u-skip4 "Skip 4 bytes" () 1 1 () () () ()) 287 288 ; For v32, we need to keep track of inputs (for movem destination 289 ; cycle penalties) and output (for e.g. memory source and jump 290 ; source cycle penalties). 291 (unit u-exec "Execution Unit" () 1 1 () 292 ((Rd INT -1) (Rs INT -1)) 293 ((Rd INT -1)) 294 ()) 295 296 ; Special case of u-exec for movem: don't treat Rd as an incoming 297 ; parameter. 298 (unit u-exec-movem "Execution Unit" () 1 1 () 299 ((Rs INT -1)) 300 ((Rd INT -1)) 301 ()) 302 303 ; Special case of u-exec when the destination is a special 304 ; register. 305 (unit u-exec-to-sr "Execution Unit" () 1 1 () 306 ((Rs INT -1)) 307 ((Pd INT -1)) ()) 308) 309 310(define-pmacro (crisv32-timing-destreg d) 311 "Timing for instructions running on a crisv32 model" 312 ((crisv32 313 (.splice unit u-exec (.unsplice d)))) 314) 315(define-pmacro (crisv32-timing) (crisv32-timing-destreg ())) 316 317(define-pmacro (cris-timing-Rd-sfield) 318 (crisv32-timing-destreg ((out Rd Rd-sfield))) 319) 320 321(define-pmacro (crisv32-timing-c-HI) 322 ((crisv32 (unit u-const16) (unit u-exec))) 323) 324 325(define-pmacro-map 326 ((crisv32-timing-c-QI crisv32-timing-c-HI) 327 ((crisv32-timing-c-SI) ((crisv32 (unit u-const32) (unit u-exec)))) 328 ((crisv32-timing-c-sr-SI) ((crisv32 (unit u-const32) (unit u-exec-to-sr)))) 329 ((crisv32-reg-sr-timing) ((crisv32 (unit u-exec-to-sr)))) 330 ((crisv32-mem-sr-timing) 331 ((crisv32 (unit u-mem) (unit u-mem-r) (unit u-exec-to-sr)))) 332 ((crisv32-mem-timing) ((crisv32 (unit u-mem) (unit u-mem-r) (unit u-exec)))) 333 ((crisv32-mem-write-timing) ((crisv32 (unit u-mem) (unit u-exec) (unit u-mem-w))))) 334) 335 336(define-pmacro-map 337 ( 338 ; Timing for instructions using memory operands. 339 ((cris-mem-timing) (.splice (.unsplice (simplecris-mem-timing)) 340 (.unsplice (crisv32-mem-timing)))) 341 ; Timing for instructions using memory operands. 342 ((cris-mem-write-timing) (.splice 343 (.unsplice (simplecris-mem-timing)) 344 (.unsplice (crisv32-mem-write-timing)))) 345 ; Timing for moves from general register to special register. 346 ((cris-reg-sr-timing) (.splice (.unsplice (simplecris-timing)) 347 (.unsplice (crisv32-reg-sr-timing)))) 348 ; Timing for moves from memory to special register. 349 ((cris-mem-sr-timing) (.splice (.unsplice (simplecris-mem-timing)) 350 (.unsplice (crisv32-mem-sr-timing)))) 351 ; Timing for non-mul, non-memory, non-special-register, 16-bit instructions. 352 ((cris-timing) (.splice (.unsplice (simplecris-timing)) 353 (.unsplice (crisv32-timing)))) 354 ; Timing for instructions with 8- or 16-bit constant operand ([PC+]). 355 ((cris-timing-const-HI) (.splice 356 (.unsplice (simplecris-const-timing-HI)) 357 (.unsplice (crisv32-timing-c-HI)))) 358 ; Timing for instructions with a 32-bit constant operand ([PC+]). 359 ((cris-timing-const-SI) (.splice 360 (.unsplice (simplecris-const-timing-SI)) 361 (.unsplice (crisv32-timing-c-SI)))) 362 ; Like cris-timing-const-SI, but destination special register. 363 ((cris-timing-const-sr-SI) (.splice 364 (.unsplice (simplecris-const-timing-SI)) 365 (.unsplice (crisv32-timing-c-sr-SI)))) 366 ; Like cris-timing-const-HI, but destination special register. 367 ((cris-timing-const-sr-HI) (.splice 368 (.unsplice (simplecris-const-timing-HI)) 369 (.unsplice (crisv32-timing-c-sr-SI))))) 370) 371 372(define-pmacro cris-timing-const-QI cris-timing-const-HI) 373(define-pmacro cris-timing-const-sr-QI cris-timing-const-sr-HI) 374 375(define-pmacro (simplecris-common-writable-specregs) 376 "The common writable special registers in pre-v32 models." 377 ((HI 5) (SI 9) (SI 10) (SI 11) (SI 12) (SI 13)) 378) 379 380(define-pmacro (simplecris-common-readable-specregs) 381 "The common readable special registers in pre-v32 models." 382 (.splice (.unsplice (simplecris-common-writable-specregs)) 383 (QI 0) (QI 1) (HI 4) (SI 8)) 384) 385 386(define-pmacro (cris-implemented-writable-specregs-v0) 387 "Special writable registers in v0 and their sizes" 388 (.splice (.unsplice (simplecris-common-writable-specregs)) (HI 6) (HI 7)) 389) 390(define-pmacro 391 cris-implemented-specregs-const-v0 392 cris-implemented-writable-specregs-v0 393) 394(define-pmacro (cris-implemented-readable-specregs-v0) 395 "Special readable registers in v0 and their sizes" 396 (.splice (.unsplice (simplecris-common-readable-specregs)) (HI 6) (HI 7)) 397) 398 399(define-pmacro (cris-implemented-writable-specregs-v3) 400 "Special writable registers in v3 and their sizes" 401 (.splice (.unsplice (cris-implemented-writable-specregs-v0)) (SI 14)) 402) 403(define-pmacro 404 cris-implemented-specregs-const-v3 405 cris-implemented-writable-specregs-v3 406) 407(define-pmacro (cris-implemented-readable-specregs-v3) 408 "Special readable registers in v3 and their sizes" 409 (.splice (.unsplice (cris-implemented-readable-specregs-v0)) (SI 14)) 410) 411 412(define-pmacro (cris-implemented-writable-specregs-v8) 413 "Special writable registers in v8 and their sizes" 414 (.splice (.unsplice (simplecris-common-writable-specregs)) (SI 14)) 415) 416(define-pmacro 417 cris-implemented-specregs-const-v8 418 cris-implemented-writable-specregs-v8 419) 420(define-pmacro (cris-implemented-readable-specregs-v8) 421 "Special readable registers in v8 and their sizes" 422 (.splice (.unsplice (simplecris-common-readable-specregs)) (SI 14)) 423) 424 425(define-pmacro (cris-implemented-writable-specregs-v10) 426 "Special writable registers in v10 and their sizes" 427 (.splice (.unsplice (simplecris-common-writable-specregs)) 428 (SI 7) (SI 14) (SI 15)) 429) 430(define-pmacro 431 cris-implemented-specregs-const-v10 432 cris-implemented-writable-specregs-v10 433) 434(define-pmacro (cris-implemented-readable-specregs-v10) 435 "Special registers in v10 and their sizes" 436 (.splice (.unsplice (simplecris-common-readable-specregs)) 437 (SI 7) (SI 14) (SI 15)) 438) 439 440(define-pmacro (cris-implemented-writable-specregs-v32) 441 "Special writable registers in v32 and their sizes" 442 ((QI 2) (QI 3) 443 (SI 5) (SI 6) (SI 7) (SI 9) 444 (SI 10) (SI 11) (SI 12) (SI 13) (SI 14) (SI 15)) 445) 446(define-pmacro (cris-implemented-readable-specregs-v32) 447 "Special readable registers in v32 and their sizes" 448 (.splice (.unsplice (cris-implemented-writable-specregs-v32)) 449 (QI 0) (QI 1) (HI 4) (SI 8)) 450) 451 452; For v32, all special register operations on constants (that is, 453; move) take 32-bit operands, not the real size of the register, as in 454; other move operations. 455(define-pmacro (cris-implemented-specregs-const-v32) 456 (.map (.pmacro (x) (SI (.cadr2 x))) 457 (cris-implemented-writable-specregs-v32)) 458) 459 460(define-pmacro cris-swap-codes 461 "CRIS Swap codes in numeric order (no zero)" 462 ( r b br w wr wb wbr 463 n nr nb nbr nw nwr nwb nwbr) 464) 465 466(define-pmacro cris-flagnames 467 "CRIS flag field values, dest and src fields concatenated" 468 (c v z n x i u p) ; ... b m for pre-v32 469) 470 471(define-pmacro-map 472 ; Bitnumber for each respective flag. 473 (.map (.pmacro (x num) ((.sym x -bitnumber) num)) 474 cris-flagnames (.iota 8)) 475) 476 477; I give up. Here's a perl-script to get the values I want for this macro 478; (not working along list principles, though). You can run this region. 479; perl -e '$x = "cvznxiup"; for ($i = 0; $i < 256; $i++) { $s = ""; 480; for ($j = 0; $j < 8; $j++) { if ($i & (1 << $j)) { 481; $s .= substr ($x, $j, 1);}} 482; printf ("%s%s", $s eq "" ? "_" : $s, (($i + 1) % 8) == 0 ? "\n " : " "); }' 483(define-pmacro cris-flag-combinations 484 "Combinations of flags in numeric order" 485 (_ c v cv z cz vz cvz 486 n cn vn cvn zn czn vzn cvzn 487 x cx vx cvx zx czx vzx cvzx 488 nx cnx vnx cvnx znx cznx vznx cvznx 489 i ci vi cvi zi czi vzi cvzi 490 ni cni vni cvni zni czni vzni cvzni 491 xi cxi vxi cvxi zxi czxi vzxi cvzxi 492 nxi cnxi vnxi cvnxi znxi cznxi vznxi cvznxi 493 u cu vu cvu zu czu vzu cvzu 494 nu cnu vnu cvnu znu cznu vznu cvznu 495 xu cxu vxu cvxu zxu czxu vzxu cvzxu 496 nxu cnxu vnxu cvnxu znxu cznxu vznxu cvznxu 497 iu ciu viu cviu ziu cziu vziu cvziu 498 niu cniu vniu cvniu zniu czniu vzniu cvzniu 499 xiu cxiu vxiu cvxiu zxiu czxiu vzxiu cvzxiu 500 nxiu cnxiu vnxiu cvnxiu znxiu cznxiu vznxiu cvznxiu 501 p cp vp cvp zp czp vzp cvzp 502 np cnp vnp cvnp znp cznp vznp cvznp 503 xp cxp vxp cvxp zxp czxp vzxp cvzxp 504 nxp cnxp vnxp cvnxp znxp cznxp vznxp cvznxp 505 ip cip vip cvip zip czip vzip cvzip 506 nip cnip vnip cvnip znip cznip vznip cvznip 507 xip cxip vxip cvxip zxip czxip vzxip cvzxip 508 nxip cnxip vnxip cvnxip znxip cznxip vznxip cvznxip 509 up cup vup cvup zup czup vzup cvzup 510 nup cnup vnup cvnup znup cznup vznup cvznup 511 xup cxup vxup cvxup zxup czxup vzxup cvzxup 512 nxup cnxup vnxup cvnxup znxup cznxup vznxup cvznxup 513 iup ciup viup cviup ziup cziup vziup cvziup 514 niup cniup vniup cvniup zniup czniup vzniup cvzniup 515 xiup cxiup vxiup cvxiup zxiup czxiup vzxiup cvzxiup 516 nxiup cnxiup vnxiup cvnxiup znxiup cznxiup vznxiup cvznxiup 517 ) 518) 519 520(define-pmacro cc-condition (not cbit)) 521(define-pmacro cs-condition cbit) 522(define-pmacro ne-condition (not zbit)) 523(define-pmacro eq-condition zbit) 524(define-pmacro vc-condition (not vbit)) 525(define-pmacro vs-condition vbit) 526(define-pmacro pl-condition (not nbit)) 527(define-pmacro mi-condition nbit) 528(define-pmacro ls-condition (or cbit zbit)) 529(define-pmacro hi-condition (not (or cbit zbit))) 530(define-pmacro ge-condition (not (xor vbit nbit))) 531(define-pmacro lt-condition (xor vbit nbit)) 532(define-pmacro gt-condition (not (or (xor vbit nbit) zbit))) 533(define-pmacro le-condition (or (xor vbit nbit) zbit)) 534(define-pmacro a-condition 1) 535 536; FIXME: define this properly for v10 and pre-v10. 537(define-pmacro wf-condition pbit) 538 539(define-pmacro (cris-condition condno) 540 "Return condition state for condition number CONDNO" 541 (sequence 542 BI 543 ((SI tmpcond) (BI condres)) 544 (set tmpcond condno) 545 (.splice 546 cond 547 (.unsplice 548 (.map 549 (.pmacro 550 (condn condc) 551 ((eq tmpcond condn) (set condres (.sym condc -condition)))) 552 (.iota 16) 553 cris-condition-codes))) 554 condres) 555) 556 557;;;;;;;;;;;;;;;;;; -keyword 558 559; General registers. 560(define-pmacro (cris-general-gregs) 561 (.splice (SP 14) (.unsplice (.map (.pmacro (n) ((.sym R n) n)) (.iota 15)))) 562) 563 564; Can't keep more than one gr-names definition at the same time; 565; generated enum declarations in sim/cris/cris-desc.h will collide. 566; FIXME: (include "different-mach-parts") 567 568(define-keyword 569 (name gr-names-pcreg) 570 (attrs MACH-PC) 571 (print-name h-gr-real-pc) 572 ; Put PC first so it is preferred over r15. 573 (.splice values (PC 15) (.unsplice (cris-general-gregs))) 574) 575 576(define-keyword 577 (name gr-names-acr) 578 (attrs MACH-ACR) 579 ; The print-name directive will control the enum prefix. With the 580 ; arguably more appropriate h-gr-v32 or h-gr-acr, we'd get names like 581 ; H_GR_ACR_R0 instead of H_GR_R0. Since we have to choose something for 582 ; unprefixed names, we use the CRISv32 names. FIXME: All users should 583 ; change to use H_GR_V32_R0 (etc.), then change this to h-gr-v32. 584 (print-name h-gr) 585 ; Put ACR first so it is preferred over r15. 586 (.splice values (ACR 15) (.unsplice (cris-general-gregs))) 587) 588 589(define-keyword 590 (name gr-names-v32) 591 (attrs MACH-V32) 592 ; In preparation for implementing the FIXME above. 593 (print-name h-gr-v32) 594 ; Put ACR first so it is preferred over r15. 595 (.splice values (ACR 15) (.unsplice (cris-general-gregs))) 596) 597 598; Special registers with names common to all. 599(define-pmacro (cris-general-pregs) 600 (.splice 601 (VR 1) 602 (SRP 11) 603 (.unsplice (.map (.pmacro (n) ((.sym P n) n)) (.iota 15)))) 604) 605 606(define-keyword 607 (name p-names-v10) 608 (attrs MACH-PRE-V32) 609 (print-name h-sr-pre-v32) 610 (.splice 611 values 612 (CCR 5) 613 (MOF 7) 614 (IBR 9) 615 (IRP 10) 616 (BAR 12) 617 (DCCR 13) 618 (BRP 14) 619 (USP 15) 620 (.unsplice (cris-general-pregs))) 621) 622 623(define-keyword 624 (name p-names-v32) 625 (attrs MACH-V32) 626 ; See comment for gr-names-acr. 627 (print-name h-sr) 628 (.splice 629 values 630 (BZ 0) 631 (PID 2) 632 (SRS 3) 633 (WZ 4) 634 (EXS 5) 635 (EDA 6) 636 (MOF 7) 637 (DZ 8) 638 (EBP 9) 639 (ERP 10) 640 (NRP 12) 641 (CCS 13) 642 (USP 14) 643 (SPC 15) 644 (.unsplice (cris-general-pregs))) 645) 646 647; Similarly as for h-gr-v32, in preparation. 648(define-keyword 649 (name p-names-v32-x) 650 (attrs MACH-V32) 651 ; See comment for gr-names-acr. 652 (print-name h-sr-v32) 653 (.splice 654 values 655 (BZ 0) 656 (PID 2) 657 (SRS 3) 658 (WZ 4) 659 (EXS 5) 660 (EDA 6) 661 (MOF 7) 662 (DZ 8) 663 (EBP 9) 664 (ERP 10) 665 (NRP 12) 666 (CCS 13) 667 (USP 14) 668 (SPC 15) 669 (.unsplice (cris-general-pregs))) 670) 671 672(define-pmacro p0 (reg h-sr 0)) 673(define-pmacro vr (reg h-sr 1)) 674(define-pmacro pid (reg h-sr 2)) 675(define-pmacro srs (reg h-sr 3)) 676(define-pmacro p4 (reg h-sr 4)) 677(define-pmacro ccr (reg h-sr 5)) 678(define-pmacro mof (reg h-sr 7)) 679(define-pmacro p8 (reg h-sr 8)) 680(define-pmacro ibr (reg h-sr 9)) 681(define-pmacro ebp (reg h-sr 9)) 682(define-pmacro erp (reg h-sr 10)) 683(define-pmacro srp (reg h-sr 11)) 684(define-pmacro ccs (reg h-sr 13)) 685(define-pmacro dccr (reg h-sr 13)) 686(define-pmacro usp (reg h-sr 14)) 687(define-pmacro spc (reg h-sr 15)) 688 689(define-pmacro sp (reg h-gr 14)) 690(define-pmacro acr (reg h-gr 15)) 691 692(define-pmacro cris-condition-codes 693 "CRIS condition codes in numeric order" 694 (cc cs ne eq vc vs pl mi ls hi ge lt gt le a wf) 695) 696 697; No use having different lists; this is the only CC that 698; differs between v10 and v32, and mostly in the name. 699(define-pmacro sb wf) 700 701 702;;;;;;;;;;;;;;;;;; -hardware 703 704;; Various constant generators. 705 706(define-hardware 707 (name h-inc) 708 (comment "autoincrement-bit syntax specifier") 709 (type immediate (UINT 1)) 710 (values keyword "" (("" 0) ("+" 1))) 711) 712 713(define-hardware 714 (name h-ccode) 715 (comment "Condition code specifier") 716 (type immediate (UINT 4)) 717 (values keyword "" 718 (.map (.pmacro (x y) ((.str x) y)) 719 cris-condition-codes (.iota 16))) 720) 721 722(define-hardware 723 (name h-swap) 724 (comment "Swap option specifier") 725 (type immediate (UINT 4)) 726 (values 727 keyword "" 728 (.splice 729 (" " 0) 730 (.unsplice 731 (.map 732 (.pmacro (x y) ((.str x) y)) cris-swap-codes (.iota 15 1))))) 733) 734 735(define-hardware 736 (name h-flagbits) 737 (comment "Flag bits specifier") 738 (type immediate (UINT 8)) 739 (values 740 keyword "" 741 (.map (.pmacro (x y) ((.str x) y)) cris-flag-combinations (.iota 256))) 742) 743 744; Apparently, the semantic-name isn't used for accessors, so external 745; users like the sim glue and SID sees the -v32 and -pre-v32 munged names. 746; Defining "dispatchers"; virtual registers whose getter and setter works 747; on the "real" mach variants, seems to help. CGEN-FIXME: Make 748; semantic-name set the generated names. 749(define-pmacro (cris-d-hwreg x-name x-type) 750 (define-hardware 751 (name x-name) 752 (comment (.str "Dispatcher for " x-name)) 753 (attrs VIRTUAL) 754 (type register x-type) 755 (get () (reg (.sym x-name -x))) 756 (set (val) (set (reg (.sym x-name -x)) val))) 757) 758(define-pmacro (cris-d-hwregf-a x-name x-type x-n x-attrs) 759 (define-hardware 760 (name x-name) 761 (comment (.str "Dispatcher for " x-name)) 762 (.splice attrs VIRTUAL (.unsplice x-attrs)) 763 (type register x-type (x-n)) 764 (get (index) (reg (.sym x-name -x) index)) 765 (set (index val) (set-quiet (reg (.sym x-name -x) index) val))) 766) 767(define-pmacro (cris-d-hwregf x-name x-type x-n) 768 (cris-d-hwregf-a x-name x-type x-n ()) 769) 770(define-pmacro (cris-d-hwregf-p x-name x-type x-n) 771 (cris-d-hwregf-a x-name x-type x-n (PROFILE)) 772) 773 774; At first glance we could use (eq-attr (current-mach) ...) for 775; everything, but that seems sometimes (always?) to yield false. For 776; ifields, it causes noncompilable C-code. For the insn semantics code, 777; it causes tests movei.ms and mulv32.ms to fail, apparently because the 778; current-mach-is-v32 usage in flags setting is miscompiled as 0 (or 779; rather, misgenerated). Instead we use different definitions of a 780; MACH-tagged virtual register yielding a constant, together with a 781; pmacro. CGEN-FIXME: If eq-attr is someday fixed, we could just remove 782; these h-v32 virtual register definitions and change the pmacro 783; definition for current-mach-is-v32. 784(define-hardware 785 (semantic-name h-v32) 786 (name h-v32-v32) 787 (attrs MACH-V32 VIRTUAL) 788 (type register BI) 789 (get () (const BI 1)) 790 (set (val) (error "Can't set h-v32")) 791) 792(define-hardware 793 (semantic-name h-v32) 794 (name h-v32-non-v32) 795 (attrs MACH-PRE-V32 VIRTUAL) 796 (type register BI) 797 (get () (const BI 0)) 798 (set (val) (error "Can't set h-v32")) 799) 800 801;; "Real" hardware. 802 803(define-hardware 804 (name h-pc) 805 (comment "program counter") 806 (attrs PC PROFILE) 807 (type pc) 808 ; There's no bit 0 in PC, so just ignore it when jumping etc. 809 (set (val) (set (raw-reg h-pc) (and val (inv 1)))) 810) 811 812; Note that setting register 15 isn't handled here, but in each insn, so 813; the proper "jump" attributes and other special stuff for speedy 814; execution can be present. 815(cris-d-hwregf-p h-gr SI 16) 816(define-hardware 817 (semantic-name h-gr-x) 818 (name h-gr-pc) 819 (attrs MACH-PC VIRTUAL) 820 (comment "General purpose registers, aborting on PC access") 821 (type register SI (16)) 822 (indices extern-keyword gr-names-pcreg) 823 (get 824 (index) 825 (if SI (eq index 15) 826 (error SI "General register read of PC is not implemented.") 827 (reg SI h-gr-real-pc index))) 828 (set 829 (index val) 830 (sequence 831 () 832 (if (eq index 15) 833 (error "General register write to PC is not implemented.")) 834 (set (reg SI h-gr-real-pc index) val))) 835) 836(define-hardware 837 (name h-gr-real-pc) 838 (attrs MACH-PC) 839 (comment "General purpose registers") 840 (type register SI (16)) 841 (indices extern-keyword gr-names-pcreg) 842) 843 844; We have to use a virtual register trick to get the "raw", unaccounted 845; contents of the global register; the raw-reg RTX only works for 846; non-virtual register files. 847(define-hardware 848 (semantic-name h-raw-gr) 849 (name h-raw-gr-pc) 850 (attrs MACH-PC VIRTUAL) 851 (comment "Unaccounted version of general purpose registers") 852 (type register SI (16)) 853 (get (index) (raw-reg h-gr-real-pc index)) 854 (set (index val) (set-quiet (raw-reg h-gr-real-pc index) val)) 855) 856(define-hardware 857 (semantic-name h-gr-x) 858 (name h-gr-acr) 859 (attrs MACH-ACR) 860 (comment "General purpose registers") 861 (type register SI (16)) 862 (indices extern-keyword gr-names-acr) 863) 864(define-hardware 865 (semantic-name h-raw-gr) 866 (name h-raw-gr-acr) 867 (attrs MACH-ACR VIRTUAL) 868 (comment "Unaccounted version of general purpose registers") 869 (type register SI (16)) 870 (get (index) (raw-reg h-gr-x index)) 871 (set (index val) (set-quiet (raw-reg h-gr-x index) val)) 872) 873 874; FIXME: get and set semantics? Unknown how to split semantics best; with 875; get/set semantics or within the insn specification. Doing the former for 876; now. Should use different names for pre-v10. 877; FIXME: No dccr for v0 and v3. Different high flag bits. 878(cris-d-hwregf-p h-sr SI 16) 879(define-pmacro 880 (cris-h-sr machver) 881 (define-hardware 882 (semantic-name h-sr-x) 883 (name (.sym h-sr-v machver)) 884 (attrs (MACH (.sym crisv machver))) 885 (comment (.str "Special registers for v" machver)) 886 (type register SI (16)) 887 (indices extern-keyword p-names-v10) 888 (get 889 (index) 890 (cond 891 SI 892 ((orif (orif (eq index (regno p0)) (eq index (regno p4))) 893 (eq index (regno p8))) 0) 894 ((eq index (regno vr)) machver) 895 ((orif (eq index (regno ccr)) 896 (eq index (regno dccr))) 897 ; Return "P U I X N Z V C" for the low 8 bits. 898 ; FIXME: More bits. 899 (or SI 900 (and SI (raw-reg SI h-sr-x (regno ccr)) #xffffff00) 901 (or 902 (zext SI (reg BI h-cbit)) 903 (or 904 (sll (zext SI (reg BI h-vbit)) 1) 905 (or 906 (sll (zext SI (reg BI h-zbit)) 2) 907 (or 908 (sll (zext SI (reg BI h-nbit)) 3) 909 (or 910 (sll (zext SI (reg BI h-xbit)) 4) 911 (or 912 (sll (zext SI (reg BI h-ibit)) 5) 913 (or 914 (sll (zext SI (reg BI h-ubit)) 6) 915 (or 916 (sll (zext SI (reg BI h-pbit)) 7) 917 0)))))))))) 918 (else (raw-reg SI h-sr-x index)))) 919 (set 920 (index val) 921 (cond 922 ((orif (orif (eq index (regno p0)) (eq index (regno p4))) 923 (orif (eq index (regno p8)) (eq index (regno vr)))) 924 (nop)) 925 ((orif (eq index (regno ccr)) (eq index (regno dccr))) 926 (sequence 927 () 928 (set (reg BI h-cbit) (if BI (ne SI (and val (sll 1 0)) 0) 1 0)) 929 (set (reg BI h-vbit) (if BI (ne SI (and val (sll 1 1)) 0) 1 0)) 930 (set (reg BI h-zbit) (if BI (ne SI (and val (sll 1 2)) 0) 1 0)) 931 (set (reg BI h-nbit) (if BI (ne SI (and val (sll 1 3)) 0) 1 0)) 932 (set (reg BI h-xbit) (if BI (ne SI (and val (sll 1 4)) 0) 1 0)) 933 (set (reg BI h-ibit) (if BI (ne SI (and val (sll 1 5)) 0) 1 0)) 934 (set (reg BI h-ubit) (if BI (ne SI (and val (sll 1 6)) 0) 1 0)) 935 (set (reg BI h-pbit) (if BI (ne SI (and val (sll 1 7)) 0) 1 0)) 936 (set-quiet (raw-reg SI h-sr-x (regno ccr)) val) 937 (set-quiet (raw-reg SI h-sr-x (regno dccr)) val))) 938 (else (set-quiet (raw-reg SI h-sr-x index) val))))) 939) 940 941(cris-h-sr 0) 942(cris-h-sr 3) 943(cris-h-sr 8) 944(cris-h-sr 10) 945 946(define-hardware 947 (semantic-name h-sr-x) 948 (name h-sr-v32) 949 (attrs MACH-V32) 950 (comment "Special registers for v32") 951 (type register SI (16)) 952 (indices extern-keyword p-names-v32) 953 954 (get 955 (index) 956 (cond 957 SI 958 ((orif (orif (eq index (regno p0)) (eq index (regno p4))) 959 (eq index (regno p8))) 0) 960 ((eq index (regno vr)) 32) 961 ((eq index (regno ccs)) 962 ; Return "S R P U I X N Z V C" for the low 10 bits. 963 (or SI 964 (and SI (raw-reg SI h-sr-x (regno ccs)) #x3ffffc00) 965 (or 966 (zext SI (reg BI h-cbit)) 967 (or 968 (sll (zext SI (reg BI h-vbit)) 1) 969 (or 970 (sll (zext SI (reg BI h-zbit)) 2) 971 (or 972 (sll (zext SI (reg BI h-nbit)) 3) 973 (or 974 (sll (zext SI (reg BI h-xbit)) 4) 975 (or 976 (sll (zext SI (reg BI h-ibit)) 5) 977 (or 978 (sll (zext SI (reg BI h-ubit)) 6) 979 (or 980 (sll (zext SI (reg BI h-pbit)) 7) 981 (or 982 (sll (zext SI (reg BI h-rbit)) 8) 983 (or 984 (sll (zext SI (reg BI h-sbit)) 9) 985 (or 986 (sll (zext SI (reg BI h-mbit)) 30) 987 (or 988 (sll (zext SI (reg BI h-qbit)) 31) 989 0)))))))))))))) 990 ((eq index (regno usp)) 991 ; In user mode, return general stack pointer. 992 (if BI (reg BI h-ubit) 993 (raw-reg SI h-gr-x (regno sp)) 994 (raw-reg SI h-sr-x (regno usp)))) 995 (else (raw-reg SI h-sr-x index)))) 996 997 (set 998 (index val) 999 (cond 1000 ((orif (orif (eq index (regno p0)) (eq index (regno p4))) 1001 (orif (eq index (regno p8)) (eq index (regno vr)))) 1002 (nop)) 1003 ((eq index (regno ccs)) 1004 (sequence 1005 () 1006 ; Protected bits are handled as such in the respective setter function. 1007 (set (reg BI h-cbit) (if BI (ne SI (and val (sll 1 0)) 0) 1 0)) 1008 (set (reg BI h-vbit) (if BI (ne SI (and val (sll 1 1)) 0) 1 0)) 1009 (set (reg BI h-zbit) (if BI (ne SI (and val (sll 1 2)) 0) 1 0)) 1010 (set (reg BI h-nbit) (if BI (ne SI (and val (sll 1 3)) 0) 1 0)) 1011 (set (reg BI h-xbit) (if BI (ne SI (and val (sll 1 4)) 0) 1 0)) 1012 (set (reg BI h-ibit) (if BI (ne SI (and val (sll 1 5)) 0) 1 0)) 1013 (set (reg BI h-sbit) (if BI (ne SI (and val (sll 1 9)) 0) 1 0)) 1014 (set (reg BI h-mbit) (if BI (ne SI (and val (sll 1 30)) 0) 1 0)) 1015 (set (reg BI h-pbit) (if BI (ne SI (and val (sll 1 7)) 0) 1 0)) 1016 (set (reg BI h-rbit) (if BI (ne SI (and val (sll 1 8)) 0) 1 0)) 1017 (set (reg BI h-qbit) (if BI (ne SI (and val (sll 1 31)) 0) 1 0)) 1018 ; Set the U bit last, so the setter functions for the other bits 1019 ; don't see it as set from this operation. It is not cleared from 1020 ; this operation, so we don't have to handle that; it's only 1021 ; cleared "manually" from within simulator-specific context-switch 1022 ; machinery. 1023 (set (reg BI h-ubit) (if BI (ne SI (and val (sll 1 6)) 0) 1 0)) 1024 (set-quiet (raw-reg SI h-sr-x index) val))) 1025 ((eq index (regno usp)) 1026 ; In user mode, set general register 14 too, whenever setting USP. 1027 (sequence 1028 () 1029 (if (reg BI h-ubit) (set (raw-reg SI h-gr-x (regno sp)) val)) 1030 (set (raw-reg SI h-sr-x (regno usp)) val))) 1031 ((eq index (regno srs)) 1032 (if (not (reg BI h-ubit)) (set (raw-reg h-sr-x (regno srs)) val))) 1033 ((eq index (regno ebp)) 1034 (if (not (reg BI h-ubit)) (set (raw-reg h-sr-x (regno ebp)) val))) 1035 ((eq index (regno pid)) 1036 (if (not (reg BI h-ubit)) 1037 (sequence 1038 () 1039 (c-call VOID "@cpu@_write_pid_handler" val) 1040 (set (raw-reg h-sr-x (regno pid)) val)))) 1041 ((eq index (regno spc)) 1042 (if (not (reg BI h-ubit)) (set (raw-reg h-sr-x (regno spc)) val))) 1043 (else (set-quiet (raw-reg SI h-sr-x index) val)))) 1044) 1045 1046(define-hardware 1047 (name h-supr) 1048 (attrs MACH-V32 VIRTUAL) 1049 (comment "Support registers") 1050 (type register SI (16)) 1051 (values keyword "" (.map (.pmacro (y) ((.str S y) y)) (.iota 16))) 1052 (get (index) (c-call SI "@cpu@_read_supr" index)) 1053 (set (index val) (c-call VOID "@cpu@_write_supr" index val)) 1054) 1055 1056(define-pmacro (cris-dsh semantic-name name comment attrs type) 1057 "Like dsh, but the semantic-name is separate" 1058 (define-full-hardware 1059 name comment attrs semantic-name type () () () () () ()) 1060) 1061 1062; We define the condition codes that hold arithmetic flags separately 1063; and "or" them in, in the get and set methods of the special 1064; registers. We define arithmetic flags as any of C V Z N X. They 1065; thankfully have that order (zero-based) in all processor versions. 1066 1067; To avoid having two variants of most move-type instructions because V32 1068; doesn't set C and V (and N and Z), we fake the setting to virtual 1069; registers which have two different implementations. 1070(define-pmacro (cris-move-flag f f-name f-whence) 1071 "Flag set differently in pre-v32 and v32 in some cases" 1072 (begin 1073 (dsh (.sym h- f bit) (.str f-name " bit") () (register BI)) 1074 (cris-d-hwreg (.sym h- f bit-move) BI) 1075 (define-hardware 1076 (semantic-name (.sym h- f bit-move-x)) 1077 (name (.sym h- f bit-move-v32)) 1078 (comment (.str f-name " bit set in " f-whence " instructions, ignored")) 1079 (attrs MACH-V32 VIRTUAL) 1080 (type register BI) 1081 (get 1082 () 1083 (sequence BI () 1084 (error (.str "Can't get h-" f "bit-move on CRISv32")) 0)) 1085 (set (val) (nop))) 1086 (define-hardware 1087 (semantic-name (.sym h- f bit-move-x)) 1088 (name (.sym h- f bit-move-pre-v32)) 1089 (comment 1090 (.str 1091 f-name " bit set in " f-whence " instructions, same as " f "bit")) 1092 (attrs MACH-PRE-V32 VIRTUAL) 1093 (type register BI) 1094 (get () (reg (.sym h- f bit))) 1095 (set (val) (set (reg (.sym h- f bit)) val)))) 1096) 1097 1098(cris-move-flag c "carry" "move-type") 1099(cris-move-flag v "overflow" "move-type") 1100(cris-move-flag z "zero" "moveq") 1101(cris-move-flag n "sign" "moveq") 1102 1103(dsh h-xbit "extended-arithmetic bit" () (register BI)) 1104(cris-d-hwreg h-ibit BI) 1105(cris-dsh h-ibit-x h-ibit-pre-v32 1106 "interrupt-enable bit" (MACH-PRE-V32) (register BI)) 1107(dsh h-pbit "sequence-broken bit" ((MACH crisv10,crisv32)) (register BI)) 1108(dsh h-rbit "carry bit for MCP+restore-p bit" (MACH-V32) (register BI)) 1109(cris-d-hwreg h-ubit BI) 1110(cris-dsh h-ubit-x h-ubit-pre-v32 1111 "user mode bit" ((MACH crisv10)) (register BI)) 1112(dsh h-gbit "guru mode bit" (MACH-V32) (register BI)) 1113 1114; When doing a transition from kernel to user mode on V32, we save the 1115; stack pointer in an internal register and copy USP to R14, so we don't 1116; need non-trivial handlers for general registers. 1117(dsh 1118 h-kernel-sp 1119 "Kernel stack pointer during user mode" 1120 (MACH-V32) 1121 (register SI) 1122) 1123 1124(define-hardware 1125 (semantic-name h-ubit-x) 1126 (name h-ubit-v32) 1127 (comment "User mode bit") 1128 (attrs MACH-V32) 1129 (type register BI) 1130 (set 1131 (val) 1132 (sequence 1133 () 1134 (if (andif val (not (raw-reg BI h-ubit-x))) 1135 (sequence 1136 () 1137 (set (reg SI h-kernel-sp) (raw-reg h-gr-x (regno sp))) 1138 (set (raw-reg h-gr-x (regno sp)) (raw-reg h-sr-x (regno usp))) 1139 (set (raw-reg BI h-ubit-x) val) 1140 (c-call VOID "@cpu@_usermode_enabled"))))) 1141) 1142 1143(define-hardware 1144 (semantic-name h-ibit-x) 1145 (name h-ibit-v32) 1146 (comment "Interrupt-enable bit") 1147 (attrs MACH-V32) 1148 (type register BI) 1149 (set 1150 (val) 1151 (sequence 1152 () 1153 (if (not (reg BI h-ubit)) 1154 (sequence 1155 ((BI enabled)) 1156 (set enabled (andif val (not (raw-reg BI h-ibit-x)))) 1157 (set (raw-reg BI h-ibit-x) val) 1158 ; Call handler when enabling. 1159 (if enabled (c-call VOID "@cpu@_interrupts_enabled")))))) 1160) 1161 1162(define-hardware 1163 (name h-mbit) 1164 (comment "NMI enable bit") 1165 (attrs MACH-V32) 1166 (type register BI) 1167 (set 1168 (val) 1169 (sequence 1170 () 1171 ; Don't allow clearing (through this handler) when once set. 1172 (if (andif val (andif (not (raw-reg BI h-mbit)) (not (reg BI h-ubit)))) 1173 (sequence 1174 () 1175 (set (raw-reg BI h-mbit) 1) 1176 ; Call handler when enabling. 1177 (c-call VOID "@cpu@_nmi_enabled"))))) 1178) 1179 1180(define-pmacro 1181 (dsh-cond-bit-v32 x-name x-comment x-cond) 1182 "dsh bit for MACH-V32, with bit only changeable when X-COND" 1183 (define-hardware 1184 (name x-name) 1185 (comment x-comment) 1186 (attrs MACH-V32) 1187 (type register BI) 1188 (set (val) (sequence () (if x-cond (set (raw-reg BI x-name) val))))) 1189) 1190(define-pmacro 1191 (dsh-protected-bit-v32 x-name x-comment) 1192 "dsh bit for MACH-V32, with bit only changeable in kernel mode" 1193 (dsh-cond-bit-v32 x-name x-comment (not (reg BI h-ubit))) 1194) 1195(dsh-protected-bit-v32 h-qbit "Pending single-step bit") 1196 1197(define-hardware 1198 (name h-sbit) 1199 (comment "Cause single step exception on ... [see CRISv32 ref] bit") 1200 (attrs MACH-V32) 1201 (type register BI) 1202 (set 1203 (val) 1204 (sequence 1205 () 1206 (if (not (reg BI h-ubit)) 1207 (sequence 1208 ((BI enabled)) 1209 (set enabled (andif val (not (raw-reg BI h-sbit)))) 1210 (set (raw-reg BI h-sbit) val) 1211 ; Call handler when enabling. 1212 (if enabled (c-call VOID "@cpu@_single_step_enabled")))))) 1213) 1214 1215(dnop cbit "" (SEM-ONLY) h-cbit f-nil) 1216(dnop cbit-move 1217 "cbit for pre-V32, nothing for newer" (SEM-ONLY) h-cbit-move f-nil) 1218(dnop vbit "" (SEM-ONLY) h-vbit f-nil) 1219(dnop vbit-move 1220 "vbit for pre-V32, nothing for newer" (SEM-ONLY) h-vbit-move f-nil) 1221(dnop zbit "" (SEM-ONLY) h-zbit f-nil) 1222(dnop zbit-move 1223 "zbit for pre-V32, nothing for newer" (SEM-ONLY) h-zbit-move f-nil) 1224(dnop nbit "" (SEM-ONLY) h-nbit f-nil) 1225(dnop nbit-move 1226 "nbit for pre-V32, nothing for newer" (SEM-ONLY) h-nbit-move f-nil) 1227(dnop xbit "" (SEM-ONLY) h-xbit f-nil) 1228(dnop ibit "" (SEM-ONLY) h-ibit f-nil) 1229(dnop ubit "" (SEM-ONLY (MACH crisv10,crisv32)) h-ubit f-nil) 1230(dnop pbit "" (SEM-ONLY (MACH crisv10,crisv32)) h-pbit f-nil) 1231(dnop 1232 rbit "carry bit for MCP+restore-P flag bit" (SEM-ONLY MACH-V32) h-rbit f-nil) 1233(dnop sbit "" (SEM-ONLY MACH-V32) h-sbit f-nil) 1234(dnop mbit "" (SEM-ONLY MACH-V32) h-mbit f-nil) 1235(dnop qbit "" (SEM-ONLY MACH-V32) h-qbit f-nil) 1236 1237(cris-d-hwreg h-insn-prefixed-p BI) 1238(cris-dsh 1239 h-insn-prefixed-p-x 1240 h-insn-prefixed-p-pre-v32 1241 "instruction-is-prefixed bit" 1242 (MACH-PRE-V32) 1243 (register BI) 1244) 1245 1246; CRISv32 has no prefixing on memory accesses. CGEN-FIXME: [Once (eq-attr 1247; (current-mach) ...) works]: can we change andif and/or orif so it 1248; doesn't look too close at short-circuited operands and avoid defining an 1249; operand that doesn't apply to a certain mach? 1250(define-hardware 1251 (semantic-name h-insn-prefixed-p-x) 1252 (name h-insn-prefixed-p-v32) 1253 (attrs MACH-V32 VIRTUAL) 1254 (comment "instruction-is-prefixed bit") 1255 (type register BI) 1256 (get () (const BI 0)) 1257 (set (val) (nop)) 1258) 1259(dnop 1260 prefix-set 1261 "Instruction-prefixed flag" 1262 (SEM-ONLY) 1263 h-insn-prefixed-p 1264 f-nil 1265) 1266 1267(cris-dsh 1268 h-prefixreg h-prefixreg-pre-v32 1269 "Prefix-address register" (MACH-PRE-V32) (register SI)) 1270(define-hardware 1271 (semantic-name h-prefixreg) 1272 (name h-prefixreg-v32) 1273 (comment "Prefix-address register, redirecting to ACR") 1274 (attrs MACH-V32 VIRTUAL) 1275 (type register SI) 1276 ; Why can't we have just a "acr" a.k.a "(reg h-gr 15)" here? 1277 (get () acr) 1278 (set (value) (set acr value)) 1279) 1280 1281(dnop 1282 prefixreg 1283 "Prefix address" 1284 (SEM-ONLY) 1285 h-prefixreg 1286 f-nil 1287) 1288 1289;;;;;;;;;;;;;;;;;; -ifield 1290 1291; 15 0 1292; +-----------+-----+-----------+-----+-----------+ 1293; | Operand2 | Mode| Opcode | Size| Operand1 | 1294; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ 1295; 1296; Figure 5. General instruction format. 1297; 1298; Some deviations from this format exist, [see below]. 1299 1300; Field specifiers in CGEN specify the highest numbered bit followed by 1301; the number of bits. 1302 1303(dnf f-operand1 "Operand1" () 3 4) 1304(dnf f-size "Size" () 5 2) 1305(dnf f-opcode "Opcode" () 9 4) 1306(dnf f-mode "Mode" () 11 2) 1307(dnf f-operand2 "Operand2" () 15 4) 1308 1309; Subfields. FIXME: unfortunately there's some limitation in CGEN so we 1310; can't (as would be somewhat intuitive) make f-mode a multi-ifield 1311; consisting of these two, concatenated. 1312(dnf f-memmode "Indirect of autoincrement" () 10 1) 1313(dnf f-membit "Memory specifier" () 11 1) 1314 1315(dnf f-b5 "Bit 5 (zero for some quick operands)" () 5 1) 1316 1317; When the addressing mode is quick immediate, the low bits are 1318; part of the operand. 1319(dnf f-opcode-hi "Opcode field, high bits" () 9 2) 1320 1321; Common synonyms for those fields. 1322(define-pmacro f-source f-operand1) 1323(define-pmacro f-dest f-operand2) 1324 1325(dnmf 1326 f-dstsrc "Dest and source fields concatenated" () UINT 1327 (f-dest f-source) 1328 ; Insert-code. 1329 (sequence 1330 ((SI tmpval)) 1331 (set tmpval (ifield f-dstsrc)) 1332 (set (ifield f-dest) (and (srl tmpval 4) #xf)) 1333 (set (ifield f-source) (and tmpval #xf))) 1334 ; Extract-code. 1335 (set 1336 (ifield f-dstsrc) 1337 (and (or (ifield f-source) (sll (ifield f-dest) 4)) #xff)) 1338) 1339 1340;The 6-bit value may be sign or zero extended depending on the instruction. 1341; 1342; 15 0 1343; +-----------+-----+-----------+-----+-----------+ 1344; | Operand2 | Mode| Opcode | Immediate value | 1345; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ 1346; 1347; Figure 6. Quick immediate addressing mode instruction format. 1348 1349(dnf f-u6 "Quick immediate unsigned 6-bit" () 5 6) 1350(df f-s6 "Quick signed 6-bit" () 5 6 INT #f #f) 1351 1352; There's also a variant used with shift insns, with one bit larger opcode 1353; and one bit smaller immediate value, though it doesn't have a general 1354; graphic description. 1355(dnf f-u5 "Quick unsigned 5-bit" () 4 5) 1356 1357; Similarly, a four-bit immediate field. 1358(dnf f-u4 "Quick unsigned 4-bit" () 3 4) 1359 1360; An 8-bit signed value, which doesn't have a general graphic description. 1361(df f-s8 "Source signed byte" () 7 8 INT #f #f) 1362 1363; The 9-bit branch offset, with bit 0 in the field being bit 8 in the 1364; offset, and bit 0 in the offset always 0. 1365(df f-disp9-hi "PC-relative 9-bit offset, sign bit" () 0 1 INT #f #f) 1366(dnf f-disp9-lo "PC-relative 9-bit offset, low bits" () 7 7) 1367 1368; It would work to have this in two mach-specific variants, but 1369; considering that current-mach-is-v32 is a compile-time constant, we 1370; don't win any simulator performance. 1371(dnmf 1372 f-disp9 "PC-relative 9-bit offset" 1373 (PCREL-ADDR) 1374 INT 1375 (f-disp9-hi f-disp9-lo) 1376 ; Insert-code. 1377 (sequence 1378 ((SI absval)) 1379 (set absval (srl (sub (sub SI (ifield f-disp9) pc) 1380 (if SI current-mach-is-v32 0 2)) 1)) 1381 (set (ifield f-disp9-hi) (if (lt absval 0) 1 0)) 1382 (set (ifield f-disp9-lo) (and absval) #x7f)) 1383 ; Extract-code. 1384 (sequence 1385 ((SI abslo) (SI absval)) 1386 (set abslo (sll (ifield f-disp9-lo) 1)) 1387 (set absval 1388 (or (if SI (ne (ifield f-disp9-hi) 0) 1389 (inv SI #xff) 1390 0) 1391 abslo)) 1392 (set (ifield f-disp9) 1393 (add SI (add SI pc absval) (if SI current-mach-is-v32 0 2)))) 1394) 1395 1396; The operand of LAPCQ is PC-relative, similar to f-disp9 but unsigned, 1397; and only four bits. 1398(df 1399 f-qo 1400 "PC-relative 4-bit unsigned offset, counted from start of insn" 1401 (MACH-V32 PCREL-ADDR) 1402 3 4 1403 UINT 1404 ; Insert-code. 1405 ((value pc) (srl SI (sub SI value pc) 1)) 1406 ; Extract-code. 1407 ((value pc) (add SI pc (sll SI value 1))) 1408) 1409 1410; 8-bit, 16-bit and 32-bit immediates. The 8-bit values are constructed 1411; through encoding/decoding functions, since the PC increment is by a 1412; word. 1413(define-pmacro (dcrisf x-name x-comment x-attrs x-word-offset x-word-length 1414 x-start x-length x-mode x-encode x-decode) 1415 (define-ifield 1416 (name x-name) 1417 (comment x-comment) 1418 (.splice attrs (.unsplice x-attrs)) 1419 (word-offset x-word-offset) 1420 (word-length x-word-length) 1421 (start x-start) 1422 (length x-length) 1423 (mode x-mode) 1424 (.splice encode (.unsplice x-encode)) 1425 (.splice decode (.unsplice x-decode)) 1426 ) 1427) 1428 1429(dcrisf 1430 f-indir-pc+-byte "[PC+] 8-bit field" (SIGN-OPT) 1431 16 16 1432 15 16 ; CGEN-FIXME: Should be 7 8 1433 INT (#f) (#f) 1434) 1435 1436(dcrisf 1437 f-indir-pc+-word "[PC+] 16-bit field" (SIGN-OPT) 1438 16 16 15 16 INT (#f) (#f) 1439) 1440 1441; CGEN-FIXME: I shouldn't have to use trunc here, should I? 1442; Sign-extension should be implicit through use of SI (as opposed to USI) 1443; and additionally through SIGN-OPT. The ext isn't actually needed, but 1444; having it there rather than implicit makes more sense than to just have 1445; the trunc. 1446(dcrisf 1447 f-indir-pc+-word-pcrel "[PC+] PC-relative 16-bit field" 1448 (PCREL-ADDR SIGN-OPT) 1449 16 16 15 16 SI 1450 ((value pc) (sub SI value (add SI pc (if SI current-mach-is-v32 0 4)))) 1451 ((value pc) (add SI (ext SI (trunc HI value)) (add SI pc (if SI current-mach-is-v32 0 4)))) 1452) 1453 1454(dcrisf 1455 f-indir-pc+-dword "PC autoincrement - 32-bit field" (SIGN-OPT) 1456 16 32 31 32 INT (#f) (#f) 1457) 1458 1459(dcrisf 1460 f-indir-pc+-dword-pcrel 1461 "[PC+] PC-relative 32-bit field, counted from start of insn" 1462 (SIGN-OPT MACH-V32 PCREL-ADDR) 1463 16 32 31 32 INT 1464 ((value pc) (sub SI value pc)) 1465 ((value pc) (add SI pc value)) 1466) 1467 1468;;;;;;;;;;;;;;;;;; -insn-enum -normal-operand -normal-derived-operand 1469 1470;; How different fields are transformed into something we put in insns. 1471 1472; m := size modifier, byte (00), word (01) or dword (10) 1473; z := size modifier, byte (0) or word (1) 1474; (For the latter, the "higher" bit is always 0, mapping trivially on m.) 1475 1476(define-normal-insn-enum 1477 insn-size 1478 "Standard instruction operand size" 1479 () 1480 SIZE_ 1481 f-size 1482 ("BYTE" "WORD" "DWORD" "FIXED") 1483) 1484 1485; The mode field for insns with "s" operand (perhaps with a partial set of 1486; operand types). 1487(define-normal-insn-enum 1488 insn-mode 1489 "Standard instruction addressing modes" 1490 () 1491 MODE_ 1492 f-mode 1493 ("QUICK_IMMEDIATE" "REGISTER" "INDIRECT" "AUTOINCREMENT") 1494) 1495 1496(define-normal-insn-enum 1497 insn-memoryness-mode 1498 "Whether the operand is indirect" 1499 () 1500 MODEMEMP_ 1501 f-membit 1502 ("NO" "YES") 1503) 1504 1505; FIXME: Needed? 1506(define-normal-insn-enum 1507 insn-memincness-mode 1508 "Whether the indirect operand is autoincrement" 1509 () 1510 MODEINCP_ 1511 f-memmode 1512 ("NO" "YES") 1513) 1514 1515; Special semantics for multiply. 1516(define-pmacro MODE_MULU MODE_INDIRECT) 1517(define-pmacro MODE_MULS MODE_AUTOINCREMENT) 1518 1519(define-normal-insn-enum 1520 insn-signed-size 1521 "Signed instruction operand size" 1522 () 1523 SIGNED_ 1524 f-size 1525 ("UNDEF_SIZE_0" "UNDEF_SIZE_1" "BYTE" "WORD") 1526) 1527 1528(define-normal-insn-enum 1529 insn-unsigned-size 1530 "Unsigned instruction operand size" 1531 () 1532 UNSIGNED_ 1533 f-size 1534 ("BYTE" "WORD" "UNDEF_SIZE_2" "UNDEF_SIZE_3") 1535) 1536 1537; Rs := source operand, register addressing mode 1538(dnop Rs "Source general register" () h-gr f-source) 1539 1540; [Rs] := source operand, indirect addressing mode 1541; = MODE_INDIRECT Rs 1542 1543; [Rs+] := source operand, autoincrement addressing mode (see note!) 1544; = MODE_AUTOINCREMENT Rs 1545 1546; The union of [Rs] and [Rs(+)] 1547; = MODEMEMP_YES Rs 1548 1549; Whether an indirect operand is increment can be obtained as an operand by 1550; = inc 1551(dnop inc "Incrementness of indirect operand" () h-inc f-memmode) 1552 1553; or as an affirmative specifier 1554; = MODEINCP_YES 1555; (or MODEINCP_NO) 1556 1557; s := source operand, any of the modes Rs, [Rs] or [Rs+] 1558; No common operand; each are handled separately, using the above definitions. 1559 1560; Ps := source operand, special register 1561; It's in the field usually used for the destination. 1562(dnop Ps "Source special register" () h-sr f-dest) 1563 1564; Ss := source operand, support register 1565; It's in the field usually used for the destination. 1566(dnop Ss "Source support register" (MACH-V32) h-supr f-dest) 1567 1568; Sd := source operand, support register 1569(dnop Sd "Destination support register" (MACH-V32) h-supr f-dest) 1570 1571; i := 6-bit signed immediate operand 1572(dnop i "Quick signed 6-bit" () h-sint f-s6) 1573 1574; j := 6-bit unsigned immediate operand 1575(dnop j "Quick unsigned 6-bit" () h-uint f-u6) 1576 1577; c := 5-bit immediate shift value 1578(dnop c "Quick unsigned 5-bit" () h-uint f-u5) 1579 1580; qo := 4-bit unsigned immediate operand 1581(dnop qo "Quick unsigned 4-bit, PC-relative" (MACH-V32) h-addr f-qo) 1582 1583; Rd := destination operand, register addressing mode 1584(dnop Rd "Destination general register" () h-gr f-dest) 1585(define-pmacro Rd-sfield Rs) 1586(define-pmacro Rs-dfield Rd) 1587 1588; [Rd] := destination operand, indirect addressing mode 1589; = MODE_INDIRECT Rd 1590 1591; [Rd+] := destination operand, autoincrement addressing mode 1592; = MODE_AUTOINCREMENT Rd 1593 1594; [PC+] := destination operand PC, autoincrement addressing mode 1595; = MODE_AUTOINCREMENT (f-dest 15) X 1596; where X is one of sconst8, uconst8, sconst16, uconst16 or const32. 1597(dnop sconst8 "Signed byte [PC+]" () h-sint f-indir-pc+-byte) 1598(dnop uconst8 "Unsigned byte [PC+]" () h-uint f-indir-pc+-byte) 1599(dnop sconst16 "Signed word [PC+]" () h-sint f-indir-pc+-word) 1600(dnop uconst16 "Unsigned word [PC+]" () h-uint f-indir-pc+-word) 1601(dnop const32 "Dword [PC+]" () h-uint f-indir-pc+-dword) 1602(dnop const32-pcrel "Dword [PC+]" () h-addr f-indir-pc+-dword-pcrel) 1603 1604; d := destination operand, any of the modes Rd, [Rd] or [Rd+] 1605; No common operand; each are handled separately, using the above definitions. 1606 1607; Pd := destination operand, special register 1608(dnop Pd "Destination special register" () h-sr f-dest) 1609 1610; o := 8-bit immediate offset value 1611(dnop o "Signed 8-bit" () h-sint f-s8) 1612 1613; The division of operand semantics and insn fields in the CRIS 1614; instruction set reference doesn't permit a simple mapping to a 1615; simulator description, and the division of insn fields and 1616; semantics in CGEN is not between the define-normal-ifield 1617; vs. define-normal-operand. For example, the "o" operand is 1618; PC-relative for branch insns, as described by the CGEN f-disp9 1619; field. 1620; See comment at f-disp9; thankfully the mach 1621; attribute works here to have two different definitions by the 1622; same name. 1623(dnop o-pcrel "9-bit signed immediate PC-rel" 1624 () 1625 h-iaddr f-disp9) 1626 1627(dnop o-word-pcrel "16-bit signed immediate PC-rel" 1628 () 1629 h-iaddr f-indir-pc+-word-pcrel) 1630 1631; cc := condition code 1632(dnop cc "Condition codes" () h-ccode f-dest) 1633 1634; n := 4 bit breakpoint exception vector index 1635(dnop n "Quick unsigned 4-bit" () h-uint f-u4) 1636 1637; The "option" in the SWAP insn. 1638(dnop swapoption "Swap option" () h-swap f-dest) 1639 1640(dnop list-of-flags "Flag bits as operand" () h-flagbits f-dstsrc) 1641 1642; Enumerations for insn codes, for use in insn definitions 1643; instead of raw numbers. See it as operand definitions for the 1644; opcode field. 1645 1646(define-normal-insn-enum 1647 insn-qi-opc 1648 "Insns for MODE_QUICK_IMMEDIATE" 1649 () 1650 Q_ 1651 f-opcode 1652 ("BCC_0" "BCC_1" "BCC_2" "BCC_3" 1653 "BDAP_0" "BDAP_1" "BDAP_2" "BDAP_3" 1654 "ADDQ" "MOVEQ" "SUBQ" "CMPQ" 1655 "ANDQ" "ORQ" "ASHQ" "LSHQ") 1656) 1657 1658(define-normal-insn-enum 1659 insn-qihi-opc 1660 "Same as insn-qi-opc, though using only the high two bits of the opcode" 1661 () 1662 QHI_ 1663 f-opcode-hi 1664 ("BCC" "BDAP" "OTHER2" "OTHER3") 1665) 1666(define-pmacro QHI_ADDOQ QHI_BDAP) 1667 1668(define-normal-insn-enum 1669 insn-r-opc 1670 "Insns for MODE_REGISTER and either SIZE_BYTE, SIZE_WORD or SIZE_DWORD" 1671 () 1672 R_ 1673 f-opcode 1674 ("ADDX" "MOVX" "SUBX" "LSL" 1675 "ADDI" "BIAP" "NEG" "BOUND" 1676 "ADD" "MOVE" "SUB" "CMP" 1677 "AND" "OR" "ASR" "LSR") 1678) 1679(define-pmacro R_ADDI_ACR R_BIAP) 1680 1681(define-normal-insn-enum 1682 insn-rfix-opc 1683 "Insns for MODE_REGISTER and SIZE_FIXED" 1684 () 1685 RFIX_ 1686 f-opcode 1687 ("ADDX" "MOVX" "SUBX" "BTST" 1688 "SCC" "ADDC" "SETF" "CLEARF" 1689 "MOVE_R_S" "MOVE_S_R" "ABS" "DSTEP" 1690 "LZ" "SWAP" "XOR" "MSTEP") 1691) 1692(define-pmacro RFIX_MCP RFIX_MSTEP) 1693 1694(define-normal-insn-enum 1695 insn-indir-opc 1696 "Insns for (MODE_INDIRECT or MODE_AUTOINCREMENT) and either SIZE_BYTE, SIZE_WORD or SIZE_DWORD" 1697 () 1698 INDIR_ 1699 f-opcode 1700 ("ADDX" "MOVX" "SUBX" "CMPX" 1701 "MUL" "BDAP_M" "ADDC" "BOUND" 1702 "ADD" "MOVE_M_R" "SUB" "CMP" 1703 "AND" "OR" "TEST" "MOVE_R_M") 1704) 1705(define-pmacro INDIR_ADDO INDIR_BDAP_M) 1706 1707(define-normal-insn-enum 1708 insn-infix-opc 1709 "Insns for (MODE_INDIRECT or MODE_AUTOINCREMENT) and SIZE_FIXED" 1710 () 1711 INFIX_ 1712 f-opcode 1713 ("ADDX" "MOVX" "SUBX" "CMPX" 1714 "JUMP_M" "DIP" "JUMP_R" "BCC_M" 1715 "MOVE_M_S" "MOVE_S_M" "BMOD" "BSTORE" 1716 "RBF" "SBFS" "MOVEM_M_R" "MOVEM_R_M") 1717) 1718 1719(define-pmacro INFIX_MOVE_SS INFIX_SBFS) 1720(define-pmacro INFIX_LAPC INFIX_DIP) 1721(define-pmacro INFIX_RFE INFIX_JUMP_M) 1722(define-pmacro INFIX_RFN INFIX_JUMP_M) 1723(define-pmacro INFIX_HALT INFIX_JUMP_M) 1724(define-pmacro INFIX_SFE INFIX_JUMP_M) 1725(define-pmacro INFIX_RFG INFIX_JUMP_M) 1726(define-pmacro INFIX_JAS_R INFIX_JUMP_R) 1727(define-pmacro INFIX_JAS_M INFIX_JUMP_R) 1728(define-pmacro INFIX_JASC INFIX_RBF) 1729(define-pmacro INFIX_JUMP_P INFIX_BCC_M) 1730(define-pmacro INFIX_BAS INFIX_BMOD) 1731(define-pmacro INFIX_BASC INFIX_BSTORE) 1732(define-pmacro INFIX_BREAK INFIX_JUMP_M) 1733(define-pmacro INFIX_FIDXI INFIX_JUMP_M) 1734(define-pmacro INFIX_FIDXD INFIX_BAS) 1735(define-pmacro INFIX_FTAGI INFIX_JUMP_M) 1736(define-pmacro INFIX_FTAGD INFIX_BAS) 1737 1738; Classes of insns: 1739; Move-to-register, move-to-memory, move-to/from-other-register, 1740; logical, arithmetic, branch. 1741; Classes of operands: 1742; quick, register, memory-indirect, memory-postinc. 1743 1744 1745;;;;;;;;;;;;;;;;;; -normal-insn 1746 1747(define-pmacro (dni-bwd-attr name comment attr syntax fmt fsem timing) 1748 (begin 1749 (dni (.sym name .b) (.str "byte " comment) attr (.str name ".b " syntax) 1750 (.splice (.unsplice fmt) SIZE_BYTE) 1751 (fsem QI) 1752 timing) 1753 (dni (.sym name .w) (.str "word " comment) attr (.str name ".w " syntax) 1754 (.splice (.unsplice fmt) SIZE_WORD) 1755 (fsem HI) 1756 timing) 1757 (dni (.sym name .d) (.str "dword " comment) attr (.str name ".d " syntax) 1758 (.splice (.unsplice fmt) SIZE_DWORD) 1759 (fsem SI) 1760 timing)) 1761) 1762 1763(define-pmacro (dni-cdt-attr name comment attr syntax fmt semantics) 1764 "dni without specifying timing" 1765 (dni name comment attr syntax fmt semantics (cris-timing)) 1766) 1767 1768(define-pmacro (dni-cdt-bwd-attr name comment attr syntax fmt fsem) 1769 (begin 1770 (dni-cdt-attr (.sym name .b-r) (.str "byte " comment) attr (.str name ".b " syntax) 1771 (.splice (.unsplice fmt) SIZE_BYTE) 1772 (fsem QI)) 1773 (dni-cdt-attr (.sym name .w-r) (.str "word " comment) attr (.str name ".w " syntax) 1774 (.splice (.unsplice fmt) SIZE_WORD) 1775 (fsem HI)) 1776 (dni-cdt-attr (.sym name .d-r) (.str "dword " comment) attr (.str name ".d " syntax) 1777 (.splice (.unsplice fmt) SIZE_DWORD) 1778 (fsem SI))) 1779) 1780 1781; Some convenience macros based on the above ones. 1782(define-pmacro (dni-cdt-bwd name comment syntax fmt fsem) 1783 (dni-cdt-bwd-attr name comment () syntax fmt fsem) 1784) 1785 1786(define-pmacro (dni-bwd name comment syntax fmt fsem timing) 1787 (dni-bwd-attr comment () syntax fmt fsem timing) 1788) 1789 1790(define-pmacro-map 1791 (((dni-cdt name comment syntax fmt semantics) 1792 (dni-cdt-attr name comment () syntax fmt semantics)) 1793 ((dni-c-QI-attr name comment attr syntax fmt fsem) 1794 (dni name comment attr syntax fmt fsem (cris-timing-const-QI))) 1795 ((dni-c-HI-attr name comment attr syntax fmt fsem) 1796 (dni name comment attr syntax fmt fsem (cris-timing-const-HI))) 1797 ((dni-c-SI-attr name comment attr syntax fmt fsem) 1798 (dni name comment attr syntax fmt fsem (cris-timing-const-SI)))) 1799) 1800 1801(define-pmacro-map 1802 (((dni-c-QI name comment syntax fmt fsem) 1803 (dni-c-QI-attr name comment () syntax fmt fsem)) 1804 ((dni-c-HI name comment syntax fmt fsem) 1805 (dni-c-HI-attr name comment () syntax fmt fsem)) 1806 ((dni-c-SI name comment syntax fmt fsem) 1807 (dni-c-SI-attr name comment () syntax fmt fsem))) 1808) 1809 1810; These flags are both cleared by all insns except prefixes (before 1811; CRISv32) and "setf x", so we put them in a handy macro. 1812(define-pmacro 1813 (reset-x-p) 1814 (sequence 1815 () 1816 (set xbit 0) 1817 (set prefix-set 0)) 1818) 1819 1820; NOP | 0 0 0 0| 0 1| 0 1 0 0| 0 0| 1 1 1 1| 1821; (For V32, "SETF" (no flags) is used.) 1822(dni-cdt-attr 1823 nop "nop" (MACH-PC) "nop" 1824 (+ (f-operand2 0) R_ADDI MODE_REGISTER SIZE_BYTE (f-operand1 15)) 1825 (reset-x-p) 1826) 1827 1828; Pre- and v32+ variants MOVE insns set flags differently. These two 1829; macros for flag settings are meant to be used in all MOVE insns. 1830(define-pmacro (setf-moveq value) 1831 (sequence 1832 () 1833 (set-quiet nbit-move (lt SI value 0)) 1834 (set-quiet zbit-move (andif BI (eq SI value 0) (if BI xbit zbit 1))) 1835 (set-quiet cbit-move 0) 1836 (set-quiet vbit-move 0) 1837 (reset-x-p)) 1838) 1839 1840(define-pmacro (setf-move size value) 1841 (sequence 1842 () 1843 (set nbit (lt size value 0)) 1844 (set zbit (andif BI (eq size value 0) (if BI xbit zbit 1))) 1845 (set-quiet cbit-move 0) 1846 (set-quiet vbit-move 0) 1847 (reset-x-p)) 1848) 1849; The CGEN binop-with-bit operations are not documented well enough that I 1850; trust their semantics to remain stable. Better define local ones: the 1851; semantics become explicit. 1852(define-pmacro-map 1853 (((add-overflow size R D S carry) 1854 (orif BI (andif BI (andif BI (lt size S 0) (lt size D 0)) (ge size R 0)) 1855 (andif BI (andif BI (ge size S 0) (ge size D 0)) (lt size R 0)))) 1856 ((add-carry size R D S carry) 1857 (orif BI (andif BI (lt size S 0) (lt size D 0)) 1858 (orif BI (andif BI (lt size D 0) (ge size R 0)) 1859 (andif BI (lt size S 0) (ge size R 0))))) 1860 ((sub-overflow size R D S carry) 1861 (orif BI (andif BI (andif BI (ge size S 0) (lt size D 0)) (ge size R 0)) 1862 (andif BI (andif BI (lt size S 0) (ge size D 0)) (lt size R 0)))) 1863 ((sub-carry size R D S carry) 1864 (orif BI (andif BI (lt size S 0) (ge size D 0)) 1865 (orif BI (andif BI (ge size D 0) (lt size R 0)) 1866 (andif BI (lt size S 0) (lt size R 0))))) 1867 ; Only valid for size := DI 1868 ((mulu-overflow size R D S carry) 1869 (ne DI R (zext DI (trunc SI R)))) 1870 ((mulu-carry size R D S carry) 1871 (andif current-mach-is-v32 carry)) 1872 ((muls-overflow size R D S carry) 1873 (ne DI R (ext DI (trunc SI R)))) 1874 ((muls-carry size R D S carry) 1875 (andif current-mach-is-v32 carry))) 1876) 1877 1878(define-pmacro (setf-arit2 size op source1 source2 result carryin carryout) 1879 "Set no-prefix, x=0, carryout, v, z and n according to operation OP in size SIZE" 1880 (sequence 1881 () 1882 (set carryout ((.sym op -carry) size result source1 source2 carryin)) 1883 (set nbit (lt size result 0)) 1884 (set zbit (andif BI (eq size result 0) (orif BI zbit (not BI xbit)))) 1885 (set vbit ((.sym op -overflow) size result source1 source2 carryin)) 1886 (reset-x-p)) 1887) 1888(define-pmacro (setf-arit size op source1 source2 result carry) 1889 "Set no-prefix, x=0, c, v, z and n according to operation OP in size SIZE" 1890 (setf-arit2 size op source1 source2 result carry cbit) 1891) 1892 1893; Let's have convienence macros for arithmetic, including evaluation of the 1894; operation, destination modification, flag setting and carry propagation. 1895(define-pmacro 1896 (cris-arit6-int arit size fdest fdest_op srcop1 srcop2 carryout carryin) 1897 "Core for performing some three-operand arithmetic with carry as parameter" 1898 (sequence 1899 ((size tmpopd) (size tmpops) (BI carry) (size newval)) 1900 (set tmpops srcop2) 1901 (set tmpopd srcop1) 1902 (set carry carryin) 1903 (set newval ((.sym arit c) tmpopd tmpops (if BI (eq xbit 0) 0 carry))) 1904 (fdest size fdest_op newval) 1905 (setf-arit2 size arit tmpopd tmpops newval carry carryout)) 1906) 1907 1908(define-pmacro 1909 (cris-arit5-int arit size destregno srcop1 srcop2 carryout carryin) 1910 "As cris-arit6-int, but to set a part of a general register" 1911 (cris-arit6-int 1912 arit 1913 size 1914 (.pmacro (sz regno val) (set-subreg-gr sz regno val)) 1915 destregno 1916 srcop1 1917 srcop2 1918 carryout 1919 carryin) 1920) 1921 1922(define-pmacro (cris-arit5 arit size destreg srcop1 srcop2 carryout carryin) 1923 "As cris-arit5-int, but takes a register as parameter, not register number" 1924 (cris-arit5-int arit size (regno destreg) srcop1 srcop2 carryout carryin) 1925) 1926(define-pmacro (cris-arit3-int arit size destregno srcop1 srcop2) 1927 "As cris-arit5-int, but with carry-in same as carry-out" 1928 (cris-arit5-int arit size destregno srcop1 srcop2 cbit cbit) 1929) 1930(define-pmacro (cris-arit3 arit size destreg srcop1 srcop2) 1931 "As cris-arit3-int, but takes a register as parameter, not register number" 1932 (cris-arit3-int arit size (regno destreg) srcop1 srcop2) 1933) 1934(define-pmacro (cris-arit arit size destreg srcop) 1935 "As cris-arit3, but with destination same as srcop1" 1936 (cris-arit3 arit size destreg destreg srcop) 1937) 1938(define-pmacro (cris-arit-3op arit size destsrcop2 srcop1 dest-3op) 1939 "Similar to cris-arit3-int, but for prefixed operand only" 1940 (cris-arit3-int arit size 1941 (if SI (andif prefix-set (not inc)) 1942 (regno dest-3op) 1943 (regno destsrcop2)) 1944 destsrcop2 srcop1) 1945) 1946 1947; Convenience macros to select a part of a value and its complement, for 1948; the <op>.b, <op>.w and <op>.d operations. 1949(define-pmacro (QI-part val) (and SI val #xff)) 1950(define-pmacro (non-QI-part val) (and SI val #xffffff00)) 1951(define-pmacro (HI-part val) (and SI val #xffff)) 1952(define-pmacro (non-HI-part val) (and SI val #xffff0000)) 1953(define-pmacro (SI-part val) val) 1954(define-pmacro (non-SI-part val) 0) 1955(define-pmacro 1956 (set-subreg-gr-bw BWD gregno newval) 1957 "Set a byte or word part or full dword of a general register" 1958 (sequence 1959 ((SI oldregval)) 1960 (set oldregval (reg h-raw-gr gregno)) 1961 (set (reg h-gr gregno) 1962 (or SI ((.sym BWD -part) newval) ((.sym non- BWD -part) oldregval)))) 1963) 1964(define-pmacro (set-subreg-gr BWD gregno newval) 1965 ((.sym set-subreg-gr- BWD) BWD gregno newval) 1966) 1967(define-pmacro (set-subreg-gr-SI SI gregno newval) 1968 (set (reg h-gr gregno) newval) 1969) 1970(define-pmacro set-subreg-gr-HI set-subreg-gr-bw) 1971(define-pmacro set-subreg-gr-QI set-subreg-gr-bw) 1972 1973; MOVE.m Rs,Rd [ Rd | 011001mm | Rs ] 1974(dni-cdt-bwd 1975 move "move.m r,R" 1976 "move.m ${Rs},${Rd}" 1977 (+ Rd MODE_REGISTER R_MOVE Rs) 1978 (.pmacro 1979 (BWD) 1980 (sequence 1981 ((BWD newval)) 1982 (set newval Rs) 1983 (set-subreg-gr BWD (regno Rd) newval) 1984 (setf-move BWD newval))) 1985) 1986 1987; MOVE.D PC,Rd [ Rd | 01100110 | 1111 ] 1988; This insn is used in PIC code to find out the code address. It's an 1989; exception to the (guarded) non-implementation of PC operands in this 1990; file. 1991(dni-cdt-attr 1992 movepcr "move.d PC,R" 1993 (MACH-PC UNCOND-CTI) 1994 "move.d PC,${Rd}" 1995 (+ Rd MODE_REGISTER R_MOVE SIZE_DWORD (f-source 15)) 1996 (sequence 1997 ((SI pcval)) 1998 (set pcval (add SI pc 2)) 1999 (set Rd pcval) 2000 (setf-move SI pcval)) 2001) 2002 2003; MOVEQ i,Rd [ Rd | 001001 | i ] 2004(dni-cdt 2005 moveq "moveq" 2006 "moveq $i,$Rd" 2007 (+ Rd MODE_QUICK_IMMEDIATE Q_MOVEQ i) 2008 (sequence 2009 ((SI newval)) 2010 (set newval i) 2011 (set Rd newval) 2012 (setf-moveq newval)) 2013) 2014 2015(define-pmacro (dni-cdt-sbw name comment syntax fmt fsem) 2016 "Insn generator for insns with signed <op>.b and <op>.w variants" 2017 (begin 2018 (dni-cdt 2019 (.sym name .b-r) (.str "byte " comment) (.str name ".b " syntax) 2020 (.splice (.unsplice fmt) SIGNED_BYTE) 2021 (fsem QI)) 2022 (dni-cdt 2023 (.sym name .w-r) (.str "word " comment) (.str name ".w " syntax) 2024 (.splice (.unsplice fmt) SIGNED_WORD) 2025 (fsem HI))) 2026) 2027 2028; MOVS.z Rs,Rd [ Rd | 0100011z | Rs ] 2029(dni-cdt-sbw 2030 movs "movs.m r,R" 2031 "movs.m ${Rs},${Rd}" 2032 (+ Rd MODE_REGISTER R_MOVX Rs) 2033 (.pmacro 2034 (BW) 2035 (sequence 2036 ((BW newval)) 2037 (set newval Rs) 2038 (set Rd (ext SI newval)) 2039 (setf-move SI newval))) 2040) 2041 2042(define-pmacro (dni-cdt-ubw name comment syntax fmt fsem) 2043 "Similar to dni-cdt-sbw but for unsigned operations" 2044 (begin 2045 (dni-cdt 2046 (.sym name .b-r) (.str "byte " comment) (.str name ".b " syntax) 2047 (.splice (.unsplice fmt) UNSIGNED_BYTE) 2048 (fsem QI)) 2049 (dni-cdt 2050 (.sym name .w-r) (.str "word " comment) (.str name ".w " syntax) 2051 (.splice (.unsplice fmt) UNSIGNED_WORD) 2052 (fsem HI))) 2053) 2054 2055; MOVU.z Rs,Rd [ Rd | 0100010z | Rs ] 2056(dni-cdt-ubw 2057 movu "movu.m r,R" 2058 "movu.m ${Rs},${Rd}" 2059 (+ Rd MODE_REGISTER R_MOVX Rs) 2060 (.pmacro 2061 (BW) 2062 (sequence 2063 ((BW newval)) 2064 (set newval Rs) 2065 (set Rd (zext SI newval)) 2066 (setf-move SI newval))) 2067) 2068 2069; (MOVE.m [PC+],Rd [ Rd | 111001mm | 1111 ]) 2070; For the moment, it doesn't seem worthwhile to make a dni-c-bwd macro; 2071; too many places to parametrize. 2072(dni-c-QI 2073 movecbr "move.b [PC+],R" 2074 "move.b ${sconst8},${Rd}" 2075 (+ Rd MODE_AUTOINCREMENT INDIR_MOVE_M_R SIZE_BYTE (f-source 15) sconst8) 2076 (sequence 2077 ((QI newval)) 2078 (set newval sconst8) 2079 (set-subreg-gr QI (regno Rd) newval) 2080 (setf-move QI newval)) 2081) 2082 2083(dni-c-HI 2084 movecwr "move.w [PC+],R" 2085 "move.w ${sconst16},${Rd}" 2086 (+ Rd MODE_AUTOINCREMENT INDIR_MOVE_M_R SIZE_WORD (f-source 15) sconst16) 2087 (sequence 2088 ((HI newval)) 2089 (set newval sconst16) 2090 (set-subreg-gr HI (regno Rd) newval) 2091 (setf-move HI newval)) 2092) 2093 2094(dni-c-SI 2095 movecdr "move.d [PC+],R" 2096 "move.d ${const32},${Rd}" 2097 (+ Rd MODE_AUTOINCREMENT INDIR_MOVE_M_R SIZE_DWORD (f-source 15) const32) 2098 (sequence 2099 ((SI newval)) 2100 (set newval const32) 2101 (set Rd newval) 2102 (setf-move SI newval)) 2103) 2104 2105; (MOVS.z [PC+],Rd [ Rd | 1100011z | 1111 ]) 2106; Similarly, no likely net improvement for a dni-c-bw. 2107(dni-c-QI 2108 movscbr "movs.b [PC+],R" 2109 "movs.b ${sconst8},${Rd}" 2110 (+ Rd MODE_AUTOINCREMENT INDIR_MOVX SIGNED_BYTE (f-source 15) sconst8) 2111 (sequence 2112 ((SI newval)) 2113 ; FIXME: Make trunc unnecessary. 2114 (set newval (ext SI (trunc QI sconst8))) 2115 (set Rd newval) 2116 (setf-move SI newval)) 2117) 2118 2119(dni-c-HI 2120 movscwr "movs.w [PC+],R" 2121 "movs.w ${sconst16},${Rd}" 2122 (+ Rd MODE_AUTOINCREMENT INDIR_MOVX SIGNED_WORD (f-source 15) sconst16) 2123 (sequence 2124 ((SI newval)) 2125 ; FIXME: Make trunc unnecessary. 2126 (set newval (ext SI (trunc HI sconst16))) 2127 (set Rd newval) 2128 (setf-move SI newval)) 2129) 2130 2131; (MOVU.z [PC+],Rd [ Rd | 1100010z | 1111 ]) 2132(dni-c-QI 2133 movucbr "movu.b [PC+],R" 2134 "movu.b ${uconst8},${Rd}" 2135 (+ Rd MODE_AUTOINCREMENT INDIR_MOVX UNSIGNED_BYTE (f-source 15) uconst8) 2136 (sequence 2137 ((SI newval)) 2138 ; FIXME: Make trunc unnecessary. 2139 (set newval (zext SI (trunc QI uconst8))) 2140 (set Rd newval) 2141 (setf-move SI newval)) 2142) 2143 2144(dni-c-HI 2145 movucwr "movu.w [PC+],R" 2146 "movu.w ${uconst16},${Rd}" 2147 (+ Rd MODE_AUTOINCREMENT INDIR_MOVX UNSIGNED_WORD (f-source 15) uconst16) 2148 (sequence 2149 ((SI newval)) 2150 ; FIXME: Make trunc unnecessary. 2151 (set newval (zext SI (trunc HI uconst16))) 2152 (set Rd newval) 2153 (setf-move SI newval)) 2154) 2155 2156; ADDQ j,Rd [ Rd | 001000 | j ] 2157(dni-cdt 2158 addq "addq j,Rd" 2159 "addq $j,$Rd" 2160 (+ Rd MODE_QUICK_IMMEDIATE Q_ADDQ j) 2161 (cris-arit add SI Rd j) 2162) 2163 2164; SUBQ j,Rd [ Rd | 001010| j ] 2165(dni-cdt 2166 subq "subq j,Rd" 2167 "subq $j,$Rd" 2168 (+ Rd MODE_QUICK_IMMEDIATE Q_SUBQ j) 2169 (cris-arit sub SI Rd j) 2170) 2171 2172; Convenience macros for insns with a memory operand. 2173(define-pmacro 2174 (dni-cmt-attr-tim name comment attr syntax fmt semantics timing) 2175 "dni with memory-access" 2176 (dni name comment attr syntax 2177 ; Specifying MODE_INDIRECT and MODE_AUTOINCREMENT in this 2178 ; manner makes the autoincrementness handily available. 2179 ; It also effectively excludes non-memory use of dni-cmt. 2180 (.splice (.unsplice fmt) MODEMEMP_YES inc) 2181 semantics 2182 timing) 2183) 2184 2185(define-pmacro (dni-cmt-attr name comment attr syntax fmt semantics) 2186 "dni with read memory-access timing" 2187 (dni-cmt-attr-tim name comment attr syntax fmt semantics 2188 (cris-mem-timing)) 2189) 2190 2191(define-pmacro (dni-cmwt-attr name comment attr syntax fmt semantics) 2192 "dni with write memory-access timing" 2193 (dni-cmt-attr-tim name comment attr syntax fmt semantics 2194 (cris-mem-write-timing)) 2195) 2196 2197(define-pmacro QI-size 1) 2198(define-pmacro HI-size 2) 2199(define-pmacro SI-size 4) 2200 2201(define-pmacro (cris-get-mem size regop) 2202 "Handle reading memory in <size>, with source address register\ 2203 (read once, maybe set once) in <regop> or prefixed" 2204 (sequence 2205 size 2206 ((SI addr) (size tmp-mem) (BI postinc)) 2207 2208 ; Cache the incrementness of the operand. 2209 (set postinc inc) 2210 2211 ; Get the address from somewhere. 2212 (set addr 2213 (if SI (eq prefix-set 0) 2214 ; If the insn was prefixed, it's in the prefix-register. 2215 regop 2216 prefixreg)) 2217 2218 ; Get the memory contents. 2219 (set tmp-mem (mem size addr)) 2220 2221 ; For non-prefixed post-increment, we increment the address by the 2222 ; size of the memory access. 2223 (if (ne postinc 0) 2224 (sequence 2225 () 2226 (if (eq prefix-set 0) 2227 (set addr (add addr (.sym size -size)))) 2228 ; Update the source-register for post-increments. 2229 (set regop addr))) 2230 2231 ; Don't forget the return-value. 2232 tmp-mem) 2233) 2234 2235(define-pmacro (cris-set-mem size regop value) 2236 "Handle writing <value> of <size> to memory, with memory address register\ 2237 (read once, maybe set once) in <regop> or prefixed." 2238 (sequence 2239 ((SI addr) (BI postinc)) 2240 2241 ; Cache the incrementness of the operand. 2242 (set postinc inc) 2243 2244 ; Get the address from somewhere. 2245 (set addr 2246 (if SI (eq prefix-set 0) 2247 ; If the insn was prefixed, it's in the prefix-register. 2248 regop 2249 prefixreg)) 2250 2251 ; Set the memory contents. Integral-write semantics apply. 2252 ; FIXME: currently v32 only; when proper semantics needed, fix v10. 2253 (if (andif current-mach-is-v32 (ne xbit 0)) 2254 (if (eq pbit 0) 2255 (sequence 2256 () 2257 (set (mem size addr) value) 2258 ; Write failures are signalled (by whatever entity "sends 2259 ; the signal") by setting P at time of the write above, if X 2260 ; is set. Here, we just need to copy P into C. 2261 (set cbit pbit)) 2262 (set cbit 1)) 2263 (set (mem size addr) value)) 2264 2265 ; For non-prefixed post-increment, we increment the address by the 2266 ; size of the memory access. As for the integral-write, this needs to 2267 ; be tweaked for pre-v32: increment should have been performed if 2268 ; there's a fault at the memory access above. 2269 (if (ne postinc 0) 2270 (sequence 2271 () 2272 (if (eq prefix-set 0) 2273 (set addr (add addr (.sym size -size)))) 2274 ; Update the source-register for post-increments. 2275 (set regop addr)))) 2276) 2277 2278(define-pmacro 2279 (dni-cmt-bwd-attr-tim name comment attr syntax fmt fsem timing) 2280 "Core generator macro for insns with <op>.b, <op>.w and <op>.d variants\ 2281 and a memory operand." 2282 (begin 2283 (dni-cmt-attr-tim 2284 (.sym name .b-m) 2285 (.str "byte mem " comment) 2286 attr 2287 (.str name ".b " syntax) 2288 (.splice (.unsplice fmt) SIZE_BYTE) 2289 (fsem QI) 2290 timing) 2291 (dni-cmt-attr-tim 2292 (.sym name .w-m) 2293 (.str "word mem " comment) 2294 attr 2295 (.str name ".w " syntax) 2296 (.splice (.unsplice fmt) SIZE_WORD) 2297 (fsem HI) 2298 timing) 2299 (dni-cmt-attr-tim 2300 (.sym name .d-m) 2301 (.str "dword mem " comment) 2302 attr 2303 (.str name ".d " syntax) 2304 (.splice (.unsplice fmt) SIZE_DWORD) 2305 (fsem SI) 2306 timing)) 2307) 2308 2309; Further refinement macros. 2310(define-pmacro (dni-cmt-bwd-attr name comment attr syntax fmt fsem) 2311 (dni-cmt-bwd-attr-tim name comment attr syntax fmt fsem 2312 (cris-mem-timing)) 2313) 2314 2315(define-pmacro (dni-cmwt-bwd name comment syntax fmt fsem) 2316 (dni-cmt-bwd-attr-tim name comment () syntax fmt fsem 2317 (cris-mem-write-timing)) 2318) 2319 2320(define-pmacro (dni-cmt-bwd name comment syntax fmt fsem) 2321 (dni-cmt-bwd-attr name comment () syntax fmt fsem) 2322) 2323 2324(define-pmacro (dni-cmt-sbw name comment syntax fmt fsem) 2325 "Core generator macro for insns with <op>.b and <op>.w variants\ 2326 and a signed memory operand." 2327 (begin 2328 (dni-cmt-attr 2329 (.sym name .b-m) (.str "byte mem " comment) 2330 () 2331 (.str name ".b " syntax) 2332 (.splice (.unsplice fmt) SIGNED_BYTE) 2333 (fsem QI)) 2334 (dni-cmt-attr 2335 (.sym name .w-m) (.str "word mem " comment) 2336 () 2337 (.str name ".w " syntax) 2338 (.splice (.unsplice fmt) SIGNED_WORD) 2339 (fsem HI))) 2340) 2341 2342(define-pmacro (dni-cmt-ubw name comment syntax fmt fsem) 2343 "Core generator macro for insns with <op>.b and <op>.w variants\ 2344 and an unsigned memory operand." 2345 (begin 2346 (dni-cmt-attr 2347 (.sym name .b-m) (.str "byte mem " comment) 2348 () 2349 (.str name ".b " syntax) 2350 (.splice (.unsplice fmt) UNSIGNED_BYTE) 2351 (fsem QI)) 2352 (dni-cmt-attr 2353 (.sym name .w-m) (.str "word mem " comment) 2354 () 2355 (.str name ".w " syntax) 2356 (.splice (.unsplice fmt) UNSIGNED_WORD) 2357 (fsem HI))) 2358) 2359 2360; CMP.m Rs,Rd [ Rd | 011011mm | Rs ] 2361(dni-cdt-bwd 2362 cmp-r "compare register to register" 2363 "$Rs,$Rd" 2364 (+ Rd MODE_REGISTER R_CMP Rs) 2365 (.pmacro 2366 (BWD) 2367 (cris-arit6-int 2368 sub BWD (.pmacro (sz regno val) (nop)) 0 2369 Rd Rs cbit cbit)) 2370) 2371 2372; CMP.m [Rs],Rd [ Rd | 101011mm | Rs ] 2373; CMP.m [Rs+],Rd [ Rd | 111011mm | Rs ] 2374(dni-cmt-bwd 2375 cmp-m "compare memory to register" 2376 "[${Rs}${inc}],${Rd}" 2377 (+ INDIR_CMP Rs Rd) 2378 (.pmacro 2379 (BWD) 2380 (cris-arit6-int 2381 sub BWD (.pmacro (sz regno val) (nop)) 0 2382 Rd (cris-get-mem BWD Rs) cbit cbit)) 2383) 2384 2385; (CMP.m [PC+],Rd [ Rd | 111011mm | 1111 ]) 2386(dni-c-QI 2387 cmpcbr "cmp constant byte to register" 2388 "cmp.b $sconst8,$Rd" 2389 (+ Rd MODE_AUTOINCREMENT INDIR_CMP SIZE_BYTE (f-source 15) sconst8) 2390 (cris-arit6-int 2391 sub QI (.pmacro (sz regno val) (nop)) 0 2392 Rd (trunc QI sconst8) cbit cbit) 2393) 2394 2395(dni-c-HI 2396 cmpcwr "cmp constant word to register" 2397 "cmp.w $sconst16,$Rd" 2398 (+ Rd MODE_AUTOINCREMENT INDIR_CMP SIZE_WORD (f-source 15) sconst16) 2399 (cris-arit6-int 2400 sub HI (.pmacro (sz regno val) (nop)) 0 2401 Rd (trunc HI sconst16) cbit cbit) 2402) 2403 2404(dni-c-SI 2405 cmpcdr "cmp constant dword to register" 2406 "cmp.d $const32,$Rd" 2407 (+ Rd MODE_AUTOINCREMENT INDIR_CMP SIZE_DWORD (f-source 15) const32) 2408 (cris-arit6-int 2409 sub SI (.pmacro (sz regno val) (nop)) 0 2410 Rd const32 cbit cbit) 2411) 2412 2413; CMPQ i,Rd [ Rd | 001011 | i ] 2414(dni-cdt 2415 cmpq "cmpq i,Rd" 2416 "cmpq $i,$Rd" 2417 (+ Rd MODE_QUICK_IMMEDIATE Q_CMPQ i) 2418 (cris-arit6-int 2419 sub SI (.pmacro (sz regno val) (nop)) 0 2420 Rd i cbit cbit) 2421) 2422 2423; CMPS.z [Rs],Rd [ Rd | 1000111z | Rs ] 2424; CMPS.z [Rs+],Rd [ Rd | 1100111z | Rs ] 2425(dni-cmt-sbw 2426 cmps-m "cmp sign-extended from memory to register" 2427 "[${Rs}${inc}],$Rd" 2428 (+ Rd INDIR_CMPX Rs) 2429 (.pmacro 2430 (BW) 2431 (cris-arit6-int 2432 sub SI (.pmacro (sz regno val) (nop)) 0 2433 Rd ((.sym BW -ext) (cris-get-mem BW Rs)) cbit cbit)) 2434) 2435 2436; (CMPS.z [PC+],Rd [ Rd | 1100111z | 1111 ]) 2437(dni-c-QI 2438 cmpscbr "cmp sign-extended constant byte to register" 2439 "[${Rs}${inc}],$Rd" 2440 (+ Rd MODE_AUTOINCREMENT INDIR_CMPX SIGNED_BYTE (f-source 15) sconst8) 2441 (cris-arit6-int 2442 sub SI (.pmacro (sz regno val) (nop)) 0 2443 Rd (ext SI (trunc QI sconst8)) cbit cbit) 2444) 2445(dni-c-HI 2446 cmpscwr "cmp sign-extended constant word to register" 2447 "[${Rs}${inc}],$Rd" 2448 (+ Rd MODE_AUTOINCREMENT INDIR_CMPX SIGNED_WORD (f-source 15) sconst16) 2449 (cris-arit6-int 2450 sub SI (.pmacro (sz regno val) (nop)) 0 2451 Rd (ext SI (trunc HI sconst16)) cbit cbit) 2452) 2453 2454; CMPU.z [Rs],Rd [ Rd | 1000110z | Rs ] 2455; CMPU.z [Rs+],Rd [ Rd | 1100110z | Rs ] 2456(dni-cmt-ubw 2457 cmpu-m "cmp zero-extended from memory to register" 2458 "[${Rs}${inc}],$Rd" 2459 (+ Rd INDIR_CMPX Rs) 2460 (.pmacro 2461 (BW) 2462 (cris-arit6-int 2463 sub SI (.pmacro (sz regno val) (nop)) 0 2464 Rd ((.sym BW -zext) (cris-get-mem BW Rs)) cbit cbit)) 2465) 2466 2467; (CMPU.z [PC+],Rd [ Rd | 1100110z | 1111 ]) 2468(dni-c-QI 2469 cmpucbr "cmp zero-extended constant byte to register" 2470 "[${Rs}${inc}],$Rd" 2471 (+ Rd MODE_AUTOINCREMENT INDIR_CMPX UNSIGNED_BYTE (f-source 15) uconst8) 2472 (cris-arit6-int 2473 sub SI (.pmacro (sz regno val) (nop)) 0 2474 Rd (zext SI (trunc QI uconst8)) cbit cbit) 2475) 2476(dni-c-HI 2477 cmpucwr "cmp zero-extended constant word to register" 2478 "[${Rs}${inc}],$Rd" 2479 (+ Rd MODE_AUTOINCREMENT INDIR_CMPX UNSIGNED_WORD (f-source 15) uconst16) 2480 (cris-arit6-int 2481 sub SI (.pmacro (sz regno val) (nop)) 0 2482 Rd (zext SI (trunc HI uconst16)) cbit cbit) 2483) 2484 2485; MOVE.m [Rs],Rd [ Rd | 101001mm | Rs ] 2486; MOVE.m [Rs+],Rd [ Rd | 111001mm | Rs ] 2487(dni-cmt-bwd 2488 move-m "move from memory to register" 2489 "[${Rs}${inc}],${Rd}" 2490 (+ INDIR_MOVE_M_R Rs Rd) 2491 (.pmacro 2492 (BWD) 2493 (sequence 2494 ((SI tmp)) 2495 (set tmp (cris-get-mem BWD Rs)) 2496 (set-subreg-gr 2497 BWD 2498 (if SI (andif prefix-set (not inc)) (regno Rs) (regno Rd)) 2499 tmp) 2500 (setf-move BWD tmp))) 2501) 2502 2503; MOVS.z [Rs],Rd [ Rd | 1000011z | Rs ] 2504; MOVS.z [Rs+],Rd [ Rd | 1100011z | Rs ] 2505(dni-cmt-sbw 2506 movs-m "movs from memory to register" 2507 "[${Rs}${inc}],${Rd}" 2508 (+ INDIR_MOVX Rs Rd) 2509 (.pmacro 2510 (BW) 2511 (sequence 2512 ((SI tmp)) 2513 (set tmp (ext SI (cris-get-mem BW Rs))) 2514 (if (andif prefix-set (not inc)) 2515 (set Rs tmp) 2516 (set Rd tmp)) 2517 (setf-move SI tmp))) 2518) 2519 2520; MOVU.z [Rs],Rd [ Rd | 1000010z | Rs ] 2521; MOVU.z [Rs+],Rd [ Rd | 1100010z | Rs ] 2522(dni-cmt-ubw 2523 movu-m "movu from memory to register" 2524 "[${Rs}${inc}],${Rd}" 2525 (+ INDIR_MOVX Rs Rd) 2526 (.pmacro 2527 (BW) 2528 (sequence 2529 ((SI tmp)) 2530 (set tmp (zext SI (cris-get-mem BW Rs))) 2531 (if (andif prefix-set (not inc)) 2532 (set Rs tmp) 2533 (set Rd tmp)) 2534 (setf-move SI tmp))) 2535) 2536 2537; MOVE Rs,Pd [ Pd | 01100011 | Rs ] 2538(.splice 2539 begin 2540 (.unsplice 2541 (.map 2542 (.pmacro 2543 (VER) 2544 (dni 2545 (.sym move-r-spr VER) 2546 "Move from general register to special register" 2547 ((MACH (.sym cris VER))) 2548 "move ${Rs},${Pd}" 2549 (+ RFIX_MOVE_R_S MODE_REGISTER SIZE_FIXED Rs Pd) 2550 (sequence 2551 ((SI tmp) (SI rno)) 2552 (set tmp Rs) 2553 (set rno (regno Pd)) 2554 (cond 2555 ; See reg-sr setter for most of the special-register semantics. 2556 ; The sanity check for known read-only registers is for program 2557 ; debug help; the real insn would be harmless and have no effect. 2558 ; CGEN-FIXME: regno of symbolic h-sr names doesn't work here. 2559 ((orif (orif (eq rno 0) (eq rno 1)) (orif (eq rno 4) (eq rno 8))) 2560 (error "move-r-spr: trying to set a read-only special register")) 2561 (else (set Pd tmp))) 2562 (reset-x-p)) 2563 (cris-reg-sr-timing))) 2564 (cris-cpu-models))) 2565) 2566 2567(define-pmacro (dni-cdt-ver-attr name comment fattr syntax fmt fsem) 2568 "Generator for each MACH, using default timing." 2569 (.splice 2570 begin 2571 (.unsplice 2572 (.map 2573 (.pmacro (v) (dni-cdt-attr name comment (fattr v) syntax fmt (fsem v))) 2574 (cris-cpu-models)))) 2575) 2576 2577; MOVE Ps,Rd [ Ps | 01100111 | Rd ] 2578; Note that in the insn format, the Rd operand is in the Rs field (the 2579; Rd field by the definition used everywhere else is the Ps position in 2580; this insn). 2581; It gets a little weird here because we can't get this insn into a 2582; define-pmacro unless we make named pmacros for e.g. a separate attr 2583; function and a semantics function: a .pmacro can't refer to the 2584; parameters of the outer define-pmacro. (The manual refers to this as 2585; not implementing "lexical scoping"). 2586(.splice 2587 begin 2588 (.unsplice 2589 (.map 2590 (.pmacro 2591 (VER) 2592 (dni-cdt-attr 2593 (.sym move-spr-r VER) 2594 "Move from special register to general register" 2595 ((MACH (.sym cris VER))) 2596 "move ${Ps},${Rd-sfield}" 2597 (+ Ps RFIX_MOVE_S_R MODE_REGISTER SIZE_FIXED Rd-sfield) 2598 (sequence 2599 ((SI grno) (SI prno) (SI newval)) 2600 (set prno (regno Ps)) 2601 ; CGEN-FIXME: Can't use the following and then "grno" below because 2602 ; CGEN will emit a "tmp_grno" *also* in decodev32.c:crisv32f_decode 2603 ; (set grno (regno Rd-sfield)) 2604 (set newval Ps) 2605 (.splice 2606 cond 2607 (.unsplice 2608 (.map 2609 (.pmacro 2610 (r) 2611 ((eq prno (.cadr2 r)) 2612 (set-subreg-gr (.car2 r) (regno Rd-sfield) newval))) 2613 ((.sym cris-implemented-readable-specregs- VER)))) 2614 (else (error "move-spr-r from unimplemented register"))) 2615 (reset-x-p)))) 2616 (cris-cpu-models))) 2617) 2618 2619; MOVE Ps,PC [ Ps | 01100111 | 1111 ] 2620; The move-special-register-to-pc insns are return-type instructions and 2621; have to be special-cased to get the delay-slot and avoid being indicated 2622; as invalid. 2623(dni-cdt-attr 2624 ret-type 2625 "ret-type" 2626 (MACH-PC) 2627 "ret/reti/retb" 2628 (+ Ps MODE_REGISTER RFIX_MOVE_S_R SIZE_FIXED (f-source 15)) 2629 (sequence 2630 ((SI retaddr)) 2631 (set retaddr Ps) 2632 (reset-x-p) 2633 (delay 1 (set pc retaddr))) 2634) 2635 2636; MOVE [Rs],Pd [ Pd | 10100011 | Rs ] 2637; MOVE [Rs+],Pd [ Pd | 11100011 | Rs ] 2638; We make variants that loads constants or memory for each MACH version, 2639; since each consider some subset of the "special registers" to have 2640; different sizes. FIXME: Should be able to simplify this. 2641(.splice 2642 begin 2643 (.unsplice 2644 (.map 2645 (.pmacro 2646 (VER) 2647 (dni 2648 (.sym move-m-spr VER) 2649 "Move from memory to special register" 2650 ((MACH (.sym cris VER))) 2651 "move [${Rs}${inc}],${Pd}" 2652 (+ Pd INFIX_MOVE_M_S MODEMEMP_YES inc SIZE_FIXED Rs) 2653 (sequence 2654 ((SI rno) (SI newval)) 2655 (set rno (regno Pd)) 2656 (.splice 2657 cond 2658 ; No sanity check for constant special register here, since the 2659 ; memory read side-effect or post-increment may be the goal, or 2660 ; for pre-v32 a prefix assignment side-effect. 2661 (.unsplice 2662 (.map 2663 (.pmacro 2664 (r) 2665 ((eq rno (.cadr2 r)) 2666 (set newval ((.sym (.car2 r) -ext) (cris-get-mem (.car2 r) Rs))))) 2667 ((.sym cris-implemented-writable-specregs- VER)))) 2668 (else (error "Trying to set unimplemented special register"))) 2669 (set Pd newval) 2670 (reset-x-p)) 2671 (cris-mem-sr-timing))) 2672 (cris-cpu-models))) 2673) 2674 2675(define-pmacro QI-operand sconst8) 2676(define-pmacro HI-operand sconst16) 2677(define-pmacro SI-operand const32) 2678 2679(define-pmacro 2680 (cris-move-c-spr VER VERFN) 2681 "Generator for loading constant into special register" 2682 (.splice 2683 begin 2684 (.unsplice 2685 (.map 2686 (.pmacro 2687 (srdef v) 2688 (dni 2689 (.sym move-c-spr v -p (.cadr2 srdef)) 2690 (.str "Move constant to special register p" (.cadr2 srdef)) 2691 ((MACH (.sym cris v))) 2692 (.str "move ${" (.sym (.car2 srdef) -operand) "},${Pd}") 2693 ; We use Pd in semantics without naming it in the format (which 2694 ; would CGEN-FIXME: cause a CGEN error for some reason, likely 2695 ; related to specifying an insn field multiple times). This 2696 ; currently works and is guarded with test-cases (specifically 2697 ; wrt. the timing model) but may need to be tweaked in the future. 2698 ; Note that using instead (ifield f-dest) causes incorrect timing 2699 ; model to be generated; the timing model requires that Pd is set. 2700 (+ (f-dest (.cadr2 srdef)) MODE_AUTOINCREMENT INFIX_MOVE_M_S SIZE_FIXED 2701 (f-source 15) (.sym (.car2 srdef) -operand)) 2702 (sequence 2703 () 2704 (set Pd (.sym (.car2 srdef) -operand)) ; (reg h-sr (.cadr2 srdef)) 2705 (reset-x-p)) 2706 ((.sym cris-timing-const-sr- (.car2 srdef))))) 2707 ((.sym cris-implemented-specregs-const- VER)) 2708 (.map VERFN ((.sym cris-implemented-specregs-const- VER)))))) 2709) 2710 2711; CGEN-FIXME: 2712; Unfortunately we can't iterate over the list of models due to the 2713; problem with referring to the parameters of a surrounding pmacro from 2714; within an enclosed .pmacro (perhaps related to "lexical scoping"). 2715; We get e.g. 'insn already defined:: (move-c-sprvn-p0)' with this: 2716;(.splice 2717; begin (.unsplice (.map (.pmacro (vn) (cris-move-c-spr vn (.pmacro (x) vn))) 2718; (cris-cpu-models))) 2719;) 2720(cris-move-c-spr v0 (.pmacro (x) v0)) 2721(cris-move-c-spr v3 (.pmacro (x) v3)) 2722(cris-move-c-spr v8 (.pmacro (x) v8)) 2723(cris-move-c-spr v10 (.pmacro (x) v10)) 2724(cris-move-c-spr v32 (.pmacro (x) v32)) 2725 2726; MOVE Ps,[Rd] [ Ps | 10100111 | Rd ] 2727; MOVE Ps,[Rd+] [ Ps | 11100111 | Rd ] 2728(.splice 2729 begin 2730 (.unsplice 2731 (.map 2732 (.pmacro 2733 (VER) 2734 (dni-cmwt-attr 2735 (.sym move-spr-m VER) 2736 "Move from special register to memory" 2737 ((MACH (.sym cris VER))) 2738 "move ${Ps},[${Rd-sfield}${inc}]" 2739 (+ INFIX_MOVE_S_M SIZE_FIXED Rd-sfield Ps) 2740 (sequence 2741 ((SI rno)) 2742 (set rno (regno Ps)) 2743 (.splice 2744 cond 2745 (.unsplice 2746 (.map 2747 (.pmacro 2748 (r) 2749 ((eq rno (.cadr2 r)) 2750 (cris-set-mem (.car2 r) Rd-sfield Ps))) 2751 ((.sym cris-implemented-readable-specregs- VER)))) 2752 (else (error "write from unimplemented special register"))) 2753 (reset-x-p)))) 2754 (cris-cpu-models))) 2755) 2756 2757; SBFS [Rs(+)] 2758; Instruction format: |0 0 1 1 1 m 1 1 0 1 1 1| Dest. | 2759(dni-cdt-attr 2760 sbfs 2761 "sbfs" 2762 ((MACH crisv10)) 2763 "sbfs [${Rd-sfield}${inc}]" 2764 (+ (f-dest 3) INFIX_SBFS SIZE_FIXED MODEMEMP_YES inc Rd-sfield) 2765 (error "SBFS isn't implemented") 2766) 2767 2768; MOVE Ss,Rd [ Ss | 11110111 | Rd ] 2769(dni-cdt-attr 2770 move-ss-r 2771 "move from support register to general register" 2772 (MACH-V32) 2773 "move ${Ss},${Rd-sfield}" 2774 (+ Ss INFIX_MOVE_SS SIZE_FIXED (f-mode 3) Rd-sfield) 2775 (sequence 2776 () 2777 (set Rd-sfield Ss) 2778 (reset-x-p)) 2779) 2780 2781; MOVE Rs,Sd [ Sd | 10110111 | Rs ] 2782(dni-cdt-attr 2783 move-r-ss 2784 "move from general register to support register" 2785 (MACH-V32) 2786 "move ${Rs},${Sd}" 2787 (+ Sd INFIX_MOVE_SS SIZE_FIXED (f-mode 2) Rs) 2788 (sequence 2789 () 2790 (set Sd Rs) 2791 (reset-x-p)) 2792) 2793 2794; MOVEM Rs,[Rd] [ Rs | 10111111 | Rd ] 2795; MOVEM Rs,[Rd+] [ Rs | 11111111 | Rd ] 2796 2797(define-pmacro (movem-to-mem-step regn) 2798 ; Without the SI attribute, UINT is generated, which isn't supported by 2799 ; the sim framework. 2800 (if (ge SI (regno Rs-dfield) regn) 2801 (sequence 2802 ((SI tmp)) 2803 (set tmp (reg h-gr regn)) 2804 (set (mem SI addr) tmp) 2805 (set addr (add addr 4)))) 2806) 2807 2808(dni 2809 movem-r-m 2810 "movem to memory" 2811 (MACH-PRE-V32) 2812 "movem ${Rs-dfield},[${Rd-sfield}${inc}]" 2813 (+ INFIX_MOVEM_R_M MODEMEMP_YES inc SIZE_FIXED Rs-dfield Rd-sfield) 2814 (sequence 2815 ((SI addr) (BI postinc)) 2816 ; FIXME: A copy of what's in cris-get-mem. 2817 2818 ; Cache the incrementness of the operand. 2819 (set postinc inc) 2820 2821 ; CGEN-FIXME: Kludge to work around a CGEN bug: it doesn't see that 2822 ; Rs-dfield is used as an input, causing the timing model to be wrong. 2823 (sequence ((SI dummy)) (set dummy Rs-dfield)) 2824 2825 ; Get the address from somewhere. If the insn was prefixed, it's in 2826 ; the prefix-register. 2827 (set addr 2828 (if SI (eq prefix-set 0) 2829 Rd-sfield 2830 prefixreg)) 2831 2832 (.splice 2833 sequence () 2834 (.unsplice (.map movem-to-mem-step (.iota 16 15 -1)))) 2835 2836 ; Update the source-register for post-increments. 2837 (if (ne postinc 0) 2838 (set Rd-sfield 2839 (if SI (eq prefix-set 0) addr prefixreg))) 2840 (reset-x-p)) 2841 (simplecris-movem-timing) 2842) 2843 2844(dni 2845 movem-r-m-v32 2846 "movem to memory" 2847 (MACH-V32) 2848 "movem ${Rs-dfield},[${Rd-sfield}${inc}]" 2849 (+ INFIX_MOVEM_R_M MODEMEMP_YES inc SIZE_FIXED Rs-dfield Rd-sfield) 2850 (sequence 2851 ((SI addr) (BI postinc)) 2852 ; FIXME: Mostly a copy of what's in cris-get-mem. 2853 2854 ; Cache the incrementness of the operand. 2855 (set postinc inc) 2856 2857 ; CGEN-FIXME: See movem-r-m. 2858 (sequence ((SI dummy)) (set dummy Rs-dfield)) 2859 2860 (set addr Rd-sfield) 2861 2862 (.splice 2863 sequence () 2864 (.unsplice (.map movem-to-mem-step (.iota 16)))) 2865 2866 ; Update the source-register for post-increments. 2867 (if (ne postinc 0) 2868 (set Rd-sfield addr)) 2869 (reset-x-p)) 2870 ; Unit u-mem must be specified before the u-movem-* for memory address 2871 ; register stall count to be right. 2872 ((crisv32 (unit u-mem) (unit u-movem-rtom) (unit u-exec-movem) 2873 (unit u-mem-w))) 2874) 2875 2876; MOVEM [Rs],Rd [ Rd | 10111011 | Rs ] 2877; MOVEM [Rs+],Rd [ Rd | 11111011 | Rs ] 2878 2879(define-pmacro 2880 (movem-to-reg-step regn) 2881 ; Without the SI attribute, UINT is generated, which isn't supported by 2882 ; the sim framework. 2883 (if (ge SI (regno Rd) regn) 2884 (sequence 2885 ((SI tmp)) 2886 (set tmp (mem SI addr)) 2887 (set (reg h-gr regn) tmp) 2888 (set addr (add addr 4)))) 2889) 2890 2891(dni 2892 movem-m-r 2893 "movem to register" 2894 (MACH-PRE-V32) 2895 "movem [${Rs}${inc}],${Rd}" 2896 (+ Rd INFIX_MOVEM_M_R MODEMEMP_YES inc SIZE_FIXED Rs) 2897 (sequence 2898 ((SI addr) (BI postinc)) 2899 ; FIXME: Mostly a copy of what's in cris-get-mem. 2900 2901 ; Cache the incrementness of the operand. 2902 (set postinc inc) 2903 2904 ; Get the address from somewhere. If the insn was prefixed, it's in 2905 ; the prefix-register. 2906 (set addr 2907 (if SI (eq prefix-set 0) 2908 Rs 2909 prefixreg)) 2910 2911 ; CGEN-FIXME: See movem-r-m. 2912 (sequence ((SI dummy)) (set dummy Rd)) 2913 2914 (.splice 2915 sequence () 2916 ; The first movem step is left out because it can't happen; it's for 2917 ; PC destination. See the pattern below. 2918 (.unsplice (.map movem-to-reg-step (.iota 15 14 -1)))) 2919 2920 ; Update the source-register for post-increments. 2921 ; FIXME: No postinc-prefixed for v0 IIRC. 2922 (if (ne postinc 0) 2923 (set Rs (if SI (eq prefix-set 0) addr prefixreg))) 2924 (reset-x-p)) 2925 (simplecris-movem-timing) 2926) 2927 2928; (MOVEM [Rs],PC [ 1111 | 10111011 | Rs ]) 2929; (MOVEM [Rs+],PC [ 1111 | 11111011 | Rs ]) 2930; We have to special-case it for PC destination; used in longjump. 2931; We shouldn't *have* to special-case it; the main reason is (FIXME:) 2932; misgeneration of the simulator when the PC case is folded into the 2933; generic PRE-V32 movem; possibly related to then being a COND-CTI rather 2934; than an UNCOND-CTI. 2935(dni-cmt-attr 2936 movem-m-pc 2937 "movem to register, ending with PC" 2938 (MACH-PRE-V32) 2939 "movem [${Rs}${inc}],${Rd}" 2940 (+ (f-dest 15) INFIX_MOVEM_M_R SIZE_FIXED Rs) 2941 (sequence 2942 ((SI addr) (BI postinc)) 2943 ; FIXME: Mostly a copy of what's in cris-get-mem. 2944 2945 ; Cache the incrementness of the operand. 2946 (set postinc inc) 2947 2948 ; Get the address from somewhere. If the insn was prefixed, it's in 2949 ; the prefix-register. 2950 (set addr 2951 (if SI (eq prefix-set 0) 2952 Rs 2953 prefixreg)) 2954 2955 ; FIXME: Add kludge here too *and* a test-case. 2956 2957 (.splice 2958 sequence () 2959 ; The first movem step is for PC destination, used in longjmp. 2960 (set pc (mem SI addr)) 2961 (set addr (add addr 4)) 2962 (.unsplice 2963 (.map 2964 (.pmacro 2965 (regn) 2966 (sequence 2967 ((SI tmp)) 2968 (set tmp (mem SI addr)) 2969 (set (reg h-gr regn) tmp) 2970 (set addr (add addr 4)))) 2971 (.iota 15 14 -1)))) 2972 2973 ; Update the source-register for post-increments. 2974 ; FIXME: No postinc-prefixed for v0. 2975 (if (ne postinc 0) 2976 (set Rs (if SI (eq prefix-set 0) addr prefixreg))) 2977 (reset-x-p)) 2978) 2979 2980(dni 2981 movem-m-r-v32 2982 "movem to register" 2983 (MACH-V32) 2984 "movem [${Rs}${inc}],${Rd}" 2985 (+ INFIX_MOVEM_M_R MODEMEMP_YES inc SIZE_FIXED Rs Rd) 2986 (sequence 2987 ((SI addr) (BI postinc)) 2988 ; FIXME: A copy of what's in cris-get-mem 2989 2990 ; Cache the incrementness of the operand. 2991 (set postinc inc) 2992 2993 ; Get the address from somewhere. 2994 (set addr Rs) 2995 2996 ; CGEN-FIXME: See movem-r-m. 2997 (sequence ((SI dummy)) (set dummy Rd)) 2998 2999 (.splice 3000 sequence () 3001 (.unsplice (.map movem-to-reg-step (.iota 16)))) 3002 3003 ; Update the source-register for post-increments. 3004 ; FIXME: No postinc-prefixed for v0 IIRC. 3005 (if (ne postinc 0) 3006 (set Rs addr)) 3007 (reset-x-p)) 3008 ; u-mem must be specified before the u-movem-* for memory source 3009 ; register stall count to be right. 3010 ((crisv32 (unit u-mem) (unit u-mem-r) (unit u-movem-mtor) 3011 (unit u-exec-movem))) 3012) 3013 3014; ADD.m Rs,Rd [ Rd | 011000mm | Rs ] 3015(dni-cdt-bwd 3016 add "add from register to register" 3017 "$Rs,$Rd" 3018 (+ Rd MODE_REGISTER R_ADD Rs) 3019 (.pmacro (BWD) (cris-arit add BWD Rd Rs)) 3020) 3021 3022; ADD.m [Rs],Rd [ Rd | 101000mm | Rs ] 3023; ADD.m [Rs+],Rd [ Rd | 111000mm | Rs ] 3024(dni-cmt-bwd 3025 add-m "add from memory to register" 3026 "[${Rs}${inc}],${Rd}" 3027 (+ INDIR_ADD Rs Rd) 3028 (.pmacro (BWD) (cris-arit-3op add BWD Rd (cris-get-mem BWD Rs) Rs)) 3029) 3030; (ADD.m [PC+],Rd [ Rd | 111000mm | 1111 ]) 3031(dni-c-QI 3032 addcbr "add constant byte to register" 3033 "add.b ${sconst8}],${Rd}" 3034 (+ Rd MODE_AUTOINCREMENT INDIR_ADD SIZE_BYTE (f-source 15) sconst8) 3035 (cris-arit add QI Rd sconst8) 3036) 3037 3038(dni-c-HI 3039 addcwr "add constant word to register" 3040 "add.w ${sconst16}],${Rd}" 3041 (+ Rd MODE_AUTOINCREMENT INDIR_ADD SIZE_WORD (f-source 15) sconst16) 3042 (cris-arit add HI Rd sconst16) 3043) 3044 3045(dni-c-SI 3046 addcdr "add constant dword to register" 3047 "add.d ${const32}],${Rd}" 3048 (+ Rd MODE_AUTOINCREMENT INDIR_ADD SIZE_DWORD (f-source 15) const32) 3049 (cris-arit add SI Rd const32) 3050) 3051 3052; (ADD.D [PC+],PC [ 1111 | 11100010 | 1111 ]) 3053; This insn is used for DSO-local jumps in PIC code. 3054(dni 3055 addcpc "Relative jump by adding constant to PC" 3056 (MACH-PC) 3057 "add.d ${sconst32},PC" 3058 (+ (f-dest 15) MODE_AUTOINCREMENT INDIR_ADD SIZE_DWORD (f-source 15) const32) 3059 (sequence 3060 ((SI newpc) (SI oldpc) (SI offs)) 3061 (set offs const32) 3062 (set oldpc (add SI pc 6)) 3063 (set newpc (add SI oldpc offs)) 3064 (set pc newpc) 3065 (setf-arit SI add oldpc offs newpc cbit)) 3066 (simplecris-common-timing ((unit u-const32) (unit u-stall) (unit u-exec))) 3067) 3068 3069; ADDS.z Rs,Rd [ Rd | 0100001z | Rs ] 3070(dni-cdt-sbw 3071 adds "add sign-extended from register to register" 3072 "$Rs,$Rd" 3073 (+ Rd MODE_REGISTER R_ADDX Rs) 3074 (.pmacro (BW) (cris-arit add SI Rd ((.sym BW -ext) (trunc BW Rs)))) 3075) 3076 3077; ADDS.z [Rs],Rd [ Rd | 1000001z | Rs ] 3078; ADDS.z [Rs+],Rd [ Rd | 1100001z | Rs ] 3079(dni-cmt-sbw 3080 adds-m "add sign-extended from memory to register" 3081 "[${Rs}${inc}],$Rd" 3082 (+ Rd INDIR_ADDX Rs) 3083 (.pmacro (BW) (cris-arit-3op add SI Rd ((.sym BW -ext) (cris-get-mem BW Rs)) Rs)) 3084) 3085 3086; (ADDS.z [PC+],Rd [ Rd | 1100001z | 1111 ]) 3087(dni-c-QI 3088 addscbr "add sign-extended constant byte to register" 3089 "[${Rs}${inc}],$Rd" 3090 (+ Rd MODE_AUTOINCREMENT INDIR_ADDX SIGNED_BYTE (f-source 15) sconst8) 3091 (cris-arit add SI Rd (ext SI (trunc QI sconst8))) 3092) 3093(dni-c-HI 3094 addscwr "add sign-extended constant word to register" 3095 "[${Rs}${inc}],$Rd" 3096 (+ Rd MODE_AUTOINCREMENT INDIR_ADDX SIGNED_WORD (f-source 15) sconst16) 3097 (cris-arit add SI Rd (ext SI (trunc HI sconst16))) 3098) 3099 3100; (ADDS.w [],PC [ 1111 | 10000011 | 1111 ]) 3101; For a PC destination, we support only the two-operand case 3102; (dest == src), which is used in switch/case statements. 3103; FIXME: Should implement ADD.D [PC],PC and ADDS.B [PC],PC for use if/when 3104; implementing CASE_VECTOR_SHORTEN_MODE. 3105(dni 3106 addspcpc "add sign-extended prefixed arg to PC" 3107 (MACH-PC) 3108 "adds.w [PC],PC" 3109 (+ (f-dest 15) MODE_INDIRECT INDIR_ADDX SIGNED_WORD (f-source 15)) 3110 (sequence 3111 ((SI newpc) (SI oldpc) (HI offs)) 3112 (if (not prefix-set) 3113 (error "Unexpected adds.w [PC],PC without prefix")) 3114 ; We don't use cris-get-mem but instead special-case this one, since we 3115 ; have most instruction fields fixed where cris-get-mem expects 3116 ; field-parametrization by certain names. 3117 (set offs (mem HI prefixreg)) 3118 (set oldpc (add SI pc 2)) 3119 (set newpc (add SI oldpc offs)) 3120 (set pc newpc) 3121 (setf-arit SI add oldpc (ext SI offs) newpc cbit)) 3122 (simplecris-common-timing ((unit u-mem) (unit u-stall) (unit u-exec))) 3123) 3124 3125; ADDU.z Rs,Rd [ Rd | 0100000z | Rs ] 3126(dni-cdt-ubw 3127 addu "add zero-extended from register to register" 3128 "$Rs,$Rd" 3129 (+ Rd MODE_REGISTER R_ADDX Rs) 3130 (.pmacro (BW) (cris-arit add SI Rd ((.sym BW -zext) (trunc BW Rs)))) 3131) 3132 3133; ADDU.z [Rs],Rd [ Rd | 1000000z | Rs ] 3134; ADDU.z [Rs+],Rd [ Rd | 1100000z | Rs ] 3135(dni-cmt-ubw 3136 addu-m "add zero-extended from memory to register" 3137 "[${Rs}${inc}],$Rd" 3138 (+ Rd INDIR_ADDX Rs) 3139 (.pmacro (BW) 3140 (cris-arit-3op add SI Rd ((.sym BW -zext) (cris-get-mem BW Rs)) Rs)) 3141) 3142 3143; (ADDU.z [PC+],Rd [ Rd | 1100000z | 1111 ]) 3144(dni-c-QI 3145 adducbr "add zero-extended constant byte to register" 3146 "[${Rs}${inc}],$Rd" 3147 (+ Rd MODE_AUTOINCREMENT INDIR_ADDX UNSIGNED_BYTE (f-source 15) sconst8) 3148 (cris-arit add SI Rd (zext SI (trunc QI sconst8))) 3149) 3150(dni-c-HI 3151 adducwr "add zero-extended constant word to register" 3152 "[${Rs}${inc}],$Rd" 3153 (+ Rd MODE_AUTOINCREMENT INDIR_ADDX UNSIGNED_WORD (f-source 15) sconst16) 3154 (cris-arit add SI Rd (zext SI (trunc HI sconst16))) 3155) 3156 3157; SUB.m Rs,Rd [ Rd | 011010mm | Rs ] 3158(dni-cdt-bwd 3159 sub "subtract from register to register" 3160 "$Rs,$Rd" 3161 (+ Rd MODE_REGISTER R_SUB Rs) 3162 (.pmacro (BWD) (cris-arit sub BWD Rd Rs)) 3163) 3164 3165; SUB.m [Rs],Rd [ Rd | 101010mm | Rs ] 3166; SUB.m [Rs+],Rd [ Rd | 111010mm | Rs ] 3167(dni-cmt-bwd 3168 sub-m "subtract from memory to register" 3169 "[${Rs}${inc}],${Rd}" 3170 (+ INDIR_SUB Rs Rd) 3171 (.pmacro (BWD) (cris-arit-3op sub BWD Rd (cris-get-mem BWD Rs) Rs)) 3172) 3173 3174; (SUB.m [PC+],Rd [ Rd | 111010mm | 1111 ] 3175(dni-c-QI 3176 subcbr "subtract constant byte from register" 3177 "sub.b ${sconst8}],${Rd}" 3178 (+ Rd MODE_AUTOINCREMENT INDIR_SUB SIZE_BYTE (f-source 15) sconst8) 3179 (cris-arit sub QI Rd sconst8) 3180) 3181 3182(dni-c-HI 3183 subcwr "subtract constant word from register" 3184 "sub.w ${sconst16}],${Rd}" 3185 (+ Rd MODE_AUTOINCREMENT INDIR_SUB SIZE_WORD (f-source 15) sconst16) 3186 (cris-arit sub HI Rd sconst16) 3187) 3188 3189(dni-c-SI 3190 subcdr "subtract constant dword from register" 3191 "sub.d ${const32}],${Rd}" 3192 (+ Rd MODE_AUTOINCREMENT INDIR_SUB SIZE_DWORD (f-source 15) const32) 3193 (cris-arit sub SI Rd const32) 3194) 3195 3196; SUBS.z Rs,Rd [ Rd | 0100101z | Rs ] 3197(dni-cdt-sbw 3198 subs "sub sign-extended from register to register" 3199 "$Rs,$Rd" 3200 (+ Rd MODE_REGISTER R_SUBX Rs) 3201 (.pmacro (BW) (cris-arit sub SI Rd ((.sym BW -ext) (trunc BW Rs)))) 3202) 3203 3204; SUBS.z [Rs],Rd [ Rd | 1000101z | Rs ] 3205; SUBS.z [Rs+],Rd [ Rd | 1100101z | Rs ] 3206(dni-cmt-sbw 3207 subs-m "sub sign-extended from memory to register" 3208 "[${Rs}${inc}],$Rd" 3209 (+ Rd INDIR_SUBX Rs) 3210 (.pmacro (BW) 3211 (cris-arit-3op sub SI Rd ((.sym BW -ext) (cris-get-mem BW Rs)) Rs)) 3212) 3213 3214; (SUBS.z [PC+],Rd [ Rd | 1100101z | 1111 ]) 3215(dni-c-QI 3216 subscbr "sub sign-extended constant byte to register" 3217 "[${Rs}${inc}],$Rd" 3218 (+ Rd MODE_AUTOINCREMENT INDIR_SUBX SIGNED_BYTE (f-source 15) sconst8) 3219 (cris-arit sub SI Rd (ext SI (trunc QI sconst8))) 3220) 3221(dni-c-HI 3222 subscwr "sub sign-extended constant word to register" 3223 "[${Rs}${inc}],$Rd" 3224 (+ Rd MODE_AUTOINCREMENT INDIR_SUBX SIGNED_WORD (f-source 15) sconst16) 3225 (cris-arit sub SI Rd (ext SI (trunc HI sconst16))) 3226) 3227 3228; SUBU.z Rs,Rd [ Rd | 0100100z | Rs ] 3229(dni-cdt-ubw 3230 subu "sub zero-extended from register to register" 3231 "$Rs,$Rd" 3232 (+ Rd MODE_REGISTER R_SUBX Rs) 3233 (.pmacro (BW) (cris-arit sub SI Rd ((.sym BW -zext) (trunc BW Rs)))) 3234) 3235 3236; SUBU.z [Rs],Rd [ Rd | 1000100z | Rs ] 3237; SUBU.z [Rs+],Rd [ Rd | 1100100z | Rs ] 3238(dni-cmt-ubw 3239 subu-m "sub zero-extended from memory to register" 3240 "[${Rs}${inc}],$Rd" 3241 (+ Rd INDIR_SUBX Rs) 3242 (.pmacro (BW) 3243 (cris-arit-3op sub SI Rd ((.sym BW -zext) (cris-get-mem BW Rs)) Rs)) 3244) 3245 3246; (SUBU.z [PC+],Rd [ Rd | 1100100z | 1111 ]) 3247(dni-c-QI 3248 subucbr "sub zero-extended constant byte to register" 3249 "[${Rs}${inc}],$Rd" 3250 (+ Rd MODE_AUTOINCREMENT INDIR_SUBX UNSIGNED_BYTE (f-source 15) sconst8) 3251 (cris-arit sub SI Rd (zext SI (trunc QI sconst8))) 3252) 3253(dni-c-HI 3254 subucwr "sub zero-extended constant word to register" 3255 "[${Rs}${inc}],$Rd" 3256 (+ Rd MODE_AUTOINCREMENT INDIR_SUBX UNSIGNED_WORD (f-source 15) sconst16) 3257 (cris-arit sub SI Rd (zext SI (trunc HI sconst16))) 3258) 3259 3260; ADDC Rs,Rd [ Rd | 01010111 | Rs ] 3261(dni-cdt-attr 3262 addc-r "addc from register to register" 3263 (MACH-V32) 3264 "addc $Rs,$Rd" 3265 (+ Rd MODE_REGISTER RFIX_ADDC SIZE_FIXED Rs) 3266 ; Since this is equivalent to "ax" plus "add.d Rs,Rd", we'll just do 3267 ; that, semantically. 3268 (sequence 3269 () 3270 (set-quiet xbit 1) 3271 (cris-arit add SI Rd Rs)) 3272) 3273 3274; ADDC [Rs],Rd [ Rd | 10011010 | Rs ] 3275; ADDC [Rs+],Rd [ Rd | 11011010 | Rs ] 3276(dni-cmt-attr 3277 addc-m "addc from memory to register" 3278 (MACH-V32) 3279 "addc [${Rs}${inc}],${Rd}" 3280 (+ Rd INDIR_ADDC SIZE_DWORD Rs) 3281 (sequence 3282 () 3283 (set-quiet xbit 1) 3284 (cris-arit add SI Rd (cris-get-mem SI Rs))) 3285) 3286 3287; (ADDC [Rs+],Rd [ Rd | 11011010 | 1111 ]) 3288(dni-c-SI-attr 3289 addc-c "addc constant to register" 3290 (MACH-V32) 3291 "addc ${const32},${Rd}" 3292 (+ Rd MODE_AUTOINCREMENT INDIR_ADDC SIZE_DWORD (f-source 15) const32) 3293 (sequence 3294 () 3295 (set-quiet xbit 1) 3296 (cris-arit add SI Rd const32)) 3297) 3298 3299; LAPC [PC+],Rd [ Rd | 11010111 1111 ] 3300(dni-c-SI-attr 3301 lapc-d "lapc.d" 3302 (MACH-V32) 3303 "lapc.d ${const32-pcrel},${Rd}" 3304 (+ Rd MODE_AUTOINCREMENT INFIX_LAPC SIZE_FIXED (f-source 15) const32-pcrel) 3305 (sequence 3306 () 3307 (set Rd const32-pcrel) 3308 (reset-x-p)) 3309) 3310 3311; LAPCQ qo,Rd [ Rd | 10010111 | qo ] 3312(dni-cdt-attr 3313 lapcq "lapcq" 3314 (MACH-V32) 3315 "lapcq ${qo},${Rd}" 3316 (+ Rd MODE_INDIRECT INFIX_LAPC SIZE_FIXED qo) 3317 (sequence 3318 () 3319 (set Rd qo) 3320 (reset-x-p)) 3321) 3322 3323; ADDI Rs.m,Rd [ Rs | 010100mm | Rd ] 3324(dni-cdt-bwd 3325 addi "addi" 3326 "${Rs-dfield}.m,${Rd-sfield}" 3327 (+ Rd-sfield MODE_REGISTER R_ADDI Rs-dfield) 3328 (.pmacro 3329 (BWD) 3330 (sequence 3331 () 3332 (set Rd-sfield (add SI Rd-sfield (mul Rs-dfield (.sym BWD -size)))) 3333 (reset-x-p))) 3334) 3335 3336; NEG.m Rs,Rd [ Rd | 010110mm | Rs ] 3337(dni-cdt-bwd 3338 neg "neg.m Rs,Rd" 3339 "$Rs,$Rd" 3340 (+ Rd MODE_REGISTER R_NEG Rs) 3341 (.pmacro (BWD) (cris-arit3 sub BWD Rd 0 Rs)) 3342) 3343 3344; TEST.m [Rs] [ 0000101110mm | Rs ] 3345; TEST.m [Rs+] [ 0000111110mm | Rs ] 3346(dni-cmt-bwd 3347 test-m "test.m [Rs(+)]" 3348 "[${Rs}${inc}]" 3349 (+ (f-dest 0) INDIR_TEST Rs) 3350 (.pmacro 3351 (BWD) 3352 (sequence 3353 ((BWD tmpd)) 3354 (set tmpd (cris-get-mem BWD Rs)) 3355 ; This is supposed to be the same result as for cmpq 0,X, hence same code. 3356 (cris-arit6-int 3357 sub BWD (.pmacro (sz regno val) (nop)) 0 tmpd 0 cbit cbit))) 3358) 3359 3360; MOVE.m Rs,[Rd] [ Rs | 101111mm | Rd ] 3361; MOVE.m Rs,[Rd+] [ Rs | 111111mm | Rd ] 3362 3363(dni-cmwt-bwd 3364 move-r-m "move.m R,[]" 3365 "${Rs-dfield},[${Rd-sfield}${inc}]" 3366 (+ Rs-dfield INDIR_MOVE_R_M Rd-sfield) 3367 (.pmacro 3368 (BWD) 3369 (sequence 3370 ((BWD tmpd)) 3371 (set tmpd Rs-dfield) 3372 (cris-set-mem BWD Rd-sfield tmpd) 3373 (reset-x-p))) 3374) 3375 3376; MULS.m Rs,Rd [ Rd | 110100mm | Rs ] 3377(dni-bwd-attr 3378 muls "muls.m Rs,Rd" 3379 ((MACH crisv10,crisv32)) 3380 "$Rs,$Rd" 3381 (+ Rd MODE_MULS INDIR_MUL Rs) 3382 (.pmacro 3383 (BWD) 3384 (sequence 3385 ((DI src1) (DI src2) (DI tmpr)) 3386 (set src1 (ext DI (trunc BWD Rs))) 3387 (set src2 (ext DI (trunc BWD Rd))) 3388 (set tmpr (mul src1 src2)) 3389 (set Rd (trunc SI tmpr)) 3390 (set mof (trunc SI (srl tmpr 32))) 3391 (setf-arit DI muls src1 src2 tmpr cbit))) 3392 ((crisv10 (unit u-multiply) (unit u-exec)) 3393 (crisv32 (unit u-multiply) (unit u-exec))) 3394) 3395 3396; MULU.m Rs,Rd [ Rd | 100100mm | Rs ] 3397(dni-bwd-attr 3398 mulu "mulu.m Rs,Rd" 3399 ((MACH crisv10,crisv32)) 3400 "$Rs,$Rd" 3401 (+ Rd MODE_MULU INDIR_MUL Rs) 3402 (.pmacro 3403 (BWD) 3404 (sequence 3405 ((DI src1) (DI src2) (DI tmpr)) 3406 (set src1 (zext DI (trunc BWD Rs))) 3407 (set src2 (zext DI (trunc BWD Rd))) 3408 (set tmpr (mul src1 src2)) 3409 (set Rd (trunc SI tmpr)) 3410 (set mof (trunc SI (srl tmpr 32))) 3411 (setf-arit DI mulu src1 src2 tmpr cbit))) 3412 ((crisv10 (unit u-multiply) (unit u-exec)) 3413 (crisv32 (unit u-multiply) (unit u-exec))) 3414) 3415 3416; MCP Ps,Rd [ Ps | 01111111 | Rd ] 3417(dni-cdt-attr 3418 mcp "Multiply Carry Propagation" 3419 (MACH-V32) 3420 "mcp $Ps,$Rd" 3421 (+ Ps MODE_REGISTER RFIX_MCP SIZE_FIXED Rd-sfield) 3422 (sequence 3423 () 3424 (set-quiet xbit 1) 3425 (set-quiet zbit 1) 3426 (cris-arit5 add SI Rd-sfield Rd-sfield Ps rbit rbit)) 3427) 3428 3429; MSTEP Rs,Rd [ Rd | 01111111 | Rs ] 3430(dni-cdt-attr 3431 mstep "Multiply step" 3432 (MACH-PRE-V32) 3433 "mstep $Rs,$Rd" 3434 (+ Rd MODE_REGISTER RFIX_MSTEP SIZE_FIXED Rs) 3435 (sequence 3436 ((SI tmpd) (SI tmps)) 3437 (set tmps Rs) 3438 (set tmpd (add (sll Rd 1) (if SI nbit tmps 0))) 3439 (set Rd tmpd) 3440 (setf-move SI tmpd)) 3441) 3442 3443; DSTEP Rs,Rd [ Rd | 01101111 | Rs ] 3444(dni-cdt 3445 dstep "Division step" 3446 "dstep $Rs,$Rd" 3447 (+ Rd MODE_REGISTER RFIX_DSTEP SIZE_FIXED Rs) 3448 (sequence 3449 ((SI tmp) (SI tmps) (SI tmpd)) 3450 (set tmps Rs) 3451 (set tmp (sll Rd 1)) 3452 (set tmpd (if SI (geu tmp tmps) (sub tmp tmps) tmp)) 3453 (set Rd tmpd) 3454 (setf-move SI tmpd)) 3455) 3456 3457; ABS Rs,Rd [ Rd | 01101011 | Rs ] 3458(dni-cdt 3459 abs "Absolut Instruction" 3460 "abs $Rs,$Rd" 3461 (+ Rd MODE_REGISTER RFIX_ABS SIZE_FIXED Rs) 3462 (sequence 3463 ((SI tmpd)) 3464 (set tmpd (abs Rs)) 3465 (set Rd tmpd) 3466 (setf-move SI tmpd)) 3467) 3468 3469; AND.m Rs,Rd [ Rd | 011100mm | Rs ] 3470(dni-cdt-bwd 3471 and "And from register to register" 3472 "$Rs,$Rd" 3473 (+ Rd MODE_REGISTER R_AND Rs) 3474 (.pmacro 3475 (BWD) 3476 (sequence 3477 ((BWD tmpd)) 3478 (set tmpd (and BWD Rd Rs)) 3479 (set-subreg-gr BWD (regno Rd) tmpd) 3480 (setf-move BWD tmpd))) 3481) 3482 3483; AND.m [Rs],Rd [ Rd | 101100mm | Rs ] 3484; AND.m [Rs+],Rd [ Rd | 111100mm | Rs ] 3485(dni-cmt-bwd 3486 and-m "And from memory to register" 3487 "[${Rs}${inc}],${Rd}" 3488 (+ INDIR_AND Rs Rd) 3489 (.pmacro 3490 (BWD) 3491 (sequence 3492 ((BWD tmpd)) 3493 (set tmpd (and BWD Rd (cris-get-mem BWD Rs))) 3494 (set-subreg-gr 3495 BWD 3496 (if SI (andif prefix-set (not inc)) (regno Rs) (regno Rd)) 3497 tmpd) 3498 (setf-move BWD tmpd))) 3499) 3500 3501; (AND.m [PC+],Rd [ Rd | 111100mm | 1111 ]) 3502(dni-c-QI 3503 andcbr "And constant byte to register" 3504 "and.b ${sconst8}],${Rd}" 3505 (+ Rd MODE_AUTOINCREMENT INDIR_AND SIZE_BYTE (f-source 15) sconst8) 3506 (sequence 3507 ((QI tmpd)) 3508 (set tmpd (and QI Rd sconst8)) 3509 (set-subreg-gr QI (regno Rd) tmpd) 3510 (setf-move QI tmpd)) 3511) 3512 3513(dni-c-HI 3514 andcwr "And constant word to register" 3515 "and.w ${sconst16}],${Rd}" 3516 (+ Rd MODE_AUTOINCREMENT INDIR_AND SIZE_WORD (f-source 15) sconst16) 3517 (sequence 3518 ((HI tmpd)) 3519 (set tmpd (and HI Rd sconst16)) 3520 (set-subreg-gr HI (regno Rd) tmpd) 3521 (setf-move HI tmpd)) 3522) 3523 3524(dni-c-SI 3525 andcdr "And constant dword to register" 3526 "and.d ${const32}],${Rd}" 3527 (+ Rd MODE_AUTOINCREMENT INDIR_AND SIZE_DWORD (f-source 15) const32) 3528 (sequence 3529 ((SI tmpd)) 3530 (set tmpd (and SI Rd const32)) 3531 (set-subreg-gr SI (regno Rd) tmpd) 3532 (setf-move SI tmpd)) 3533) 3534 3535; ANDQ i,Rd [ Rd | 001100 | i ] 3536(dni-cdt 3537 andq "And quick-immediate to register" 3538 "andq $i,$Rd" 3539 (+ Rd MODE_QUICK_IMMEDIATE Q_ANDQ i) 3540 (sequence 3541 ((SI tmpd)) 3542 (set tmpd (and SI Rd i)) 3543 (set-subreg-gr SI (regno Rd) tmpd) 3544 (setf-move SI tmpd)) 3545) 3546 3547; OR.m Rs,Rd [ Rd | 011101mm | Rs ] 3548(dni-cdt-bwd 3549 orr "Or from register to register" 3550 "$Rs,$Rd" 3551 (+ Rd MODE_REGISTER R_OR Rs) 3552 (.pmacro 3553 (BWD) 3554 (sequence 3555 ((BWD tmpd)) 3556 (set tmpd (or BWD Rd Rs)) 3557 (set-subreg-gr BWD (regno Rd) tmpd) 3558 (setf-move BWD tmpd))) 3559) 3560 3561; OR.m [Rs],Rd [ Rd | 101101mm | Rs ] 3562; OR.m [Rs+],Rd [ Rd | 111101mm | Rs ] 3563(dni-cmt-bwd 3564 or-m "Or from memory to register" 3565 "[${Rs}${inc}],${Rd}" 3566 (+ INDIR_OR Rs Rd) 3567 (.pmacro 3568 (BWD) 3569 (sequence 3570 ((BWD tmpd)) 3571 (set tmpd (or BWD Rd (cris-get-mem BWD Rs))) 3572 (set-subreg-gr 3573 BWD 3574 (if SI (andif prefix-set (not inc)) (regno Rs) (regno Rd)) 3575 tmpd) 3576 (setf-move BWD tmpd))) 3577) 3578 3579; (OR.m [PC+],Rd [ Rd | 111101mm | 1111 ]) 3580(dni-c-QI 3581 orcbr "Or constant byte to register" 3582 "or.b ${sconst8}],${Rd}" 3583 (+ Rd MODE_AUTOINCREMENT INDIR_OR SIZE_BYTE (f-source 15) sconst8) 3584 (sequence 3585 ((QI tmpd)) 3586 (set tmpd (or QI Rd sconst8)) 3587 (set-subreg-gr QI (regno Rd) tmpd) 3588 (setf-move QI tmpd)) 3589) 3590 3591(dni-c-HI 3592 orcwr "Or constant word to register" 3593 "or.w ${sconst16}],${Rd}" 3594 (+ Rd MODE_AUTOINCREMENT INDIR_OR SIZE_WORD (f-source 15) sconst16) 3595 (sequence 3596 ((HI tmpd)) 3597 (set tmpd (or HI Rd sconst16)) 3598 (set-subreg-gr HI (regno Rd) tmpd) 3599 (setf-move HI tmpd)) 3600) 3601 3602(dni-c-SI 3603 orcdr "Or constant dword to register" 3604 "or.d ${const32}],${Rd}" 3605 (+ Rd MODE_AUTOINCREMENT INDIR_OR SIZE_DWORD (f-source 15) const32) 3606 (sequence 3607 ((SI tmpd)) 3608 (set tmpd (or SI Rd const32)) 3609 (set-subreg-gr SI (regno Rd) tmpd) 3610 (setf-move SI tmpd)) 3611) 3612 3613; ORQ i,Rd [ Rd | 001101 | i ] 3614(dni-cdt 3615 orq "Or quick-immediate to register" 3616 "orq $i,$Rd" 3617 (+ Rd MODE_QUICK_IMMEDIATE Q_ORQ i) 3618 (sequence 3619 ((SI tmpd)) 3620 (set tmpd (or SI Rd i)) 3621 (set-subreg-gr SI (regno Rd) tmpd) 3622 (setf-move SI tmpd)) 3623) 3624 3625; XOR Rs,Rd [ Rd | 01111011 | Rs ] 3626(dni-cdt 3627 xor "Xor from register to register" 3628 "xor $Rs,$Rd" 3629 (+ Rd MODE_REGISTER RFIX_XOR SIZE_FIXED Rs) 3630 (sequence 3631 ((SI tmpd)) 3632 (set tmpd (xor SI Rd Rs)) 3633 (set Rd tmpd) 3634 (setf-move SI tmpd)) 3635) 3636 3637(define-pmacro (swap-r x) 3638 "Perform bit-wise swap within each byte" 3639 (sequence 3640 SI 3641 ((SI tmpr)) 3642 (set tmpr x) 3643 (or (sll (and tmpr #x1010101) 7) 3644 (or (sll (and tmpr #x2020202) 5) 3645 (or (sll (and tmpr #x4040404) 3) 3646 (or (sll (and tmpr #x8080808) 1) 3647 (or (srl (and tmpr #x10101010) 1) 3648 (or (srl (and tmpr #x20202020) 3) 3649 (or (srl (and tmpr #x40404040) 5) 3650 (srl (and tmpr #x80808080) 7))))))))) 3651) 3652 3653(define-pmacro (swap-b x) 3654 "Perform byte-wise swap within each word" 3655 (sequence 3656 SI 3657 ((SI tmpb)) 3658 (set tmpb x) 3659 (or (and (sll tmpb 8) #xff00ff00) 3660 (and (srl tmpb 8) #xff00ff))) 3661) 3662 3663(define-pmacro (swap-w x) 3664 "Perform word-wise swap within each dword" 3665 (sequence 3666 SI 3667 ((SI tmpb)) 3668 (set tmpb x) 3669 (or (and (sll tmpb 16) #xffff0000) 3670 (and (srl tmpb 16) #xffff))) 3671) 3672 3673(define-pmacro (swap-_ x) 3674 "Do nothing swap-wise" 3675 (error SI "SWAP without swap modifier isn't implemented") 3676) 3677 3678(define-pmacro (swap-n x) 3679 "Perform bitwise not (that is, perform a not, not not perform)" 3680 (inv x) 3681) 3682 3683(define-pmacro (swap-br x) "Combine swap-r and swap-b" (swap-r (swap-b x))) 3684(define-pmacro (swap-wr x) "Combine swap-r and swap-w" (swap-r (swap-w x))) 3685(define-pmacro (swap-wb x) "Combine swap-b and swap-w" (swap-b (swap-w x))) 3686(define-pmacro (swap-wbr x) "Combine swap-r and swap-wb" (swap-r (swap-wb x))) 3687(define-pmacro (swap-nr x) "Combine swap-r and swap-n" (swap-r (swap-n x))) 3688(define-pmacro (swap-nb x) "Combine swap-n and swap-b" (swap-b (swap-n x))) 3689(define-pmacro (swap-nbr x) "Combine swap-r and swap-nb" (swap-r (swap-nb x))) 3690(define-pmacro (swap-nw x) "Combine swap-n and swap-w" (swap-w (swap-n x))) 3691(define-pmacro (swap-nwr x) "Combine swap-r and swap-nw" (swap-r (swap-nw x))) 3692(define-pmacro (swap-nwb x) "Combine swap-b and swap-nw" (swap-b (swap-nw x))) 3693(define-pmacro (swap-nwbr x) "Combine swap-r and swap-nwb" (swap-r (swap-nwb x))) 3694 3695(define-pmacro (cris-swap swapcode val) 3696 (sequence 3697 SI 3698 ((SI tmpcode) (SI tmpval) (SI tmpres)) 3699 (set tmpcode swapcode) 3700 (set tmpval val) 3701 (.splice 3702 cond 3703 (.unsplice 3704 (.map 3705 (.pmacro 3706 (x-swapcode x-swap) 3707 ((eq tmpcode x-swapcode) 3708 (set tmpres ((.sym swap- x-swap) tmpval)))) 3709 (.iota 16) 3710 (.splice _ (.unsplice cris-swap-codes))))) 3711 tmpres) 3712) 3713 3714; NOT Rd alias for SWAPN Rd 3715(dni-cdt-attr 3716 not "Not" 3717 ((MACH crisv0,crisv3)) 3718 "not ${Rs}" 3719 (+ (f-dest 8) RFIX_SWAP MODE_REGISTER SIZE_FIXED Rd-sfield) 3720 (sequence 3721 ((SI tmp) (SI tmpd)) 3722 (set tmp Rd-sfield) 3723 (set tmpd (cris-swap 8 tmp)) 3724 (set Rd-sfield tmpd) 3725 (setf-move SI tmpd)) 3726) 3727 3728; SWAP<option> Rd [ N W B R | 01110111 | Rd ] 3729(dni-cdt-attr 3730 swap "Swap" 3731 ((MACH crisv8,crisv10,crisv32)) 3732 "swap${swapoption} ${Rs}" 3733 (+ swapoption RFIX_SWAP MODE_REGISTER SIZE_FIXED Rd-sfield) 3734 (sequence 3735 ((SI tmps) (SI tmpd)) 3736 (set tmps Rd-sfield) 3737 (set tmpd (cris-swap swapoption tmps)) 3738 (set Rd-sfield tmpd) 3739 (setf-move SI tmpd)) 3740) 3741 3742; ASR.m Rs,Rd [ Rd | 011110mm | Rs ] 3743(dni-cdt-bwd 3744 asrr "Arithmetic shift right register count" 3745 "$Rs,$Rd" 3746 (+ Rd MODE_REGISTER R_ASR Rs) 3747 (.pmacro 3748 (BWD) 3749 (sequence 3750 ((BWD tmpd) (SI cnt1) (SI cnt2)) 3751 (set cnt1 Rs) 3752 (set cnt2 (if SI (ne (and cnt1 32) 0) 31 (and cnt1 31))) 3753 (set tmpd (sra SI (ext SI (trunc BWD Rd)) cnt2)) 3754 (set-subreg-gr BWD (regno Rd) tmpd) 3755 (setf-move BWD tmpd))) 3756) 3757 3758; ASRQ c,Rd [ Rd | 0011101 | c ] 3759(dni-cdt 3760 asrq "Arithmetic shift right quick-immediate count" 3761 "asrq $c,${Rd}" 3762 (+ Rd Q_ASHQ MODE_QUICK_IMMEDIATE (f-b5 1) c) 3763 (sequence 3764 ((SI tmpd)) 3765 (set tmpd (sra Rd c)) 3766 (set Rd tmpd) 3767 (setf-move SI tmpd)) 3768) 3769 3770; LSR.m Rs,Rd [ Rd | 011111mm | Rs ] 3771(dni-cdt-bwd 3772 lsrr "Logical shift right register count" 3773 "$Rs,$Rd" 3774 (+ Rd MODE_REGISTER R_LSR Rs) 3775 (.pmacro 3776 (BWD) 3777 (sequence 3778 ((SI tmpd) (SI cnt)) 3779 (set cnt (and Rs 63)) 3780 (set 3781 tmpd 3782 (if SI (ne (and cnt 32) 0) 3783 0 3784 (srl SI (zext SI (trunc BWD Rd)) (and cnt 31)))) 3785 (set-subreg-gr BWD (regno Rd) tmpd) 3786 (setf-move BWD tmpd))) 3787) 3788 3789; LSRQ c,Rd [ Rd | 0011111 | c ] 3790(dni-cdt 3791 lsrq "Logical shift right quick-immediate count" 3792 "lsrq $c,${Rd}" 3793 (+ Rd Q_LSHQ MODE_QUICK_IMMEDIATE (f-b5 1) c) 3794 (sequence 3795 ((SI tmpd)) 3796 (set tmpd (srl Rd c)) 3797 (set Rd tmpd) 3798 (setf-move SI tmpd)) 3799) 3800 3801; LSL.m Rs,Rd [ Rd | 010011mm | Rs ] 3802(dni-cdt-bwd 3803 lslr "Logical shift left register count" 3804 "$Rs,$Rd" 3805 (+ Rd MODE_REGISTER R_LSL Rs) 3806 (.pmacro 3807 (BWD) 3808 (sequence 3809 ((SI tmpd) (SI cnt)) 3810 (set cnt (and Rs 63)) 3811 (set 3812 tmpd 3813 (if SI (ne (and cnt 32) 0) 3814 0 3815 (sll SI (zext SI (trunc BWD Rd)) (and cnt 31)))) 3816 (set-subreg-gr BWD (regno Rd) tmpd) 3817 (setf-move BWD tmpd))) 3818) 3819 3820; LSLQ c,Rd [ Rd | 0011110 | c ] 3821(dni-cdt 3822 lslq "Logical shift left quick-immediate count" 3823 "lslq $c,${Rd}" 3824 (+ Rd Q_LSHQ MODE_QUICK_IMMEDIATE (f-b5 0) c) 3825 (sequence 3826 ((SI tmpd)) 3827 (set tmpd (sll Rd c)) 3828 (set Rd tmpd) 3829 (setf-move SI tmpd)) 3830) 3831 3832; BTST Rs,Rd [ Rd | 01001111 | Rs ] 3833(dni-cdt 3834 btst "Bit test register number" 3835 "$Rs,$Rd" 3836 (+ Rd MODE_REGISTER RFIX_BTST SIZE_FIXED Rs) 3837 (sequence 3838 ((SI tmpd) (SI cnt)) 3839 (set tmpd (sll Rd (sub 31 (and Rs 31)))) 3840 (setf-move SI tmpd)) 3841) 3842 3843; BTSTQ c,Rd [ Rd | 0011100 | c ] 3844(dni-cdt 3845 btstq "Bit test quick-immediate number" 3846 "btstq $c,${Rd}" 3847 (+ Rd Q_ASHQ MODE_QUICK_IMMEDIATE (f-b5 0) c) 3848 (sequence 3849 ((SI tmpd)) 3850 (set tmpd (sll Rd (sub 31 c))) 3851 (setf-move SI tmpd)) 3852) 3853 3854; SETF <list of flags> [ P U I X | 01011011 | N Z V C ] 3855(dni-cdt 3856 setf "Set condition code flags explicitly" 3857 "setf ${list-of-flags}" 3858 ; The zero-flags case gets flag operands wrong; there's a "_" 3859 ; where there should have been nothing. Also, flags are in 3860 ; assembly code allowed to be specified in any order, which 3861 ; doesn't match the "flagbits" settings. Luckily we don't 3862 ; use this field for assembly. 3863 (+ RFIX_SETF MODE_REGISTER SIZE_FIXED list-of-flags) 3864 (.splice 3865 sequence 3866 ((SI tmp)) 3867 (set tmp list-of-flags) 3868 (.unsplice 3869 (.map 3870 (.pmacro (ccbit) 3871 (if (ne (and tmp (sll 1 (.sym ccbit -bitnumber))) 0) 3872 (set (.sym ccbit bit) 1))) 3873 cris-flagnames)) 3874 (set prefix-set 0) 3875 ; Unless x was specified to be set, set it to 0. 3876 (if (eq (and tmp (sll 1 x-bitnumber)) 0) 3877 (set xbit 0))) 3878) 3879 3880; CLEARF <list of flags> [ P U I X | 01011111 | N Z V C ] 3881(dni-cdt 3882 clearf "Clear condition code flags explicitly" 3883 "clearf ${list-of-flags}" 3884 ; The zero-flags case gets flag operands wrong; there's a "_" 3885 ; where there should have been nothing. Also, flags are in 3886 ; assembly code allowed to be specified in any order, which 3887 ; doesn't match the "flagbits" settings. Luckily we don't 3888 ; use this field for assembly. 3889 (+ RFIX_CLEARF MODE_REGISTER SIZE_FIXED list-of-flags) 3890 (.splice 3891 sequence 3892 ((SI tmp)) 3893 (set tmp list-of-flags) 3894 (.unsplice 3895 (.map 3896 (.pmacro (ccbit) 3897 (if (ne (and tmp (sll 1 (.sym ccbit -bitnumber))) 0) 3898 (set (.sym ccbit bit) 0))) 3899 cris-flagnames)) 3900 (reset-x-p)) 3901) 3902 3903(define-pmacro 3904 (rfe-rfn-guts) 3905 "Common parts of RFE and RFN" 3906 (sequence 3907 ((USI oldccs) (USI samebits) (USI shiftbits) (USI keepmask) (BI p1)) 3908 (set oldccs ccs) 3909 ; Keeping U, S and I in user mode is handled by the CCS setter, so we 3910 ; don't have to bother. Actually Q and M are handled too. The reason 3911 ; to mask those out is to not have them shifted down into the second 3912 ; flags level. 3913 (set keepmask #xc0000000) 3914 (set samebits (and oldccs keepmask)) 3915 ; The P bit has its own equation. 3916 (set shiftbits (and (srl (and oldccs #x3ffdfc00) 10) (inv keepmask))) 3917 (set p1 (ne 0 (and oldccs #x20000))) 3918 (set ccs (or (or samebits shiftbits) 3919 (if SI (and rbit (not p1)) 0 #x80)))) 3920) 3921 3922; RFE [ 0010 10010011 0000 ] 3923(dni-cdt-attr 3924 rfe 3925 "RFE" 3926 (MACH-V32) 3927 "rfe" 3928 (+ (f-dest 2) MODE_INDIRECT INFIX_RFE SIZE_FIXED (f-source 0)) 3929 (rfe-rfn-guts) 3930) 3931 3932; SFE [ 0011 10010011 0000 ] 3933(dni-cdt-attr 3934 sfe 3935 "SFE" 3936 (MACH-V32) 3937 "sfe" 3938 (+ (f-dest 3) MODE_INDIRECT INFIX_SFE SIZE_FIXED (f-source 0)) 3939 (sequence 3940 ((SI oldccs) (SI savemask)) 3941 (set savemask #xc0000000) 3942 (set oldccs ccs) 3943 (set ccs 3944 (or (and savemask oldccs) 3945 (and (inv savemask) (sll oldccs 10))))) 3946) 3947 3948; RFG [ 0100 10010011 0000 ] 3949(dni-cdt-attr 3950 rfg 3951 "RFG" 3952 (MACH-V32) 3953 "rfg" 3954 (+ (f-dest 4) MODE_INDIRECT INFIX_RFG SIZE_FIXED (f-source 0)) 3955 (c-call VOID "@cpu@_rfg_handler" pc) 3956) 3957 3958; RFN [ 0101 10010011 0000 ] 3959(dni-cdt-attr 3960 rfn 3961 "RFN" 3962 (MACH-V32) 3963 "rfn" 3964 (+ (f-dest 5) MODE_INDIRECT INFIX_RFN SIZE_FIXED (f-source 0)) 3965 (sequence () (rfe-rfn-guts) (set mbit 1)) 3966) 3967 3968; HALT [ 1111 10010011 0000 ] 3969(dni-cdt-attr 3970 halt 3971 "HALT" 3972 (MACH-V32) 3973 "halt" 3974 (+ (f-dest 15) MODE_INDIRECT INFIX_HALT SIZE_FIXED (f-source 0)) 3975 (set pc (c-call USI "@cpu@_halt_handler" pc)) 3976) 3977 3978; Bcc o [ cc | 0000 | o ] 3979(dni 3980 bcc-b "bcc byte operand" 3981 () 3982 "b${cc} ${o-pcrel}" 3983 (+ cc QHI_BCC MODE_QUICK_IMMEDIATE o-pcrel) 3984 (sequence 3985 ((BI truthval)) 3986 (set truthval (cris-condition cc)) 3987 3988 ; Amazing as it may seem, there's no simpler way to find out 3989 ; whether a branch is taken or not than to mark it through a kludge 3990 ; like this. 3991 (c-call VOID "@cpu@_branch_taken" pc o-pcrel truthval) 3992 3993 (reset-x-p) 3994 (if truthval 3995 (delay 1 3996 (set pc o-pcrel)))) 3997 (.splice (.unsplice (simplecris-timing)) 3998 (crisv32 (unit u-branch) (unit u-exec))) 3999) 4000(dni 4001 ba-b "ba byte operand" 4002 () 4003 "ba ${o-pcrel}" 4004 (+ (f-dest 14) QHI_BCC MODE_QUICK_IMMEDIATE o-pcrel) 4005 (sequence 4006 () 4007 (reset-x-p) 4008 (delay 1 4009 (set pc o-pcrel))) 4010 ((crisv32 (unit u-jump) (unit u-exec))) 4011) 4012 4013; Bcc [PC+] [ cc | 11011111 1111 ] 4014; (We don't implement the generic for pre-V32 but unused variant 4015; "Bcc [Rn(+)]" where n != 15.) 4016(dni 4017 bcc-w "bcc, word operand" 4018 () 4019 "b${cc} ${o-word-pcrel}" 4020 (+ cc MODE_AUTOINCREMENT INFIX_BCC_M SIZE_FIXED (f-source 15) o-word-pcrel) 4021 (sequence 4022 ((BI truthval)) 4023 (set truthval (cris-condition cc)) 4024 4025 ; Amazing as it may seem, there's no simpler way to find out 4026 ; whether a branch is taken or not than to mark it through a kludge 4027 ; like this. 4028 (c-call VOID "@cpu@_branch_taken" pc o-word-pcrel truthval) 4029 4030 (reset-x-p) 4031 (if truthval 4032 (delay 1 4033 (set pc o-word-pcrel)))) 4034 (.splice 4035 (.unsplice (simplecris-common-timing ((unit u-const16) (unit u-exec)))) 4036 (crisv32 (unit u-const16) (unit u-branch) (unit u-exec))) 4037) 4038(dni 4039 ba-w "ba word operand" 4040 () 4041 "ba ${o-word-pcrel}" 4042 (+ (f-dest 14) MODE_AUTOINCREMENT INFIX_BCC_M SIZE_FIXED (f-source 15) o-word-pcrel) 4043 (sequence 4044 () 4045 (reset-x-p) 4046 (delay 1 4047 (set pc o-word-pcrel))) 4048 (.splice 4049 (.unsplice (simplecris-common-timing ((unit u-const16) (unit u-exec)))) 4050 (crisv32 (unit u-const16) (unit u-jump) (unit u-exec))) 4051) 4052 4053; JAS Rs,Pd [ Pd | 10011011 | Rs ] 4054(dni 4055 jas-r "JAS register" 4056 (MACH-V32) 4057 "jas ${Rs},${Pd}" 4058 (+ Pd MODE_INDIRECT INFIX_JAS_R SIZE_FIXED Rs) 4059 (sequence 4060 () 4061 (reset-x-p) 4062 (if (andif (eq (regno Rs) 1) (eq (regno Pd) 11)) 4063 ; We use this as a trigger; a normally reasonably rare instruction 4064 ; used in the v32 trampoline. See comment at bdapqpc. 4065 ; CGEN-FIXME: can't use (regno srp) [== (regno (reg h-sr 11))] 4066 (c-call VOID "cris_flush_simulator_decode_cache" pc)) 4067 (delay 1 4068 (sequence 4069 () 4070 (set Pd (add SI pc 4)) 4071 (set pc Rs)))) 4072 ((crisv32 (unit u-jump-r) (unit u-jump) (unit u-exec))) 4073) 4074; Same semantics in pre-V32, except no delay-slot. 4075; FIXME: Missing JIRC/JSRC/JBRC. 4076(dni-cdt-attr 4077 jump-r "JUMP/JSR/JIR register" 4078 (MACH-PC) 4079 "jump/jsr/jir ${Rs}" 4080 (+ Pd MODE_INDIRECT INFIX_JUMP_R SIZE_FIXED Rs) 4081 (sequence 4082 () 4083 (set Pd (add SI pc 2)) 4084 (set pc Rs) 4085 (reset-x-p)) 4086) 4087 4088; JAS [PC+],Pd [ Pd | 11011011 1111 ] 4089(dni 4090 jas-c "JAS constant" 4091 (MACH-V32) 4092 "jas ${const32},${Pd}" 4093 (+ Pd MODE_AUTOINCREMENT INFIX_JAS_M SIZE_FIXED (f-source 15) const32) 4094 (sequence 4095 () 4096 (reset-x-p) 4097 (delay 1 4098 (sequence 4099 () 4100 (set Pd (add SI pc 8)) 4101 (set pc const32)))) 4102 ((crisv32 (unit u-const32) (unit u-jump) (unit u-exec))) 4103) 4104 4105; JUMP/JSR/JIR | Special r.| 1 m| 0 1 0 0| 1 1| Source | 4106(dni-cmt-attr 4107 jump-m "JUMP/JSR/JIR memory" 4108 (MACH-PC) 4109 "jump/jsr/jir [${Rs}${inc}]" 4110 (+ Pd INFIX_JUMP_M SIZE_FIXED Rs) 4111 (sequence 4112 () 4113 (set Pd (add SI pc 2)) 4114 (set pc (cris-get-mem SI Rs)) 4115 (reset-x-p)) 4116) 4117(dni-c-SI-attr 4118 jump-c "JUMP/JSR/JIR constant" 4119 (MACH-PC) 4120 "jump/jsr/jir ${const32}" 4121 (+ Pd MODE_AUTOINCREMENT INFIX_JUMP_M SIZE_FIXED (f-source 15) const32) 4122 (sequence 4123 () 4124 (set Pd (add SI pc 6)) 4125 (set pc const32) 4126 (reset-x-p)) 4127) 4128 4129; JUMP Ps [ Ps | 10011111 0000 ] 4130(dni 4131 jump-p "JUMP special register" 4132 (MACH-V32) 4133 "jump ${Ps}" 4134 (+ Ps MODE_INDIRECT INFIX_JUMP_P SIZE_FIXED (f-source 0)) 4135 (sequence 4136 () 4137 (reset-x-p) 4138 (delay 1 4139 (set pc Ps))) 4140 ((crisv32 (unit u-jump-sr) 4141 (unit u-exec))) 4142) 4143 4144; BAS [PC+],Pd [ Pd | 11101011 1111 ] 4145(dni 4146 bas-c "BAS constant" 4147 (MACH-V32) 4148 "bas ${const32},${Pd}" 4149 (+ Pd MODE_AUTOINCREMENT INFIX_BAS SIZE_FIXED (f-source 15) const32-pcrel) 4150 (sequence 4151 () 4152 (reset-x-p) 4153 (delay 1 4154 (sequence 4155 () 4156 (set Pd (add SI pc 8)) 4157 (set pc const32-pcrel)))) 4158 ((crisv32 (unit u-const32) (unit u-jump) (unit u-exec))) 4159) 4160 4161; JASC Rs,Pd [ Pd | 10110011 | Rs ] 4162(dni 4163 jasc-r "JASC register" 4164 (MACH-V32) 4165 "jasc ${Rs},${Pd}" 4166 (+ Pd MODE_INDIRECT INFIX_JASC SIZE_FIXED Rs) 4167 (sequence 4168 () 4169 (reset-x-p) 4170 (delay 1 4171 (sequence 4172 () 4173 (set Pd (add SI pc 8)) 4174 (set pc Rs)))) 4175 ((crisv32 (unit u-jump-r) (unit u-skip4) (unit u-jump) (unit u-exec))) 4176) 4177 4178; JASC [PC+],Pd [ Pd | 11110011 1111 ] 4179(dni 4180 jasc-c "JASC constant" 4181 (MACH-V32) 4182 "jasc ${const32},${Pd}" 4183 (+ Pd MODE_AUTOINCREMENT INFIX_JASC SIZE_FIXED (f-source 15) const32) 4184 (sequence 4185 () 4186 (reset-x-p) 4187 (delay 1 4188 (sequence 4189 () 4190 (set Pd (add SI pc 12)) 4191 (set pc const32)))) 4192 ((crisv32 (unit u-const32) (unit u-skip4) (unit u-jump) (unit u-exec))) 4193) 4194 4195; BASC [PC+],Pd [ Pd | 11101111 1111 ] 4196(dni 4197 basc-c "BASC constant" 4198 (MACH-V32) 4199 "basc ${const32},${Pd}" 4200 (+ Pd MODE_AUTOINCREMENT INFIX_BASC SIZE_FIXED (f-source 15) const32-pcrel) 4201 (sequence 4202 () 4203 (reset-x-p) 4204 (delay 1 4205 (sequence 4206 () 4207 (set Pd (add SI pc 12)) 4208 (set pc const32-pcrel)))) 4209 ((crisv32 (unit u-const32) (unit u-skip4) (unit u-jump) (unit u-exec))) 4210) 4211 4212; BREAK n [ 1110 | 10010011 | n ] 4213 4214(dni-cdt 4215 break "break" 4216 "break $n" 4217 (+ (f-operand2 #xe) MODE_INDIRECT INFIX_BREAK SIZE_FIXED n) 4218 (sequence () (reset-x-p) (set pc (c-call USI "@cpu@_break_handler" n pc))) 4219) 4220 4221; BOUND.m Rs,Rd [ Rd | 010111mm | Rs ] 4222(dni-cdt-bwd 4223 bound-r "Bound register" 4224 "${Rs},${Rd}" 4225 (+ Rd R_BOUND MODE_REGISTER Rs) 4226 (.pmacro 4227 (BWD) 4228 (sequence 4229 ((SI tmpopd) (SI tmpops) (SI newval)) 4230 (set tmpops ((.sym BWD -zext) (trunc BWD Rs))) 4231 (set tmpopd Rd) 4232 (set newval (if SI (ltu tmpops tmpopd) tmpops tmpopd)) 4233 (set Rd newval) 4234 (setf-move SI newval))) 4235) 4236 4237; BOUND.m [Rs],Rd [ Rd | 100111mm | Rs ] 4238; BOUND.m [Rs+],Rd [ Rd | 110111mm | Rs ] 4239(dni-cmt-bwd-attr 4240 bound-m "Bound memory" 4241 (MACH-PRE-V32) 4242 "[${Rs}${inc}],${Rd}" 4243 (+ Rd INDIR_BOUND Rs) 4244 (.pmacro 4245 (BWD) 4246 (sequence 4247 ((SI tmpopd) (SI tmpops) (SI newval)) 4248 (set tmpops ((.sym BWD -zext) (cris-get-mem BWD Rs))) 4249 (set tmpopd Rd) 4250 (set newval (if SI (ltu tmpops tmpopd) tmpops tmpopd)) 4251 (if (andif prefix-set (not inc)) 4252 (set Rs newval) 4253 (set Rd newval)) 4254 (setf-move SI newval))) 4255) 4256 4257; (BOUND.m [PC+],Rd [ Rd | 110111mm | 1111 ]) 4258(dni-c-QI 4259 bound-cb "Bound constant byte" 4260 "bound.b [PC+],${Rd}" 4261 (+ Rd MODE_AUTOINCREMENT INDIR_BOUND SIZE_BYTE (f-source 15) uconst8) 4262 (sequence 4263 ((SI tmpopd) (SI tmpops) (SI newval)) 4264 (set tmpops (zext SI (trunc QI uconst8))) 4265 (set tmpopd Rd) 4266 (set newval (if SI (ltu tmpops tmpopd) tmpops tmpopd)) 4267 (set Rd newval) 4268 (setf-move SI newval)) 4269) 4270(dni-c-HI 4271 bound-cw "Bound constant word" 4272 "bound.w [PC+],${Rd}" 4273 (+ Rd MODE_AUTOINCREMENT INDIR_BOUND SIZE_WORD (f-source 15) uconst16) 4274 (sequence 4275 ((SI tmpopd) (SI tmpops) (SI newval)) 4276 (set tmpops (zext SI uconst16)) 4277 (set tmpopd Rd) 4278 (set newval (if SI (ltu tmpops tmpopd) tmpops tmpopd)) 4279 (set Rd newval) 4280 (setf-move SI newval)) 4281) 4282(dni-c-SI 4283 bound-cd "Bound constant dword" 4284 "bound.d [PC+],${Rd}" 4285 (+ Rd MODE_AUTOINCREMENT INDIR_BOUND SIZE_DWORD (f-source 15) const32) 4286 (sequence 4287 ((SI tmpopd) (SI tmpops) (SI newval)) 4288 (set tmpops const32) 4289 (set tmpopd Rd) 4290 (set newval (if SI (ltu tmpops tmpopd) tmpops tmpopd)) 4291 (set Rd newval) 4292 (setf-move SI newval)) 4293) 4294 4295; Scc Rd [ cc | 01010011 | Rd ] 4296(dni-cdt 4297 scc "scc" 4298 "s${cc} ${Rd-sfield}" 4299 (+ cc MODE_REGISTER RFIX_SCC SIZE_FIXED Rd-sfield) 4300 (sequence 4301 ((BI truthval)) 4302 (set truthval (cris-condition cc)) 4303 (set Rd-sfield (zext SI truthval)) 4304 (reset-x-p)) 4305) 4306 4307; LZ Rs,Rd [ Rd | 01110011 | Rs ] 4308(dni-cdt-attr 4309 lz "lz" 4310 (MACH-V3-UP) 4311 "lz ${Rs},${Rd}" 4312 (+ Rd MODE_REGISTER RFIX_LZ SIZE_FIXED Rs) 4313 (sequence 4314 ((SI tmpd) (SI tmp)) 4315 (set tmp Rs) 4316 (set tmpd 0) 4317 (.splice 4318 sequence 4319 () 4320 (.unsplice 4321 (.map 4322 (.pmacro (n) 4323 (if (ge tmp 0) 4324 (sequence 4325 () 4326 (set tmp (sll tmp 1)) 4327 (set tmpd (add tmpd 1))))) 4328 (.iota 32)))) 4329 (set Rd tmpd) 4330 (setf-move SI tmpd)) 4331) 4332 4333; ADDOQ o,Rs,ACR [ Rs | 0001 | o ] 4334(dni-cdt 4335 addoq "addoq" 4336 "addoq $o,$Rs,ACR" 4337 (+ Rs-dfield MODE_QUICK_IMMEDIATE QHI_ADDOQ o) 4338 (sequence 4339 () 4340 (set prefixreg (add SI Rs-dfield o)) 4341 (set prefix-set 1)) 4342) 4343 4344; (BDAPQ o,PC [ 1111 | 0001 | o ]) 4345; This [PC+I] prefix is used in trampolines. 4346(dni-cdt-attr 4347 bdapqpc "bdapq pc operand" 4348 (MACH-PC UNCOND-CTI) 4349 "bdapq $o,PC" 4350 (+ (f-dest 15) MODE_QUICK_IMMEDIATE QHI_BDAP o) 4351 (sequence 4352 () 4353 (set prefixreg (add SI (add SI pc 2) o)) 4354 (set prefix-set 1) 4355 ; When this *rare* instruction is seen, we're may be about to write 4356 ; into code to be executed soon, *probably* covering addresses decoded 4357 ; and executed before. If the simulator does not implement snooping 4358 ; and automatic decoder flush, it will execute old code. This call 4359 ; is a kludge for such simulators, asking it to abandon such cached 4360 ; information. Anyway, it is hopefully enough to make CGEN-sim not 4361 ; hork on gcc trampolines. 4362 ; We mark this insn as UNCOND-CTI so this insn will end a simulator 4363 ; basic block (the atomic unit of translation). 4364 (c-call VOID "cris_flush_simulator_decode_cache" pc)) 4365) 4366 4367; (BDAP.D [PC+],PC [ 1111 | 11010110 | 1111 ] 4368; This [PC+I] prefix is used for DSO-local jumps in PIC code, together with 4369; move-m-pcplus-p0: "move [pc=pc+N],p0" 4370(dni-c-SI-attr 4371 bdap-32-pc "bdap.d [PC+],PC" 4372 (MACH-PC) 4373 "bdap ${sconst32},PC" 4374 (+ (f-dest 15) MODE_AUTOINCREMENT INDIR_BDAP_M SIZE_DWORD (f-source 15) const32) 4375 (sequence 4376 ((SI newpc) (SI oldpc) (SI offs)) 4377 (set offs const32) 4378 (set oldpc (add SI pc 6)) 4379 (set newpc (add SI oldpc offs)) 4380 (set prefixreg newpc) 4381 (set prefix-set 1)) 4382) 4383 4384; (MOVE [PC+],P0 [ 0000 | 11100011 | 1111 ]) 4385; This insn is used for DSO-local jumps in PIC code. See bdap-32-pc. 4386(dni ; Must not use dni-cmt-* because we force MODE_AUTOINCREMENT. 4387 move-m-pcplus-p0 "move [PC+],P0" 4388 (MACH-PC) 4389 "move [PC+],P0" 4390 (+ (f-dest 0) MODE_AUTOINCREMENT INFIX_MOVE_M_S SIZE_FIXED (f-source 15)) 4391 (if prefix-set 4392 (sequence 4393 ((QI dummy)) 4394 ; We model the memory read, but throw the result away, as the 4395 ; destination register is read-only. We need to assign the result of 4396 ; cris-get-mem though, as CGEN-FIXME: invalid C code will otherwise 4397 ; be generated. 4398 (set dummy (cris-get-mem QI pc)) 4399 (reset-x-p)) 4400 (error "move [PC+],P0 without prefix is not implemented")) 4401 (cris-mem-timing) 4402) 4403 4404; This insn is used in Linux in the form "move [$sp=$sp+16],$p8"; it's 4405; similar to move-m-pcplus-p0 above. The same comments apply here. 4406(dni 4407 move-m-spplus-p8 "move [SP+],P8" 4408 (MACH-PC) 4409 "move [SP+],P8" 4410 (+ (f-dest 8) MODE_AUTOINCREMENT INFIX_MOVE_M_S SIZE_FIXED (f-source 14)) 4411 (if prefix-set 4412 (sequence 4413 ((SI dummy)) 4414 (set dummy (cris-get-mem SI sp)) 4415 (reset-x-p)) 4416 (error "move [SP+],P8 without prefix is not implemented")) 4417 (cris-mem-timing) 4418) 4419 4420; ADDO.m [Rs],Rd,ACR [ Rd | 100101mm | Rs ] 4421; ADDO.m [Rs+],Rd,ACR [ Rd | 110101mm | Rs ] 4422(dni-cmt-bwd 4423 addo-m "addo.m memory" 4424 "[${Rs}${inc}],$Rd,ACR" 4425 (+ Rd INDIR_ADDO Rs) 4426 (.pmacro 4427 (BWD) 4428 (sequence 4429 ((BWD tmps)) 4430 (set tmps (cris-get-mem BWD Rs)) 4431 (set prefixreg (add SI Rd ((.sym BWD -ext) tmps))) 4432 (set prefix-set 1))) 4433) 4434 4435; (ADDO.m [PC+],Rd,ACR [ Rd | 110101mm | 1111 ] 4436(dni-c-QI 4437 addo-cb "addo.b const" 4438 "addo.b [PC+],$Rd,ACR" 4439 (+ Rd MODE_AUTOINCREMENT INDIR_ADDO SIZE_BYTE (f-source 15) sconst8) 4440 (sequence 4441 () 4442 (set prefixreg (add SI Rd (ext SI (trunc QI sconst8)))) 4443 (set prefix-set 1)) 4444) 4445(dni-c-HI 4446 addo-cw "addo.w const" 4447 "addo.w [PC+],$Rd,ACR" 4448 (+ Rd MODE_AUTOINCREMENT INDIR_ADDO SIZE_WORD (f-source 15) sconst16) 4449 (sequence 4450 () 4451 (set prefixreg (add SI Rd (ext SI (trunc HI sconst16)))) 4452 (set prefix-set 1)) 4453) 4454(dni-c-SI 4455 addo-cd "addo.d const" 4456 "addo.d [PC+],$Rd,ACR" 4457 (+ Rd MODE_AUTOINCREMENT INDIR_ADDO SIZE_DWORD (f-source 15) const32) 4458 (sequence 4459 () 4460 (set prefixreg (add SI Rd const32)) 4461 (set prefix-set 1)) 4462) 4463 4464; DIP [] | 0 0 0 0| 1 m| 0 1 0 1| 1 1| Source | 4465 4466(dni-cmt-attr 4467 dip-m "dip mem" 4468 (MACH-PRE-V32) 4469 "dip [${Rs}${inc}]" 4470 (+ (f-dest 0) INFIX_DIP SIZE_FIXED Rs) 4471 (sequence 4472 ((SI tmps)) 4473 (set tmps (cris-get-mem SI Rs)) 4474 (set prefixreg tmps) 4475 (set prefix-set 1)) 4476) 4477 4478; (DIP [] | 0 0 0 0| 1 m| 0 1 0 1| 1 1| Source | ) 4479(dni-c-SI-attr 4480 dip-c "dip [PC+]" 4481 (MACH-PC) 4482 "dip [PC+]" 4483 (+ (f-dest 0) MODE_AUTOINCREMENT INFIX_DIP SIZE_FIXED (f-source 15) const32) 4484 (sequence 4485 () 4486 (set prefixreg const32) 4487 (set prefix-set 1)) 4488) 4489 4490; ADDI Rs.m,Rd,ACR [ Rs | 010101mm | Rd ] 4491; a.k.a. biap 4492(dni-cdt-bwd 4493 addi-acr "addi prefix" 4494 "${Rs-dfield}.m,${Rd-sfield},ACR" 4495 (+ Rd-sfield MODE_REGISTER R_ADDI_ACR Rs-dfield) 4496 (.pmacro 4497 (BWD) 4498 (sequence 4499 () 4500 (set prefixreg (add SI Rd-sfield (mul Rs-dfield (.sym BWD -size)))) 4501 (set prefix-set 1))) 4502) 4503 4504(dni-cdt-bwd-attr 4505 biap-pc "biap.m ${Rs-dfield},PC" 4506 (MACH-PC) 4507 "${Rs-dfield}.m,PC" 4508 (+ Rs-dfield MODE_REGISTER R_ADDI_ACR (f-source 15)) 4509 (.pmacro 4510 (BWD) 4511 (sequence 4512 () 4513 (set prefixreg (add SI (add SI pc 4) (mul Rs-dfield (.sym BWD -size)))) 4514 (set prefix-set 1))) 4515) 4516 4517; FIDXI [Rs] [ 0000 | 11010011 | Rs ] 4518(dni-cdt-attr 4519 fidxi "fidxi [Rs]" 4520 (MACH-V32) 4521 "fidxi [$Rs]" 4522 (+ (f-dest 0) MODE_AUTOINCREMENT INFIX_FIDXI SIZE_FIXED Rs) 4523 (set pc (c-call USI "@cpu@_fidxi_handler" pc Rs)) 4524) 4525 4526; FTAGI [Rs] [ 0001 | 11010011 | Rs ] 4527(dni-cdt-attr 4528 ftagi "ftagi [Rs]" 4529 (MACH-V32) 4530 "fidxi [$Rs]" 4531 (+ (f-dest 1) MODE_AUTOINCREMENT INFIX_FTAGI SIZE_FIXED Rs) 4532 (set pc (c-call USI "@cpu@_ftagi_handler" pc Rs)) 4533) 4534 4535; FIDXD [Rs] [ 0000 | 10101011 | Rs ] 4536(dni-cdt-attr 4537 fidxd "fidxd [Rs]" 4538 (MACH-V32) 4539 "fidxd [$Rs]" 4540 (+ (f-dest 0) MODE_INDIRECT INFIX_FIDXD SIZE_FIXED Rs) 4541 (set pc (c-call USI "@cpu@_fidxd_handler" pc Rs)) 4542) 4543 4544; FTAGD [Rs] [ 0001 | 10101011 | Rs ] 4545(dni-cdt-attr 4546 ftagd "ftagd [Rs]" 4547 (MACH-V32) 4548 "ftagd [$Rs]" 4549 (+ (f-dest 1) MODE_INDIRECT INFIX_FTAGD SIZE_FIXED Rs) 4550 (set pc (c-call USI "@cpu@_ftagd_handler" pc Rs)) 4551) 4552