1/* 2 * This program is free software; you can redistribute it and/or 3 * modify it under the terms of the GNU General Public License as 4 * published by the Free Software Foundation; either version 2 of 5 * the License, or (at your option) any later version. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 * 12 * You should have received a copy of the GNU General Public License 13 * along with this program; if not, write to the Free Software 14 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 15 * MA 02111-1307 USA 16 */ 17#include <stdio.h> 18#include <unistd.h> 19#include <string.h> 20#include <sys/ioctl.h> 21#include <sys/socket.h> 22#include <linux/if.h> 23#include <linux/autoconf.h> 24#include <linux/ethtool.h> 25#include <linux/sockios.h> 26#include <net/if_arp.h> 27#include <shutils.h> 28#include "ra_ioctl.h" 29#include "ra3052.h" 30#include <dual_wan.h> 31 32int esw_fd; 33 34/* 35enum daul_wan_type //-> p0~p4 36{ 37 WLLLL, 38 WLLLW, 39 LWLLW, 40 LLWLW, 41 LLLWW, 42 LLWWW 43}; 44*/ 45 46int 47switch_init(void) 48{ 49 esw_fd = socket(AF_INET, SOCK_DGRAM, 0); 50 if (esw_fd < 0) { 51 perror("socket"); 52 return -1; 53 } 54 return 0; 55} 56 57void 58switch_fini(void) 59{ 60 close(esw_fd); 61} 62 63int ra3052_reg_read(int offset, int *value) 64{ 65 struct ifreq ifr; 66 esw_reg reg; 67 68 if (value == NULL) 69 return -1; 70 reg.off = offset; 71 strncpy(ifr.ifr_name, "eth2", 5); 72 ifr.ifr_data = ® 73 if (-1 == ioctl(esw_fd, RAETH_ESW_REG_READ, &ifr)) { 74 perror("ioctl"); 75 close(esw_fd); 76 return -1; 77 } 78 *value = reg.val; 79 return 0; 80} 81 82int ra3052_reg_write(int offset, int value) 83{ 84 struct ifreq ifr; 85 esw_reg reg; 86 87 reg.off = offset; 88 reg.val = value; 89 strncpy(ifr.ifr_name, "eth2", 5); 90 ifr.ifr_data = ® 91 if (-1 == ioctl(esw_fd, RAETH_ESW_REG_WRITE, &ifr)) { 92 perror("ioctl"); 93 close(esw_fd); 94 exit(0); 95 } 96 return 0; 97} 98 99int 100config_3052(int type) 101{ 102 if(switch_init() < 0) 103 return -1; 104 105 ra3052_reg_write(0x14, 0x405555); 106 ra3052_reg_write(0x50, 0x2001); 107 ra3052_reg_write(0x98, 0x7f3f); 108 ra3052_reg_write(0xe4, 0x3f); // double vlan tag 109 110 /*LLLLW*/ 111 switch(type) 112 { 113 case WLLLL: 114 ra3052_reg_write(0x40, 0x1002); 115 ra3052_reg_write(0x44, 0x1001); 116 ra3052_reg_write(0x48, 0x1001); 117 ra3052_reg_write(0x70, 0xffff417e); 118 break; 119 case WLLLW: 120 ra3052_reg_write(0x40, 0x1002); 121 ra3052_reg_write(0x44, 0x1001); 122 ra3052_reg_write(0x48, 0x1002); 123 ra3052_reg_write(0x70, 0xffff516e); 124 break; 125 case LWLLW: 126 ra3052_reg_write(0x40, 0x2001); 127 ra3052_reg_write(0x44, 0x1001); 128 ra3052_reg_write(0x48, 0x1002); 129 ra3052_reg_write(0x70, 0xffff526d); 130 break; 131 case LLWLW: 132 ra3052_reg_write(0x40, 0x1001); 133 ra3052_reg_write(0x44, 0x1002); 134 ra3052_reg_write(0x48, 0x1002); 135 ra3052_reg_write(0x70, 0xffff546b); 136 break; 137 case LLLWW: 138 ra3052_reg_write(0x40, 0x1001); 139 ra3052_reg_write(0x44, 0x2001); 140 ra3052_reg_write(0x48, 0x1002); 141 ra3052_reg_write(0x70, 0xffff5867); 142 break; 143 case LLWWW: 144 ra3052_reg_write(0x40, 0x1001); 145 ra3052_reg_write(0x44, 0x2002); 146 ra3052_reg_write(0x48, 0x1002); 147 ra3052_reg_write(0x70, 0xffff5c63); 148 break; 149 default: /*LLLLW*/ 150 ra3052_reg_write(0x40, 0x1001); 151 ra3052_reg_write(0x44, 0x1001); 152 ra3052_reg_write(0x48, 0x1002); 153 ra3052_reg_write(0x70, 0xffff506f); 154 } 155 156 switch_fini(); 157 return 0; 158} 159 160 161int 162restore_3052() 163{ 164 if(switch_init() < 0) 165 return -1; 166 167 ra3052_reg_write(0x14, 0x5555); 168 ra3052_reg_write(0x40, 0x1001); 169 ra3052_reg_write(0x44, 0x1001); 170 ra3052_reg_write(0x48, 0x1001); 171 ra3052_reg_write(0x4c, 0x1); 172 ra3052_reg_write(0x50, 0x2001); 173 ra3052_reg_write(0x70, 0xffffffff); 174 ra3052_reg_write(0x98, 0x7f7f); 175 176 switch_fini(); 177 return 0; 178} 179 180