1/* Simulator header for sh. 2 3THIS FILE IS MACHINE GENERATED WITH CGEN. 4 5Copyright 1996-2005 Free Software Foundation, Inc. 6 7This file is part of the GNU simulators. 8 9This program is free software; you can redistribute it and/or modify 10it under the terms of the GNU General Public License as published by 11the Free Software Foundation; either version 3 of the License, or 12(at your option) any later version. 13 14This program is distributed in the hope that it will be useful, 15but WITHOUT ANY WARRANTY; without even the implied warranty of 16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17GNU General Public License for more details. 18 19You should have received a copy of the GNU General Public License 20along with this program. If not, see <http://www.gnu.org/licenses/>. 21 22*/ 23 24#ifndef SH_ARCH_H 25#define SH_ARCH_H 26 27#define TARGET_BIG_ENDIAN 1 28 29/* Enum declaration for model types. */ 30typedef enum model_type { 31 MODEL_SH2A_NOFPU, MODEL_SH2A_FPU, MODEL_SH4_NOFPU, MODEL_SH4 32 , MODEL_SH4A_NOFPU, MODEL_SH4A, MODEL_SH4AL, MODEL_SH5 33 , MODEL_SH5_MEDIA, MODEL_SH2, MODEL_SH2E, MODEL_SH3 34 , MODEL_SH3E, MODEL_MAX 35} MODEL_TYPE; 36 37#define MAX_MODELS ((int) MODEL_MAX) 38 39/* Enum declaration for unit types. */ 40typedef enum unit_type { 41 UNIT_NONE, UNIT_SH2A_NOFPU_U_MULR_GR, UNIT_SH2A_NOFPU_U_MULR, UNIT_SH2A_NOFPU_U_TRAP 42 , UNIT_SH2A_NOFPU_U_WRITE_BACK, UNIT_SH2A_NOFPU_U_USE_MULTIPLY_RESULT, UNIT_SH2A_NOFPU_U_SHIFT, UNIT_SH2A_NOFPU_U_TAS 43 , UNIT_SH2A_NOFPU_U_MULSW, UNIT_SH2A_NOFPU_U_MULL, UNIT_SH2A_NOFPU_U_DMUL, UNIT_SH2A_NOFPU_U_MACL 44 , UNIT_SH2A_NOFPU_U_MACW, UNIT_SH2A_NOFPU_U_MULTIPLY, UNIT_SH2A_NOFPU_U_SET_MAC, UNIT_SH2A_NOFPU_U_LOAD_MAC 45 , UNIT_SH2A_NOFPU_U_LOAD_VBR, UNIT_SH2A_NOFPU_U_LOAD_GBR, UNIT_SH2A_NOFPU_U_USE_GR, UNIT_SH2A_NOFPU_U_LOAD_GR 46 , UNIT_SH2A_NOFPU_U_STC_VBR, UNIT_SH2A_NOFPU_U_LDCL_VBR, UNIT_SH2A_NOFPU_U_LDCL, UNIT_SH2A_NOFPU_U_USE_TBIT 47 , UNIT_SH2A_NOFPU_U_LDC_GBR, UNIT_SH2A_NOFPU_U_LDC_SR, UNIT_SH2A_NOFPU_U_SET_SR_BIT, UNIT_SH2A_NOFPU_U_USE_PR 48 , UNIT_SH2A_NOFPU_U_LOAD_PR, UNIT_SH2A_NOFPU_U_STS_PR, UNIT_SH2A_NOFPU_U_LDS_PR, UNIT_SH2A_NOFPU_U_MEMORY_ACCESS 49 , UNIT_SH2A_NOFPU_U_LOGIC_B, UNIT_SH2A_NOFPU_U_JSR, UNIT_SH2A_NOFPU_U_JMP, UNIT_SH2A_NOFPU_U_BRANCH 50 , UNIT_SH2A_NOFPU_U_SX, UNIT_SH2A_NOFPU_U_EXEC, UNIT_SH2A_FPU_U_USE_DR, UNIT_SH2A_FPU_U_LOAD_DR 51 , UNIT_SH2A_FPU_U_SET_DR, UNIT_SH2A_FPU_U_MULR_GR, UNIT_SH2A_FPU_U_MULR, UNIT_SH2A_FPU_U_FCNV 52 , UNIT_SH2A_FPU_U_FCMP, UNIT_SH2A_FPU_U_FSQRT, UNIT_SH2A_FPU_U_FDIV, UNIT_SH2A_FPU_U_FPU_LOAD_GR 53 , UNIT_SH2A_FPU_U_USE_FPSCR, UNIT_SH2A_FPU_U_LDSL_FPSCR, UNIT_SH2A_FPU_U_LDS_FPSCR, UNIT_SH2A_FPU_U_USE_FPUL 54 , UNIT_SH2A_FPU_U_FLDS_FPUL, UNIT_SH2A_FPU_U_LOAD_FPUL, UNIT_SH2A_FPU_U_SET_FPUL, UNIT_SH2A_FPU_U_FPU_MEMORY_ACCESS 55 , UNIT_SH2A_FPU_U_USE_FR, UNIT_SH2A_FPU_U_SET_FR_0, UNIT_SH2A_FPU_U_SET_FR, UNIT_SH2A_FPU_U_LOAD_FR 56 , UNIT_SH2A_FPU_U_MAYBE_FPU, UNIT_SH2A_FPU_U_FPU, UNIT_SH2A_FPU_U_TRAP, UNIT_SH2A_FPU_U_WRITE_BACK 57 , UNIT_SH2A_FPU_U_USE_MULTIPLY_RESULT, UNIT_SH2A_FPU_U_SHIFT, UNIT_SH2A_FPU_U_TAS, UNIT_SH2A_FPU_U_MULSW 58 , UNIT_SH2A_FPU_U_MULL, UNIT_SH2A_FPU_U_DMUL, UNIT_SH2A_FPU_U_MACL, UNIT_SH2A_FPU_U_MACW 59 , UNIT_SH2A_FPU_U_MULTIPLY, UNIT_SH2A_FPU_U_SET_MAC, UNIT_SH2A_FPU_U_LOAD_MAC, UNIT_SH2A_FPU_U_LOAD_VBR 60 , UNIT_SH2A_FPU_U_LOAD_GBR, UNIT_SH2A_FPU_U_USE_GR, UNIT_SH2A_FPU_U_LOAD_GR, UNIT_SH2A_FPU_U_STC_VBR 61 , UNIT_SH2A_FPU_U_LDCL_VBR, UNIT_SH2A_FPU_U_LDCL, UNIT_SH2A_FPU_U_USE_TBIT, UNIT_SH2A_FPU_U_LDC_GBR 62 , UNIT_SH2A_FPU_U_LDC_SR, UNIT_SH2A_FPU_U_SET_SR_BIT, UNIT_SH2A_FPU_U_USE_PR, UNIT_SH2A_FPU_U_LOAD_PR 63 , UNIT_SH2A_FPU_U_STS_PR, UNIT_SH2A_FPU_U_LDS_PR, UNIT_SH2A_FPU_U_MEMORY_ACCESS, UNIT_SH2A_FPU_U_LOGIC_B 64 , UNIT_SH2A_FPU_U_JSR, UNIT_SH2A_FPU_U_JMP, UNIT_SH2A_FPU_U_BRANCH, UNIT_SH2A_FPU_U_SX 65 , UNIT_SH2A_FPU_U_EXEC, UNIT_SH4_NOFPU_U_OCB, UNIT_SH4_NOFPU_U_MULR_GR, UNIT_SH4_NOFPU_U_MULR 66 , UNIT_SH4_NOFPU_U_TRAP, UNIT_SH4_NOFPU_U_WRITE_BACK, UNIT_SH4_NOFPU_U_USE_MULTIPLY_RESULT, UNIT_SH4_NOFPU_U_SHIFT 67 , UNIT_SH4_NOFPU_U_TAS, UNIT_SH4_NOFPU_U_MULSW, UNIT_SH4_NOFPU_U_MULL, UNIT_SH4_NOFPU_U_DMUL 68 , UNIT_SH4_NOFPU_U_MACL, UNIT_SH4_NOFPU_U_MACW, UNIT_SH4_NOFPU_U_MULTIPLY, UNIT_SH4_NOFPU_U_SET_MAC 69 , UNIT_SH4_NOFPU_U_LOAD_MAC, UNIT_SH4_NOFPU_U_LOAD_VBR, UNIT_SH4_NOFPU_U_LOAD_GBR, UNIT_SH4_NOFPU_U_USE_GR 70 , UNIT_SH4_NOFPU_U_LOAD_GR, UNIT_SH4_NOFPU_U_STC_VBR, UNIT_SH4_NOFPU_U_LDCL_VBR, UNIT_SH4_NOFPU_U_LDCL 71 , UNIT_SH4_NOFPU_U_USE_TBIT, UNIT_SH4_NOFPU_U_LDC_GBR, UNIT_SH4_NOFPU_U_LDC_SR, UNIT_SH4_NOFPU_U_SET_SR_BIT 72 , UNIT_SH4_NOFPU_U_USE_PR, UNIT_SH4_NOFPU_U_LOAD_PR, UNIT_SH4_NOFPU_U_STS_PR, UNIT_SH4_NOFPU_U_LDS_PR 73 , UNIT_SH4_NOFPU_U_MEMORY_ACCESS, UNIT_SH4_NOFPU_U_LOGIC_B, UNIT_SH4_NOFPU_U_JSR, UNIT_SH4_NOFPU_U_JMP 74 , UNIT_SH4_NOFPU_U_BRANCH, UNIT_SH4_NOFPU_U_SX, UNIT_SH4_NOFPU_U_EXEC, UNIT_SH4_U_FTRV 75 , UNIT_SH4_U_FIPR, UNIT_SH4_U_OCB, UNIT_SH4_U_MULR_GR, UNIT_SH4_U_MULR 76 , UNIT_SH4_U_USE_DR, UNIT_SH4_U_LOAD_DR, UNIT_SH4_U_SET_DR, UNIT_SH4_U_FCNV 77 , UNIT_SH4_U_FCMP, UNIT_SH4_U_FSQRT, UNIT_SH4_U_FDIV, UNIT_SH4_U_FPU_LOAD_GR 78 , UNIT_SH4_U_USE_FPSCR, UNIT_SH4_U_LDSL_FPSCR, UNIT_SH4_U_LDS_FPSCR, UNIT_SH4_U_USE_FPUL 79 , UNIT_SH4_U_FLDS_FPUL, UNIT_SH4_U_LOAD_FPUL, UNIT_SH4_U_SET_FPUL, UNIT_SH4_U_FPU_MEMORY_ACCESS 80 , UNIT_SH4_U_USE_FR, UNIT_SH4_U_SET_FR_0, UNIT_SH4_U_SET_FR, UNIT_SH4_U_LOAD_FR 81 , UNIT_SH4_U_MAYBE_FPU, UNIT_SH4_U_FPU, UNIT_SH4_U_TRAP, UNIT_SH4_U_WRITE_BACK 82 , UNIT_SH4_U_USE_MULTIPLY_RESULT, UNIT_SH4_U_SHIFT, UNIT_SH4_U_TAS, UNIT_SH4_U_MULSW 83 , UNIT_SH4_U_MULL, UNIT_SH4_U_DMUL, UNIT_SH4_U_MACL, UNIT_SH4_U_MACW 84 , UNIT_SH4_U_MULTIPLY, UNIT_SH4_U_SET_MAC, UNIT_SH4_U_LOAD_MAC, UNIT_SH4_U_LOAD_VBR 85 , UNIT_SH4_U_LOAD_GBR, UNIT_SH4_U_USE_GR, UNIT_SH4_U_LOAD_GR, UNIT_SH4_U_STC_VBR 86 , UNIT_SH4_U_LDCL_VBR, UNIT_SH4_U_LDCL, UNIT_SH4_U_USE_TBIT, UNIT_SH4_U_LDC_GBR 87 , UNIT_SH4_U_LDC_SR, UNIT_SH4_U_SET_SR_BIT, UNIT_SH4_U_USE_PR, UNIT_SH4_U_LOAD_PR 88 , UNIT_SH4_U_STS_PR, UNIT_SH4_U_LDS_PR, UNIT_SH4_U_MEMORY_ACCESS, UNIT_SH4_U_LOGIC_B 89 , UNIT_SH4_U_JSR, UNIT_SH4_U_JMP, UNIT_SH4_U_BRANCH, UNIT_SH4_U_SX 90 , UNIT_SH4_U_EXEC, UNIT_SH4A_NOFPU_U_OCB, UNIT_SH4A_NOFPU_U_MULR_GR, UNIT_SH4A_NOFPU_U_MULR 91 , UNIT_SH4A_NOFPU_U_FCNV, UNIT_SH4A_NOFPU_U_FCMP, UNIT_SH4A_NOFPU_U_FSQRT, UNIT_SH4A_NOFPU_U_FDIV 92 , UNIT_SH4A_NOFPU_U_FPU_LOAD_GR, UNIT_SH4A_NOFPU_U_USE_FPSCR, UNIT_SH4A_NOFPU_U_LDSL_FPSCR, UNIT_SH4A_NOFPU_U_LDS_FPSCR 93 , UNIT_SH4A_NOFPU_U_USE_FPUL, UNIT_SH4A_NOFPU_U_FLDS_FPUL, UNIT_SH4A_NOFPU_U_LOAD_FPUL, UNIT_SH4A_NOFPU_U_SET_FPUL 94 , UNIT_SH4A_NOFPU_U_FPU_MEMORY_ACCESS, UNIT_SH4A_NOFPU_U_USE_FR, UNIT_SH4A_NOFPU_U_SET_FR_0, UNIT_SH4A_NOFPU_U_SET_FR 95 , UNIT_SH4A_NOFPU_U_LOAD_FR, UNIT_SH4A_NOFPU_U_MAYBE_FPU, UNIT_SH4A_NOFPU_U_FPU, UNIT_SH4A_NOFPU_U_TRAP 96 , UNIT_SH4A_NOFPU_U_WRITE_BACK, UNIT_SH4A_NOFPU_U_USE_MULTIPLY_RESULT, UNIT_SH4A_NOFPU_U_SHIFT, UNIT_SH4A_NOFPU_U_TAS 97 , UNIT_SH4A_NOFPU_U_MULSW, UNIT_SH4A_NOFPU_U_MULL, UNIT_SH4A_NOFPU_U_DMUL, UNIT_SH4A_NOFPU_U_MACL 98 , UNIT_SH4A_NOFPU_U_MACW, UNIT_SH4A_NOFPU_U_MULTIPLY, UNIT_SH4A_NOFPU_U_SET_MAC, UNIT_SH4A_NOFPU_U_LOAD_MAC 99 , UNIT_SH4A_NOFPU_U_LOAD_VBR, UNIT_SH4A_NOFPU_U_LOAD_GBR, UNIT_SH4A_NOFPU_U_USE_GR, UNIT_SH4A_NOFPU_U_LOAD_GR 100 , UNIT_SH4A_NOFPU_U_STC_VBR, UNIT_SH4A_NOFPU_U_LDCL_VBR, UNIT_SH4A_NOFPU_U_LDCL, UNIT_SH4A_NOFPU_U_USE_TBIT 101 , UNIT_SH4A_NOFPU_U_LDC_GBR, UNIT_SH4A_NOFPU_U_LDC_SR, UNIT_SH4A_NOFPU_U_SET_SR_BIT, UNIT_SH4A_NOFPU_U_USE_PR 102 , UNIT_SH4A_NOFPU_U_LOAD_PR, UNIT_SH4A_NOFPU_U_STS_PR, UNIT_SH4A_NOFPU_U_LDS_PR, UNIT_SH4A_NOFPU_U_MEMORY_ACCESS 103 , UNIT_SH4A_NOFPU_U_LOGIC_B, UNIT_SH4A_NOFPU_U_JSR, UNIT_SH4A_NOFPU_U_JMP, UNIT_SH4A_NOFPU_U_BRANCH 104 , UNIT_SH4A_NOFPU_U_SX, UNIT_SH4A_NOFPU_U_EXEC, UNIT_SH4A_U_FTRV, UNIT_SH4A_U_FIPR 105 , UNIT_SH4A_U_OCB, UNIT_SH4A_U_MULR_GR, UNIT_SH4A_U_MULR, UNIT_SH4A_U_FCNV 106 , UNIT_SH4A_U_FCMP, UNIT_SH4A_U_FSQRT, UNIT_SH4A_U_FDIV, UNIT_SH4A_U_FPU_LOAD_GR 107 , UNIT_SH4A_U_USE_FPSCR, UNIT_SH4A_U_LDSL_FPSCR, UNIT_SH4A_U_LDS_FPSCR, UNIT_SH4A_U_USE_FPUL 108 , UNIT_SH4A_U_FLDS_FPUL, UNIT_SH4A_U_LOAD_FPUL, UNIT_SH4A_U_SET_FPUL, UNIT_SH4A_U_FPU_MEMORY_ACCESS 109 , UNIT_SH4A_U_USE_FR, UNIT_SH4A_U_SET_FR_0, UNIT_SH4A_U_SET_FR, UNIT_SH4A_U_LOAD_FR 110 , UNIT_SH4A_U_MAYBE_FPU, UNIT_SH4A_U_FPU, UNIT_SH4A_U_TRAP, UNIT_SH4A_U_WRITE_BACK 111 , UNIT_SH4A_U_USE_MULTIPLY_RESULT, UNIT_SH4A_U_SHIFT, UNIT_SH4A_U_TAS, UNIT_SH4A_U_MULSW 112 , UNIT_SH4A_U_MULL, UNIT_SH4A_U_DMUL, UNIT_SH4A_U_MACL, UNIT_SH4A_U_MACW 113 , UNIT_SH4A_U_MULTIPLY, UNIT_SH4A_U_SET_MAC, UNIT_SH4A_U_LOAD_MAC, UNIT_SH4A_U_LOAD_VBR 114 , UNIT_SH4A_U_LOAD_GBR, UNIT_SH4A_U_USE_GR, UNIT_SH4A_U_LOAD_GR, UNIT_SH4A_U_STC_VBR 115 , UNIT_SH4A_U_LDCL_VBR, UNIT_SH4A_U_LDCL, UNIT_SH4A_U_USE_TBIT, UNIT_SH4A_U_LDC_GBR 116 , UNIT_SH4A_U_LDC_SR, UNIT_SH4A_U_SET_SR_BIT, UNIT_SH4A_U_USE_PR, UNIT_SH4A_U_LOAD_PR 117 , UNIT_SH4A_U_STS_PR, UNIT_SH4A_U_LDS_PR, UNIT_SH4A_U_MEMORY_ACCESS, UNIT_SH4A_U_LOGIC_B 118 , UNIT_SH4A_U_JSR, UNIT_SH4A_U_JMP, UNIT_SH4A_U_BRANCH, UNIT_SH4A_U_SX 119 , UNIT_SH4A_U_EXEC, UNIT_SH4AL_U_OCB, UNIT_SH4AL_U_MULR_GR, UNIT_SH4AL_U_MULR 120 , UNIT_SH4AL_U_FCNV, UNIT_SH4AL_U_FCMP, UNIT_SH4AL_U_FSQRT, UNIT_SH4AL_U_FDIV 121 , UNIT_SH4AL_U_FPU_LOAD_GR, UNIT_SH4AL_U_USE_FPSCR, UNIT_SH4AL_U_LDSL_FPSCR, UNIT_SH4AL_U_LDS_FPSCR 122 , UNIT_SH4AL_U_USE_FPUL, UNIT_SH4AL_U_FLDS_FPUL, UNIT_SH4AL_U_LOAD_FPUL, UNIT_SH4AL_U_SET_FPUL 123 , UNIT_SH4AL_U_FPU_MEMORY_ACCESS, UNIT_SH4AL_U_USE_FR, UNIT_SH4AL_U_SET_FR_0, UNIT_SH4AL_U_SET_FR 124 , UNIT_SH4AL_U_LOAD_FR, UNIT_SH4AL_U_MAYBE_FPU, UNIT_SH4AL_U_FPU, UNIT_SH4AL_U_TRAP 125 , UNIT_SH4AL_U_WRITE_BACK, UNIT_SH4AL_U_USE_MULTIPLY_RESULT, UNIT_SH4AL_U_SHIFT, UNIT_SH4AL_U_TAS 126 , UNIT_SH4AL_U_MULSW, UNIT_SH4AL_U_MULL, UNIT_SH4AL_U_DMUL, UNIT_SH4AL_U_MACL 127 , UNIT_SH4AL_U_MACW, UNIT_SH4AL_U_MULTIPLY, UNIT_SH4AL_U_SET_MAC, UNIT_SH4AL_U_LOAD_MAC 128 , UNIT_SH4AL_U_LOAD_VBR, UNIT_SH4AL_U_LOAD_GBR, UNIT_SH4AL_U_USE_GR, UNIT_SH4AL_U_LOAD_GR 129 , UNIT_SH4AL_U_STC_VBR, UNIT_SH4AL_U_LDCL_VBR, UNIT_SH4AL_U_LDCL, UNIT_SH4AL_U_USE_TBIT 130 , UNIT_SH4AL_U_LDC_GBR, UNIT_SH4AL_U_LDC_SR, UNIT_SH4AL_U_SET_SR_BIT, UNIT_SH4AL_U_USE_PR 131 , UNIT_SH4AL_U_LOAD_PR, UNIT_SH4AL_U_STS_PR, UNIT_SH4AL_U_LDS_PR, UNIT_SH4AL_U_MEMORY_ACCESS 132 , UNIT_SH4AL_U_LOGIC_B, UNIT_SH4AL_U_JSR, UNIT_SH4AL_U_JMP, UNIT_SH4AL_U_BRANCH 133 , UNIT_SH4AL_U_SX, UNIT_SH4AL_U_EXEC, UNIT_SH5_U_FTRV, UNIT_SH5_U_FIPR 134 , UNIT_SH5_U_OCB, UNIT_SH5_U_MULR_GR, UNIT_SH5_U_MULR, UNIT_SH5_U_USE_DR 135 , UNIT_SH5_U_LOAD_DR, UNIT_SH5_U_SET_DR, UNIT_SH5_U_FCNV, UNIT_SH5_U_FCMP 136 , UNIT_SH5_U_FSQRT, UNIT_SH5_U_FDIV, UNIT_SH5_U_FPU_LOAD_GR, UNIT_SH5_U_USE_FPSCR 137 , UNIT_SH5_U_LDSL_FPSCR, UNIT_SH5_U_LDS_FPSCR, UNIT_SH5_U_USE_FPUL, UNIT_SH5_U_FLDS_FPUL 138 , UNIT_SH5_U_LOAD_FPUL, UNIT_SH5_U_SET_FPUL, UNIT_SH5_U_FPU_MEMORY_ACCESS, UNIT_SH5_U_USE_FR 139 , UNIT_SH5_U_SET_FR_0, UNIT_SH5_U_SET_FR, UNIT_SH5_U_LOAD_FR, UNIT_SH5_U_MAYBE_FPU 140 , UNIT_SH5_U_FPU, UNIT_SH5_U_TRAP, UNIT_SH5_U_WRITE_BACK, UNIT_SH5_U_USE_MULTIPLY_RESULT 141 , UNIT_SH5_U_SHIFT, UNIT_SH5_U_TAS, UNIT_SH5_U_MULSW, UNIT_SH5_U_MULL 142 , UNIT_SH5_U_DMUL, UNIT_SH5_U_MACL, UNIT_SH5_U_MACW, UNIT_SH5_U_MULTIPLY 143 , UNIT_SH5_U_SET_MAC, UNIT_SH5_U_LOAD_MAC, UNIT_SH5_U_LOAD_VBR, UNIT_SH5_U_LOAD_GBR 144 , UNIT_SH5_U_USE_GR, UNIT_SH5_U_LOAD_GR, UNIT_SH5_U_STC_VBR, UNIT_SH5_U_LDCL_VBR 145 , UNIT_SH5_U_LDCL, UNIT_SH5_U_USE_TBIT, UNIT_SH5_U_LDC_GBR, UNIT_SH5_U_LDC_SR 146 , UNIT_SH5_U_SET_SR_BIT, UNIT_SH5_U_USE_PR, UNIT_SH5_U_LOAD_PR, UNIT_SH5_U_STS_PR 147 , UNIT_SH5_U_LDS_PR, UNIT_SH5_U_MEMORY_ACCESS, UNIT_SH5_U_LOGIC_B, UNIT_SH5_U_JSR 148 , UNIT_SH5_U_JMP, UNIT_SH5_U_BRANCH, UNIT_SH5_U_SX, UNIT_SH5_U_EXEC 149 , UNIT_SH5_MEDIA_U_PUTCFG, UNIT_SH5_MEDIA_U_GETCFG, UNIT_SH5_MEDIA_U_PT, UNIT_SH5_MEDIA_U_FTRVS 150 , UNIT_SH5_MEDIA_U_FSQRTD, UNIT_SH5_MEDIA_U_FDIVD, UNIT_SH5_MEDIA_U_COND_BRANCH, UNIT_SH5_MEDIA_U_BLINK 151 , UNIT_SH5_MEDIA_U_USE_TR, UNIT_SH5_MEDIA_U_USE_MTRX, UNIT_SH5_MEDIA_U_USE_FV, UNIT_SH5_MEDIA_U_USE_FP 152 , UNIT_SH5_MEDIA_U_LOAD_MTRX, UNIT_SH5_MEDIA_U_LOAD_FV, UNIT_SH5_MEDIA_U_LOAD_FP, UNIT_SH5_MEDIA_U_SET_MTRX 153 , UNIT_SH5_MEDIA_U_SET_FV, UNIT_SH5_MEDIA_U_SET_FP, UNIT_SH5_MEDIA_U_SET_GR, UNIT_SH5_MEDIA_U_FTRV 154 , UNIT_SH5_MEDIA_U_FIPR, UNIT_SH5_MEDIA_U_OCB, UNIT_SH5_MEDIA_U_MULR_GR, UNIT_SH5_MEDIA_U_MULR 155 , UNIT_SH5_MEDIA_U_USE_DR, UNIT_SH5_MEDIA_U_LOAD_DR, UNIT_SH5_MEDIA_U_SET_DR, UNIT_SH5_MEDIA_U_FCNV 156 , UNIT_SH5_MEDIA_U_FCMP, UNIT_SH5_MEDIA_U_FSQRT, UNIT_SH5_MEDIA_U_FDIV, UNIT_SH5_MEDIA_U_FPU_LOAD_GR 157 , UNIT_SH5_MEDIA_U_USE_FPSCR, UNIT_SH5_MEDIA_U_LDSL_FPSCR, UNIT_SH5_MEDIA_U_LDS_FPSCR, UNIT_SH5_MEDIA_U_USE_FPUL 158 , UNIT_SH5_MEDIA_U_FLDS_FPUL, UNIT_SH5_MEDIA_U_LOAD_FPUL, UNIT_SH5_MEDIA_U_SET_FPUL, UNIT_SH5_MEDIA_U_FPU_MEMORY_ACCESS 159 , UNIT_SH5_MEDIA_U_USE_FR, UNIT_SH5_MEDIA_U_SET_FR_0, UNIT_SH5_MEDIA_U_SET_FR, UNIT_SH5_MEDIA_U_LOAD_FR 160 , UNIT_SH5_MEDIA_U_MAYBE_FPU, UNIT_SH5_MEDIA_U_FPU, UNIT_SH5_MEDIA_U_TRAP, UNIT_SH5_MEDIA_U_WRITE_BACK 161 , UNIT_SH5_MEDIA_U_USE_MULTIPLY_RESULT, UNIT_SH5_MEDIA_U_SHIFT, UNIT_SH5_MEDIA_U_TAS, UNIT_SH5_MEDIA_U_MULSW 162 , UNIT_SH5_MEDIA_U_MULL, UNIT_SH5_MEDIA_U_DMUL, UNIT_SH5_MEDIA_U_MACL, UNIT_SH5_MEDIA_U_MACW 163 , UNIT_SH5_MEDIA_U_MULTIPLY, UNIT_SH5_MEDIA_U_SET_MAC, UNIT_SH5_MEDIA_U_LOAD_MAC, UNIT_SH5_MEDIA_U_LOAD_VBR 164 , UNIT_SH5_MEDIA_U_LOAD_GBR, UNIT_SH5_MEDIA_U_USE_GR, UNIT_SH5_MEDIA_U_LOAD_GR, UNIT_SH5_MEDIA_U_STC_VBR 165 , UNIT_SH5_MEDIA_U_LDCL_VBR, UNIT_SH5_MEDIA_U_LDCL, UNIT_SH5_MEDIA_U_USE_TBIT, UNIT_SH5_MEDIA_U_LDC_GBR 166 , UNIT_SH5_MEDIA_U_LDC_SR, UNIT_SH5_MEDIA_U_SET_SR_BIT, UNIT_SH5_MEDIA_U_USE_PR, UNIT_SH5_MEDIA_U_LOAD_PR 167 , UNIT_SH5_MEDIA_U_STS_PR, UNIT_SH5_MEDIA_U_LDS_PR, UNIT_SH5_MEDIA_U_MEMORY_ACCESS, UNIT_SH5_MEDIA_U_LOGIC_B 168 , UNIT_SH5_MEDIA_U_JSR, UNIT_SH5_MEDIA_U_JMP, UNIT_SH5_MEDIA_U_BRANCH, UNIT_SH5_MEDIA_U_SX 169 , UNIT_SH5_MEDIA_U_EXEC, UNIT_SH2_U_TRAP, UNIT_SH2_U_WRITE_BACK, UNIT_SH2_U_USE_MULTIPLY_RESULT 170 , UNIT_SH2_U_SHIFT, UNIT_SH2_U_TAS, UNIT_SH2_U_MULSW, UNIT_SH2_U_MULL 171 , UNIT_SH2_U_DMUL, UNIT_SH2_U_MACL, UNIT_SH2_U_MACW, UNIT_SH2_U_MULTIPLY 172 , UNIT_SH2_U_SET_MAC, UNIT_SH2_U_LOAD_MAC, UNIT_SH2_U_LOAD_VBR, UNIT_SH2_U_LOAD_GBR 173 , UNIT_SH2_U_USE_GR, UNIT_SH2_U_LOAD_GR, UNIT_SH2_U_STC_VBR, UNIT_SH2_U_LDCL_VBR 174 , UNIT_SH2_U_LDCL, UNIT_SH2_U_USE_TBIT, UNIT_SH2_U_LDC_GBR, UNIT_SH2_U_LDC_SR 175 , UNIT_SH2_U_SET_SR_BIT, UNIT_SH2_U_USE_PR, UNIT_SH2_U_LOAD_PR, UNIT_SH2_U_STS_PR 176 , UNIT_SH2_U_LDS_PR, UNIT_SH2_U_MEMORY_ACCESS, UNIT_SH2_U_LOGIC_B, UNIT_SH2_U_JSR 177 , UNIT_SH2_U_JMP, UNIT_SH2_U_BRANCH, UNIT_SH2_U_SX, UNIT_SH2_U_EXEC 178 , UNIT_SH2E_U_FCNV, UNIT_SH2E_U_FCMP, UNIT_SH2E_U_FSQRT, UNIT_SH2E_U_FDIV 179 , UNIT_SH2E_U_FPU_LOAD_GR, UNIT_SH2E_U_USE_FPSCR, UNIT_SH2E_U_LDSL_FPSCR, UNIT_SH2E_U_LDS_FPSCR 180 , UNIT_SH2E_U_USE_FPUL, UNIT_SH2E_U_FLDS_FPUL, UNIT_SH2E_U_LOAD_FPUL, UNIT_SH2E_U_SET_FPUL 181 , UNIT_SH2E_U_FPU_MEMORY_ACCESS, UNIT_SH2E_U_USE_FR, UNIT_SH2E_U_SET_FR_0, UNIT_SH2E_U_SET_FR 182 , UNIT_SH2E_U_LOAD_FR, UNIT_SH2E_U_MAYBE_FPU, UNIT_SH2E_U_FPU, UNIT_SH2E_U_TRAP 183 , UNIT_SH2E_U_WRITE_BACK, UNIT_SH2E_U_USE_MULTIPLY_RESULT, UNIT_SH2E_U_SHIFT, UNIT_SH2E_U_TAS 184 , UNIT_SH2E_U_MULSW, UNIT_SH2E_U_MULL, UNIT_SH2E_U_DMUL, UNIT_SH2E_U_MACL 185 , UNIT_SH2E_U_MACW, UNIT_SH2E_U_MULTIPLY, UNIT_SH2E_U_SET_MAC, UNIT_SH2E_U_LOAD_MAC 186 , UNIT_SH2E_U_LOAD_VBR, UNIT_SH2E_U_LOAD_GBR, UNIT_SH2E_U_USE_GR, UNIT_SH2E_U_LOAD_GR 187 , UNIT_SH2E_U_STC_VBR, UNIT_SH2E_U_LDCL_VBR, UNIT_SH2E_U_LDCL, UNIT_SH2E_U_USE_TBIT 188 , UNIT_SH2E_U_LDC_GBR, UNIT_SH2E_U_LDC_SR, UNIT_SH2E_U_SET_SR_BIT, UNIT_SH2E_U_USE_PR 189 , UNIT_SH2E_U_LOAD_PR, UNIT_SH2E_U_STS_PR, UNIT_SH2E_U_LDS_PR, UNIT_SH2E_U_MEMORY_ACCESS 190 , UNIT_SH2E_U_LOGIC_B, UNIT_SH2E_U_JSR, UNIT_SH2E_U_JMP, UNIT_SH2E_U_BRANCH 191 , UNIT_SH2E_U_SX, UNIT_SH2E_U_EXEC, UNIT_SH3_U_TRAP, UNIT_SH3_U_WRITE_BACK 192 , UNIT_SH3_U_USE_MULTIPLY_RESULT, UNIT_SH3_U_SHIFT, UNIT_SH3_U_TAS, UNIT_SH3_U_MULSW 193 , UNIT_SH3_U_MULL, UNIT_SH3_U_DMUL, UNIT_SH3_U_MACL, UNIT_SH3_U_MACW 194 , UNIT_SH3_U_MULTIPLY, UNIT_SH3_U_SET_MAC, UNIT_SH3_U_LOAD_MAC, UNIT_SH3_U_LOAD_VBR 195 , UNIT_SH3_U_LOAD_GBR, UNIT_SH3_U_USE_GR, UNIT_SH3_U_LOAD_GR, UNIT_SH3_U_STC_VBR 196 , UNIT_SH3_U_LDCL_VBR, UNIT_SH3_U_LDCL, UNIT_SH3_U_USE_TBIT, UNIT_SH3_U_LDC_GBR 197 , UNIT_SH3_U_LDC_SR, UNIT_SH3_U_SET_SR_BIT, UNIT_SH3_U_USE_PR, UNIT_SH3_U_LOAD_PR 198 , UNIT_SH3_U_STS_PR, UNIT_SH3_U_LDS_PR, UNIT_SH3_U_MEMORY_ACCESS, UNIT_SH3_U_LOGIC_B 199 , UNIT_SH3_U_JSR, UNIT_SH3_U_JMP, UNIT_SH3_U_BRANCH, UNIT_SH3_U_SX 200 , UNIT_SH3_U_EXEC, UNIT_SH3E_U_FCNV, UNIT_SH3E_U_FCMP, UNIT_SH3E_U_FSQRT 201 , UNIT_SH3E_U_FDIV, UNIT_SH3E_U_FPU_LOAD_GR, UNIT_SH3E_U_USE_FPSCR, UNIT_SH3E_U_LDSL_FPSCR 202 , UNIT_SH3E_U_LDS_FPSCR, UNIT_SH3E_U_USE_FPUL, UNIT_SH3E_U_FLDS_FPUL, UNIT_SH3E_U_LOAD_FPUL 203 , UNIT_SH3E_U_SET_FPUL, UNIT_SH3E_U_FPU_MEMORY_ACCESS, UNIT_SH3E_U_USE_FR, UNIT_SH3E_U_SET_FR_0 204 , UNIT_SH3E_U_SET_FR, UNIT_SH3E_U_LOAD_FR, UNIT_SH3E_U_MAYBE_FPU, UNIT_SH3E_U_FPU 205 , UNIT_SH3E_U_TRAP, UNIT_SH3E_U_WRITE_BACK, UNIT_SH3E_U_USE_MULTIPLY_RESULT, UNIT_SH3E_U_SHIFT 206 , UNIT_SH3E_U_TAS, UNIT_SH3E_U_MULSW, UNIT_SH3E_U_MULL, UNIT_SH3E_U_DMUL 207 , UNIT_SH3E_U_MACL, UNIT_SH3E_U_MACW, UNIT_SH3E_U_MULTIPLY, UNIT_SH3E_U_SET_MAC 208 , UNIT_SH3E_U_LOAD_MAC, UNIT_SH3E_U_LOAD_VBR, UNIT_SH3E_U_LOAD_GBR, UNIT_SH3E_U_USE_GR 209 , UNIT_SH3E_U_LOAD_GR, UNIT_SH3E_U_STC_VBR, UNIT_SH3E_U_LDCL_VBR, UNIT_SH3E_U_LDCL 210 , UNIT_SH3E_U_USE_TBIT, UNIT_SH3E_U_LDC_GBR, UNIT_SH3E_U_LDC_SR, UNIT_SH3E_U_SET_SR_BIT 211 , UNIT_SH3E_U_USE_PR, UNIT_SH3E_U_LOAD_PR, UNIT_SH3E_U_STS_PR, UNIT_SH3E_U_LDS_PR 212 , UNIT_SH3E_U_MEMORY_ACCESS, UNIT_SH3E_U_LOGIC_B, UNIT_SH3E_U_JSR, UNIT_SH3E_U_JMP 213 , UNIT_SH3E_U_BRANCH, UNIT_SH3E_U_SX, UNIT_SH3E_U_EXEC, UNIT_MAX 214} UNIT_TYPE; 215 216#define MAX_UNITS (9) 217 218#endif /* SH_ARCH_H */ 219