1/* e500 registers, for PSIM, the PowerPC simulator.
2
3   Copyright 2003, 2007 Free Software Foundation, Inc.
4
5   Contributed by Red Hat Inc; developed under contract from Motorola.
6   Written by matthew green <mrg@redhat.com>.
7
8   This file is part of GDB.
9
10   This program is free software; you can redistribute it and/or modify
11   it under the terms of the GNU General Public License as published by
12   the Free Software Foundation; either version 3 of the License, or
13   (at your option) any later version.
14
15   This program is distributed in the hope that it will be useful,
16   but WITHOUT ANY WARRANTY; without even the implied warranty of
17   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18   GNU General Public License for more details.
19
20   You should have received a copy of the GNU General Public License
21   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
22
23/* e500 accumulator.  */
24
25typedef unsigned64 accreg;
26
27enum {
28  msr_e500_spu_enable = BIT(38)
29};
30
31/* E500 regsiters.  */
32
33enum
34  {
35  spefscr_sovh = BIT(32),	/* summary integer overlow (high) */
36  spefscr_ovh = BIT(33),	/* int overflow (high) */
37  spefscr_fgh = BIT(34),	/* FP guard (high) */
38  spefscr_fxh = BIT(35),	/* FP sticky (high) */
39  spefscr_finvh = BIT(36),	/* FP invalid operand (high) */
40  spefscr_fdbzh = BIT(37),	/* FP divide by zero (high) */
41  spefscr_funfh = BIT(38),	/* FP underflow (high) */
42  spefscr_fovfh = BIT(39),	/* FP overflow (high) */
43  spefscr_finxs = BIT(42),	/* FP inexact sticky */
44  spefscr_finvs = BIT(43),	/* FP invalid operand sticky */
45  spefscr_fdbzs = BIT(44),	/* FP divide by zero sticky */
46  spefscr_funfs = BIT(45),	/* FP underflow sticky */
47  spefscr_fovfs = BIT(46),	/* FP overflow sticky */
48  spefscr_mode = BIT(47),	/* SPU MODE (read only) */
49  spefscr_sov = BIT(48),	/* Summary integer overlow (low) */
50  spefscr_ov = BIT(49),		/* int overflow (low) */
51  spefscr_fg = BIT(50),		/* FP guard (low) */
52  spefscr_fx = BIT(51),		/* FP sticky (low) */
53  spefscr_finv = BIT(52),	/* FP invalid operand (low) */
54  spefscr_fdbz = BIT(53),	/* FP divide by zero (low) */
55  spefscr_funf = BIT(54),	/* FP underflow (low) */
56  spefscr_fovf = BIT(55),	/* FP overflow (low) */
57  spefscr_finxe = BIT(57),	/* FP inexact enable */
58  spefscr_finve = BIT(58),	/* FP invalid operand enable */
59  spefscr_fdbze = BIT(59),	/* FP divide by zero enable */
60  spefscr_funfe = BIT(60),	/* FP underflow enable */
61  spefscr_fovfe = BIT(61),	/* FP overflow enable */
62  spefscr_frmc0 = BIT(62),	/* FP round mode control */
63  spefscr_frmc1 = BIT(63),
64  spefscr_frmc = (spefscr_frmc0 | spefscr_frmc1),
65};
66
67struct e500_regs {
68  /* e500 high bits.  */
69  signed_word gprh[32];
70  /* Accumulator */
71  accreg acc;
72};
73
74/* SPE partially visible acculator */
75#define ACC		cpu_registers(processor)->e500.acc
76
77/* e500 register high bits */
78#define GPRH(N)		cpu_registers(processor)->e500.gprh[N]
79
80/* e500 unified vector register
81   We need to cast the gpr value to an unsigned type so that it
82   doesn't get sign-extended when it's or-ed with a 64-bit value; that
83   would wipe out the upper 32 bits of the register's value.  */
84#define EVR(N)		((((unsigned64)GPRH(N)) << 32) | (unsigned32) GPR(N))
85