1/* This file is part of the program psim. 2 3 Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au> 4 5 This program is free software; you can redistribute it and/or modify 6 it under the terms of the GNU General Public License as published by 7 the Free Software Foundation; either version 2 of the License, or 8 (at your option) any later version. 9 10 This program is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 GNU General Public License for more details. 14 15 You should have received a copy of the GNU General Public License 16 along with this program; if not, write to the Free Software 17 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 18 19 */ 20 21 22#ifndef _CPU_H_ 23#define _CPU_H_ 24 25#include "basics.h" 26#include "registers.h" 27#include "device.h" 28#include "corefile.h" 29#include "vm.h" 30#include "events.h" 31#include "interrupts.h" 32#include "psim.h" 33#include "idecode.h" 34#include "itable.h" 35#include "os_emul.h" 36#include "mon.h" 37#include "model.h" 38 39#ifndef CONST_ATTRIBUTE 40#define CONST_ATTRIBUTE __attribute__((__const__)) 41#endif 42 43/* typedef struct _cpu cpu; 44 45 Declared in basics.h because it is used opaquely throughout the 46 code */ 47 48 49/* Create a cpu object */ 50 51INLINE_CPU\ 52(cpu *) cpu_create 53(psim *system, 54 core *memory, 55 cpu_mon *monitor, 56 os_emul *cpu_emulation, 57 int cpu_nr); 58 59INLINE_CPU\ 60(void) cpu_init 61(cpu *processor); 62 63/* Find our way home */ 64 65INLINE_CPU\ 66(psim *) cpu_system 67(cpu *processor) CONST_ATTRIBUTE; 68 69INLINE_CPU\ 70(cpu_mon *) cpu_monitor 71(cpu *processor) CONST_ATTRIBUTE; 72 73INLINE_CPU\ 74(os_emul *) cpu_os_emulation 75(cpu *processor); 76 77INLINE_CPU\ 78(int) cpu_nr 79(cpu *processor) CONST_ATTRIBUTE; 80 81 82/* manipulate the processors program counter and execution state. 83 84 The program counter is not included in the register file. Instead 85 it is extracted and then later restored (set, reset, halt). This 86 is to give the user of the cpu (and the compiler) the chance to 87 minimize the need to load/store the cpu's PC value. (Especially in 88 the case of a single processor) */ 89 90INLINE_CPU\ 91(void) cpu_set_program_counter 92(cpu *processor, 93 unsigned_word new_program_counter); 94 95INLINE_CPU\ 96(unsigned_word) cpu_get_program_counter 97(cpu *processor); 98 99INLINE_CPU\ 100(void) cpu_restart 101(cpu *processor, 102 unsigned_word nia); 103 104INLINE_CPU\ 105(void) cpu_halt 106(cpu *processor, 107 unsigned_word nia, 108 stop_reason reason, 109 int signal); 110 111EXTERN_CPU\ 112(void) cpu_error 113(cpu *processor, 114 unsigned_word cia, 115 const char *fmt, 116 ...) __attribute__ ((format (printf, 3, 4))); 117 118 119/* The processors local concept of time */ 120 121INLINE_CPU\ 122(signed64) cpu_get_time_base 123(cpu *processor); 124 125INLINE_CPU\ 126(void) cpu_set_time_base 127(cpu *processor, 128 signed64 time_base); 129 130INLINE_CPU\ 131(signed32) cpu_get_decrementer 132(cpu *processor); 133 134INLINE_CPU\ 135(void) cpu_set_decrementer 136(cpu *processor, 137 signed32 decrementer); 138 139 140#if WITH_IDECODE_CACHE_SIZE 141/* Return the cache entry that matches the given CIA. No guarentee 142 that the cache entry actually contains the instruction for that 143 address */ 144 145INLINE_CPU\ 146(idecode_cache) *cpu_icache_entry 147(cpu *processor, 148 unsigned_word cia); 149 150INLINE_CPU\ 151(void) cpu_flush_icache 152(cpu *processor); 153#endif 154 155 156/* reveal the processors VM: 157 158 At first sight it may seem better to, instead of exposing the cpu's 159 inner vm maps, to have the cpu its self provide memory manipulation 160 functions. (eg cpu_instruction_fetch() cpu_data_read_4()) 161 162 Unfortunatly in addition to these functions is the need (for the 163 debugger) to be able to read/write to memory in ways that violate 164 the vm protection (eg store breakpoint instruction in the 165 instruction map). */ 166 167INLINE_CPU\ 168(vm_data_map *) cpu_data_map 169(cpu *processor); 170 171INLINE_CPU\ 172(vm_instruction_map *) cpu_instruction_map 173(cpu *processor); 174 175INLINE_CPU\ 176(void) cpu_page_tlb_invalidate_entry 177(cpu *processor, 178 unsigned_word ea); 179 180INLINE_CPU\ 181(void) cpu_page_tlb_invalidate_all 182(cpu *processor); 183 184 185/* reveal the processors interrupt state */ 186 187INLINE_CPU\ 188(interrupts *) cpu_interrupts 189(cpu *processor); 190 191 192/* grant access to the reservation information */ 193 194typedef struct _memory_reservation { 195 int valid; 196 unsigned_word addr; 197 unsigned_word data; 198} memory_reservation; 199 200INLINE_CPU\ 201(memory_reservation *) cpu_reservation 202(cpu *processor); 203 204 205/* Registers: 206 207 This model exploits the PowerPC's requirement for a synchronization 208 to occure after (or before) the update of any context controlling 209 register. All context sync points must call the sync function 210 below to when ever a synchronization point is reached */ 211 212INLINE_CPU\ 213(registers *) cpu_registers 214(cpu *processor) CONST_ATTRIBUTE; 215 216INLINE_CPU\ 217(void) cpu_synchronize_context 218(cpu *processor, 219 unsigned_word cia); 220 221#define IS_PROBLEM_STATE(PROCESSOR) \ 222(CURRENT_ENVIRONMENT == OPERATING_ENVIRONMENT \ 223 ? (cpu_registers(PROCESSOR)->msr & msr_problem_state) \ 224 : 1) 225 226#define IS_64BIT_MODE(PROCESSOR) \ 227(WITH_TARGET_WORD_BITSIZE == 64 \ 228 ? (CURRENT_ENVIRONMENT == OPERATING_ENVIRONMENT \ 229 ? (cpu_registers(PROCESSOR)->msr & msr_64bit_mode) \ 230 : 1) \ 231 : 0) 232 233#define IS_FP_AVAILABLE(PROCESSOR) \ 234(CURRENT_ENVIRONMENT == OPERATING_ENVIRONMENT \ 235 ? (cpu_registers(PROCESSOR)->msr & msr_floating_point_available) \ 236 : 1) 237 238 239 240INLINE_CPU\ 241(void) cpu_print_info 242(cpu *processor, 243 int verbose); 244 245INLINE_CPU\ 246(model_data *) cpu_model 247(cpu *processor) CONST_ATTRIBUTE; 248 249 250#if (CPU_INLINE & INCLUDE_MODULE) 251# include "cpu.c" 252#endif 253 254#endif 255