1ChangeLog 2 3See the ChangeLog file looking for lines taged with the word FIXME. 4 5 6COREFILE.C: 7 8The implementation of corefile.c (defined by corefile.h) isn't the 9best. It is intended to be functionaly correct rather than fast. One 10option being considered is to add a data cache to reduce the overhead 11of the most common case of data read/writes. 12 13 14VEA: 15 16Missing VEA system calls. 17 18ppc-instructions: 19 20Missing or commented out instructions. 21 22 2364bit: 24 2564bit target untested. 64bit host broken. For instance use of scanf 26"%x", &long long. 27 28 29 30hw_*.c: 31 32Better and more devices. 33 34PORTABILITY: 35 36(Notes taken from Michael Meissner): Heavy use of the ## operator - 37fix using the clasic X/**/Y hack; Use of the signed keyword. In 38particular, signed char has no analogue in classic C (though most 39implementations of classic C use signed chars); Use of long long which 40restricts the target compiler to be GCC. 41 42 43TRACING: 44 45debug.c: Macro's should be extended to include: 46 47 IS_*TRACE: True if tracing enabled 48 *TRACE_PREFIX: Outputs just the prefix line 49 50hw_trace.c: Flush, replace with a psim_set_tracing or some 51 such program. 52 53 54CIA/NIA: 55 56Replace with functions to return/increment the CIA? 57 58 59 60SMP & GDB: 61 62GDB doesn't understand SMP! 63 64 65 66 67OVERALL STRUCTURE: 68 69A new file pstruct.h is to be created that contains a single flat data 70structure containing: 71 72 pstruct { 73 events; 74 core; 75 processor[nr_cpus]; 76 monitor; 77 devices; 78 trace; 79 } 80 81The CPU's structure, in turn would contain the VM sub structures. 82 83When SMP==0, everything would have PSTRUCT passed. In SMP mode, 84however, there are two choices: PSTRUCT + CPU_NR or PROCESSOR. I 85suspect the latter is better. 86 87It is believed that this would significantly improve performance (at 88the price of reduced control over object scope). 89 90 91 92 93IGEN: 94 95Igen at present can't do the following: 96 97 o duplication is an all or nothing afair. 98 99 It should be configurable according to 100 the instruction or the sub-table. 101 102 103 o Due to the naming, only a single generated 104 simulator can be included in a program. 105 106 IGEN should be able to generate multiple 107 engines that can all be included in a program 108 109 o handle alternate architectures. 110 111 112 o Igen should support the generation of a 113 disasembler and posibly an assembler. 114 115 I suggest that the table be extended to 116 include, for each instruction, additional 117 lines describing the extual format of the 118 instruction. 119 120 One possible format is: 121 122 "mtlr %RS":SPR.something 123 "mtspr %SPR, %RS" 124