1/* gdb.c --- sim interface to GDB.
2
3Copyright (C) 2005, 2007 Free Software Foundation, Inc.
4Contributed by Red Hat, Inc.
5
6This file is part of the GNU simulators.
7
8This program is free software; you can redistribute it and/or modify
9it under the terms of the GNU General Public License as published by
10the Free Software Foundation; either version 3 of the License, or
11(at your option) any later version.
12
13This program is distributed in the hope that it will be useful,
14but WITHOUT ANY WARRANTY; without even the implied warranty of
15MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16GNU General Public License for more details.
17
18You should have received a copy of the GNU General Public License
19along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
20
21
22#include <stdio.h>
23#include <assert.h>
24#include <signal.h>
25#include <string.h>
26#include <ctype.h>
27
28#include "ansidecl.h"
29#include "gdb/callback.h"
30#include "gdb/remote-sim.h"
31#include "gdb/signals.h"
32#include "gdb/sim-m32c.h"
33
34#include "cpu.h"
35#include "mem.h"
36#include "load.h"
37#include "syscalls.h"
38
39/* I don't want to wrap up all the minisim's data structures in an
40   object and pass that around.  That'd be a big change, and neither
41   GDB nor run needs that ability.
42
43   So we just have one instance, that lives in global variables, and
44   each time we open it, we re-initialize it.  */
45struct sim_state
46{
47  const char *message;
48};
49
50static struct sim_state the_minisim = {
51  "This is the sole m32c minisim instance.  See libsim.a's global variables."
52};
53
54static int open;
55
56SIM_DESC
57sim_open (SIM_OPEN_KIND kind,
58	  struct host_callback_struct *callback,
59	  struct bfd *abfd, char **argv)
60{
61  if (open)
62    fprintf (stderr, "m32c minisim: re-opened sim\n");
63
64  /* The 'run' interface doesn't use this function, so we don't care
65     about KIND; it's always SIM_OPEN_DEBUG.  */
66  if (kind != SIM_OPEN_DEBUG)
67    fprintf (stderr, "m32c minisim: sim_open KIND != SIM_OPEN_DEBUG: %d\n",
68	     kind);
69
70  if (abfd)
71    m32c_set_mach (bfd_get_mach (abfd));
72
73  /* We can use ABFD, if non-NULL to select the appropriate
74     architecture.  But we only support the r8c right now.  */
75
76  set_callbacks (callback);
77
78  /* We don't expect any command-line arguments.  */
79
80  init_mem ();
81  init_regs ();
82
83  open = 1;
84  return &the_minisim;
85}
86
87static void
88check_desc (SIM_DESC sd)
89{
90  if (sd != &the_minisim)
91    fprintf (stderr, "m32c minisim: desc != &the_minisim\n");
92}
93
94void
95sim_close (SIM_DESC sd, int quitting)
96{
97  check_desc (sd);
98
99  /* Not much to do.  At least free up our memory.  */
100  init_mem ();
101
102  open = 0;
103}
104
105static bfd *
106open_objfile (const char *filename)
107{
108  bfd *prog = bfd_openr (filename, 0);
109
110  if (!prog)
111    {
112      fprintf (stderr, "Can't read %s\n", filename);
113      return 0;
114    }
115
116  if (!bfd_check_format (prog, bfd_object))
117    {
118      fprintf (stderr, "%s not a m32c program\n", filename);
119      return 0;
120    }
121
122  return prog;
123}
124
125
126SIM_RC
127sim_load (SIM_DESC sd, char *prog, struct bfd *abfd, int from_tty)
128{
129  check_desc (sd);
130
131  if (!abfd)
132    abfd = open_objfile (prog);
133  if (!abfd)
134    return SIM_RC_FAIL;
135
136  m32c_load (abfd);
137
138  return SIM_RC_OK;
139}
140
141SIM_RC
142sim_create_inferior (SIM_DESC sd, struct bfd *abfd, char **argv, char **env)
143{
144  check_desc (sd);
145
146  if (abfd)
147    m32c_load (abfd);
148
149  return SIM_RC_OK;
150}
151
152int
153sim_read (SIM_DESC sd, SIM_ADDR mem, unsigned char *buf, int length)
154{
155  check_desc (sd);
156
157  if (mem == 0)
158    return 0;
159
160  mem_get_blk ((int) mem, buf, length);
161
162  return length;
163}
164
165int
166sim_write (SIM_DESC sd, SIM_ADDR mem, unsigned char *buf, int length)
167{
168  check_desc (sd);
169
170  mem_put_blk ((int) mem, buf, length);
171
172  return length;
173}
174
175
176/* Read the LENGTH bytes at BUF as an little-endian value.  */
177static DI
178get_le (unsigned char *buf, int length)
179{
180  DI acc = 0;
181  while (--length >= 0)
182    acc = (acc << 8) + buf[length];
183
184  return acc;
185}
186
187/* Store VAL as a little-endian value in the LENGTH bytes at BUF.  */
188static void
189put_le (unsigned char *buf, int length, DI val)
190{
191  int i;
192
193  for (i = 0; i < length; i++)
194    {
195      buf[i] = val & 0xff;
196      val >>= 8;
197    }
198}
199
200static int
201check_regno (enum m32c_sim_reg regno)
202{
203  return 0 <= regno && regno < m32c_sim_reg_num_regs;
204}
205
206static size_t
207mask_size (int addr_mask)
208{
209  switch (addr_mask)
210    {
211    case 0xffff:
212      return 2;
213    case 0xfffff:
214    case 0xffffff:
215      return 3;
216    default:
217      fprintf (stderr,
218	       "m32c minisim: addr_mask_size: unexpected mask 0x%x\n",
219	       addr_mask);
220      return sizeof (addr_mask);
221    }
222}
223
224static size_t
225reg_size (enum m32c_sim_reg regno)
226{
227  switch (regno)
228    {
229    case m32c_sim_reg_r0_bank0:
230    case m32c_sim_reg_r1_bank0:
231    case m32c_sim_reg_r2_bank0:
232    case m32c_sim_reg_r3_bank0:
233    case m32c_sim_reg_r0_bank1:
234    case m32c_sim_reg_r1_bank1:
235    case m32c_sim_reg_r2_bank1:
236    case m32c_sim_reg_r3_bank1:
237    case m32c_sim_reg_flg:
238    case m32c_sim_reg_svf:
239      return 2;
240
241    case m32c_sim_reg_a0_bank0:
242    case m32c_sim_reg_a1_bank0:
243    case m32c_sim_reg_fb_bank0:
244    case m32c_sim_reg_sb_bank0:
245    case m32c_sim_reg_a0_bank1:
246    case m32c_sim_reg_a1_bank1:
247    case m32c_sim_reg_fb_bank1:
248    case m32c_sim_reg_sb_bank1:
249    case m32c_sim_reg_usp:
250    case m32c_sim_reg_isp:
251      return mask_size (addr_mask);
252
253    case m32c_sim_reg_pc:
254    case m32c_sim_reg_intb:
255    case m32c_sim_reg_svp:
256    case m32c_sim_reg_vct:
257      return mask_size (membus_mask);
258
259    case m32c_sim_reg_dmd0:
260    case m32c_sim_reg_dmd1:
261      return 1;
262
263    case m32c_sim_reg_dct0:
264    case m32c_sim_reg_dct1:
265    case m32c_sim_reg_drc0:
266    case m32c_sim_reg_drc1:
267      return 2;
268
269    case m32c_sim_reg_dma0:
270    case m32c_sim_reg_dma1:
271    case m32c_sim_reg_dsa0:
272    case m32c_sim_reg_dsa1:
273    case m32c_sim_reg_dra0:
274    case m32c_sim_reg_dra1:
275      return 3;
276
277    default:
278      fprintf (stderr, "m32c minisim: unrecognized register number: %d\n",
279	       regno);
280      return -1;
281    }
282}
283
284int
285sim_fetch_register (SIM_DESC sd, int regno, unsigned char *buf, int length)
286{
287  size_t size;
288
289  check_desc (sd);
290
291  if (!check_regno (regno))
292    return 0;
293
294  size = reg_size (regno);
295  if (length == size)
296    {
297      DI val;
298
299      switch (regno)
300	{
301	case m32c_sim_reg_r0_bank0:
302	  val = regs.r[0].r_r0;
303	  break;
304	case m32c_sim_reg_r1_bank0:
305	  val = regs.r[0].r_r1;
306	  break;
307	case m32c_sim_reg_r2_bank0:
308	  val = regs.r[0].r_r2;
309	  break;
310	case m32c_sim_reg_r3_bank0:
311	  val = regs.r[0].r_r3;
312	  break;
313	case m32c_sim_reg_a0_bank0:
314	  val = regs.r[0].r_a0;
315	  break;
316	case m32c_sim_reg_a1_bank0:
317	  val = regs.r[0].r_a1;
318	  break;
319	case m32c_sim_reg_fb_bank0:
320	  val = regs.r[0].r_fb;
321	  break;
322	case m32c_sim_reg_sb_bank0:
323	  val = regs.r[0].r_sb;
324	  break;
325	case m32c_sim_reg_r0_bank1:
326	  val = regs.r[1].r_r0;
327	  break;
328	case m32c_sim_reg_r1_bank1:
329	  val = regs.r[1].r_r1;
330	  break;
331	case m32c_sim_reg_r2_bank1:
332	  val = regs.r[1].r_r2;
333	  break;
334	case m32c_sim_reg_r3_bank1:
335	  val = regs.r[1].r_r3;
336	  break;
337	case m32c_sim_reg_a0_bank1:
338	  val = regs.r[1].r_a0;
339	  break;
340	case m32c_sim_reg_a1_bank1:
341	  val = regs.r[1].r_a1;
342	  break;
343	case m32c_sim_reg_fb_bank1:
344	  val = regs.r[1].r_fb;
345	  break;
346	case m32c_sim_reg_sb_bank1:
347	  val = regs.r[1].r_sb;
348	  break;
349
350	case m32c_sim_reg_usp:
351	  val = regs.r_usp;
352	  break;
353	case m32c_sim_reg_isp:
354	  val = regs.r_isp;
355	  break;
356	case m32c_sim_reg_pc:
357	  val = regs.r_pc;
358	  break;
359	case m32c_sim_reg_intb:
360	  val = regs.r_intbl * 65536 + regs.r_intbl;
361	  break;
362	case m32c_sim_reg_flg:
363	  val = regs.r_flags;
364	  break;
365
366	  /* These registers aren't implemented by the minisim.  */
367	case m32c_sim_reg_svf:
368	case m32c_sim_reg_svp:
369	case m32c_sim_reg_vct:
370	case m32c_sim_reg_dmd0:
371	case m32c_sim_reg_dmd1:
372	case m32c_sim_reg_dct0:
373	case m32c_sim_reg_dct1:
374	case m32c_sim_reg_drc0:
375	case m32c_sim_reg_drc1:
376	case m32c_sim_reg_dma0:
377	case m32c_sim_reg_dma1:
378	case m32c_sim_reg_dsa0:
379	case m32c_sim_reg_dsa1:
380	case m32c_sim_reg_dra0:
381	case m32c_sim_reg_dra1:
382	  return 0;
383
384	default:
385	  fprintf (stderr, "m32c minisim: unrecognized register number: %d\n",
386		   regno);
387	  return -1;
388	}
389
390      put_le (buf, length, val);
391    }
392
393  return size;
394}
395
396int
397sim_store_register (SIM_DESC sd, int regno, unsigned char *buf, int length)
398{
399  size_t size;
400
401  check_desc (sd);
402
403  if (!check_regno (regno))
404    return 0;
405
406  size = reg_size (regno);
407
408  if (length == size)
409    {
410      DI val = get_le (buf, length);
411
412      switch (regno)
413	{
414	case m32c_sim_reg_r0_bank0:
415	  regs.r[0].r_r0 = val & 0xffff;
416	  break;
417	case m32c_sim_reg_r1_bank0:
418	  regs.r[0].r_r1 = val & 0xffff;
419	  break;
420	case m32c_sim_reg_r2_bank0:
421	  regs.r[0].r_r2 = val & 0xffff;
422	  break;
423	case m32c_sim_reg_r3_bank0:
424	  regs.r[0].r_r3 = val & 0xffff;
425	  break;
426	case m32c_sim_reg_a0_bank0:
427	  regs.r[0].r_a0 = val & addr_mask;
428	  break;
429	case m32c_sim_reg_a1_bank0:
430	  regs.r[0].r_a1 = val & addr_mask;
431	  break;
432	case m32c_sim_reg_fb_bank0:
433	  regs.r[0].r_fb = val & addr_mask;
434	  break;
435	case m32c_sim_reg_sb_bank0:
436	  regs.r[0].r_sb = val & addr_mask;
437	  break;
438	case m32c_sim_reg_r0_bank1:
439	  regs.r[1].r_r0 = val & 0xffff;
440	  break;
441	case m32c_sim_reg_r1_bank1:
442	  regs.r[1].r_r1 = val & 0xffff;
443	  break;
444	case m32c_sim_reg_r2_bank1:
445	  regs.r[1].r_r2 = val & 0xffff;
446	  break;
447	case m32c_sim_reg_r3_bank1:
448	  regs.r[1].r_r3 = val & 0xffff;
449	  break;
450	case m32c_sim_reg_a0_bank1:
451	  regs.r[1].r_a0 = val & addr_mask;
452	  break;
453	case m32c_sim_reg_a1_bank1:
454	  regs.r[1].r_a1 = val & addr_mask;
455	  break;
456	case m32c_sim_reg_fb_bank1:
457	  regs.r[1].r_fb = val & addr_mask;
458	  break;
459	case m32c_sim_reg_sb_bank1:
460	  regs.r[1].r_sb = val & addr_mask;
461	  break;
462
463	case m32c_sim_reg_usp:
464	  regs.r_usp = val & addr_mask;
465	  break;
466	case m32c_sim_reg_isp:
467	  regs.r_isp = val & addr_mask;
468	  break;
469	case m32c_sim_reg_pc:
470	  regs.r_pc = val & membus_mask;
471	  break;
472	case m32c_sim_reg_intb:
473	  regs.r_intbl = (val & membus_mask) & 0xffff;
474	  regs.r_intbh = (val & membus_mask) >> 16;
475	  break;
476	case m32c_sim_reg_flg:
477	  regs.r_flags = val & 0xffff;
478	  break;
479
480	  /* These registers aren't implemented by the minisim.  */
481	case m32c_sim_reg_svf:
482	case m32c_sim_reg_svp:
483	case m32c_sim_reg_vct:
484	case m32c_sim_reg_dmd0:
485	case m32c_sim_reg_dmd1:
486	case m32c_sim_reg_dct0:
487	case m32c_sim_reg_dct1:
488	case m32c_sim_reg_drc0:
489	case m32c_sim_reg_drc1:
490	case m32c_sim_reg_dma0:
491	case m32c_sim_reg_dma1:
492	case m32c_sim_reg_dsa0:
493	case m32c_sim_reg_dsa1:
494	case m32c_sim_reg_dra0:
495	case m32c_sim_reg_dra1:
496	  return 0;
497
498	default:
499	  fprintf (stderr, "m32c minisim: unrecognized register number: %d\n",
500		   regno);
501	  return -1;
502	}
503    }
504
505  return size;
506}
507
508void
509sim_info (SIM_DESC sd, int verbose)
510{
511  check_desc (sd);
512
513  printf ("The m32c minisim doesn't collect any statistics.\n");
514}
515
516static volatile int stop;
517static enum sim_stop reason;
518int siggnal;
519
520
521/* Given a signal number used by the M32C bsp (that is, newlib),
522   return a host signal number.  (Oddly, the gdb/sim interface uses
523   host signal numbers...)  */
524int
525m32c_signal_to_host (int m32c)
526{
527  switch (m32c)
528    {
529    case 4:
530#ifdef SIGILL
531      return SIGILL;
532#else
533      return SIGSEGV;
534#endif
535
536    case 5:
537      return SIGTRAP;
538
539    case 10:
540#ifdef SIGBUS
541      return SIGBUS;
542#else
543      return SIGSEGV;
544#endif
545
546    case 11:
547      return SIGSEGV;
548
549    case 24:
550#ifdef SIGXCPU
551      return SIGXCPU;
552#else
553      break;
554#endif
555
556    case 2:
557      return SIGINT;
558
559    case 8:
560#ifdef SIGFPE
561      return SIGFPE;
562#else
563      break;
564#endif
565
566    case 6:
567      return SIGABRT;
568    }
569
570  return 0;
571}
572
573
574/* Take a step return code RC and set up the variables consulted by
575   sim_stop_reason appropriately.  */
576void
577handle_step (int rc)
578{
579  if (M32C_STEPPED (rc) || M32C_HIT_BREAK (rc))
580    {
581      reason = sim_stopped;
582      siggnal = TARGET_SIGNAL_TRAP;
583    }
584  else if (M32C_STOPPED (rc))
585    {
586      reason = sim_stopped;
587      siggnal = m32c_signal_to_host (M32C_STOP_SIG (rc));
588    }
589  else
590    {
591      assert (M32C_EXITED (rc));
592      reason = sim_exited;
593      siggnal = M32C_EXIT_STATUS (rc);
594    }
595}
596
597
598void
599sim_resume (SIM_DESC sd, int step, int sig_to_deliver)
600{
601  check_desc (sd);
602
603  if (sig_to_deliver != 0)
604    {
605      fprintf (stderr,
606	       "Warning: the m32c minisim does not implement "
607	       "signal delivery yet.\n" "Resuming with no signal.\n");
608    }
609
610  if (step)
611    handle_step (decode_opcode ());
612  else
613    {
614      /* We don't clear 'stop' here, because then we would miss
615         interrupts that arrived on the way here.  Instead, we clear
616         the flag in sim_stop_reason, after GDB has disabled the
617         interrupt signal handler.  */
618      for (;;)
619	{
620	  if (stop)
621	    {
622	      stop = 0;
623	      reason = sim_stopped;
624	      siggnal = TARGET_SIGNAL_INT;
625	      break;
626	    }
627
628	  int rc = decode_opcode ();
629
630	  if (!M32C_STEPPED (rc))
631	    {
632	      handle_step (rc);
633	      break;
634	    }
635	}
636    }
637}
638
639int
640sim_stop (SIM_DESC sd)
641{
642  stop = 1;
643
644  return 1;
645}
646
647void
648sim_stop_reason (SIM_DESC sd, enum sim_stop *reason_p, int *sigrc_p)
649{
650  check_desc (sd);
651
652  *reason_p = reason;
653  *sigrc_p = siggnal;
654}
655
656void
657sim_do_command (SIM_DESC sd, char *cmd)
658{
659  check_desc (sd);
660
661  char *p = cmd;
662
663  /* Skip leading whitespace.  */
664  while (isspace (*p))
665    p++;
666
667  /* Find the extent of the command word.  */
668  for (p = cmd; *p; p++)
669    if (isspace (*p))
670      break;
671
672  /* Null-terminate the command word, and record the start of any
673     further arguments.  */
674  char *args;
675  if (*p)
676    {
677      *p = '\0';
678      args = p + 1;
679      while (isspace (*args))
680	args++;
681    }
682  else
683    args = p;
684
685  if (strcmp (cmd, "trace") == 0)
686    {
687      if (strcmp (args, "on") == 0)
688	trace = 1;
689      else if (strcmp (args, "off") == 0)
690	trace = 0;
691      else
692	printf ("The 'sim trace' command expects 'on' or 'off' "
693		"as an argument.\n");
694    }
695  else if (strcmp (cmd, "verbose") == 0)
696    {
697      if (strcmp (args, "on") == 0)
698	verbose = 1;
699      else if (strcmp (args, "off") == 0)
700	verbose = 0;
701      else
702	printf ("The 'sim verbose' command expects 'on' or 'off'"
703		" as an argument.\n");
704    }
705  else
706    printf ("The 'sim' command expects either 'trace' or 'verbose'"
707	    " as a subcommand.\n");
708}
709