1# Simulator main loop for IQ2000. -*- C -*-
2# Copyright (C) 1998, 1999, 2007 Free Software Foundation, Inc.
3# Contributed by Cygnus Solutions.
4#
5# This file is part of the GNU Simulators.
6#
7# This program is free software; you can redistribute it and/or modify
8# it under the terms of the GNU General Public License as published by
9# the Free Software Foundation; either version 3 of the License, or
10# (at your option) any later version.
11#
12# This program is distributed in the hope that it will be useful,
13# but WITHOUT ANY WARRANTY; without even the implied warranty of
14# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15# GNU General Public License for more details.
16#
17# You should have received a copy of the GNU General Public License
18# along with this program.  If not, see <http://www.gnu.org/licenses/>.
19
20# Syntax:
21# /bin/sh mainloop.in command
22#
23# Command is one of:
24#
25# init
26# support
27# extract-{simple,scache,pbb}
28# {full,fast}-exec-{simple,scache,pbb}
29#
30# A target need only provide a "full" version of one of simple,scache,pbb.
31# If the target wants it can also provide a fast version of same.
32# It can't provide more than this, however for illustration's sake the IQ2000
33# port provides examples of all.
34
35# ??? After a few more ports are done, revisit.
36# Will eventually need to machine generate a lot of this.
37
38case "x$1" in
39
40xsupport)
41
42cat <<EOF
43
44static INLINE const IDESC *
45extract (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, ARGBUF *abuf,
46         int fast_p)
47{
48  const IDESC *id = @cpu@_decode (current_cpu, pc, insn, insn, abuf);
49  @cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
50  if (! fast_p)
51    {
52      int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
53      int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
54      @cpu@_fill_argbuf_tp (current_cpu, abuf, trace_p, profile_p);
55    }
56  return id;
57}
58
59static INLINE SEM_PC
60execute (SIM_CPU *current_cpu, SCACHE *sc, int fast_p)
61{
62  SEM_PC vpc;
63
64  /* Force R0 to zero before every insn.  */
65  @cpu@_h_gr_set (current_cpu, 0, 0);
66
67  if (fast_p)
68    {
69#if ! WITH_SEM_SWITCH_FAST
70#if WITH_SCACHE
71      vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, sc);
72#else
73      vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, &sc->argbuf);
74#endif
75#else
76      abort ();
77#endif /* WITH_SEM_SWITCH_FAST */
78    }
79  else
80    {
81#if ! WITH_SEM_SWITCH_FULL
82      ARGBUF *abuf = &sc->argbuf;
83      const IDESC *idesc = abuf->idesc;
84#if WITH_SCACHE_PBB
85      int virtual_p = CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_VIRTUAL);
86#else
87      int virtual_p = 0;
88#endif
89
90      if (! virtual_p)
91	{
92	  /* FIXME: call x-before */
93	  if (ARGBUF_PROFILE_P (abuf))
94	    PROFILE_COUNT_INSN (current_cpu, abuf->addr, idesc->num);
95	  /* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}.  */
96	  if (PROFILE_MODEL_P (current_cpu)
97	      && ARGBUF_PROFILE_P (abuf))
98	    @cpu@_model_insn_before (current_cpu, 1 /*first_p*/);
99	  TRACE_INSN_INIT (current_cpu, abuf, 1);
100	  TRACE_INSN (current_cpu, idesc->idata,
101		      (const struct argbuf *) abuf, abuf->addr);
102	}
103#if WITH_SCACHE
104      vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, sc);
105#else
106      vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, abuf);
107#endif
108      if (! virtual_p)
109	{
110	  /* FIXME: call x-after */
111	  if (PROFILE_MODEL_P (current_cpu)
112	      && ARGBUF_PROFILE_P (abuf))
113	    {
114	      int cycles;
115
116	      cycles = (*idesc->timing->model_fn) (current_cpu, sc);
117	      @cpu@_model_insn_after (current_cpu, 1 /*last_p*/, cycles);
118	    }
119	  TRACE_INSN_FINI (current_cpu, abuf, 1);
120	}
121#else
122      abort ();
123#endif /* WITH_SEM_SWITCH_FULL */
124    }
125
126  return vpc;
127}
128
129EOF
130;;
131
132xinit)
133;;
134
135xextract-simple | xextract-scache)
136
137# Inputs:  current_cpu, vpc, sc, FAST_P
138# Outputs: sc filled in
139
140cat <<EOF
141{
142  CGEN_INSN_INT insn = GETIMEMUSI (current_cpu, CPU2INSN(vpc));
143  extract (current_cpu, vpc, insn, SEM_ARGBUF (sc), FAST_P);
144  SEM_SKIP_COMPILE (current_cpu, sc, 1);
145}
146EOF
147
148;;
149
150xextract-pbb)
151
152# Inputs:  current_cpu, pc, sc, max_insns, FAST_P
153# Outputs: sc, pc
154# sc must be left pointing past the last created entry.
155# pc must be left pointing past the last created entry.
156# If the pbb is terminated by a cti insn, SET_CTI_VPC(sc) must be called
157# to record the vpc of the cti insn.
158# SET_INSN_COUNT(n) must be called to record number of real insns.
159
160cat <<EOF
161{
162  const IDESC *idesc;
163  int icount = 0;
164
165  /* Is the CTI instruction at the end of the PBB a likely branch?  */
166  int likely_cti;
167
168  while (max_insns > 0)
169    {
170      USI insn = GETIMEMUSI (current_cpu, CPU2INSN(pc));
171      
172      idesc = extract (current_cpu, pc, insn, &sc->argbuf, FAST_P);
173      SEM_SKIP_COMPILE (current_cpu, sc, 1);
174      ++sc;
175      --max_insns;
176      ++icount;
177      pc += idesc->length;
178
179      if (IDESC_CTI_P (idesc))
180        {
181          /* Likely branches annul their delay slot if the branch is
182	     not taken by using the (skip ..) rtx.  We'll rely on
183	     that.  */
184          likely_cti = (IDESC_SKIP_P (idesc));
185
186          SET_CTI_VPC (sc - 1);
187
188          if (CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_DELAY_SLOT))
189	    {
190              USI insn = GETIMEMUSI (current_cpu, CPU2INSN(pc));
191	      idesc = extract (current_cpu, pc, insn, &sc->argbuf, FAST_P);
192
193              if (likely_cti && IDESC_CTI_P (idesc))
194	        {
195	          /* malformed program */
196	          sim_io_eprintf (CPU_STATE (current_cpu),
197		    "malformed program, \`%s' insn in branch likely delay slot\n",
198		    CGEN_INSN_NAME (idesc->idata));
199	        }
200	      else
201	        {
202	          ++sc;
203	          --max_insns;
204	          ++icount;
205	          pc += idesc->length;
206	        }
207            }  
208	  break;
209	}
210    }
211
212 Finish:
213  SET_INSN_COUNT (icount);
214}
215EOF
216
217;;
218
219xfull-exec-* | xfast-exec-*)
220
221# Inputs: current_cpu, sc, FAST_P
222# Outputs: vpc
223# vpc contains the address of the next insn to execute
224
225cat <<EOF
226{
227#if (! FAST_P && WITH_SEM_SWITCH_FULL) || (FAST_P && WITH_SEM_SWITCH_FAST)
228#define DEFINE_SWITCH
229#include "sem-switch.c"
230#else
231  vpc = execute (current_cpu, vpc, FAST_P);
232#endif
233}
234EOF
235
236;;
237
238*)
239  echo "Invalid argument to mainloop.in: $1" >&2
240  exit 1
241  ;;
242
243esac
244