1/* mips.h. Mips opcode list for GDB, the GNU debugger. 2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 3 2003, 2004, 2005 4 Free Software Foundation, Inc. 5 Contributed by Ralph Campbell and OSF 6 Commented and modified by Ian Lance Taylor, Cygnus Support 7 8This file is part of GDB, GAS, and the GNU binutils. 9 10GDB, GAS, and the GNU binutils are free software; you can redistribute 11them and/or modify them under the terms of the GNU General Public 12License as published by the Free Software Foundation; either version 131, or (at your option) any later version. 14 15GDB, GAS, and the GNU binutils are distributed in the hope that they 16will be useful, but WITHOUT ANY WARRANTY; without even the implied 17warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 18the GNU General Public License for more details. 19 20You should have received a copy of the GNU General Public License 21along with this file; see the file COPYING. If not, write to the Free 22Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 23 24#ifndef _MIPS_H_ 25#define _MIPS_H_ 26 27/* These are bit masks and shift counts to use to access the various 28 fields of an instruction. To retrieve the X field of an 29 instruction, use the expression 30 (i >> OP_SH_X) & OP_MASK_X 31 To set the same field (to j), use 32 i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X) 33 34 Make sure you use fields that are appropriate for the instruction, 35 of course. 36 37 The 'i' format uses OP, RS, RT and IMMEDIATE. 38 39 The 'j' format uses OP and TARGET. 40 41 The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT. 42 43 The 'b' format uses OP, RS, RT and DELTA. 44 45 The floating point 'i' format uses OP, RS, RT and IMMEDIATE. 46 47 The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT. 48 49 A breakpoint instruction uses OP, CODE and SPEC (10 bits of the 50 breakpoint instruction are not defined; Kane says the breakpoint 51 code field in BREAK is 20 bits; yet MIPS assemblers and debuggers 52 only use ten bits). An optional two-operand form of break/sdbbp 53 allows the lower ten bits to be set too, and MIPS32 and later 54 architectures allow 20 bits to be set with a signal operand 55 (using CODE20). 56 57 The syscall instruction uses CODE20. 58 59 The general coprocessor instructions use COPZ. */ 60 61#define OP_MASK_OP 0x3f 62#define OP_SH_OP 26 63#define OP_MASK_RS 0x1f 64#define OP_SH_RS 21 65#define OP_MASK_FR 0x1f 66#define OP_SH_FR 21 67#define OP_MASK_FMT 0x1f 68#define OP_SH_FMT 21 69#define OP_MASK_BCC 0x7 70#define OP_SH_BCC 18 71#define OP_MASK_CODE 0x3ff 72#define OP_SH_CODE 16 73#define OP_MASK_CODE2 0x3ff 74#define OP_SH_CODE2 6 75#define OP_MASK_RT 0x1f 76#define OP_SH_RT 16 77#define OP_MASK_FT 0x1f 78#define OP_SH_FT 16 79#define OP_MASK_CACHE 0x1f 80#define OP_SH_CACHE 16 81#define OP_MASK_RD 0x1f 82#define OP_SH_RD 11 83#define OP_MASK_FS 0x1f 84#define OP_SH_FS 11 85#define OP_MASK_PREFX 0x1f 86#define OP_SH_PREFX 11 87#define OP_MASK_CCC 0x7 88#define OP_SH_CCC 8 89#define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */ 90#define OP_SH_CODE20 6 91#define OP_MASK_SHAMT 0x1f 92#define OP_SH_SHAMT 6 93#define OP_MASK_FD 0x1f 94#define OP_SH_FD 6 95#define OP_MASK_TARGET 0x3ffffff 96#define OP_SH_TARGET 0 97#define OP_MASK_COPZ 0x1ffffff 98#define OP_SH_COPZ 0 99#define OP_MASK_IMMEDIATE 0xffff 100#define OP_SH_IMMEDIATE 0 101#define OP_MASK_DELTA 0xffff 102#define OP_SH_DELTA 0 103#define OP_MASK_FUNCT 0x3f 104#define OP_SH_FUNCT 0 105#define OP_MASK_SPEC 0x3f 106#define OP_SH_SPEC 0 107#define OP_SH_LOCC 8 /* FP condition code. */ 108#define OP_SH_HICC 18 /* FP condition code. */ 109#define OP_MASK_CC 0x7 110#define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */ 111#define OP_MASK_COP1NORM 0x1 /* a single bit. */ 112#define OP_SH_COP1SPEC 21 /* COP1 encodings. */ 113#define OP_MASK_COP1SPEC 0xf 114#define OP_MASK_COP1SCLR 0x4 115#define OP_MASK_COP1CMP 0x3 116#define OP_SH_COP1CMP 4 117#define OP_SH_FORMAT 21 /* FP short format field. */ 118#define OP_MASK_FORMAT 0x7 119#define OP_SH_TRUE 16 120#define OP_MASK_TRUE 0x1 121#define OP_SH_GE 17 122#define OP_MASK_GE 0x01 123#define OP_SH_UNSIGNED 16 124#define OP_MASK_UNSIGNED 0x1 125#define OP_SH_HINT 16 126#define OP_MASK_HINT 0x1f 127#define OP_SH_MMI 0 /* Multimedia (parallel) op. */ 128#define OP_MASK_MMI 0x3f 129#define OP_SH_MMISUB 6 130#define OP_MASK_MMISUB 0x1f 131#define OP_MASK_PERFREG 0x1f /* Performance monitoring. */ 132#define OP_SH_PERFREG 1 133#define OP_SH_SEL 0 /* Coprocessor select field. */ 134#define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */ 135#define OP_SH_CODE19 6 /* 19 bit wait code. */ 136#define OP_MASK_CODE19 0x7ffff 137#define OP_SH_ALN 21 138#define OP_MASK_ALN 0x7 139#define OP_SH_VSEL 21 140#define OP_MASK_VSEL 0x1f 141#define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits, 142 but 0x8-0xf don't select bytes. */ 143#define OP_SH_VECBYTE 22 144#define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */ 145#define OP_SH_VECALIGN 21 146#define OP_MASK_INSMSB 0x1f /* "ins" MSB. */ 147#define OP_SH_INSMSB 11 148#define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ 149#define OP_SH_EXTMSBD 11 150 151/* MIPS DSP ASE */ 152#define OP_SH_DSPACC 11 153#define OP_MASK_DSPACC 0x3 154#define OP_SH_DSPACC_S 21 155#define OP_MASK_DSPACC_S 0x3 156#define OP_SH_DSPSFT 20 157#define OP_MASK_DSPSFT 0x3f 158#define OP_SH_DSPSFT_7 19 159#define OP_MASK_DSPSFT_7 0x7f 160#define OP_SH_SA3 21 161#define OP_MASK_SA3 0x7 162#define OP_SH_SA4 21 163#define OP_MASK_SA4 0xf 164#define OP_SH_IMM8 16 165#define OP_MASK_IMM8 0xff 166#define OP_SH_IMM10 16 167#define OP_MASK_IMM10 0x3ff 168#define OP_SH_WRDSP 11 169#define OP_MASK_WRDSP 0x3f 170#define OP_SH_RDDSP 16 171#define OP_MASK_RDDSP 0x3f 172#define OP_SH_BP 11 173#define OP_MASK_BP 0x3 174 175/* MIPS MT ASE */ 176#define OP_SH_MT_U 5 177#define OP_MASK_MT_U 0x1 178#define OP_SH_MT_H 4 179#define OP_MASK_MT_H 0x1 180#define OP_SH_MTACC_T 18 181#define OP_MASK_MTACC_T 0x3 182#define OP_SH_MTACC_D 13 183#define OP_MASK_MTACC_D 0x3 184 185#define OP_OP_COP0 0x10 186#define OP_OP_COP1 0x11 187#define OP_OP_COP2 0x12 188#define OP_OP_COP3 0x13 189#define OP_OP_LWC1 0x31 190#define OP_OP_LWC2 0x32 191#define OP_OP_LWC3 0x33 /* a.k.a. pref */ 192#define OP_OP_LDC1 0x35 193#define OP_OP_LDC2 0x36 194#define OP_OP_LDC3 0x37 /* a.k.a. ld */ 195#define OP_OP_SWC1 0x39 196#define OP_OP_SWC2 0x3a 197#define OP_OP_SWC3 0x3b 198#define OP_OP_SDC1 0x3d 199#define OP_OP_SDC2 0x3e 200#define OP_OP_SDC3 0x3f /* a.k.a. sd */ 201 202/* Values in the 'VSEL' field. */ 203#define MDMX_FMTSEL_IMM_QH 0x1d 204#define MDMX_FMTSEL_IMM_OB 0x1e 205#define MDMX_FMTSEL_VEC_QH 0x15 206#define MDMX_FMTSEL_VEC_OB 0x16 207 208/* UDI */ 209#define OP_SH_UDI1 6 210#define OP_MASK_UDI1 0x1f 211#define OP_SH_UDI2 6 212#define OP_MASK_UDI2 0x3ff 213#define OP_SH_UDI3 6 214#define OP_MASK_UDI3 0x7fff 215#define OP_SH_UDI4 6 216#define OP_MASK_UDI4 0xfffff 217 218/* This structure holds information for a particular instruction. */ 219 220struct mips_opcode 221{ 222 /* The name of the instruction. */ 223 const char *name; 224 /* A string describing the arguments for this instruction. */ 225 const char *args; 226 /* The basic opcode for the instruction. When assembling, this 227 opcode is modified by the arguments to produce the actual opcode 228 that is used. If pinfo is INSN_MACRO, then this is 0. */ 229 unsigned long match; 230 /* If pinfo is not INSN_MACRO, then this is a bit mask for the 231 relevant portions of the opcode when disassembling. If the 232 actual opcode anded with the match field equals the opcode field, 233 then we have found the correct instruction. If pinfo is 234 INSN_MACRO, then this field is the macro identifier. */ 235 unsigned long mask; 236 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection 237 of bits describing the instruction, notably any relevant hazard 238 information. */ 239 unsigned long pinfo; 240 /* A collection of additional bits describing the instruction. */ 241 unsigned long pinfo2; 242 /* A collection of bits describing the instruction sets of which this 243 instruction or macro is a member. */ 244 unsigned long membership; 245}; 246 247/* These are the characters which may appear in the args field of an 248 instruction. They appear in the order in which the fields appear 249 when the instruction is used. Commas and parentheses in the args 250 string are ignored when assembling, and written into the output 251 when disassembling. 252 253 Each of these characters corresponds to a mask field defined above. 254 255 "<" 5 bit shift amount (OP_*_SHAMT) 256 ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT) 257 "a" 26 bit target address (OP_*_TARGET) 258 "b" 5 bit base register (OP_*_RS) 259 "c" 10 bit breakpoint code (OP_*_CODE) 260 "d" 5 bit destination register specifier (OP_*_RD) 261 "h" 5 bit prefx hint (OP_*_PREFX) 262 "i" 16 bit unsigned immediate (OP_*_IMMEDIATE) 263 "j" 16 bit signed immediate (OP_*_DELTA) 264 "k" 5 bit cache opcode in target register position (OP_*_CACHE) 265 Also used for immediate operands in vr5400 vector insns. 266 "o" 16 bit signed offset (OP_*_DELTA) 267 "p" 16 bit PC relative branch target address (OP_*_DELTA) 268 "q" 10 bit extra breakpoint code (OP_*_CODE2) 269 "r" 5 bit same register used as both source and target (OP_*_RS) 270 "s" 5 bit source register specifier (OP_*_RS) 271 "t" 5 bit target register (OP_*_RT) 272 "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE) 273 "v" 5 bit same register used as both source and destination (OP_*_RS) 274 "w" 5 bit same register used as both target and destination (OP_*_RT) 275 "U" 5 bit same destination register in both OP_*_RD and OP_*_RT 276 (used by clo and clz) 277 "C" 25 bit coprocessor function code (OP_*_COPZ) 278 "B" 20 bit syscall/breakpoint function code (OP_*_CODE20) 279 "J" 19 bit wait function code (OP_*_CODE19) 280 "x" accept and ignore register name 281 "z" must be zero register 282 "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD) 283 "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes 284 LSB (OP_*_SHAMT). 285 Enforces: 0 <= pos < 32. 286 "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB). 287 Requires that "+A" or "+E" occur first to set position. 288 Enforces: 0 < (pos+size) <= 32. 289 "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD). 290 Requires that "+A" or "+E" occur first to set position. 291 Enforces: 0 < (pos+size) <= 32. 292 (Also used by "dext" w/ different limits, but limits for 293 that are checked by the M_DEXT macro.) 294 "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT). 295 Enforces: 32 <= pos < 64. 296 "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB). 297 Requires that "+A" or "+E" occur first to set position. 298 Enforces: 32 < (pos+size) <= 64. 299 "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD). 300 Requires that "+A" or "+E" occur first to set position. 301 Enforces: 32 < (pos+size) <= 64. 302 "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD). 303 Requires that "+A" or "+E" occur first to set position. 304 Enforces: 32 < (pos+size) <= 64. 305 306 Floating point instructions: 307 "D" 5 bit destination register (OP_*_FD) 308 "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up) 309 "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up) 310 "S" 5 bit fs source 1 register (OP_*_FS) 311 "T" 5 bit ft source 2 register (OP_*_FT) 312 "R" 5 bit fr source 3 register (OP_*_FR) 313 "V" 5 bit same register used as floating source and destination (OP_*_FS) 314 "W" 5 bit same register used as floating target and destination (OP_*_FT) 315 316 Coprocessor instructions: 317 "E" 5 bit target register (OP_*_RT) 318 "G" 5 bit destination register (OP_*_RD) 319 "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL) 320 "P" 5 bit performance-monitor register (OP_*_PERFREG) 321 "e" 5 bit vector register byte specifier (OP_*_VECBYTE) 322 "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) 323 see also "k" above 324 "+D" Combined destination register ("G") and sel ("H") for CP0 ops, 325 for pretty-printing in disassembly only. 326 327 Macro instructions: 328 "A" General 32 bit expression 329 "I" 32 bit immediate (value placed in imm_expr). 330 "+I" 32 bit immediate (value placed in imm2_expr). 331 "F" 64 bit floating point constant in .rdata 332 "L" 64 bit floating point constant in .lit8 333 "f" 32 bit floating point constant 334 "l" 32 bit floating point constant in .lit4 335 336 MDMX instruction operands (note that while these use the FP register 337 fields, they accept both $fN and $vN names for the registers): 338 "O" MDMX alignment offset (OP_*_ALN) 339 "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT) 340 "X" MDMX destination register (OP_*_FD) 341 "Y" MDMX source register (OP_*_FS) 342 "Z" MDMX source register (OP_*_FT) 343 344 DSP ASE usage: 345 "2" 2 bit unsigned immediate for byte align (OP_*_BP) 346 "3" 3 bit unsigned immediate (OP_*_SA3) 347 "4" 4 bit unsigned immediate (OP_*_SA4) 348 "5" 8 bit unsigned immediate (OP_*_IMM8) 349 "6" 5 bit unsigned immediate (OP_*_RS) 350 "7" 2 bit dsp accumulator register (OP_*_DSPACC) 351 "8" 6 bit unsigned immediate (OP_*_WRDSP) 352 "9" 2 bit dsp accumulator register (OP_*_DSPACC_S) 353 "0" 6 bit signed immediate (OP_*_DSPSFT) 354 ":" 7 bit signed immediate (OP_*_DSPSFT_7) 355 "'" 6 bit unsigned immediate (OP_*_RDDSP) 356 "@" 10 bit signed immediate (OP_*_IMM10) 357 358 MT ASE usage: 359 "!" 1 bit usermode flag (OP_*_MT_U) 360 "$" 1 bit load high flag (OP_*_MT_H) 361 "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T) 362 "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D) 363 "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD) 364 "+t" 5 bit coprocessor 0 destination register (OP_*_RT) 365 "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only 366 367 UDI immediates: 368 "+1" UDI immediate bits 6-10 369 "+2" UDI immediate bits 6-15 370 "+3" UDI immediate bits 6-20 371 "+4" UDI immediate bits 6-25 372 373 Other: 374 "()" parens surrounding optional value 375 "," separates operands 376 "[]" brackets around index for vector-op scalar operand specifier (vr5400) 377 "+" Start of extension sequence. 378 379 Characters used so far, for quick reference when adding more: 380 "234567890" 381 "%[]<>(),+:'@!$*&" 382 "ABCDEFGHIJKLMNOPQRSTUVWXYZ" 383 "abcdefghijklopqrstuvwxz" 384 385 Extension character sequences used so far ("+" followed by the 386 following), for quick reference when adding more: 387 "1234" 388 "ABCDEFGHIT" 389 "t" 390*/ 391 392/* These are the bits which may be set in the pinfo field of an 393 instructions, if it is not equal to INSN_MACRO. */ 394 395/* Modifies the general purpose register in OP_*_RD. */ 396#define INSN_WRITE_GPR_D 0x00000001 397/* Modifies the general purpose register in OP_*_RT. */ 398#define INSN_WRITE_GPR_T 0x00000002 399/* Modifies general purpose register 31. */ 400#define INSN_WRITE_GPR_31 0x00000004 401/* Modifies the floating point register in OP_*_FD. */ 402#define INSN_WRITE_FPR_D 0x00000008 403/* Modifies the floating point register in OP_*_FS. */ 404#define INSN_WRITE_FPR_S 0x00000010 405/* Modifies the floating point register in OP_*_FT. */ 406#define INSN_WRITE_FPR_T 0x00000020 407/* Reads the general purpose register in OP_*_RS. */ 408#define INSN_READ_GPR_S 0x00000040 409/* Reads the general purpose register in OP_*_RT. */ 410#define INSN_READ_GPR_T 0x00000080 411/* Reads the floating point register in OP_*_FS. */ 412#define INSN_READ_FPR_S 0x00000100 413/* Reads the floating point register in OP_*_FT. */ 414#define INSN_READ_FPR_T 0x00000200 415/* Reads the floating point register in OP_*_FR. */ 416#define INSN_READ_FPR_R 0x00000400 417/* Modifies coprocessor condition code. */ 418#define INSN_WRITE_COND_CODE 0x00000800 419/* Reads coprocessor condition code. */ 420#define INSN_READ_COND_CODE 0x00001000 421/* TLB operation. */ 422#define INSN_TLB 0x00002000 423/* Reads coprocessor register other than floating point register. */ 424#define INSN_COP 0x00004000 425/* Instruction loads value from memory, requiring delay. */ 426#define INSN_LOAD_MEMORY_DELAY 0x00008000 427/* Instruction loads value from coprocessor, requiring delay. */ 428#define INSN_LOAD_COPROC_DELAY 0x00010000 429/* Instruction has unconditional branch delay slot. */ 430#define INSN_UNCOND_BRANCH_DELAY 0x00020000 431/* Instruction has conditional branch delay slot. */ 432#define INSN_COND_BRANCH_DELAY 0x00040000 433/* Conditional branch likely: if branch not taken, insn nullified. */ 434#define INSN_COND_BRANCH_LIKELY 0x00080000 435/* Moves to coprocessor register, requiring delay. */ 436#define INSN_COPROC_MOVE_DELAY 0x00100000 437/* Loads coprocessor register from memory, requiring delay. */ 438#define INSN_COPROC_MEMORY_DELAY 0x00200000 439/* Reads the HI register. */ 440#define INSN_READ_HI 0x00400000 441/* Reads the LO register. */ 442#define INSN_READ_LO 0x00800000 443/* Modifies the HI register. */ 444#define INSN_WRITE_HI 0x01000000 445/* Modifies the LO register. */ 446#define INSN_WRITE_LO 0x02000000 447/* Takes a trap (easier to keep out of delay slot). */ 448#define INSN_TRAP 0x04000000 449/* Instruction stores value into memory. */ 450#define INSN_STORE_MEMORY 0x08000000 451/* Instruction uses single precision floating point. */ 452#define FP_S 0x10000000 453/* Instruction uses double precision floating point. */ 454#define FP_D 0x20000000 455/* Instruction is part of the tx39's integer multiply family. */ 456#define INSN_MULT 0x40000000 457/* Instruction synchronize shared memory. */ 458#define INSN_SYNC 0x80000000 459 460/* These are the bits which may be set in the pinfo2 field of an 461 instruction. */ 462 463/* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */ 464#define INSN2_ALIAS 0x00000001 465/* Instruction reads MDMX accumulator. */ 466#define INSN2_READ_MDMX_ACC 0x00000002 467/* Instruction writes MDMX accumulator. */ 468#define INSN2_WRITE_MDMX_ACC 0x00000004 469 470/* Instruction is actually a macro. It should be ignored by the 471 disassembler, and requires special treatment by the assembler. */ 472#define INSN_MACRO 0xffffffff 473 474/* Masks used to mark instructions to indicate which MIPS ISA level 475 they were introduced in. ISAs, as defined below, are logical 476 ORs of these bits, indicating that they support the instructions 477 defined at the given level. */ 478 479#define INSN_ISA_MASK 0x00000fff 480#define INSN_ISA1 0x00000001 481#define INSN_ISA2 0x00000002 482#define INSN_ISA3 0x00000004 483#define INSN_ISA4 0x00000008 484#define INSN_ISA5 0x00000010 485#define INSN_ISA32 0x00000020 486#define INSN_ISA64 0x00000040 487#define INSN_ISA32R2 0x00000080 488#define INSN_ISA64R2 0x00000100 489 490/* Masks used for MIPS-defined ASEs. */ 491#define INSN_ASE_MASK 0x3c00f000 492 493/* DSP ASE */ 494#define INSN_DSP 0x00001000 495#define INSN_DSP64 0x00002000 496/* MIPS 16 ASE */ 497#define INSN_MIPS16 0x00004000 498/* MIPS-3D ASE */ 499#define INSN_MIPS3D 0x00008000 500 501/* Chip specific instructions. These are bitmasks. */ 502 503/* MIPS R4650 instruction. */ 504#define INSN_4650 0x00010000 505/* LSI R4010 instruction. */ 506#define INSN_4010 0x00020000 507/* NEC VR4100 instruction. */ 508#define INSN_4100 0x00040000 509/* Toshiba R3900 instruction. */ 510#define INSN_3900 0x00080000 511/* MIPS R10000 instruction. */ 512#define INSN_10000 0x00100000 513/* Broadcom SB-1 instruction. */ 514#define INSN_SB1 0x00200000 515/* NEC VR4111/VR4181 instruction. */ 516#define INSN_4111 0x00400000 517/* NEC VR4120 instruction. */ 518#define INSN_4120 0x00800000 519/* NEC VR5400 instruction. */ 520#define INSN_5400 0x01000000 521/* NEC VR5500 instruction. */ 522#define INSN_5500 0x02000000 523 524/* MDMX ASE */ 525#define INSN_MDMX 0x04000000 526/* MT ASE */ 527#define INSN_MT 0x08000000 528/* SmartMIPS ASE */ 529#define INSN_SMARTMIPS 0x10000000 530/* DSP R2 ASE */ 531#define INSN_DSPR2 0x20000000 532 533/* MIPS ISA defines, use instead of hardcoding ISA level. */ 534 535#define ISA_UNKNOWN 0 /* Gas internal use. */ 536#define ISA_MIPS1 (INSN_ISA1) 537#define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2) 538#define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3) 539#define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4) 540#define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5) 541 542#define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32) 543#define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64) 544 545#define ISA_MIPS32R2 (ISA_MIPS32 | INSN_ISA32R2) 546#define ISA_MIPS64R2 (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2) 547 548 549/* CPU defines, use instead of hardcoding processor number. Keep this 550 in sync with bfd/archures.c in order for machine selection to work. */ 551#define CPU_UNKNOWN 0 /* Gas internal use. */ 552#define CPU_R3000 3000 553#define CPU_R3900 3900 554#define CPU_R4000 4000 555#define CPU_R4010 4010 556#define CPU_VR4100 4100 557#define CPU_R4111 4111 558#define CPU_VR4120 4120 559#define CPU_R4300 4300 560#define CPU_R4400 4400 561#define CPU_R4600 4600 562#define CPU_R4650 4650 563#define CPU_R5000 5000 564#define CPU_VR5400 5400 565#define CPU_VR5500 5500 566#define CPU_R6000 6000 567#define CPU_RM7000 7000 568#define CPU_R8000 8000 569#define CPU_RM9000 9000 570#define CPU_R10000 10000 571#define CPU_R12000 12000 572#define CPU_MIPS16 16 573#define CPU_MIPS32 32 574#define CPU_MIPS32R2 33 575#define CPU_MIPS5 5 576#define CPU_MIPS64 64 577#define CPU_MIPS64R2 65 578#define CPU_SB1 12310201 /* octal 'SB', 01. */ 579 580/* Test for membership in an ISA including chip specific ISAs. INSN 581 is pointer to an element of the opcode table; ISA is the specified 582 ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to 583 test, or zero if no CPU specific ISA test is desired. */ 584 585#define OPCODE_IS_MEMBER(insn, isa, cpu) \ 586 (((insn)->membership & isa) != 0 \ 587 || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \ 588 || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \ 589 || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \ 590 || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \ 591 || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \ 592 || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \ 593 || ((cpu == CPU_R10000 || cpu == CPU_R12000) \ 594 && ((insn)->membership & INSN_10000) != 0) \ 595 || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \ 596 || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \ 597 || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \ 598 || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \ 599 || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \ 600 || 0) /* Please keep this term for easier source merging. */ 601 602/* This is a list of macro expanded instructions. 603 604 _I appended means immediate 605 _A appended means address 606 _AB appended means address with base register 607 _D appended means 64 bit floating point constant 608 _S appended means 32 bit floating point constant. */ 609 610enum 611{ 612 M_ABS, 613 M_ADD_I, 614 M_ADDU_I, 615 M_AND_I, 616 M_BALIGN, 617 M_BEQ, 618 M_BEQ_I, 619 M_BEQL_I, 620 M_BGE, 621 M_BGEL, 622 M_BGE_I, 623 M_BGEL_I, 624 M_BGEU, 625 M_BGEUL, 626 M_BGEU_I, 627 M_BGEUL_I, 628 M_BGT, 629 M_BGTL, 630 M_BGT_I, 631 M_BGTL_I, 632 M_BGTU, 633 M_BGTUL, 634 M_BGTU_I, 635 M_BGTUL_I, 636 M_BLE, 637 M_BLEL, 638 M_BLE_I, 639 M_BLEL_I, 640 M_BLEU, 641 M_BLEUL, 642 M_BLEU_I, 643 M_BLEUL_I, 644 M_BLT, 645 M_BLTL, 646 M_BLT_I, 647 M_BLTL_I, 648 M_BLTU, 649 M_BLTUL, 650 M_BLTU_I, 651 M_BLTUL_I, 652 M_BNE, 653 M_BNE_I, 654 M_BNEL_I, 655 M_CACHE_AB, 656 M_DABS, 657 M_DADD_I, 658 M_DADDU_I, 659 M_DDIV_3, 660 M_DDIV_3I, 661 M_DDIVU_3, 662 M_DDIVU_3I, 663 M_DEXT, 664 M_DINS, 665 M_DIV_3, 666 M_DIV_3I, 667 M_DIVU_3, 668 M_DIVU_3I, 669 M_DLA_AB, 670 M_DLCA_AB, 671 M_DLI, 672 M_DMUL, 673 M_DMUL_I, 674 M_DMULO, 675 M_DMULO_I, 676 M_DMULOU, 677 M_DMULOU_I, 678 M_DREM_3, 679 M_DREM_3I, 680 M_DREMU_3, 681 M_DREMU_3I, 682 M_DSUB_I, 683 M_DSUBU_I, 684 M_DSUBU_I_2, 685 M_J_A, 686 M_JAL_1, 687 M_JAL_2, 688 M_JAL_A, 689 M_L_DOB, 690 M_L_DAB, 691 M_LA_AB, 692 M_LB_A, 693 M_LB_AB, 694 M_LBU_A, 695 M_LBU_AB, 696 M_LCA_AB, 697 M_LD_A, 698 M_LD_OB, 699 M_LD_AB, 700 M_LDC1_AB, 701 M_LDC2_AB, 702 M_LDC3_AB, 703 M_LDL_AB, 704 M_LDR_AB, 705 M_LH_A, 706 M_LH_AB, 707 M_LHU_A, 708 M_LHU_AB, 709 M_LI, 710 M_LI_D, 711 M_LI_DD, 712 M_LI_S, 713 M_LI_SS, 714 M_LL_AB, 715 M_LLD_AB, 716 M_LS_A, 717 M_LW_A, 718 M_LW_AB, 719 M_LWC0_A, 720 M_LWC0_AB, 721 M_LWC1_A, 722 M_LWC1_AB, 723 M_LWC2_A, 724 M_LWC2_AB, 725 M_LWC3_A, 726 M_LWC3_AB, 727 M_LWL_A, 728 M_LWL_AB, 729 M_LWR_A, 730 M_LWR_AB, 731 M_LWU_AB, 732 M_MOVE, 733 M_MUL, 734 M_MUL_I, 735 M_MULO, 736 M_MULO_I, 737 M_MULOU, 738 M_MULOU_I, 739 M_NOR_I, 740 M_OR_I, 741 M_REM_3, 742 M_REM_3I, 743 M_REMU_3, 744 M_REMU_3I, 745 M_DROL, 746 M_ROL, 747 M_DROL_I, 748 M_ROL_I, 749 M_DROR, 750 M_ROR, 751 M_DROR_I, 752 M_ROR_I, 753 M_S_DA, 754 M_S_DOB, 755 M_S_DAB, 756 M_S_S, 757 M_SC_AB, 758 M_SCD_AB, 759 M_SD_A, 760 M_SD_OB, 761 M_SD_AB, 762 M_SDC1_AB, 763 M_SDC2_AB, 764 M_SDC3_AB, 765 M_SDL_AB, 766 M_SDR_AB, 767 M_SEQ, 768 M_SEQ_I, 769 M_SGE, 770 M_SGE_I, 771 M_SGEU, 772 M_SGEU_I, 773 M_SGT, 774 M_SGT_I, 775 M_SGTU, 776 M_SGTU_I, 777 M_SLE, 778 M_SLE_I, 779 M_SLEU, 780 M_SLEU_I, 781 M_SLT_I, 782 M_SLTU_I, 783 M_SNE, 784 M_SNE_I, 785 M_SB_A, 786 M_SB_AB, 787 M_SH_A, 788 M_SH_AB, 789 M_SW_A, 790 M_SW_AB, 791 M_SWC0_A, 792 M_SWC0_AB, 793 M_SWC1_A, 794 M_SWC1_AB, 795 M_SWC2_A, 796 M_SWC2_AB, 797 M_SWC3_A, 798 M_SWC3_AB, 799 M_SWL_A, 800 M_SWL_AB, 801 M_SWR_A, 802 M_SWR_AB, 803 M_SUB_I, 804 M_SUBU_I, 805 M_SUBU_I_2, 806 M_TEQ_I, 807 M_TGE_I, 808 M_TGEU_I, 809 M_TLT_I, 810 M_TLTU_I, 811 M_TNE_I, 812 M_TRUNCWD, 813 M_TRUNCWS, 814 M_ULD, 815 M_ULD_A, 816 M_ULH, 817 M_ULH_A, 818 M_ULHU, 819 M_ULHU_A, 820 M_ULW, 821 M_ULW_A, 822 M_USH, 823 M_USH_A, 824 M_USW, 825 M_USW_A, 826 M_USD, 827 M_USD_A, 828 M_XOR_I, 829 M_COP0, 830 M_COP1, 831 M_COP2, 832 M_COP3, 833 M_NUM_MACROS 834}; 835 836 837/* The order of overloaded instructions matters. Label arguments and 838 register arguments look the same. Instructions that can have either 839 for arguments must apear in the correct order in this table for the 840 assembler to pick the right one. In other words, entries with 841 immediate operands must apear after the same instruction with 842 registers. 843 844 Many instructions are short hand for other instructions (i.e., The 845 jal <register> instruction is short for jalr <register>). */ 846 847extern const struct mips_opcode mips_builtin_opcodes[]; 848extern const int bfd_mips_num_builtin_opcodes; 849extern struct mips_opcode *mips_opcodes; 850extern int bfd_mips_num_opcodes; 851#define NUMOPCODES bfd_mips_num_opcodes 852 853 854/* The rest of this file adds definitions for the mips16 TinyRISC 855 processor. */ 856 857/* These are the bitmasks and shift counts used for the different 858 fields in the instruction formats. Other than OP, no masks are 859 provided for the fixed portions of an instruction, since they are 860 not needed. 861 862 The I format uses IMM11. 863 864 The RI format uses RX and IMM8. 865 866 The RR format uses RX, and RY. 867 868 The RRI format uses RX, RY, and IMM5. 869 870 The RRR format uses RX, RY, and RZ. 871 872 The RRI_A format uses RX, RY, and IMM4. 873 874 The SHIFT format uses RX, RY, and SHAMT. 875 876 The I8 format uses IMM8. 877 878 The I8_MOVR32 format uses RY and REGR32. 879 880 The IR_MOV32R format uses REG32R and MOV32Z. 881 882 The I64 format uses IMM8. 883 884 The RI64 format uses RY and IMM5. 885 */ 886 887#define MIPS16OP_MASK_OP 0x1f 888#define MIPS16OP_SH_OP 11 889#define MIPS16OP_MASK_IMM11 0x7ff 890#define MIPS16OP_SH_IMM11 0 891#define MIPS16OP_MASK_RX 0x7 892#define MIPS16OP_SH_RX 8 893#define MIPS16OP_MASK_IMM8 0xff 894#define MIPS16OP_SH_IMM8 0 895#define MIPS16OP_MASK_RY 0x7 896#define MIPS16OP_SH_RY 5 897#define MIPS16OP_MASK_IMM5 0x1f 898#define MIPS16OP_SH_IMM5 0 899#define MIPS16OP_MASK_RZ 0x7 900#define MIPS16OP_SH_RZ 2 901#define MIPS16OP_MASK_IMM4 0xf 902#define MIPS16OP_SH_IMM4 0 903#define MIPS16OP_MASK_REGR32 0x1f 904#define MIPS16OP_SH_REGR32 0 905#define MIPS16OP_MASK_REG32R 0x1f 906#define MIPS16OP_SH_REG32R 3 907#define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18)) 908#define MIPS16OP_MASK_MOVE32Z 0x7 909#define MIPS16OP_SH_MOVE32Z 0 910#define MIPS16OP_MASK_IMM6 0x3f 911#define MIPS16OP_SH_IMM6 5 912 913/* These are the characters which may appears in the args field of an 914 instruction. They appear in the order in which the fields appear 915 when the instruction is used. Commas and parentheses in the args 916 string are ignored when assembling, and written into the output 917 when disassembling. 918 919 "y" 3 bit register (MIPS16OP_*_RY) 920 "x" 3 bit register (MIPS16OP_*_RX) 921 "z" 3 bit register (MIPS16OP_*_RZ) 922 "Z" 3 bit register (MIPS16OP_*_MOVE32Z) 923 "v" 3 bit same register as source and destination (MIPS16OP_*_RX) 924 "w" 3 bit same register as source and destination (MIPS16OP_*_RY) 925 "0" zero register ($0) 926 "S" stack pointer ($sp or $29) 927 "P" program counter 928 "R" return address register ($ra or $31) 929 "X" 5 bit MIPS register (MIPS16OP_*_REGR32) 930 "Y" 5 bit MIPS register (MIPS16OP_*_REG32R) 931 "6" 6 bit unsigned break code (MIPS16OP_*_IMM6) 932 "a" 26 bit jump address 933 "e" 11 bit extension value 934 "l" register list for entry instruction 935 "L" register list for exit instruction 936 937 The remaining codes may be extended. Except as otherwise noted, 938 the full extended operand is a 16 bit signed value. 939 "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned) 940 ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned) 941 "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned) 942 "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned) 943 "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed) 944 "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5) 945 "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5) 946 "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5) 947 "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5) 948 "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5) 949 "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) 950 "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8) 951 "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8) 952 "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned) 953 "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8) 954 "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8) 955 "p" 8 bit conditional branch address (MIPS16OP_*_IMM8) 956 "q" 11 bit branch address (MIPS16OP_*_IMM11) 957 "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8) 958 "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5) 959 "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5) 960 "m" 7 bit register list for save instruction (18 bit extended) 961 "M" 7 bit register list for restore instruction (18 bit extended) 962 */ 963 964/* Save/restore encoding for the args field when all 4 registers are 965 either saved as arguments or saved/restored as statics. */ 966#define MIPS16_ALL_ARGS 0xe 967#define MIPS16_ALL_STATICS 0xb 968 969/* For the mips16, we use the same opcode table format and a few of 970 the same flags. However, most of the flags are different. */ 971 972/* Modifies the register in MIPS16OP_*_RX. */ 973#define MIPS16_INSN_WRITE_X 0x00000001 974/* Modifies the register in MIPS16OP_*_RY. */ 975#define MIPS16_INSN_WRITE_Y 0x00000002 976/* Modifies the register in MIPS16OP_*_RZ. */ 977#define MIPS16_INSN_WRITE_Z 0x00000004 978/* Modifies the T ($24) register. */ 979#define MIPS16_INSN_WRITE_T 0x00000008 980/* Modifies the SP ($29) register. */ 981#define MIPS16_INSN_WRITE_SP 0x00000010 982/* Modifies the RA ($31) register. */ 983#define MIPS16_INSN_WRITE_31 0x00000020 984/* Modifies the general purpose register in MIPS16OP_*_REG32R. */ 985#define MIPS16_INSN_WRITE_GPR_Y 0x00000040 986/* Reads the register in MIPS16OP_*_RX. */ 987#define MIPS16_INSN_READ_X 0x00000080 988/* Reads the register in MIPS16OP_*_RY. */ 989#define MIPS16_INSN_READ_Y 0x00000100 990/* Reads the register in MIPS16OP_*_MOVE32Z. */ 991#define MIPS16_INSN_READ_Z 0x00000200 992/* Reads the T ($24) register. */ 993#define MIPS16_INSN_READ_T 0x00000400 994/* Reads the SP ($29) register. */ 995#define MIPS16_INSN_READ_SP 0x00000800 996/* Reads the RA ($31) register. */ 997#define MIPS16_INSN_READ_31 0x00001000 998/* Reads the program counter. */ 999#define MIPS16_INSN_READ_PC 0x00002000 1000/* Reads the general purpose register in MIPS16OP_*_REGR32. */ 1001#define MIPS16_INSN_READ_GPR_X 0x00004000 1002/* Is a branch insn. */ 1003#define MIPS16_INSN_BRANCH 0x00010000 1004 1005/* The following flags have the same value for the mips16 opcode 1006 table: 1007 INSN_UNCOND_BRANCH_DELAY 1008 INSN_COND_BRANCH_DELAY 1009 INSN_COND_BRANCH_LIKELY (never used) 1010 INSN_READ_HI 1011 INSN_READ_LO 1012 INSN_WRITE_HI 1013 INSN_WRITE_LO 1014 INSN_TRAP 1015 INSN_ISA3 1016 */ 1017 1018extern const struct mips_opcode mips16_opcodes[]; 1019extern const int bfd_mips16_num_opcodes; 1020 1021#endif /* _MIPS_H_ */ 1022