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56<h3 class="section">6.53 x86 specific memory model extensions for transactional memory</h3>
57
58<p>The i386 architecture supports additional memory ordering flags
59to mark lock critical sections for hardware lock elision. 
60These must be specified in addition to an existing memory model to
61atomic intrinsics.
62
63     <dl>
64<dt><code>__ATOMIC_HLE_ACQUIRE</code><dd>Start lock elision on a lock variable. 
65Memory model must be <code>__ATOMIC_ACQUIRE</code> or stronger. 
66<br><dt><code>__ATOMIC_HLE_RELEASE</code><dd>End lock elision on a lock variable. 
67Memory model must be <code>__ATOMIC_RELEASE</code> or stronger. 
68</dl>
69
70 <p>When a lock acquire fails it's required for good performance to abort
71the transaction quickly. This can be done with a <code>_mm_pause</code>
72
73<pre class="smallexample">     #include &lt;immintrin.h&gt; // For _mm_pause
74     
75     /* Acquire lock with lock elision */
76     while (__atomic_exchange_n(&amp;lockvar, 1, __ATOMIC_ACQUIRE|__ATOMIC_HLE_ACQUIRE))
77         _mm_pause(); /* Abort failed transaction */
78     ...
79     /* Free lock with lock elision */
80     __atomic_clear(&amp;lockvar, __ATOMIC_RELEASE|__ATOMIC_HLE_RELEASE);
81</pre>
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