1<html lang="en"> 2<head> 3<title>ARM - Untitled</title> 4<meta http-equiv="Content-Type" content="text/html"> 5<meta name="description" content="Untitled"> 6<meta name="generator" content="makeinfo 4.13"> 7<link title="Top" rel="start" href="index.html#Top"> 8<link rel="up" href="Machine-Dependent.html#Machine-Dependent" title="Machine Dependent"> 9<link rel="prev" href="i960.html#i960" title="i960"> 10<link rel="next" href="HPPA-ELF32.html#HPPA-ELF32" title="HPPA ELF32"> 11<link href="http://www.gnu.org/software/texinfo/" rel="generator-home" title="Texinfo Homepage"> 12<!-- 13This file documents the GNU linker LD 14(Sourcery CodeBench Lite 2011.09-69) 15version 2.21.53. 16 17Copyright (C) 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 182001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc. 19 20Permission is granted to copy, distribute and/or modify this document 21under the terms of the GNU Free Documentation License, Version 1.3 22or any later version published by the Free Software Foundation; 23with no Invariant Sections, with no Front-Cover Texts, and with no 24Back-Cover Texts. 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These stubs only work with code that has 54been compiled and assembled with the ‘<samp><span class="samp">-mthumb-interwork</span></samp>’ command 55line option. If it is necessary to link with old ARM object files or 56libraries, which have not been compiled with the -mthumb-interwork 57option then the ‘<samp><span class="samp">--support-old-code</span></samp>’ command line switch should be 58given to the linker. This will make it generate larger stub functions 59which will work with non-interworking aware ARM code. Note, however, 60the linker does not support generating stubs for function calls to 61non-interworking aware Thumb code. 62 63 <p><a name="index-thumb-entry-point-586"></a><a name="index-entry-point_002c-thumb-587"></a><a name="index-g_t_002d_002dthumb_002dentry_003d_0040var_007bentry_007d-588"></a>The ‘<samp><span class="samp">--thumb-entry</span></samp>’ switch is a duplicate of the generic 64‘<samp><span class="samp">--entry</span></samp>’ switch, in that it sets the program's starting address. 65But it also sets the bottom bit of the address, so that it can be 66branched to using a BX instruction, and the program will start 67executing in Thumb mode straight away. 68 69 <p><a name="index-PE-import-table-prefixing-589"></a><a name="index-g_t_002d_002duse_002dnul_002dprefixed_002dimport_002dtables-590"></a>The ‘<samp><span class="samp">--use-nul-prefixed-import-tables</span></samp>’ switch is specifying, that 70the import tables idata4 and idata5 have to be generated with a zero 71elememt prefix for import libraries. This is the old style to generate 72import tables. By default this option is turned off. 73 74 <p><a name="index-BE8-591"></a><a name="index-g_t_002d_002dbe8-592"></a>The ‘<samp><span class="samp">--be8</span></samp>’ switch instructs <samp><span class="command">ld</span></samp> to generate BE8 format 75executables. This option is only valid when linking big-endian objects. 76The resulting image will contain big-endian data and little-endian code. 77 78 <p><a name="index-TARGET1-593"></a><a name="index-g_t_002d_002dtarget1_002drel-594"></a><a name="index-g_t_002d_002dtarget1_002dabs-595"></a>The ‘<samp><span class="samp">R_ARM_TARGET1</span></samp>’ relocation is typically used for entries in the 79‘<samp><span class="samp">.init_array</span></samp>’ section. It is interpreted as either ‘<samp><span class="samp">R_ARM_REL32</span></samp>’ 80or ‘<samp><span class="samp">R_ARM_ABS32</span></samp>’, depending on the target. The ‘<samp><span class="samp">--target1-rel</span></samp>’ 81and ‘<samp><span class="samp">--target1-abs</span></samp>’ switches override the default. 82 83 <p><a name="index-TARGET2-596"></a><a name="index-g_t_002d_002dtarget2_003d_0040var_007btype_007d-597"></a>The ‘<samp><span class="samp">--target2=type</span></samp>’ switch overrides the default definition of the 84‘<samp><span class="samp">R_ARM_TARGET2</span></samp>’ relocation. Valid values for ‘<samp><span class="samp">type</span></samp>’, their 85meanings, and target defaults are as follows: 86 <dl> 87<dt>‘<samp><span class="samp">rel</span></samp>’<dd>‘<samp><span class="samp">R_ARM_REL32</span></samp>’ (arm*-*-elf, arm*-*-eabi) 88<br><dt>‘<samp><span class="samp">abs</span></samp>’<dd>‘<samp><span class="samp">R_ARM_ABS32</span></samp>’ (arm*-*-symbianelf) 89<br><dt>‘<samp><span class="samp">got-rel</span></samp>’<dd>‘<samp><span class="samp">R_ARM_GOT_PREL</span></samp>’ (arm*-*-linux, arm*-*-*bsd) 90</dl> 91 92 <p><a name="index-FIX_005fV4BX-598"></a><a name="index-g_t_002d_002dfix_002dv4bx-599"></a>The ‘<samp><span class="samp">R_ARM_V4BX</span></samp>’ relocation (defined by the ARM AAELF 93specification) enables objects compiled for the ARMv4 architecture to be 94interworking-safe when linked with other objects compiled for ARMv4t, but 95also allows pure ARMv4 binaries to be built from the same ARMv4 objects. 96 97 <p>In the latter case, the switch <samp><span class="option">--fix-v4bx</span></samp> must be passed to the 98linker, which causes v4t <code>BX rM</code> instructions to be rewritten as 99<code>MOV PC,rM</code>, since v4 processors do not have a <code>BX</code> instruction. 100 101 <p>In the former case, the switch should not be used, and ‘<samp><span class="samp">R_ARM_V4BX</span></samp>’ 102relocations are ignored. 103 104 <p><a name="index-FIX_005fV4BX_005fINTERWORKING-600"></a><a name="index-g_t_002d_002dfix_002dv4bx_002dinterworking-601"></a>Replace <code>BX rM</code> instructions identified by ‘<samp><span class="samp">R_ARM_V4BX</span></samp>’ 105relocations with a branch to the following veneer: 106 107<pre class="smallexample"> TST rM, #1 108 MOVEQ PC, rM 109 BX Rn 110</pre> 111 <p>This allows generation of libraries/applications that work on ARMv4 cores 112and are still interworking safe. Note that the above veneer clobbers the 113condition flags, so may cause incorrect progrm behavior in rare cases. 114 115 <p><a name="index-USE_005fBLX-602"></a><a name="index-g_t_002d_002duse_002dblx-603"></a>The ‘<samp><span class="samp">--use-blx</span></samp>’ switch enables the linker to use ARM/Thumb 116BLX instructions (available on ARMv5t and above) in various 117situations. Currently it is used to perform calls via the PLT from Thumb 118code using BLX rather than using BX and a mode-switching stub before 119each PLT entry. This should lead to such calls executing slightly faster. 120 121 <p>This option is enabled implicitly for SymbianOS, so there is no need to 122specify it if you are using that target. 123 124 <p><a name="index-VFP11_005fDENORM_005fFIX-604"></a><a name="index-g_t_002d_002dvfp11_002ddenorm_002dfix-605"></a>The ‘<samp><span class="samp">--vfp11-denorm-fix</span></samp>’ switch enables a link-time workaround for a 125bug in certain VFP11 coprocessor hardware, which sometimes allows 126instructions with denorm operands (which must be handled by support code) 127to have those operands overwritten by subsequent instructions before 128the support code can read the intended values. 129 130 <p>The bug may be avoided in scalar mode if you allow at least one 131intervening instruction between a VFP11 instruction which uses a register 132and another instruction which writes to the same register, or at least two 133intervening instructions if vector mode is in use. The bug only affects 134full-compliance floating-point mode: you do not need this workaround if 135you are using "runfast" mode. Please contact ARM for further details. 136 137 <p>This workaround is enabled for scalar code by default for 138pre-ARMv7 architectures, but disabled by default for later 139architectures. If you know you are not using buggy VFP11 hardware, 140you can disable the workaround by specifying the linker option 141‘<samp><span class="samp">--vfp-denorm-fix=none</span></samp>’. If you are using VFP vector mode, you 142should specify ‘<samp><span class="samp">--vfp-denorm-fix=vector</span></samp>’. 143 144 <p>If the workaround is enabled, instructions are scanned for 145potentially-troublesome sequences, and a veneer is created for each 146such sequence which may trigger the erratum. The veneer consists of the 147first instruction of the sequence and a branch back to the subsequent 148instruction. The original instruction is then replaced with a branch to 149the veneer. The extra cycles required to call and return from the veneer 150are sufficient to avoid the erratum in both the scalar and vector cases. 151 152 <p><a name="index-ARM1176-erratum-workaround-606"></a><a name="index-g_t_002d_002dfix_002darm1176-607"></a><a name="index-g_t_002d_002dno_002dfix_002darm1176-608"></a>The ‘<samp><span class="samp">--fix-arm1176</span></samp>’ switch enables a link-time workaround for an erratum 153in certain ARM1176 processors. The workaround is enabled by default if you 154are targetting ARM v6 (excluding ARM v6T2) or earlier. It can be disabled 155unconditionally by specifying ‘<samp><span class="samp">--no-fix-arm1176</span></samp>’. 156 157 <p>Further information is available in the “ARM1176JZ-S and ARM1176JZF-S 158Programmer Advice Notice” available on the ARM documentaion website at: 159http://infocenter.arm.com/. 160 161 <p><a name="index-NO_005fENUM_005fSIZE_005fWARNING-609"></a><a name="index-g_t_002d_002dno_002denum_002dsize_002dwarning-610"></a>The <samp><span class="option">--no-enum-size-warning</span></samp> switch prevents the linker from 162warning when linking object files that specify incompatible EABI 163enumeration size attributes. For example, with this switch enabled, 164linking of an object file using 32-bit enumeration values with another 165using enumeration values fitted into the smallest possible space will 166not be diagnosed. 167 168 <p><a name="index-NO_005fWCHAR_005fSIZE_005fWARNING-611"></a><a name="index-g_t_002d_002dno_002dwchar_002dsize_002dwarning-612"></a>The <samp><span class="option">--no-wchar-size-warning</span></samp> switch prevents the linker from 169warning when linking object files that specify incompatible EABI 170<code>wchar_t</code> size attributes. For example, with this switch enabled, 171linking of an object file using 32-bit <code>wchar_t</code> values with another 172using 16-bit <code>wchar_t</code> values will not be diagnosed. 173 174 <p><a name="index-PIC_005fVENEER-613"></a><a name="index-g_t_002d_002dpic_002dveneer-614"></a>The ‘<samp><span class="samp">--pic-veneer</span></samp>’ switch makes the linker use PIC sequences for 175ARM/Thumb interworking veneers, even if the rest of the binary 176is not PIC. This avoids problems on uClinux targets where 177‘<samp><span class="samp">--emit-relocs</span></samp>’ is used to generate relocatable binaries. 178 179 <p><a name="index-STUB_005fGROUP_005fSIZE-615"></a><a name="index-g_t_002d_002dstub_002dgroup_002dsize_003d_0040var_007bN_007d-616"></a>The linker will automatically generate and insert small sequences of 180code into a linked ARM ELF executable whenever an attempt is made to 181perform a function call to a symbol that is too far away. The 182placement of these sequences of instructions - called stubs - is 183controlled by the command line option <samp><span class="option">--stub-group-size=N</span></samp>. 184The placement is important because a poor choice can create a need for 185duplicate stubs, increasing the code sizw. The linker will try to 186group stubs together in order to reduce interruptions to the flow of 187code, but it needs guidance as to how big these groups should be and 188where they should be placed. 189 190 <p>The value of ‘<samp><span class="samp">N</span></samp>’, the parameter to the 191<samp><span class="option">--stub-group-size=</span></samp> option controls where the stub groups are 192placed. If it is negative then all stubs are placed after the first 193branch that needs them. If it is positive then the stubs can be 194placed either before or after the branches that need them. If the 195value of ‘<samp><span class="samp">N</span></samp>’ is 1 (either +1 or -1) then the linker will choose 196exactly where to place groups of stubs, using its built in heuristics. 197A value of ‘<samp><span class="samp">N</span></samp>’ greater than 1 (or smaller than -1) tells the 198linker that a single group of stubs can service at most ‘<samp><span class="samp">N</span></samp>’ bytes 199from the input sections. 200 201 <p>The default, if <samp><span class="option">--stub-group-size=</span></samp> is not specified, is 202‘<samp><span class="samp">N = +1</span></samp>’. 203 204 <p>Farcalls stubs insertion is fully supported for the ARM-EABI target 205only, because it relies on object files properties not present 206otherwise. 207 208 <p><a name="index-Cortex_002dA8-erratum-workaround-617"></a><a name="index-g_t_002d_002dfix_002dcortex_002da8-618"></a><a name="index-g_t_002d_002dno_002dfix_002dcortex_002da8-619"></a>The ‘<samp><span class="samp">--fix-cortex-a8</span></samp>’ switch enables a link-time workaround for an erratum in certain Cortex-A8 processors. The workaround is enabled by default if you are targeting the ARM v7-A architecture profile. It can be enabled otherwise by specifying ‘<samp><span class="samp">--fix-cortex-a8</span></samp>’, or disabled unconditionally by specifying ‘<samp><span class="samp">--no-fix-cortex-a8</span></samp>’. 209 210 <p>The erratum only affects Thumb-2 code. Please contact ARM for further details. 211 212 </body></html> 213 214