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55
56<h4 class="subsection">6.42.1 Simple Constraints</h4>
57
58<p><a name="index-simple-constraints-2628"></a>
59The simplest kind of constraint is a string full of letters, each of
60which describes one kind of operand that is permitted.  Here are
61the letters that are allowed:
62
63     <dl>
64<dt>whitespace<dd>Whitespace characters are ignored and can be inserted at any position
65except the first.  This enables each alternative for different operands to
66be visually aligned in the machine description even if they have different
67number of constraints and modifiers.
68
69     <p><a name="index-g_t_0040samp_007bm_007d-in-constraint-2629"></a><a name="index-memory-references-in-constraints-2630"></a><br><dt>&lsquo;<samp><span class="samp">m</span></samp>&rsquo;<dd>A memory operand is allowed, with any kind of address that the machine
70supports in general. 
71Note that the letter used for the general memory constraint can be
72re-defined by a back end using the <code>TARGET_MEM_CONSTRAINT</code> macro.
73
74     <p><a name="index-offsettable-address-2631"></a><a name="index-g_t_0040samp_007bo_007d-in-constraint-2632"></a><br><dt>&lsquo;<samp><span class="samp">o</span></samp>&rsquo;<dd>A memory operand is allowed, but only if the address is
75<dfn>offsettable</dfn>.  This means that adding a small integer (actually,
76the width in bytes of the operand, as determined by its machine mode)
77may be added to the address and the result is also a valid memory
78address.
79
80     <p><a name="index-autoincrement_002fdecrement-addressing-2633"></a>For example, an address which is constant is offsettable; so is an
81address that is the sum of a register and a constant (as long as a
82slightly larger constant is also within the range of address-offsets
83supported by the machine); but an autoincrement or autodecrement
84address is not offsettable.  More complicated indirect/indexed
85addresses may or may not be offsettable depending on the other
86addressing modes that the machine supports.
87
88     <p>Note that in an output operand which can be matched by another
89operand, the constraint letter &lsquo;<samp><span class="samp">o</span></samp>&rsquo; is valid only when accompanied
90by both &lsquo;<samp><span class="samp">&lt;</span></samp>&rsquo; (if the target machine has predecrement addressing)
91and &lsquo;<samp><span class="samp">&gt;</span></samp>&rsquo; (if the target machine has preincrement addressing).
92
93     <p><a name="index-g_t_0040samp_007bV_007d-in-constraint-2634"></a><br><dt>&lsquo;<samp><span class="samp">V</span></samp>&rsquo;<dd>A memory operand that is not offsettable.  In other words, anything that
94would fit the &lsquo;<samp><span class="samp">m</span></samp>&rsquo; constraint but not the &lsquo;<samp><span class="samp">o</span></samp>&rsquo; constraint.
95
96     <p><a name="index-g_t_0040samp_007b_003c_007d-in-constraint-2635"></a><br><dt>&lsquo;<samp><span class="samp">&lt;</span></samp>&rsquo;<dd>A memory operand with autodecrement addressing (either predecrement or
97postdecrement) is allowed.  In inline <code>asm</code> this constraint is only
98allowed if the operand is used exactly once in an instruction that can
99handle the side-effects.  Not using an operand with &lsquo;<samp><span class="samp">&lt;</span></samp>&rsquo; in constraint
100string in the inline <code>asm</code> pattern at all or using it in multiple
101instructions isn't valid, because the side-effects wouldn't be performed
102or would be performed more than once.  Furthermore, on some targets
103the operand with &lsquo;<samp><span class="samp">&lt;</span></samp>&rsquo; in constraint string must be accompanied by
104special instruction suffixes like <code>%U0</code> instruction suffix on PowerPC
105or <code>%P0</code> on IA-64.
106
107     <p><a name="index-g_t_0040samp_007b_003e_007d-in-constraint-2636"></a><br><dt>&lsquo;<samp><span class="samp">&gt;</span></samp>&rsquo;<dd>A memory operand with autoincrement addressing (either preincrement or
108postincrement) is allowed.  In inline <code>asm</code> the same restrictions
109as for &lsquo;<samp><span class="samp">&lt;</span></samp>&rsquo; apply.
110
111     <p><a name="index-g_t_0040samp_007br_007d-in-constraint-2637"></a><a name="index-registers-in-constraints-2638"></a><br><dt>&lsquo;<samp><span class="samp">r</span></samp>&rsquo;<dd>A register operand is allowed provided that it is in a general
112register.
113
114     <p><a name="index-constants-in-constraints-2639"></a><a name="index-g_t_0040samp_007bi_007d-in-constraint-2640"></a><br><dt>&lsquo;<samp><span class="samp">i</span></samp>&rsquo;<dd>An immediate integer operand (one with constant value) is allowed. 
115This includes symbolic constants whose values will be known only at
116assembly time or later.
117
118     <p><a name="index-g_t_0040samp_007bn_007d-in-constraint-2641"></a><br><dt>&lsquo;<samp><span class="samp">n</span></samp>&rsquo;<dd>An immediate integer operand with a known numeric value is allowed. 
119Many systems cannot support assembly-time constants for operands less
120than a word wide.  Constraints for these operands should use &lsquo;<samp><span class="samp">n</span></samp>&rsquo;
121rather than &lsquo;<samp><span class="samp">i</span></samp>&rsquo;.
122
123     <p><a name="index-g_t_0040samp_007bI_007d-in-constraint-2642"></a><br><dt>&lsquo;<samp><span class="samp">I</span></samp>&rsquo;, &lsquo;<samp><span class="samp">J</span></samp>&rsquo;, &lsquo;<samp><span class="samp">K</span></samp>&rsquo;, <small class="dots">...</small> &lsquo;<samp><span class="samp">P</span></samp>&rsquo;<dd>Other letters in the range &lsquo;<samp><span class="samp">I</span></samp>&rsquo; through &lsquo;<samp><span class="samp">P</span></samp>&rsquo; may be defined in
124a machine-dependent fashion to permit immediate integer operands with
125explicit integer values in specified ranges.  For example, on the
12668000, &lsquo;<samp><span class="samp">I</span></samp>&rsquo; is defined to stand for the range of values 1 to 8. 
127This is the range permitted as a shift count in the shift
128instructions.
129
130     <p><a name="index-g_t_0040samp_007bE_007d-in-constraint-2643"></a><br><dt>&lsquo;<samp><span class="samp">E</span></samp>&rsquo;<dd>An immediate floating operand (expression code <code>const_double</code>) is
131allowed, but only if the target floating point format is the same as
132that of the host machine (on which the compiler is running).
133
134     <p><a name="index-g_t_0040samp_007bF_007d-in-constraint-2644"></a><br><dt>&lsquo;<samp><span class="samp">F</span></samp>&rsquo;<dd>An immediate floating operand (expression code <code>const_double</code> or
135<code>const_vector</code>) is allowed.
136
137     <p><a name="index-g_t_0040samp_007bG_007d-in-constraint-2645"></a><a name="index-g_t_0040samp_007bH_007d-in-constraint-2646"></a><br><dt>&lsquo;<samp><span class="samp">G</span></samp>&rsquo;, &lsquo;<samp><span class="samp">H</span></samp>&rsquo;<dd>&lsquo;<samp><span class="samp">G</span></samp>&rsquo; and &lsquo;<samp><span class="samp">H</span></samp>&rsquo; may be defined in a machine-dependent fashion to
138permit immediate floating operands in particular ranges of values.
139
140     <p><a name="index-g_t_0040samp_007bs_007d-in-constraint-2647"></a><br><dt>&lsquo;<samp><span class="samp">s</span></samp>&rsquo;<dd>An immediate integer operand whose value is not an explicit integer is
141allowed.
142
143     <p>This might appear strange; if an insn allows a constant operand with a
144value not known at compile time, it certainly must allow any known
145value.  So why use &lsquo;<samp><span class="samp">s</span></samp>&rsquo; instead of &lsquo;<samp><span class="samp">i</span></samp>&rsquo;?  Sometimes it allows
146better code to be generated.
147
148     <p>For example, on the 68000 in a fullword instruction it is possible to
149use an immediate operand; but if the immediate value is between &minus;128
150and 127, better code results from loading the value into a register and
151using the register.  This is because the load into the register can be
152done with a &lsquo;<samp><span class="samp">moveq</span></samp>&rsquo; instruction.  We arrange for this to happen
153by defining the letter &lsquo;<samp><span class="samp">K</span></samp>&rsquo; to mean &ldquo;any integer outside the
154range &minus;128 to 127&rdquo;, and then specifying &lsquo;<samp><span class="samp">Ks</span></samp>&rsquo; in the operand
155constraints.
156
157     <p><a name="index-g_t_0040samp_007bg_007d-in-constraint-2648"></a><br><dt>&lsquo;<samp><span class="samp">g</span></samp>&rsquo;<dd>Any register, memory or immediate integer operand is allowed, except for
158registers that are not general registers.
159
160     <p><a name="index-g_t_0040samp_007bX_007d-in-constraint-2649"></a><br><dt>&lsquo;<samp><span class="samp">X</span></samp>&rsquo;<dd>Any operand whatsoever is allowed.
161
162     <p><a name="index-g_t_0040samp_007b0_007d-in-constraint-2650"></a><a name="index-digits-in-constraint-2651"></a><br><dt>&lsquo;<samp><span class="samp">0</span></samp>&rsquo;, &lsquo;<samp><span class="samp">1</span></samp>&rsquo;, &lsquo;<samp><span class="samp">2</span></samp>&rsquo;, <small class="dots">...</small> &lsquo;<samp><span class="samp">9</span></samp>&rsquo;<dd>An operand that matches the specified operand number is allowed.  If a
163digit is used together with letters within the same alternative, the
164digit should come last.
165
166     <p>This number is allowed to be more than a single digit.  If multiple
167digits are encountered consecutively, they are interpreted as a single
168decimal integer.  There is scant chance for ambiguity, since to-date
169it has never been desirable that &lsquo;<samp><span class="samp">10</span></samp>&rsquo; be interpreted as matching
170either operand 1 <em>or</em> operand 0.  Should this be desired, one
171can use multiple alternatives instead.
172
173     <p><a name="index-matching-constraint-2652"></a><a name="index-constraint_002c-matching-2653"></a>This is called a <dfn>matching constraint</dfn> and what it really means is
174that the assembler has only a single operand that fills two roles
175which <code>asm</code> distinguishes.  For example, an add instruction uses
176two input operands and an output operand, but on most CISC
177machines an add instruction really has only two operands, one of them an
178input-output operand:
179
180     <pre class="smallexample">          addl #35,r12
181</pre>
182     <p>Matching constraints are used in these circumstances. 
183More precisely, the two operands that match must include one input-only
184operand and one output-only operand.  Moreover, the digit must be a
185smaller number than the number of the operand that uses it in the
186constraint.
187
188     <p><a name="index-load-address-instruction-2654"></a><a name="index-push-address-instruction-2655"></a><a name="index-address-constraints-2656"></a><a name="index-g_t_0040samp_007bp_007d-in-constraint-2657"></a><br><dt>&lsquo;<samp><span class="samp">p</span></samp>&rsquo;<dd>An operand that is a valid memory address is allowed.  This is
189for &ldquo;load address&rdquo; and &ldquo;push address&rdquo; instructions.
190
191     <p><a name="index-address_005foperand-2658"></a>&lsquo;<samp><span class="samp">p</span></samp>&rsquo; in the constraint must be accompanied by <code>address_operand</code>
192as the predicate in the <code>match_operand</code>.  This predicate interprets
193the mode specified in the <code>match_operand</code> as the mode of the memory
194reference for which the address would be valid.
195
196     <p><a name="index-other-register-constraints-2659"></a><a name="index-extensible-constraints-2660"></a><br><dt><var>other-letters</var><dd>Other letters can be defined in machine-dependent fashion to stand for
197particular classes of registers or other arbitrary operand types. 
198&lsquo;<samp><span class="samp">d</span></samp>&rsquo;, &lsquo;<samp><span class="samp">a</span></samp>&rsquo; and &lsquo;<samp><span class="samp">f</span></samp>&rsquo; are defined on the 68000/68020 to stand
199for data, address and floating point registers. 
200</dl>
201
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