1<html lang="en"> 2<head> 3<title>SPARC Options - Using the GNU Compiler Collection (GCC)</title> 4<meta http-equiv="Content-Type" content="text/html"> 5<meta name="description" content="Using the GNU Compiler Collection (GCC)"> 6<meta name="generator" content="makeinfo 4.13"> 7<link title="Top" rel="start" href="index.html#Top"> 8<link rel="up" href="Submodel-Options.html#Submodel-Options" title="Submodel Options"> 9<link rel="prev" href="Solaris-2-Options.html#Solaris-2-Options" title="Solaris 2 Options"> 10<link rel="next" href="SPU-Options.html#SPU-Options" title="SPU Options"> 11<link href="http://www.gnu.org/software/texinfo/" rel="generator-home" title="Texinfo Homepage"> 12<!-- 13Copyright (C) 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 141998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 152010 Free Software Foundation, Inc. 16 17Permission is granted to copy, distribute and/or modify this document 18under the terms of the GNU Free Documentation License, Version 1.3 or 19any later version published by the Free Software Foundation; with the 20Invariant Sections being ``Funding Free Software'', the Front-Cover 21Texts being (a) (see below), and with the Back-Cover Texts being (b) 22(see below). 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This 66is the default. 67 68 <p>To be fully SVR4 ABI compliant at the cost of some performance loss, 69specify <samp><span class="option">-mno-app-regs</span></samp>. You should compile libraries and system 70software with this option. 71 72 <br><dt><code>-mfpu</code><dt><code>-mhard-float</code><dd><a name="index-mfpu-2063"></a><a name="index-mhard_002dfloat-2064"></a>Generate output containing floating point instructions. This is the 73default. 74 75 <br><dt><code>-mno-fpu</code><dt><code>-msoft-float</code><dd><a name="index-mno_002dfpu-2065"></a><a name="index-msoft_002dfloat-2066"></a>Generate output containing library calls for floating point. 76<strong>Warning:</strong> the requisite libraries are not available for all SPARC 77targets. Normally the facilities of the machine's usual C compiler are 78used, but this cannot be done directly in cross-compilation. You must make 79your own arrangements to provide suitable library functions for 80cross-compilation. The embedded targets ‘<samp><span class="samp">sparc-*-aout</span></samp>’ and 81‘<samp><span class="samp">sparclite-*-*</span></samp>’ do provide software floating point support. 82 83 <p><samp><span class="option">-msoft-float</span></samp> changes the calling convention in the output file; 84therefore, it is only useful if you compile <em>all</em> of a program with 85this option. In particular, you need to compile <samp><span class="file">libgcc.a</span></samp>, the 86library that comes with GCC, with <samp><span class="option">-msoft-float</span></samp> in order for 87this to work. 88 89 <br><dt><code>-mhard-quad-float</code><dd><a name="index-mhard_002dquad_002dfloat-2067"></a>Generate output containing quad-word (long double) floating point 90instructions. 91 92 <br><dt><code>-msoft-quad-float</code><dd><a name="index-msoft_002dquad_002dfloat-2068"></a>Generate output containing library calls for quad-word (long double) 93floating point instructions. The functions called are those specified 94in the SPARC ABI. This is the default. 95 96 <p>As of this writing, there are no SPARC implementations that have hardware 97support for the quad-word floating point instructions. They all invoke 98a trap handler for one of these instructions, and then the trap handler 99emulates the effect of the instruction. Because of the trap handler overhead, 100this is much slower than calling the ABI library routines. Thus the 101<samp><span class="option">-msoft-quad-float</span></samp> option is the default. 102 103 <br><dt><code>-mno-unaligned-doubles</code><dt><code>-munaligned-doubles</code><dd><a name="index-mno_002dunaligned_002ddoubles-2069"></a><a name="index-munaligned_002ddoubles-2070"></a>Assume that doubles have 8 byte alignment. This is the default. 104 105 <p>With <samp><span class="option">-munaligned-doubles</span></samp>, GCC assumes that doubles have 8 byte 106alignment only if they are contained in another type, or if they have an 107absolute address. Otherwise, it assumes they have 4 byte alignment. 108Specifying this option avoids some rare compatibility problems with code 109generated by other compilers. It is not the default because it results 110in a performance loss, especially for floating point code. 111 112 <br><dt><code>-mno-faster-structs</code><dt><code>-mfaster-structs</code><dd><a name="index-mno_002dfaster_002dstructs-2071"></a><a name="index-mfaster_002dstructs-2072"></a>With <samp><span class="option">-mfaster-structs</span></samp>, the compiler assumes that structures 113should have 8 byte alignment. This enables the use of pairs of 114<code>ldd</code> and <code>std</code> instructions for copies in structure 115assignment, in place of twice as many <code>ld</code> and <code>st</code> pairs. 116However, the use of this changed alignment directly violates the SPARC 117ABI. Thus, it's intended only for use on targets where the developer 118acknowledges that their resulting code will not be directly in line with 119the rules of the ABI. 120 121 <br><dt><code>-mcpu=</code><var>cpu_type</var><dd><a name="index-mcpu-2073"></a>Set the instruction set, register set, and instruction scheduling parameters 122for machine type <var>cpu_type</var>. Supported values for <var>cpu_type</var> are 123‘<samp><span class="samp">v7</span></samp>’, ‘<samp><span class="samp">cypress</span></samp>’, ‘<samp><span class="samp">v8</span></samp>’, ‘<samp><span class="samp">supersparc</span></samp>’, ‘<samp><span class="samp">hypersparc</span></samp>’, 124‘<samp><span class="samp">leon</span></samp>’, ‘<samp><span class="samp">sparclite</span></samp>’, ‘<samp><span class="samp">f930</span></samp>’, ‘<samp><span class="samp">f934</span></samp>’, ‘<samp><span class="samp">sparclite86x</span></samp>’, 125‘<samp><span class="samp">sparclet</span></samp>’, ‘<samp><span class="samp">tsc701</span></samp>’, ‘<samp><span class="samp">v9</span></samp>’, ‘<samp><span class="samp">ultrasparc</span></samp>’, 126‘<samp><span class="samp">ultrasparc3</span></samp>’, ‘<samp><span class="samp">niagara</span></samp>’ and ‘<samp><span class="samp">niagara2</span></samp>’. 127 128 <p>Default instruction scheduling parameters are used for values that select 129an architecture and not an implementation. These are ‘<samp><span class="samp">v7</span></samp>’, ‘<samp><span class="samp">v8</span></samp>’, 130‘<samp><span class="samp">sparclite</span></samp>’, ‘<samp><span class="samp">sparclet</span></samp>’, ‘<samp><span class="samp">v9</span></samp>’. 131 132 <p>Here is a list of each supported architecture and their supported 133implementations. 134 135 <pre class="smallexample"> v7: cypress 136 v8: supersparc, hypersparc, leon 137 sparclite: f930, f934, sparclite86x 138 sparclet: tsc701 139 v9: ultrasparc, ultrasparc3, niagara, niagara2 140</pre> 141 <p>By default (unless configured otherwise), GCC generates code for the V7 142variant of the SPARC architecture. With <samp><span class="option">-mcpu=cypress</span></samp>, the compiler 143additionally optimizes it for the Cypress CY7C602 chip, as used in the 144SPARCStation/SPARCServer 3xx series. This is also appropriate for the older 145SPARCStation 1, 2, IPX etc. 146 147 <p>With <samp><span class="option">-mcpu=v8</span></samp>, GCC generates code for the V8 variant of the SPARC 148architecture. The only difference from V7 code is that the compiler emits 149the integer multiply and integer divide instructions which exist in SPARC-V8 150but not in SPARC-V7. With <samp><span class="option">-mcpu=supersparc</span></samp>, the compiler additionally 151optimizes it for the SuperSPARC chip, as used in the SPARCStation 10, 1000 and 1522000 series. 153 154 <p>With <samp><span class="option">-mcpu=sparclite</span></samp>, GCC generates code for the SPARClite variant of 155the SPARC architecture. This adds the integer multiply, integer divide step 156and scan (<code>ffs</code>) instructions which exist in SPARClite but not in SPARC-V7. 157With <samp><span class="option">-mcpu=f930</span></samp>, the compiler additionally optimizes it for the 158Fujitsu MB86930 chip, which is the original SPARClite, with no FPU. With 159<samp><span class="option">-mcpu=f934</span></samp>, the compiler additionally optimizes it for the Fujitsu 160MB86934 chip, which is the more recent SPARClite with FPU. 161 162 <p>With <samp><span class="option">-mcpu=sparclet</span></samp>, GCC generates code for the SPARClet variant of 163the SPARC architecture. This adds the integer multiply, multiply/accumulate, 164integer divide step and scan (<code>ffs</code>) instructions which exist in SPARClet 165but not in SPARC-V7. With <samp><span class="option">-mcpu=tsc701</span></samp>, the compiler additionally 166optimizes it for the TEMIC SPARClet chip. 167 168 <p>With <samp><span class="option">-mcpu=v9</span></samp>, GCC generates code for the V9 variant of the SPARC 169architecture. This adds 64-bit integer and floating-point move instructions, 1703 additional floating-point condition code registers and conditional move 171instructions. With <samp><span class="option">-mcpu=ultrasparc</span></samp>, the compiler additionally 172optimizes it for the Sun UltraSPARC I/II/IIi chips. With 173<samp><span class="option">-mcpu=ultrasparc3</span></samp>, the compiler additionally optimizes it for the 174Sun UltraSPARC III/III+/IIIi/IIIi+/IV/IV+ chips. With 175<samp><span class="option">-mcpu=niagara</span></samp>, the compiler additionally optimizes it for 176Sun UltraSPARC T1 chips. With <samp><span class="option">-mcpu=niagara2</span></samp>, the compiler 177additionally optimizes it for Sun UltraSPARC T2 chips. 178 179 <br><dt><code>-mtune=</code><var>cpu_type</var><dd><a name="index-mtune-2074"></a>Set the instruction scheduling parameters for machine type 180<var>cpu_type</var>, but do not set the instruction set or register set that the 181option <samp><span class="option">-mcpu=</span><var>cpu_type</var></samp> would. 182 183 <p>The same values for <samp><span class="option">-mcpu=</span><var>cpu_type</var></samp> can be used for 184<samp><span class="option">-mtune=</span><var>cpu_type</var></samp>, but the only useful values are those 185that select a particular CPU implementation. Those are ‘<samp><span class="samp">cypress</span></samp>’, 186‘<samp><span class="samp">supersparc</span></samp>’, ‘<samp><span class="samp">hypersparc</span></samp>’, ‘<samp><span class="samp">leon</span></samp>’, ‘<samp><span class="samp">f930</span></samp>’, ‘<samp><span class="samp">f934</span></samp>’, 187‘<samp><span class="samp">sparclite86x</span></samp>’, ‘<samp><span class="samp">tsc701</span></samp>’, ‘<samp><span class="samp">ultrasparc</span></samp>’, ‘<samp><span class="samp">ultrasparc3</span></samp>’, 188‘<samp><span class="samp">niagara</span></samp>’, and ‘<samp><span class="samp">niagara2</span></samp>’. 189 190 <br><dt><code>-mv8plus</code><dt><code>-mno-v8plus</code><dd><a name="index-mv8plus-2075"></a><a name="index-mno_002dv8plus-2076"></a>With <samp><span class="option">-mv8plus</span></samp>, GCC generates code for the SPARC-V8+ ABI. The 191difference from the V8 ABI is that the global and out registers are 192considered 64-bit wide. This is enabled by default on Solaris in 32-bit 193mode for all SPARC-V9 processors. 194 195 <br><dt><code>-mvis</code><dt><code>-mno-vis</code><dd><a name="index-mvis-2077"></a><a name="index-mno_002dvis-2078"></a>With <samp><span class="option">-mvis</span></samp>, GCC generates code that takes advantage of the UltraSPARC 196Visual Instruction Set extensions. The default is <samp><span class="option">-mno-vis</span></samp>. 197</dl> 198 199 <p>These ‘<samp><span class="samp">-m</span></samp>’ options are supported in addition to the above 200on SPARC-V9 processors in 64-bit environments: 201 202 <dl> 203<dt><code>-mlittle-endian</code><dd><a name="index-mlittle_002dendian-2079"></a>Generate code for a processor running in little-endian mode. It is only 204available for a few configurations and most notably not on Solaris and Linux. 205 206 <br><dt><code>-m32</code><dt><code>-m64</code><dd><a name="index-m32-2080"></a><a name="index-m64-2081"></a>Generate code for a 32-bit or 64-bit environment. 207The 32-bit environment sets int, long and pointer to 32 bits. 208The 64-bit environment sets int to 32 bits and long and pointer 209to 64 bits. 210 211 <br><dt><code>-mcmodel=medlow</code><dd><a name="index-mcmodel_003dmedlow-2082"></a>Generate code for the Medium/Low code model: 64-bit addresses, programs 212must be linked in the low 32 bits of memory. Programs can be statically 213or dynamically linked. 214 215 <br><dt><code>-mcmodel=medmid</code><dd><a name="index-mcmodel_003dmedmid-2083"></a>Generate code for the Medium/Middle code model: 64-bit addresses, programs 216must be linked in the low 44 bits of memory, the text and data segments must 217be less than 2GB in size and the data segment must be located within 2GB of 218the text segment. 219 220 <br><dt><code>-mcmodel=medany</code><dd><a name="index-mcmodel_003dmedany-2084"></a>Generate code for the Medium/Anywhere code model: 64-bit addresses, programs 221may be linked anywhere in memory, the text and data segments must be less 222than 2GB in size and the data segment must be located within 2GB of the 223text segment. 224 225 <br><dt><code>-mcmodel=embmedany</code><dd><a name="index-mcmodel_003dembmedany-2085"></a>Generate code for the Medium/Anywhere code model for embedded systems: 22664-bit addresses, the text and data segments must be less than 2GB in 227size, both starting anywhere in memory (determined at link time). The 228global register %g4 points to the base of the data segment. Programs 229are statically linked and PIC is not supported. 230 231 <br><dt><code>-mstack-bias</code><dt><code>-mno-stack-bias</code><dd><a name="index-mstack_002dbias-2086"></a><a name="index-mno_002dstack_002dbias-2087"></a>With <samp><span class="option">-mstack-bias</span></samp>, GCC assumes that the stack pointer, and 232frame pointer if present, are offset by −2047 which must be added back 233when making stack frame references. This is the default in 64-bit mode. 234Otherwise, assume no such offset is present. 235</dl> 236 237 </body></html> 238 239