1<html lang="en"> 2<head> 3<title>RS/6000 and PowerPC Options - Using the GNU Compiler Collection (GCC)</title> 4<meta http-equiv="Content-Type" content="text/html"> 5<meta name="description" content="Using the GNU Compiler Collection (GCC)"> 6<meta name="generator" content="makeinfo 4.13"> 7<link title="Top" rel="start" href="index.html#Top"> 8<link rel="up" href="Submodel-Options.html#Submodel-Options" title="Submodel Options"> 9<link rel="prev" href="PowerPC-Options.html#PowerPC-Options" title="PowerPC Options"> 10<link rel="next" href="RX-Options.html#RX-Options" title="RX Options"> 11<link href="http://www.gnu.org/software/texinfo/" rel="generator-home" title="Texinfo Homepage"> 12<!-- 13Copyright (C) 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 141998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 152010 Free Software Foundation, Inc. 16 17Permission is granted to copy, distribute and/or modify this document 18under the terms of the GNU Free Documentation License, Version 1.3 or 19any later version published by the Free Software Foundation; with the 20Invariant Sections being ``Funding Free Software'', the Front-Cover 21Texts being (a) (see below), and with the Back-Cover Texts being (b) 22(see below). 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The <dfn>POWER</dfn> instruction set are those 66instructions supported by the ‘<samp><span class="samp">rios</span></samp>’ chip set used in the original 67RS/6000 systems and the <dfn>PowerPC</dfn> instruction set is the 68architecture of the Freescale MPC5xx, MPC6xx, MPC8xx microprocessors, and 69the IBM 4xx, 6xx, and follow-on microprocessors. 70 71 <p>Neither architecture is a subset of the other. However there is a 72large common subset of instructions supported by both. An MQ 73register is included in processors supporting the POWER architecture. 74 75 <p>You use these options to specify which instructions are available on the 76processor you are using. The default value of these options is 77determined when configuring GCC. Specifying the 78<samp><span class="option">-mcpu=</span><var>cpu_type</var></samp> overrides the specification of these 79options. We recommend you use the <samp><span class="option">-mcpu=</span><var>cpu_type</var></samp> option 80rather than the options listed above. 81 82 <p>The <samp><span class="option">-mpower</span></samp> option allows GCC to generate instructions that 83are found only in the POWER architecture and to use the MQ register. 84Specifying <samp><span class="option">-mpower2</span></samp> implies <samp><span class="option">-power</span></samp> and also allows GCC 85to generate instructions that are present in the POWER2 architecture but 86not the original POWER architecture. 87 88 <p>The <samp><span class="option">-mpowerpc</span></samp> option allows GCC to generate instructions that 89are found only in the 32-bit subset of the PowerPC architecture. 90Specifying <samp><span class="option">-mpowerpc-gpopt</span></samp> implies <samp><span class="option">-mpowerpc</span></samp> and also allows 91GCC to use the optional PowerPC architecture instructions in the 92General Purpose group, including floating-point square root. Specifying 93<samp><span class="option">-mpowerpc-gfxopt</span></samp> implies <samp><span class="option">-mpowerpc</span></samp> and also allows GCC to 94use the optional PowerPC architecture instructions in the Graphics 95group, including floating-point select. 96 97 <p>The <samp><span class="option">-mmfcrf</span></samp> option allows GCC to generate the move from 98condition register field instruction implemented on the POWER4 99processor and other processors that support the PowerPC V2.01 100architecture. 101The <samp><span class="option">-mpopcntb</span></samp> option allows GCC to generate the popcount and 102double precision FP reciprocal estimate instruction implemented on the 103POWER5 processor and other processors that support the PowerPC V2.02 104architecture. 105The <samp><span class="option">-mpopcntd</span></samp> option allows GCC to generate the popcount 106instruction implemented on the POWER7 processor and other processors 107that support the PowerPC V2.06 architecture. 108The <samp><span class="option">-mfprnd</span></samp> option allows GCC to generate the FP round to 109integer instructions implemented on the POWER5+ processor and other 110processors that support the PowerPC V2.03 architecture. 111The <samp><span class="option">-mcmpb</span></samp> option allows GCC to generate the compare bytes 112instruction implemented on the POWER6 processor and other processors 113that support the PowerPC V2.05 architecture. 114The <samp><span class="option">-mmfpgpr</span></samp> option allows GCC to generate the FP move to/from 115general purpose register instructions implemented on the POWER6X 116processor and other processors that support the extended PowerPC V2.05 117architecture. 118The <samp><span class="option">-mhard-dfp</span></samp> option allows GCC to generate the decimal floating 119point instructions implemented on some POWER processors. 120 121 <p>The <samp><span class="option">-mpowerpc64</span></samp> option allows GCC to generate the additional 12264-bit instructions that are found in the full PowerPC64 architecture 123and to treat GPRs as 64-bit, doubleword quantities. GCC defaults to 124<samp><span class="option">-mno-powerpc64</span></samp>. 125 126 <p>If you specify both <samp><span class="option">-mno-power</span></samp> and <samp><span class="option">-mno-powerpc</span></samp>, GCC 127will use only the instructions in the common subset of both 128architectures plus some special AIX common-mode calls, and will not use 129the MQ register. Specifying both <samp><span class="option">-mpower</span></samp> and <samp><span class="option">-mpowerpc</span></samp> 130permits GCC to use any instruction from either architecture and to 131allow use of the MQ register; specify this for the Motorola MPC601. 132 133 <br><dt><code>-mnew-mnemonics</code><dt><code>-mold-mnemonics</code><dd><a name="index-mnew_002dmnemonics-1825"></a><a name="index-mold_002dmnemonics-1826"></a>Select which mnemonics to use in the generated assembler code. With 134<samp><span class="option">-mnew-mnemonics</span></samp>, GCC uses the assembler mnemonics defined for 135the PowerPC architecture. With <samp><span class="option">-mold-mnemonics</span></samp> it uses the 136assembler mnemonics defined for the POWER architecture. Instructions 137defined in only one architecture have only one mnemonic; GCC uses that 138mnemonic irrespective of which of these options is specified. 139 140 <p>GCC defaults to the mnemonics appropriate for the architecture in 141use. Specifying <samp><span class="option">-mcpu=</span><var>cpu_type</var></samp> sometimes overrides the 142value of these option. Unless you are building a cross-compiler, you 143should normally not specify either <samp><span class="option">-mnew-mnemonics</span></samp> or 144<samp><span class="option">-mold-mnemonics</span></samp>, but should instead accept the default. 145 146 <br><dt><code>-mcpu=</code><var>cpu_type</var><dd><a name="index-mcpu-1827"></a>Set architecture type, register usage, choice of mnemonics, and 147instruction scheduling parameters for machine type <var>cpu_type</var>. 148Supported values for <var>cpu_type</var> are ‘<samp><span class="samp">401</span></samp>’, ‘<samp><span class="samp">403</span></samp>’, 149‘<samp><span class="samp">405</span></samp>’, ‘<samp><span class="samp">405fp</span></samp>’, ‘<samp><span class="samp">440</span></samp>’, ‘<samp><span class="samp">440fp</span></samp>’, ‘<samp><span class="samp">464</span></samp>’, ‘<samp><span class="samp">464fp</span></samp>’, 150‘<samp><span class="samp">476</span></samp>’, ‘<samp><span class="samp">476fp</span></samp>’, ‘<samp><span class="samp">505</span></samp>’, ‘<samp><span class="samp">601</span></samp>’, ‘<samp><span class="samp">602</span></samp>’, ‘<samp><span class="samp">603</span></samp>’, 151‘<samp><span class="samp">603e</span></samp>’, ‘<samp><span class="samp">604</span></samp>’, ‘<samp><span class="samp">604e</span></samp>’, ‘<samp><span class="samp">620</span></samp>’, ‘<samp><span class="samp">630</span></samp>’, ‘<samp><span class="samp">740</span></samp>’, 152‘<samp><span class="samp">7400</span></samp>’, ‘<samp><span class="samp">7450</span></samp>’, ‘<samp><span class="samp">750</span></samp>’, ‘<samp><span class="samp">801</span></samp>’, ‘<samp><span class="samp">821</span></samp>’, ‘<samp><span class="samp">823</span></samp>’, 153‘<samp><span class="samp">860</span></samp>’, ‘<samp><span class="samp">970</span></samp>’, ‘<samp><span class="samp">8540</span></samp>’, ‘<samp><span class="samp">a2</span></samp>’, ‘<samp><span class="samp">e300c2</span></samp>’, 154‘<samp><span class="samp">e300c3</span></samp>’, ‘<samp><span class="samp">e500mc</span></samp>’, ‘<samp><span class="samp">e500mc64</span></samp>’, ‘<samp><span class="samp">ec603e</span></samp>’, ‘<samp><span class="samp">G3</span></samp>’, 155‘<samp><span class="samp">G4</span></samp>’, ‘<samp><span class="samp">G5</span></samp>’, ‘<samp><span class="samp">titan</span></samp>’, ‘<samp><span class="samp">power</span></samp>’, ‘<samp><span class="samp">power2</span></samp>’, ‘<samp><span class="samp">power3</span></samp>’, 156‘<samp><span class="samp">power4</span></samp>’, ‘<samp><span class="samp">power5</span></samp>’, ‘<samp><span class="samp">power5+</span></samp>’, ‘<samp><span class="samp">power6</span></samp>’, ‘<samp><span class="samp">power6x</span></samp>’, 157‘<samp><span class="samp">power7</span></samp>’, ‘<samp><span class="samp">common</span></samp>’, ‘<samp><span class="samp">powerpc</span></samp>’, ‘<samp><span class="samp">powerpc64</span></samp>’, ‘<samp><span class="samp">rios</span></samp>’, 158‘<samp><span class="samp">rios1</span></samp>’, ‘<samp><span class="samp">rios2</span></samp>’, ‘<samp><span class="samp">rsc</span></samp>’, and ‘<samp><span class="samp">rs64</span></samp>’. 159 160 <p><samp><span class="option">-mcpu=common</span></samp> selects a completely generic processor. Code 161generated under this option will run on any POWER or PowerPC processor. 162GCC will use only the instructions in the common subset of both 163architectures, and will not use the MQ register. GCC assumes a generic 164processor model for scheduling purposes. 165 166 <p><samp><span class="option">-mcpu=power</span></samp>, <samp><span class="option">-mcpu=power2</span></samp>, <samp><span class="option">-mcpu=powerpc</span></samp>, and 167<samp><span class="option">-mcpu=powerpc64</span></samp> specify generic POWER, POWER2, pure 32-bit 168PowerPC (i.e., not MPC601), and 64-bit PowerPC architecture machine 169types, with an appropriate, generic processor model assumed for 170scheduling purposes. 171 172 <p>The other options specify a specific processor. Code generated under 173those options will run best on that processor, and may not run at all on 174others. 175 176 <p>The <samp><span class="option">-mcpu</span></samp> options automatically enable or disable the 177following options: 178 179 <pre class="smallexample"> -maltivec -mfprnd -mhard-float -mmfcrf -mmultiple 180 -mnew-mnemonics -mpopcntb -mpopcntd -mpower -mpower2 -mpowerpc64 181 -mpowerpc-gpopt -mpowerpc-gfxopt -msingle-float -mdouble-float 182 -msimple-fpu -mstring -mmulhw -mdlmzb -mmfpgpr -mvsx 183</pre> 184 <p>The particular options set for any particular CPU will vary between 185compiler versions, depending on what setting seems to produce optimal 186code for that CPU; it doesn't necessarily reflect the actual hardware's 187capabilities. If you wish to set an individual option to a particular 188value, you may specify it after the <samp><span class="option">-mcpu</span></samp> option, like 189‘<samp><span class="samp">-mcpu=970 -mno-altivec</span></samp>’. 190 191 <p>On AIX, the <samp><span class="option">-maltivec</span></samp> and <samp><span class="option">-mpowerpc64</span></samp> options are 192not enabled or disabled by the <samp><span class="option">-mcpu</span></samp> option at present because 193AIX does not have full support for these options. You may still 194enable or disable them individually if you're sure it'll work in your 195environment. 196 197 <br><dt><code>-mtune=</code><var>cpu_type</var><dd><a name="index-mtune-1828"></a>Set the instruction scheduling parameters for machine type 198<var>cpu_type</var>, but do not set the architecture type, register usage, or 199choice of mnemonics, as <samp><span class="option">-mcpu=</span><var>cpu_type</var></samp> would. The same 200values for <var>cpu_type</var> are used for <samp><span class="option">-mtune</span></samp> as for 201<samp><span class="option">-mcpu</span></samp>. If both are specified, the code generated will use the 202architecture, registers, and mnemonics set by <samp><span class="option">-mcpu</span></samp>, but the 203scheduling parameters set by <samp><span class="option">-mtune</span></samp>. 204 205 <br><dt><code>-mcmodel=small</code><dd><a name="index-mcmodel_003dsmall-1829"></a>Generate PowerPC64 code for the small model: The TOC is limited to 20664k. 207 208 <br><dt><code>-mcmodel=medium</code><dd><a name="index-mcmodel_003dmedium-1830"></a>Generate PowerPC64 code for the medium model: The TOC and other static 209data may be up to a total of 4G in size. 210 211 <br><dt><code>-mcmodel=large</code><dd><a name="index-mcmodel_003dlarge-1831"></a>Generate PowerPC64 code for the large model: The TOC may be up to 4G 212in size. Other data and code is only limited by the 64-bit address 213space. 214 215 <br><dt><code>-maltivec</code><dt><code>-mno-altivec</code><dd><a name="index-maltivec-1832"></a><a name="index-mno_002daltivec-1833"></a>Generate code that uses (does not use) AltiVec instructions, and also 216enable the use of built-in functions that allow more direct access to 217the AltiVec instruction set. You may also need to set 218<samp><span class="option">-mabi=altivec</span></samp> to adjust the current ABI with AltiVec ABI 219enhancements. 220 221 <br><dt><code>-mvrsave</code><dt><code>-mno-vrsave</code><dd><a name="index-mvrsave-1834"></a><a name="index-mno_002dvrsave-1835"></a>Generate VRSAVE instructions when generating AltiVec code. 222 223 <br><dt><code>-mgen-cell-microcode</code><dd><a name="index-mgen_002dcell_002dmicrocode-1836"></a>Generate Cell microcode instructions 224 225 <br><dt><code>-mwarn-cell-microcode</code><dd><a name="index-mwarn_002dcell_002dmicrocode-1837"></a>Warning when a Cell microcode instruction is going to emitted. An example 226of a Cell microcode instruction is a variable shift. 227 228 <br><dt><code>-msecure-plt</code><dd><a name="index-msecure_002dplt-1838"></a>Generate code that allows ld and ld.so to build executables and shared 229libraries with non-exec .plt and .got sections. This is a PowerPC 23032-bit SYSV ABI option. 231 232 <br><dt><code>-mbss-plt</code><dd><a name="index-mbss_002dplt-1839"></a>Generate code that uses a BSS .plt section that ld.so fills in, and 233requires .plt and .got sections that are both writable and executable. 234This is a PowerPC 32-bit SYSV ABI option. 235 236 <br><dt><code>-misel</code><dt><code>-mno-isel</code><dd><a name="index-misel-1840"></a><a name="index-mno_002disel-1841"></a>This switch enables or disables the generation of ISEL instructions. 237 238 <br><dt><code>-misel=</code><var>yes/no</var><dd>This switch has been deprecated. Use <samp><span class="option">-misel</span></samp> and 239<samp><span class="option">-mno-isel</span></samp> instead. 240 241 <br><dt><code>-mspe</code><dt><code>-mno-spe</code><dd><a name="index-mspe-1842"></a><a name="index-mno_002dspe-1843"></a>This switch enables or disables the generation of SPE simd 242instructions. 243 244 <br><dt><code>-mpaired</code><dt><code>-mno-paired</code><dd><a name="index-mpaired-1844"></a><a name="index-mno_002dpaired-1845"></a>This switch enables or disables the generation of PAIRED simd 245instructions. 246 247 <br><dt><code>-mspe=</code><var>yes/no</var><dd>This option has been deprecated. Use <samp><span class="option">-mspe</span></samp> and 248<samp><span class="option">-mno-spe</span></samp> instead. 249 250 <br><dt><code>-mvsx</code><dt><code>-mno-vsx</code><dd><a name="index-mvsx-1846"></a><a name="index-mno_002dvsx-1847"></a>Generate code that uses (does not use) vector/scalar (VSX) 251instructions, and also enable the use of built-in functions that allow 252more direct access to the VSX instruction set. 253 254 <br><dt><code>-mfloat-gprs=</code><var>yes/single/double/no</var><dt><code>-mfloat-gprs</code><dd><a name="index-mfloat_002dgprs-1848"></a>This switch enables or disables the generation of floating point 255operations on the general purpose registers for architectures that 256support it. 257 258 <p>The argument <var>yes</var> or <var>single</var> enables the use of 259single-precision floating point operations. 260 261 <p>The argument <var>double</var> enables the use of single and 262double-precision floating point operations. 263 264 <p>The argument <var>no</var> disables floating point operations on the 265general purpose registers. 266 267 <p>This option is currently only available on the MPC854x. 268 269 <br><dt><code>-m32</code><dt><code>-m64</code><dd><a name="index-m32-1849"></a><a name="index-m64-1850"></a>Generate code for 32-bit or 64-bit environments of Darwin and SVR4 270targets (including GNU/Linux). The 32-bit environment sets int, long 271and pointer to 32 bits and generates code that runs on any PowerPC 272variant. The 64-bit environment sets int to 32 bits and long and 273pointer to 64 bits, and generates code for PowerPC64, as for 274<samp><span class="option">-mpowerpc64</span></samp>. 275 276 <br><dt><code>-mfull-toc</code><dt><code>-mno-fp-in-toc</code><dt><code>-mno-sum-in-toc</code><dt><code>-mminimal-toc</code><dd><a name="index-mfull_002dtoc-1851"></a><a name="index-mno_002dfp_002din_002dtoc-1852"></a><a name="index-mno_002dsum_002din_002dtoc-1853"></a><a name="index-mminimal_002dtoc-1854"></a>Modify generation of the TOC (Table Of Contents), which is created for 277every executable file. The <samp><span class="option">-mfull-toc</span></samp> option is selected by 278default. In that case, GCC will allocate at least one TOC entry for 279each unique non-automatic variable reference in your program. GCC 280will also place floating-point constants in the TOC. However, only 28116,384 entries are available in the TOC. 282 283 <p>If you receive a linker error message that saying you have overflowed 284the available TOC space, you can reduce the amount of TOC space used 285with the <samp><span class="option">-mno-fp-in-toc</span></samp> and <samp><span class="option">-mno-sum-in-toc</span></samp> options. 286<samp><span class="option">-mno-fp-in-toc</span></samp> prevents GCC from putting floating-point 287constants in the TOC and <samp><span class="option">-mno-sum-in-toc</span></samp> forces GCC to 288generate code to calculate the sum of an address and a constant at 289run-time instead of putting that sum into the TOC. You may specify one 290or both of these options. Each causes GCC to produce very slightly 291slower and larger code at the expense of conserving TOC space. 292 293 <p>If you still run out of space in the TOC even when you specify both of 294these options, specify <samp><span class="option">-mminimal-toc</span></samp> instead. This option causes 295GCC to make only one TOC entry for every file. When you specify this 296option, GCC will produce code that is slower and larger but which 297uses extremely little TOC space. You may wish to use this option 298only on files that contain less frequently executed code. 299 300 <br><dt><code>-maix64</code><dt><code>-maix32</code><dd><a name="index-maix64-1855"></a><a name="index-maix32-1856"></a>Enable 64-bit AIX ABI and calling convention: 64-bit pointers, 64-bit 301<code>long</code> type, and the infrastructure needed to support them. 302Specifying <samp><span class="option">-maix64</span></samp> implies <samp><span class="option">-mpowerpc64</span></samp> and 303<samp><span class="option">-mpowerpc</span></samp>, while <samp><span class="option">-maix32</span></samp> disables the 64-bit ABI and 304implies <samp><span class="option">-mno-powerpc64</span></samp>. GCC defaults to <samp><span class="option">-maix32</span></samp>. 305 306 <br><dt><code>-mxl-compat</code><dt><code>-mno-xl-compat</code><dd><a name="index-mxl_002dcompat-1857"></a><a name="index-mno_002dxl_002dcompat-1858"></a>Produce code that conforms more closely to IBM XL compiler semantics 307when using AIX-compatible ABI. Pass floating-point arguments to 308prototyped functions beyond the register save area (RSA) on the stack 309in addition to argument FPRs. Do not assume that most significant 310double in 128-bit long double value is properly rounded when comparing 311values and converting to double. Use XL symbol names for long double 312support routines. 313 314 <p>The AIX calling convention was extended but not initially documented to 315handle an obscure K&R C case of calling a function that takes the 316address of its arguments with fewer arguments than declared. IBM XL 317compilers access floating point arguments which do not fit in the 318RSA from the stack when a subroutine is compiled without 319optimization. Because always storing floating-point arguments on the 320stack is inefficient and rarely needed, this option is not enabled by 321default and only is necessary when calling subroutines compiled by IBM 322XL compilers without optimization. 323 324 <br><dt><code>-mpe</code><dd><a name="index-mpe-1859"></a>Support <dfn>IBM RS/6000 SP</dfn> <dfn>Parallel Environment</dfn> (PE). Link an 325application written to use message passing with special startup code to 326enable the application to run. The system must have PE installed in the 327standard location (<samp><span class="file">/usr/lpp/ppe.poe/</span></samp>), or the <samp><span class="file">specs</span></samp> file 328must be overridden with the <samp><span class="option">-specs=</span></samp> option to specify the 329appropriate directory location. The Parallel Environment does not 330support threads, so the <samp><span class="option">-mpe</span></samp> option and the <samp><span class="option">-pthread</span></samp> 331option are incompatible. 332 333 <br><dt><code>-malign-natural</code><dt><code>-malign-power</code><dd><a name="index-malign_002dnatural-1860"></a><a name="index-malign_002dpower-1861"></a>On AIX, 32-bit Darwin, and 64-bit PowerPC GNU/Linux, the option 334<samp><span class="option">-malign-natural</span></samp> overrides the ABI-defined alignment of larger 335types, such as floating-point doubles, on their natural size-based boundary. 336The option <samp><span class="option">-malign-power</span></samp> instructs GCC to follow the ABI-specified 337alignment rules. GCC defaults to the standard alignment defined in the ABI. 338 339 <p>On 64-bit Darwin, natural alignment is the default, and <samp><span class="option">-malign-power</span></samp> 340is not supported. 341 342 <br><dt><code>-msoft-float</code><dt><code>-mhard-float</code><dd><a name="index-msoft_002dfloat-1862"></a><a name="index-mhard_002dfloat-1863"></a>Generate code that does not use (uses) the floating-point register set. 343Software floating point emulation is provided if you use the 344<samp><span class="option">-msoft-float</span></samp> option, and pass the option to GCC when linking. 345 346 <br><dt><code>-msingle-float</code><dt><code>-mdouble-float</code><dd><a name="index-msingle_002dfloat-1864"></a><a name="index-mdouble_002dfloat-1865"></a>Generate code for single or double-precision floating point operations. 347<samp><span class="option">-mdouble-float</span></samp> implies <samp><span class="option">-msingle-float</span></samp>. 348 349 <br><dt><code>-msimple-fpu</code><dd><a name="index-msimple_002dfpu-1866"></a>Do not generate sqrt and div instructions for hardware floating point unit. 350 351 <br><dt><code>-mfpu</code><dd><a name="index-mfpu-1867"></a>Specify type of floating point unit. Valid values are <var>sp_lite</var> 352(equivalent to -msingle-float -msimple-fpu), <var>dp_lite</var> (equivalent 353to -mdouble-float -msimple-fpu), <var>sp_full</var> (equivalent to -msingle-float), 354and <var>dp_full</var> (equivalent to -mdouble-float). 355 356 <br><dt><code>-mxilinx-fpu</code><dd><a name="index-mxilinx_002dfpu-1868"></a>Perform optimizations for floating point unit on Xilinx PPC 405/440. 357 358 <br><dt><code>-mmultiple</code><dt><code>-mno-multiple</code><dd><a name="index-mmultiple-1869"></a><a name="index-mno_002dmultiple-1870"></a>Generate code that uses (does not use) the load multiple word 359instructions and the store multiple word instructions. These 360instructions are generated by default on POWER systems, and not 361generated on PowerPC systems. Do not use <samp><span class="option">-mmultiple</span></samp> on little 362endian PowerPC systems, since those instructions do not work when the 363processor is in little endian mode. The exceptions are PPC740 and 364PPC750 which permit the instructions usage in little endian mode. 365 366 <br><dt><code>-mstring</code><dt><code>-mno-string</code><dd><a name="index-mstring-1871"></a><a name="index-mno_002dstring-1872"></a>Generate code that uses (does not use) the load string instructions 367and the store string word instructions to save multiple registers and 368do small block moves. These instructions are generated by default on 369POWER systems, and not generated on PowerPC systems. Do not use 370<samp><span class="option">-mstring</span></samp> on little endian PowerPC systems, since those 371instructions do not work when the processor is in little endian mode. 372The exceptions are PPC740 and PPC750 which permit the instructions 373usage in little endian mode. 374 375 <br><dt><code>-mupdate</code><dt><code>-mno-update</code><dd><a name="index-mupdate-1873"></a><a name="index-mno_002dupdate-1874"></a>Generate code that uses (does not use) the load or store instructions 376that update the base register to the address of the calculated memory 377location. These instructions are generated by default. If you use 378<samp><span class="option">-mno-update</span></samp>, there is a small window between the time that the 379stack pointer is updated and the address of the previous frame is 380stored, which means code that walks the stack frame across interrupts or 381signals may get corrupted data. 382 383 <br><dt><code>-mavoid-indexed-addresses</code><dt><code>-mno-avoid-indexed-addresses</code><dd><a name="index-mavoid_002dindexed_002daddresses-1875"></a><a name="index-mno_002davoid_002dindexed_002daddresses-1876"></a>Generate code that tries to avoid (not avoid) the use of indexed load 384or store instructions. These instructions can incur a performance 385penalty on Power6 processors in certain situations, such as when 386stepping through large arrays that cross a 16M boundary. This option 387is enabled by default when targetting Power6 and disabled otherwise. 388 389 <br><dt><code>-mfused-madd</code><dt><code>-mno-fused-madd</code><dd><a name="index-mfused_002dmadd-1877"></a><a name="index-mno_002dfused_002dmadd-1878"></a>Generate code that uses (does not use) the floating point multiply and 390accumulate instructions. These instructions are generated by default 391if hardware floating point is used. The machine dependent 392<samp><span class="option">-mfused-madd</span></samp> option is now mapped to the machine independent 393<samp><span class="option">-ffp-contract=fast</span></samp> option, and <samp><span class="option">-mno-fused-madd</span></samp> is 394mapped to <samp><span class="option">-ffp-contract=off</span></samp>. 395 396 <br><dt><code>-mmulhw</code><dt><code>-mno-mulhw</code><dd><a name="index-mmulhw-1879"></a><a name="index-mno_002dmulhw-1880"></a>Generate code that uses (does not use) the half-word multiply and 397multiply-accumulate instructions on the IBM 405, 440, 464 and 476 processors. 398These instructions are generated by default when targetting those 399processors. 400 401 <br><dt><code>-mdlmzb</code><dt><code>-mno-dlmzb</code><dd><a name="index-mdlmzb-1881"></a><a name="index-mno_002ddlmzb-1882"></a>Generate code that uses (does not use) the string-search ‘<samp><span class="samp">dlmzb</span></samp>’ 402instruction on the IBM 405, 440, 464 and 476 processors. This instruction is 403generated by default when targetting those processors. 404 405 <br><dt><code>-mno-bit-align</code><dt><code>-mbit-align</code><dd><a name="index-mno_002dbit_002dalign-1883"></a><a name="index-mbit_002dalign-1884"></a>On System V.4 and embedded PowerPC systems do not (do) force structures 406and unions that contain bit-fields to be aligned to the base type of the 407bit-field. 408 409 <p>For example, by default a structure containing nothing but 8 410<code>unsigned</code> bit-fields of length 1 would be aligned to a 4 byte 411boundary and have a size of 4 bytes. By using <samp><span class="option">-mno-bit-align</span></samp>, 412the structure would be aligned to a 1 byte boundary and be one byte in 413size. 414 415 <br><dt><code>-mno-strict-align</code><dt><code>-mstrict-align</code><dd><a name="index-mno_002dstrict_002dalign-1885"></a><a name="index-mstrict_002dalign-1886"></a>On System V.4 and embedded PowerPC systems do not (do) assume that 416unaligned memory references will be handled by the system. 417 418 <br><dt><code>-mrelocatable</code><dt><code>-mno-relocatable</code><dd><a name="index-mrelocatable-1887"></a><a name="index-mno_002drelocatable-1888"></a>Generate code that allows (does not allow) a static executable to be 419relocated to a different address at runtime. A simple embedded 420PowerPC system loader should relocate the entire contents of 421<code>.got2</code> and 4-byte locations listed in the <code>.fixup</code> section, 422a table of 32-bit addresses generated by this option. For this to 423work, all objects linked together must be compiled with 424<samp><span class="option">-mrelocatable</span></samp> or <samp><span class="option">-mrelocatable-lib</span></samp>. 425<samp><span class="option">-mrelocatable</span></samp> code aligns the stack to an 8 byte boundary. 426 427 <br><dt><code>-mrelocatable-lib</code><dt><code>-mno-relocatable-lib</code><dd><a name="index-mrelocatable_002dlib-1889"></a><a name="index-mno_002drelocatable_002dlib-1890"></a>Like <samp><span class="option">-mrelocatable</span></samp>, <samp><span class="option">-mrelocatable-lib</span></samp> generates a 428<code>.fixup</code> section to allow static executables to be relocated at 429runtime, but <samp><span class="option">-mrelocatable-lib</span></samp> does not use the smaller stack 430alignment of <samp><span class="option">-mrelocatable</span></samp>. Objects compiled with 431<samp><span class="option">-mrelocatable-lib</span></samp> may be linked with objects compiled with 432any combination of the <samp><span class="option">-mrelocatable</span></samp> options. 433 434 <br><dt><code>-mno-toc</code><dt><code>-mtoc</code><dd><a name="index-mno_002dtoc-1891"></a><a name="index-mtoc-1892"></a>On System V.4 and embedded PowerPC systems do not (do) assume that 435register 2 contains a pointer to a global area pointing to the addresses 436used in the program. 437 438 <br><dt><code>-mlittle</code><dt><code>-mlittle-endian</code><dd><a name="index-mlittle-1893"></a><a name="index-mlittle_002dendian-1894"></a>On System V.4 and embedded PowerPC systems compile code for the 439processor in little endian mode. The <samp><span class="option">-mlittle-endian</span></samp> option is 440the same as <samp><span class="option">-mlittle</span></samp>. 441 442 <br><dt><code>-mbig</code><dt><code>-mbig-endian</code><dd><a name="index-mbig-1895"></a><a name="index-mbig_002dendian-1896"></a>On System V.4 and embedded PowerPC systems compile code for the 443processor in big endian mode. The <samp><span class="option">-mbig-endian</span></samp> option is 444the same as <samp><span class="option">-mbig</span></samp>. 445 446 <br><dt><code>-mdynamic-no-pic</code><dd><a name="index-mdynamic_002dno_002dpic-1897"></a>On Darwin and Mac OS X systems, compile code so that it is not 447relocatable, but that its external references are relocatable. The 448resulting code is suitable for applications, but not shared 449libraries. 450 451 <br><dt><code>-msingle-pic-base</code><dd><a name="index-msingle_002dpic_002dbase-1898"></a>Treat the register used for PIC addressing as read-only, rather than 452loading it in the prologue for each function. The run-time system is 453responsible for initializing this register with an appropriate value 454before execution begins. 455 456 <br><dt><code>-mprioritize-restricted-insns=</code><var>priority</var><dd><a name="index-mprioritize_002drestricted_002dinsns-1899"></a>This option controls the priority that is assigned to 457dispatch-slot restricted instructions during the second scheduling 458pass. The argument <var>priority</var> takes the value <var>0/1/2</var> to assign 459<var>no/highest/second-highest</var> priority to dispatch slot restricted 460instructions. 461 462 <br><dt><code>-msched-costly-dep=</code><var>dependence_type</var><dd><a name="index-msched_002dcostly_002ddep-1900"></a>This option controls which dependences are considered costly 463by the target during instruction scheduling. The argument 464<var>dependence_type</var> takes one of the following values: 465<var>no</var>: no dependence is costly, 466<var>all</var>: all dependences are costly, 467<var>true_store_to_load</var>: a true dependence from store to load is costly, 468<var>store_to_load</var>: any dependence from store to load is costly, 469<var>number</var>: any dependence which latency >= <var>number</var> is costly. 470 471 <br><dt><code>-minsert-sched-nops=</code><var>scheme</var><dd><a name="index-minsert_002dsched_002dnops-1901"></a>This option controls which nop insertion scheme will be used during 472the second scheduling pass. The argument <var>scheme</var> takes one of the 473following values: 474<var>no</var>: Don't insert nops. 475<var>pad</var>: Pad with nops any dispatch group which has vacant issue slots, 476according to the scheduler's grouping. 477<var>regroup_exact</var>: Insert nops to force costly dependent insns into 478separate groups. Insert exactly as many nops as needed to force an insn 479to a new group, according to the estimated processor grouping. 480<var>number</var>: Insert nops to force costly dependent insns into 481separate groups. Insert <var>number</var> nops to force an insn to a new group. 482 483 <br><dt><code>-mcall-sysv</code><dd><a name="index-mcall_002dsysv-1902"></a>On System V.4 and embedded PowerPC systems compile code using calling 484conventions that adheres to the March 1995 draft of the System V 485Application Binary Interface, PowerPC processor supplement. This is the 486default unless you configured GCC using ‘<samp><span class="samp">powerpc-*-eabiaix</span></samp>’. 487 488 <br><dt><code>-mcall-sysv-eabi</code><dt><code>-mcall-eabi</code><dd><a name="index-mcall_002dsysv_002deabi-1903"></a><a name="index-mcall_002deabi-1904"></a>Specify both <samp><span class="option">-mcall-sysv</span></samp> and <samp><span class="option">-meabi</span></samp> options. 489 490 <br><dt><code>-mcall-sysv-noeabi</code><dd><a name="index-mcall_002dsysv_002dnoeabi-1905"></a>Specify both <samp><span class="option">-mcall-sysv</span></samp> and <samp><span class="option">-mno-eabi</span></samp> options. 491 492 <br><dt><code>-mcall-aixdesc</code><dd><a name="index-m-1906"></a>On System V.4 and embedded PowerPC systems compile code for the AIX 493operating system. 494 495 <br><dt><code>-mcall-linux</code><dd><a name="index-mcall_002dlinux-1907"></a>On System V.4 and embedded PowerPC systems compile code for the 496Linux-based GNU system. 497 498 <br><dt><code>-mcall-gnu</code><dd><a name="index-mcall_002dgnu-1908"></a>On System V.4 and embedded PowerPC systems compile code for the 499Hurd-based GNU system. 500 501 <br><dt><code>-mcall-freebsd</code><dd><a name="index-mcall_002dfreebsd-1909"></a>On System V.4 and embedded PowerPC systems compile code for the 502FreeBSD operating system. 503 504 <br><dt><code>-mcall-netbsd</code><dd><a name="index-mcall_002dnetbsd-1910"></a>On System V.4 and embedded PowerPC systems compile code for the 505NetBSD operating system. 506 507 <br><dt><code>-mcall-openbsd</code><dd><a name="index-mcall_002dnetbsd-1911"></a>On System V.4 and embedded PowerPC systems compile code for the 508OpenBSD operating system. 509 510 <br><dt><code>-maix-struct-return</code><dd><a name="index-maix_002dstruct_002dreturn-1912"></a>Return all structures in memory (as specified by the AIX ABI). 511 512 <br><dt><code>-msvr4-struct-return</code><dd><a name="index-msvr4_002dstruct_002dreturn-1913"></a>Return structures smaller than 8 bytes in registers (as specified by the 513SVR4 ABI). 514 515 <br><dt><code>-mabi=</code><var>abi-type</var><dd><a name="index-mabi-1914"></a>Extend the current ABI with a particular extension, or remove such extension. 516Valid values are <var>altivec</var>, <var>no-altivec</var>, <var>spe</var>, 517<var>no-spe</var>, <var>ibmlongdouble</var>, <var>ieeelongdouble</var>. 518 519 <br><dt><code>-mabi=spe</code><dd><a name="index-mabi_003dspe-1915"></a>Extend the current ABI with SPE ABI extensions. This does not change 520the default ABI, instead it adds the SPE ABI extensions to the current 521ABI. 522 523 <br><dt><code>-mabi=no-spe</code><dd><a name="index-mabi_003dno_002dspe-1916"></a>Disable Booke SPE ABI extensions for the current ABI. 524 525 <br><dt><code>-mabi=ibmlongdouble</code><dd><a name="index-mabi_003dibmlongdouble-1917"></a>Change the current ABI to use IBM extended precision long double. 526This is a PowerPC 32-bit SYSV ABI option. 527 528 <br><dt><code>-mabi=ieeelongdouble</code><dd><a name="index-mabi_003dieeelongdouble-1918"></a>Change the current ABI to use IEEE extended precision long double. 529This is a PowerPC 32-bit Linux ABI option. 530 531 <br><dt><code>-mprototype</code><dt><code>-mno-prototype</code><dd><a name="index-mprototype-1919"></a><a name="index-mno_002dprototype-1920"></a>On System V.4 and embedded PowerPC systems assume that all calls to 532variable argument functions are properly prototyped. Otherwise, the 533compiler must insert an instruction before every non prototyped call to 534set or clear bit 6 of the condition code register (<var>CR</var>) to 535indicate whether floating point values were passed in the floating point 536registers in case the function takes a variable arguments. With 537<samp><span class="option">-mprototype</span></samp>, only calls to prototyped variable argument functions 538will set or clear the bit. 539 540 <br><dt><code>-msim</code><dd><a name="index-msim-1921"></a>On embedded PowerPC systems, assume that the startup module is called 541<samp><span class="file">sim-crt0.o</span></samp> and that the standard C libraries are <samp><span class="file">libsim.a</span></samp> and 542<samp><span class="file">libc.a</span></samp>. This is the default for ‘<samp><span class="samp">powerpc-*-eabisim</span></samp>’ 543configurations. 544 545 <br><dt><code>-mmvme</code><dd><a name="index-mmvme-1922"></a>On embedded PowerPC systems, assume that the startup module is called 546<samp><span class="file">crt0.o</span></samp> and the standard C libraries are <samp><span class="file">libmvme.a</span></samp> and 547<samp><span class="file">libc.a</span></samp>. 548 549 <br><dt><code>-mads</code><dd><a name="index-mads-1923"></a>On embedded PowerPC systems, assume that the startup module is called 550<samp><span class="file">crt0.o</span></samp> and the standard C libraries are <samp><span class="file">libads.a</span></samp> and 551<samp><span class="file">libc.a</span></samp>. 552 553 <br><dt><code>-myellowknife</code><dd><a name="index-myellowknife-1924"></a>On embedded PowerPC systems, assume that the startup module is called 554<samp><span class="file">crt0.o</span></samp> and the standard C libraries are <samp><span class="file">libyk.a</span></samp> and 555<samp><span class="file">libc.a</span></samp>. 556 557 <br><dt><code>-mvxworks</code><dd><a name="index-mvxworks-1925"></a>On System V.4 and embedded PowerPC systems, specify that you are 558compiling for a VxWorks system. 559 560 <br><dt><code>-memb</code><dd><a name="index-memb-1926"></a>On embedded PowerPC systems, set the <var>PPC_EMB</var> bit in the ELF flags 561header to indicate that ‘<samp><span class="samp">eabi</span></samp>’ extended relocations are used. 562 563 <br><dt><code>-meabi</code><dt><code>-mno-eabi</code><dd><a name="index-meabi-1927"></a><a name="index-mno_002deabi-1928"></a>On System V.4 and embedded PowerPC systems do (do not) adhere to the 564Embedded Applications Binary Interface (eabi) which is a set of 565modifications to the System V.4 specifications. Selecting <samp><span class="option">-meabi</span></samp> 566means that the stack is aligned to an 8 byte boundary, 567and the <samp><span class="option">-msdata</span></samp> option can use both <code>r2</code> and 568<code>r13</code> to point to two separate small data areas. Selecting 569<samp><span class="option">-mno-eabi</span></samp> means that the stack is aligned to a 16 byte boundary, 570and the 571<samp><span class="option">-msdata</span></samp> option will only use <code>r13</code> to point to a single 572small data area. The <samp><span class="option">-meabi</span></samp> option is on by default if you 573configured GCC using one of the ‘<samp><span class="samp">powerpc*-*-eabi*</span></samp>’ options. 574 575 <br><dt><code>-msdata=eabi</code><dd><a name="index-msdata_003deabi-1929"></a>On System V.4 and embedded PowerPC systems, put small initialized 576<code>const</code> global and static data in the ‘<samp><span class="samp">.sdata2</span></samp>’ section, which 577is pointed to by register <code>r2</code>. Put small initialized 578non-<code>const</code> global and static data in the ‘<samp><span class="samp">.sdata</span></samp>’ section, 579which is pointed to by register <code>r13</code>. Put small uninitialized 580global and static data in the ‘<samp><span class="samp">.sbss</span></samp>’ section, which is adjacent to 581the ‘<samp><span class="samp">.sdata</span></samp>’ section. The <samp><span class="option">-msdata=eabi</span></samp> option is 582incompatible with the <samp><span class="option">-mrelocatable</span></samp> option. The 583<samp><span class="option">-msdata=eabi</span></samp> option also sets the <samp><span class="option">-memb</span></samp> option. 584 585 <br><dt><code>-msdata=sysv</code><dd><a name="index-msdata_003dsysv-1930"></a>On System V.4 and embedded PowerPC systems, put small global and static 586data in the ‘<samp><span class="samp">.sdata</span></samp>’ section, which is pointed to by register 587<code>r13</code>. Put small uninitialized global and static data in the 588‘<samp><span class="samp">.sbss</span></samp>’ section, which is adjacent to the ‘<samp><span class="samp">.sdata</span></samp>’ section. 589The <samp><span class="option">-msdata=sysv</span></samp> option is incompatible with the 590<samp><span class="option">-mrelocatable</span></samp> option. 591 592 <br><dt><code>-msdata=default</code><dt><code>-msdata</code><dd><a name="index-msdata_003ddefault-1931"></a><a name="index-msdata-1932"></a>On System V.4 and embedded PowerPC systems, if <samp><span class="option">-meabi</span></samp> is used, 593compile code the same as <samp><span class="option">-msdata=eabi</span></samp>, otherwise compile code the 594same as <samp><span class="option">-msdata=sysv</span></samp>. 595 596 <br><dt><code>-msdata=data</code><dd><a name="index-msdata_003ddata-1933"></a>On System V.4 and embedded PowerPC systems, put small global 597data in the ‘<samp><span class="samp">.sdata</span></samp>’ section. Put small uninitialized global 598data in the ‘<samp><span class="samp">.sbss</span></samp>’ section. Do not use register <code>r13</code> 599to address small data however. This is the default behavior unless 600other <samp><span class="option">-msdata</span></samp> options are used. 601 602 <br><dt><code>-msdata=none</code><dt><code>-mno-sdata</code><dd><a name="index-msdata_003dnone-1934"></a><a name="index-mno_002dsdata-1935"></a>On embedded PowerPC systems, put all initialized global and static data 603in the ‘<samp><span class="samp">.data</span></samp>’ section, and all uninitialized data in the 604‘<samp><span class="samp">.bss</span></samp>’ section. 605 606 <br><dt><code>-mblock-move-inline-limit=</code><var>num</var><dd><a name="index-mblock_002dmove_002dinline_002dlimit-1936"></a>Inline all block moves (such as calls to <code>memcpy</code> or structure 607copies) less than or equal to <var>num</var> bytes. The minimum value for 608<var>num</var> is 32 bytes on 32-bit targets and 64 bytes on 64-bit 609targets. The default value is target-specific. 610 611 <br><dt><code>-G </code><var>num</var><dd><a name="index-G-1937"></a><a name="index-smaller-data-references-_0028PowerPC_0029-1938"></a><a name="index-g_t_002esdata_002f_002esdata2-references-_0028PowerPC_0029-1939"></a>On embedded PowerPC systems, put global and static items less than or 612equal to <var>num</var> bytes into the small data or bss sections instead of 613the normal data or bss section. By default, <var>num</var> is 8. The 614<samp><span class="option">-G </span><var>num</var></samp> switch is also passed to the linker. 615All modules should be compiled with the same <samp><span class="option">-G </span><var>num</var></samp> value. 616 617 <br><dt><code>-mregnames</code><dt><code>-mno-regnames</code><dd><a name="index-mregnames-1940"></a><a name="index-mno_002dregnames-1941"></a>On System V.4 and embedded PowerPC systems do (do not) emit register 618names in the assembly language output using symbolic forms. 619 620 <br><dt><code>-mlongcall</code><dt><code>-mno-longcall</code><dd><a name="index-mlongcall-1942"></a><a name="index-mno_002dlongcall-1943"></a>By default assume that all calls are far away so that a longer more 621expensive calling sequence is required. This is required for calls 622further than 32 megabytes (33,554,432 bytes) from the current location. 623A short call will be generated if the compiler knows 624the call cannot be that far away. This setting can be overridden by 625the <code>shortcall</code> function attribute, or by <code>#pragma 626longcall(0)</code>. 627 628 <p>Some linkers are capable of detecting out-of-range calls and generating 629glue code on the fly. On these systems, long calls are unnecessary and 630generate slower code. As of this writing, the AIX linker can do this, 631as can the GNU linker for PowerPC/64. It is planned to add this feature 632to the GNU linker for 32-bit PowerPC systems as well. 633 634 <p>On Darwin/PPC systems, <code>#pragma longcall</code> will generate “jbsr 635callee, L42”, plus a “branch island” (glue code). The two target 636addresses represent the callee and the “branch island”. The 637Darwin/PPC linker will prefer the first address and generate a “bl 638callee” if the PPC “bl” instruction will reach the callee directly; 639otherwise, the linker will generate “bl L42” to call the “branch 640island”. The “branch island” is appended to the body of the 641calling function; it computes the full 32-bit address of the callee 642and jumps to it. 643 644 <p>On Mach-O (Darwin) systems, this option directs the compiler emit to 645the glue for every direct call, and the Darwin linker decides whether 646to use or discard it. 647 648 <p>In the future, we may cause GCC to ignore all longcall specifications 649when the linker is known to generate glue. 650 651 <br><dt><code>-mtls-markers</code><dt><code>-mno-tls-markers</code><dd><a name="index-mtls_002dmarkers-1944"></a><a name="index-mno_002dtls_002dmarkers-1945"></a>Mark (do not mark) calls to <code>__tls_get_addr</code> with a relocation 652specifying the function argument. The relocation allows ld to 653reliably associate function call with argument setup instructions for 654TLS optimization, which in turn allows gcc to better schedule the 655sequence. 656 657 <br><dt><code>-pthread</code><dd><a name="index-pthread-1946"></a>Adds support for multithreading with the <dfn>pthreads</dfn> library. 658This option sets flags for both the preprocessor and linker. 659 660 <br><dt><code>-mrecip</code><dt><code>-mno-recip</code><dd><a name="index-mrecip-1947"></a>This option will enable GCC to use the reciprocal estimate and 661reciprocal square root estimate instructions with additional 662Newton-Raphson steps to increase precision instead of doing a divide or 663square root and divide for floating point arguments. You should use 664the <samp><span class="option">-ffast-math</span></samp> option when using <samp><span class="option">-mrecip</span></samp> (or at 665least <samp><span class="option">-funsafe-math-optimizations</span></samp>, 666<samp><span class="option">-finite-math-only</span></samp>, <samp><span class="option">-freciprocal-math</span></samp> and 667<samp><span class="option">-fno-trapping-math</span></samp>). Note that while the throughput of the 668sequence is generally higher than the throughput of the non-reciprocal 669instruction, the precision of the sequence can be decreased by up to 2 670ulp (i.e. the inverse of 1.0 equals 0.99999994) for reciprocal square 671roots. 672 673 <br><dt><code>-mrecip=</code><var>opt</var><dd><a name="index-mrecip_003dopt-1948"></a>This option allows to control which reciprocal estimate instructions 674may be used. <var>opt</var> is a comma separated list of options, that may 675be preceded by a <code>!</code> to invert the option: 676<code>all</code>: enable all estimate instructions, 677<code>default</code>: enable the default instructions, equivalent to <samp><span class="option">-mrecip</span></samp>, 678<code>none</code>: disable all estimate instructions, equivalent to <samp><span class="option">-mno-recip</span></samp>; 679<code>div</code>: enable the reciprocal approximation instructions for both single and double precision; 680<code>divf</code>: enable the single precision reciprocal approximation instructions; 681<code>divd</code>: enable the double precision reciprocal approximation instructions; 682<code>rsqrt</code>: enable the reciprocal square root approximation instructions for both single and double precision; 683<code>rsqrtf</code>: enable the single precision reciprocal square root approximation instructions; 684<code>rsqrtd</code>: enable the double precision reciprocal square root approximation instructions; 685 686 <p>So for example, <samp><span class="option">-mrecip=all,!rsqrtd</span></samp> would enable the 687all of the reciprocal estimate instructions, except for the 688<code>FRSQRTE</code>, <code>XSRSQRTEDP</code>, and <code>XVRSQRTEDP</code> instructions 689which handle the double precision reciprocal square root calculations. 690 691 <br><dt><code>-mrecip-precision</code><dt><code>-mno-recip-precision</code><dd><a name="index-mrecip_002dprecision-1949"></a>Assume (do not assume) that the reciprocal estimate instructions 692provide higher precision estimates than is mandated by the powerpc 693ABI. Selecting <samp><span class="option">-mcpu=power6</span></samp> or <samp><span class="option">-mcpu=power7</span></samp> 694automatically selects <samp><span class="option">-mrecip-precision</span></samp>. The double 695precision square root estimate instructions are not generated by 696default on low precision machines, since they do not provide an 697estimate that converges after three steps. 698 699 <br><dt><code>-mveclibabi=</code><var>type</var><dd><a name="index-mveclibabi-1950"></a>Specifies the ABI type to use for vectorizing intrinsics using an 700external library. The only type supported at present is <code>mass</code>, 701which specifies to use IBM's Mathematical Acceleration Subsystem 702(MASS) libraries for vectorizing intrinsics using external libraries. 703GCC will currently emit calls to <code>acosd2</code>, <code>acosf4</code>, 704<code>acoshd2</code>, <code>acoshf4</code>, <code>asind2</code>, <code>asinf4</code>, 705<code>asinhd2</code>, <code>asinhf4</code>, <code>atan2d2</code>, <code>atan2f4</code>, 706<code>atand2</code>, <code>atanf4</code>, <code>atanhd2</code>, <code>atanhf4</code>, 707<code>cbrtd2</code>, <code>cbrtf4</code>, <code>cosd2</code>, <code>cosf4</code>, 708<code>coshd2</code>, <code>coshf4</code>, <code>erfcd2</code>, <code>erfcf4</code>, 709<code>erfd2</code>, <code>erff4</code>, <code>exp2d2</code>, <code>exp2f4</code>, 710<code>expd2</code>, <code>expf4</code>, <code>expm1d2</code>, <code>expm1f4</code>, 711<code>hypotd2</code>, <code>hypotf4</code>, <code>lgammad2</code>, <code>lgammaf4</code>, 712<code>log10d2</code>, <code>log10f4</code>, <code>log1pd2</code>, <code>log1pf4</code>, 713<code>log2d2</code>, <code>log2f4</code>, <code>logd2</code>, <code>logf4</code>, 714<code>powd2</code>, <code>powf4</code>, <code>sind2</code>, <code>sinf4</code>, <code>sinhd2</code>, 715<code>sinhf4</code>, <code>sqrtd2</code>, <code>sqrtf4</code>, <code>tand2</code>, 716<code>tanf4</code>, <code>tanhd2</code>, and <code>tanhf4</code> when generating code 717for power7. Both <samp><span class="option">-ftree-vectorize</span></samp> and 718<samp><span class="option">-funsafe-math-optimizations</span></samp> have to be enabled. The MASS 719libraries will have to be specified at link time. 720 721 <br><dt><code>-mfriz</code><dt><code>-mno-friz</code><dd><a name="index-mfriz-1951"></a>Generate (do not generate) the <code>friz</code> instruction when the 722<samp><span class="option">-funsafe-math-optimizations</span></samp> option is used to optimize 723rounding a floating point value to 64-bit integer and back to floating 724point. The <code>friz</code> instruction does not return the same value if 725the floating point number is too large to fit in an integer. 726</dl> 727 728 </body></html> 729 730