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58
59<h4 class="subsection">6.54.8 MIPS Paired-Single Support</h4>
60
61<p>The MIPS64 architecture includes a number of instructions that
62operate on pairs of single-precision floating-point values. 
63Each pair is packed into a 64-bit floating-point register,
64with one element being designated the &ldquo;upper half&rdquo; and
65the other being designated the &ldquo;lower half&rdquo;.
66
67 <p>GCC supports paired-single operations using both the generic
68vector extensions (see <a href="Vector-Extensions.html#Vector-Extensions">Vector Extensions</a>) and a collection of
69MIPS-specific built-in functions.  Both kinds of support are
70enabled by the <samp><span class="option">-mpaired-single</span></samp> command-line option.
71
72 <p>The vector type associated with paired-single values is usually
73called <code>v2sf</code>.  It can be defined in C as follows:
74
75<pre class="smallexample">     typedef float v2sf __attribute__ ((vector_size (8)));
76</pre>
77 <p><code>v2sf</code> values are initialized in the same way as aggregates. 
78For example:
79
80<pre class="smallexample">     v2sf a = {1.5, 9.1};
81     v2sf b;
82     float e, f;
83     b = (v2sf) {e, f};
84</pre>
85 <p><em>Note:</em> The CPU's endianness determines which value is stored in
86the upper half of a register and which value is stored in the lower half. 
87On little-endian targets, the first value is the lower one and the second
88value is the upper one.  The opposite order applies to big-endian targets. 
89For example, the code above will set the lower half of <code>a</code> to
90<code>1.5</code> on little-endian targets and <code>9.1</code> on big-endian targets.
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