1<html lang="en"> 2<head> 3<title>MIPS Options - Using the GNU Compiler Collection (GCC)</title> 4<meta http-equiv="Content-Type" content="text/html"> 5<meta name="description" content="Using the GNU Compiler Collection (GCC)"> 6<meta name="generator" content="makeinfo 4.13"> 7<link title="Top" rel="start" href="index.html#Top"> 8<link rel="up" href="Submodel-Options.html#Submodel-Options" title="Submodel Options"> 9<link rel="prev" href="MicroBlaze-Options.html#MicroBlaze-Options" title="MicroBlaze Options"> 10<link rel="next" href="MMIX-Options.html#MMIX-Options" title="MMIX Options"> 11<link href="http://www.gnu.org/software/texinfo/" rel="generator-home" title="Texinfo Homepage"> 12<!-- 13Copyright (C) 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 141998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 152010 Free Software Foundation, Inc. 16 17Permission is granted to copy, distribute and/or modify this document 18under the terms of the GNU Free Documentation License, Version 1.3 or 19any later version published by the Free Software Foundation; with the 20Invariant Sections being ``Funding Free Software'', the Front-Cover 21Texts being (a) (see below), and with the Back-Cover Texts being (b) 22(see below). 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This is the default for ‘<samp><span class="samp">mips*el-*-*</span></samp>’ 65configurations. 66 67 <br><dt><code>-march=</code><var>arch</var><dd><a name="index-march-1630"></a>Generate code that will run on <var>arch</var>, which can be the name of a 68generic MIPS ISA, or the name of a particular processor. 69The ISA names are: 70‘<samp><span class="samp">mips1</span></samp>’, ‘<samp><span class="samp">mips2</span></samp>’, ‘<samp><span class="samp">mips3</span></samp>’, ‘<samp><span class="samp">mips4</span></samp>’, 71‘<samp><span class="samp">mips32</span></samp>’, ‘<samp><span class="samp">mips32r2</span></samp>’, ‘<samp><span class="samp">mips64</span></samp>’ and ‘<samp><span class="samp">mips64r2</span></samp>’. 72The processor names are: 73‘<samp><span class="samp">4kc</span></samp>’, ‘<samp><span class="samp">4km</span></samp>’, ‘<samp><span class="samp">4kp</span></samp>’, ‘<samp><span class="samp">4ksc</span></samp>’, 74‘<samp><span class="samp">4kec</span></samp>’, ‘<samp><span class="samp">4kem</span></samp>’, ‘<samp><span class="samp">4kep</span></samp>’, ‘<samp><span class="samp">4ksd</span></samp>’, 75‘<samp><span class="samp">5kc</span></samp>’, ‘<samp><span class="samp">5kf</span></samp>’, 76‘<samp><span class="samp">20kc</span></samp>’, 77‘<samp><span class="samp">24kc</span></samp>’, ‘<samp><span class="samp">24kf2_1</span></samp>’, ‘<samp><span class="samp">24kf1_1</span></samp>’, 78‘<samp><span class="samp">24kec</span></samp>’, ‘<samp><span class="samp">24kef2_1</span></samp>’, ‘<samp><span class="samp">24kef1_1</span></samp>’, 79‘<samp><span class="samp">34kc</span></samp>’, ‘<samp><span class="samp">34kf2_1</span></samp>’, ‘<samp><span class="samp">34kf1_1</span></samp>’, 80‘<samp><span class="samp">74kc</span></samp>’, ‘<samp><span class="samp">74kf2_1</span></samp>’, ‘<samp><span class="samp">74kf1_1</span></samp>’, ‘<samp><span class="samp">74kf3_2</span></samp>’, 81‘<samp><span class="samp">1004kc</span></samp>’, ‘<samp><span class="samp">1004kf2_1</span></samp>’, ‘<samp><span class="samp">1004kf1_1</span></samp>’, 82‘<samp><span class="samp">loongson2e</span></samp>’, ‘<samp><span class="samp">loongson2f</span></samp>’, ‘<samp><span class="samp">loongson3a</span></samp>’, 83‘<samp><span class="samp">m4k</span></samp>’, ‘<samp><span class="samp">m14ke</span></samp>’, ‘<samp><span class="samp">m14kec</span></samp>’, 84‘<samp><span class="samp">octeon</span></samp>’, 85‘<samp><span class="samp">orion</span></samp>’, 86‘<samp><span class="samp">r2000</span></samp>’, ‘<samp><span class="samp">r3000</span></samp>’, ‘<samp><span class="samp">r3900</span></samp>’, ‘<samp><span class="samp">r4000</span></samp>’, ‘<samp><span class="samp">r4400</span></samp>’, 87‘<samp><span class="samp">r4600</span></samp>’, ‘<samp><span class="samp">r4650</span></samp>’, ‘<samp><span class="samp">r6000</span></samp>’, ‘<samp><span class="samp">r8000</span></samp>’, 88‘<samp><span class="samp">rm7000</span></samp>’, ‘<samp><span class="samp">rm9000</span></samp>’, 89‘<samp><span class="samp">r10000</span></samp>’, ‘<samp><span class="samp">r12000</span></samp>’, ‘<samp><span class="samp">r14000</span></samp>’, ‘<samp><span class="samp">r16000</span></samp>’, 90‘<samp><span class="samp">sb1</span></samp>’, 91‘<samp><span class="samp">sr71000</span></samp>’, 92‘<samp><span class="samp">vr4100</span></samp>’, ‘<samp><span class="samp">vr4111</span></samp>’, ‘<samp><span class="samp">vr4120</span></samp>’, ‘<samp><span class="samp">vr4130</span></samp>’, ‘<samp><span class="samp">vr4300</span></samp>’, 93‘<samp><span class="samp">vr5000</span></samp>’, ‘<samp><span class="samp">vr5400</span></samp>’, ‘<samp><span class="samp">vr5500</span></samp>’ 94and ‘<samp><span class="samp">xlr</span></samp>’. 95The special value ‘<samp><span class="samp">from-abi</span></samp>’ selects the 96most compatible architecture for the selected ABI (that is, 97‘<samp><span class="samp">mips1</span></samp>’ for 32-bit ABIs and ‘<samp><span class="samp">mips3</span></samp>’ for 64-bit ABIs). 98 99 <p>Native Linux/GNU toolchains also support the value ‘<samp><span class="samp">native</span></samp>’, 100which selects the best architecture option for the host processor. 101<samp><span class="option">-march=native</span></samp> has no effect if GCC does not recognize 102the processor. 103 104 <p>In processor names, a final ‘<samp><span class="samp">000</span></samp>’ can be abbreviated as ‘<samp><span class="samp">k</span></samp>’ 105(for example, ‘<samp><span class="samp">-march=r2k</span></samp>’). Prefixes are optional, and 106‘<samp><span class="samp">vr</span></samp>’ may be written ‘<samp><span class="samp">r</span></samp>’. 107 108 <p>Names of the form ‘<samp><var>n</var><span class="samp">f2_1</span></samp>’ refer to processors with 109FPUs clocked at half the rate of the core, names of the form 110‘<samp><var>n</var><span class="samp">f1_1</span></samp>’ refer to processors with FPUs clocked at the same 111rate as the core, and names of the form ‘<samp><var>n</var><span class="samp">f3_2</span></samp>’ refer to 112processors with FPUs clocked a ratio of 3:2 with respect to the core. 113For compatibility reasons, ‘<samp><var>n</var><span class="samp">f</span></samp>’ is accepted as a synonym 114for ‘<samp><var>n</var><span class="samp">f2_1</span></samp>’ while ‘<samp><var>n</var><span class="samp">x</span></samp>’ and ‘<samp><var>b</var><span class="samp">fx</span></samp>’ are 115accepted as synonyms for ‘<samp><var>n</var><span class="samp">f1_1</span></samp>’. 116 117 <p>GCC defines two macros based on the value of this option. The first 118is ‘<samp><span class="samp">_MIPS_ARCH</span></samp>’, which gives the name of target architecture, as 119a string. The second has the form ‘<samp><span class="samp">_MIPS_ARCH_</span><var>foo</var></samp>’, 120where <var>foo</var> is the capitalized value of ‘<samp><span class="samp">_MIPS_ARCH</span></samp>’. 121For example, ‘<samp><span class="samp">-march=r2000</span></samp>’ will set ‘<samp><span class="samp">_MIPS_ARCH</span></samp>’ 122to ‘<samp><span class="samp">"r2000"</span></samp>’ and define the macro ‘<samp><span class="samp">_MIPS_ARCH_R2000</span></samp>’. 123 124 <p>Note that the ‘<samp><span class="samp">_MIPS_ARCH</span></samp>’ macro uses the processor names given 125above. In other words, it will have the full prefix and will not 126abbreviate ‘<samp><span class="samp">000</span></samp>’ as ‘<samp><span class="samp">k</span></samp>’. In the case of ‘<samp><span class="samp">from-abi</span></samp>’, 127the macro names the resolved architecture (either ‘<samp><span class="samp">"mips1"</span></samp>’ or 128‘<samp><span class="samp">"mips3"</span></samp>’). It names the default architecture when no 129<samp><span class="option">-march</span></samp> option is given. 130 131 <br><dt><code>-mtune=</code><var>arch</var><dd><a name="index-mtune-1631"></a>Optimize for <var>arch</var>. Among other things, this option controls 132the way instructions are scheduled, and the perceived cost of arithmetic 133operations. The list of <var>arch</var> values is the same as for 134<samp><span class="option">-march</span></samp>. 135 136 <p>When this option is not used, GCC will optimize for the processor 137specified by <samp><span class="option">-march</span></samp>. By using <samp><span class="option">-march</span></samp> and 138<samp><span class="option">-mtune</span></samp> together, it is possible to generate code that will 139run on a family of processors, but optimize the code for one 140particular member of that family. 141 142 <p>‘<samp><span class="samp">-mtune</span></samp>’ defines the macros ‘<samp><span class="samp">_MIPS_TUNE</span></samp>’ and 143‘<samp><span class="samp">_MIPS_TUNE_</span><var>foo</var></samp>’, which work in the same way as the 144‘<samp><span class="samp">-march</span></samp>’ ones described above. 145 146 <br><dt><code>-mips1</code><dd><a name="index-mips1-1632"></a>Equivalent to ‘<samp><span class="samp">-march=mips1</span></samp>’. 147 148 <br><dt><code>-mips2</code><dd><a name="index-mips2-1633"></a>Equivalent to ‘<samp><span class="samp">-march=mips2</span></samp>’. 149 150 <br><dt><code>-mips3</code><dd><a name="index-mips3-1634"></a>Equivalent to ‘<samp><span class="samp">-march=mips3</span></samp>’. 151 152 <br><dt><code>-mips4</code><dd><a name="index-mips4-1635"></a>Equivalent to ‘<samp><span class="samp">-march=mips4</span></samp>’. 153 154 <br><dt><code>-mips32</code><dd><a name="index-mips32-1636"></a>Equivalent to ‘<samp><span class="samp">-march=mips32</span></samp>’. 155 156 <br><dt><code>-mips32r2</code><dd><a name="index-mips32r2-1637"></a>Equivalent to ‘<samp><span class="samp">-march=mips32r2</span></samp>’. 157 158 <br><dt><code>-mips64</code><dd><a name="index-mips64-1638"></a>Equivalent to ‘<samp><span class="samp">-march=mips64</span></samp>’. 159 160 <br><dt><code>-mips64r2</code><dd><a name="index-mips64r2-1639"></a>Equivalent to ‘<samp><span class="samp">-march=mips64r2</span></samp>’. 161 162 <br><dt><code>-mips16</code><dt><code>-mips16e</code><dt><code>-mno-mips16</code><dd><a name="index-mips16-1640"></a><a name="index-mips16e-1641"></a><a name="index-mno_002dmips16-1642"></a>Generate (do not generate) MIPS16 code. If GCC is targetting a 163MIPS32 or MIPS64 architecture, it will make use of the MIPS16e ASE. 164<samp><span class="option">-mips16e</span></samp> is a deprecated alias for <samp><span class="option">-mips16</span></samp>. 165 166 <p>MIPS16 code generation can also be controlled on a per-function basis 167by means of <code>mips16</code> and <code>nomips16</code> attributes. 168See <a href="Function-Attributes.html#Function-Attributes">Function Attributes</a>, for more information. 169 170 <br><dt><code>-mflip-mips16</code><dd><a name="index-mflip_002dmips16-1643"></a>Generate MIPS16 code on alternating functions. This option is provided 171for regression testing of mixed MIPS16/non-MIPS16 code generation, and is 172not intended for ordinary use in compiling user code. 173 174 <br><dt><code>-minterlink-mips16</code><dt><code>-mno-interlink-mips16</code><dd><a name="index-minterlink_002dmips16-1644"></a><a name="index-mno_002dinterlink_002dmips16-1645"></a>Require (do not require) that non-MIPS16 code be link-compatible with 175MIPS16 code. 176 177 <p>For example, non-MIPS16 code cannot jump directly to MIPS16 code; 178it must either use a call or an indirect jump. <samp><span class="option">-minterlink-mips16</span></samp> 179therefore disables direct jumps unless GCC knows that the target of the 180jump is not MIPS16. 181 182 <br><dt><code>-mabi=32</code><dt><code>-mabi=o64</code><dt><code>-mabi=n32</code><dt><code>-mabi=64</code><dt><code>-mabi=eabi</code><dd><a name="index-mabi_003d32-1646"></a><a name="index-mabi_003do64-1647"></a><a name="index-mabi_003dn32-1648"></a><a name="index-mabi_003d64-1649"></a><a name="index-mabi_003deabi-1650"></a>Generate code for the given ABI. 183 184 <p>Note that the EABI has a 32-bit and a 64-bit variant. GCC normally 185generates 64-bit code when you select a 64-bit architecture, but you 186can use <samp><span class="option">-mgp32</span></samp> to get 32-bit code instead. 187 188 <p>For information about the O64 ABI, see 189<a href="http://gcc.gnu.org/projects/mipso64-abi.html">http://gcc.gnu.org/projects/mipso64-abi.html</a>. 190 191 <p>GCC supports a variant of the o32 ABI in which floating-point registers 192are 64 rather than 32 bits wide. You can select this combination with 193<samp><span class="option">-mabi=32</span></samp> <samp><span class="option">-mfp64</span></samp>. This ABI relies on the ‘<samp><span class="samp">mthc1</span></samp>’ 194and ‘<samp><span class="samp">mfhc1</span></samp>’ instructions and is therefore only supported for 195MIPS32R2 processors. 196 197 <p>The register assignments for arguments and return values remain the 198same, but each scalar value is passed in a single 64-bit register 199rather than a pair of 32-bit registers. For example, scalar 200floating-point values are returned in ‘<samp><span class="samp">$f0</span></samp>’ only, not a 201‘<samp><span class="samp">$f0</span></samp>’/‘<samp><span class="samp">$f1</span></samp>’ pair. The set of call-saved registers also 202remains the same, but all 64 bits are saved. 203 204 <br><dt><code>-mabicalls</code><dt><code>-mno-abicalls</code><dd><a name="index-mabicalls-1651"></a><a name="index-mno_002dabicalls-1652"></a>Generate (do not generate) code that is suitable for SVR4-style 205dynamic objects. <samp><span class="option">-mabicalls</span></samp> is the default for SVR4-based 206systems. 207 208 <br><dt><code>-mshared</code><dt><code>-mno-shared</code><dd>Generate (do not generate) code that is fully position-independent, 209and that can therefore be linked into shared libraries. This option 210only affects <samp><span class="option">-mabicalls</span></samp>. 211 212 <p>All <samp><span class="option">-mabicalls</span></samp> code has traditionally been position-independent, 213regardless of options like <samp><span class="option">-fPIC</span></samp> and <samp><span class="option">-fpic</span></samp>. However, 214as an extension, the GNU toolchain allows executables to use absolute 215accesses for locally-binding symbols. It can also use shorter GP 216initialization sequences and generate direct calls to locally-defined 217functions. This mode is selected by <samp><span class="option">-mno-shared</span></samp>. 218 219 <p><samp><span class="option">-mno-shared</span></samp> depends on binutils 2.16 or higher and generates 220objects that can only be linked by the GNU linker. However, the option 221does not affect the ABI of the final executable; it only affects the ABI 222of relocatable objects. Using <samp><span class="option">-mno-shared</span></samp> will generally make 223executables both smaller and quicker. 224 225 <p><samp><span class="option">-mshared</span></samp> is the default. 226 227 <br><dt><code>-mplt</code><dt><code>-mno-plt</code><dd><a name="index-mplt-1653"></a><a name="index-mno_002dplt-1654"></a>Assume (do not assume) that the static and dynamic linkers 228support PLTs and copy relocations. This option only affects 229‘<samp><span class="samp">-mno-shared -mabicalls</span></samp>’. For the n64 ABI, this option 230has no effect without ‘<samp><span class="samp">-msym32</span></samp>’. 231 232 <p>You can make <samp><span class="option">-mplt</span></samp> the default by configuring 233GCC with <samp><span class="option">--with-mips-plt</span></samp>. The default is 234<samp><span class="option">-mno-plt</span></samp> otherwise. 235 236 <br><dt><code>-mxgot</code><dt><code>-mno-xgot</code><dd><a name="index-mxgot-1655"></a><a name="index-mno_002dxgot-1656"></a>Lift (do not lift) the usual restrictions on the size of the global 237offset table. 238 239 <p>GCC normally uses a single instruction to load values from the GOT. 240While this is relatively efficient, it will only work if the GOT 241is smaller than about 64k. Anything larger will cause the linker 242to report an error such as: 243 244 <p><a name="index-relocation-truncated-to-fit-_0028MIPS_0029-1657"></a> 245 <pre class="smallexample"> relocation truncated to fit: R_MIPS_GOT16 foobar 246</pre> 247 <p>If this happens, you should recompile your code with <samp><span class="option">-mxgot</span></samp>. 248It should then work with very large GOTs, although it will also be 249less efficient, since it will take three instructions to fetch the 250value of a global symbol. 251 252 <p>Note that some linkers can create multiple GOTs. If you have such a 253linker, you should only need to use <samp><span class="option">-mxgot</span></samp> when a single object 254file accesses more than 64k's worth of GOT entries. Very few do. 255 256 <p>These options have no effect unless GCC is generating position 257independent code. 258 259 <br><dt><code>-mgp32</code><dd><a name="index-mgp32-1658"></a>Assume that general-purpose registers are 32 bits wide. 260 261 <br><dt><code>-mgp64</code><dd><a name="index-mgp64-1659"></a>Assume that general-purpose registers are 64 bits wide. 262 263 <br><dt><code>-mfp32</code><dd><a name="index-mfp32-1660"></a>Assume that floating-point registers are 32 bits wide. 264 265 <br><dt><code>-mfp64</code><dd><a name="index-mfp64-1661"></a>Assume that floating-point registers are 64 bits wide. 266 267 <br><dt><code>-mhard-float</code><dd><a name="index-mhard_002dfloat-1662"></a>Use floating-point coprocessor instructions. 268 269 <br><dt><code>-msoft-float</code><dd><a name="index-msoft_002dfloat-1663"></a>Do not use floating-point coprocessor instructions. Implement 270floating-point calculations using library calls instead. 271 272 <br><dt><code>-msingle-float</code><dd><a name="index-msingle_002dfloat-1664"></a>Assume that the floating-point coprocessor only supports single-precision 273operations. 274 275 <br><dt><code>-mdouble-float</code><dd><a name="index-mdouble_002dfloat-1665"></a>Assume that the floating-point coprocessor supports double-precision 276operations. This is the default. 277 278 <br><dt><code>-mllsc</code><dt><code>-mno-llsc</code><dd><a name="index-mllsc-1666"></a><a name="index-mno_002dllsc-1667"></a>Use (do not use) ‘<samp><span class="samp">ll</span></samp>’, ‘<samp><span class="samp">sc</span></samp>’, and ‘<samp><span class="samp">sync</span></samp>’ instructions to 279implement atomic memory built-in functions. When neither option is 280specified, GCC will use the instructions if the target architecture 281supports them. 282 283 <p><samp><span class="option">-mllsc</span></samp> is useful if the runtime environment can emulate the 284instructions and <samp><span class="option">-mno-llsc</span></samp> can be useful when compiling for 285nonstandard ISAs. You can make either option the default by 286configuring GCC with <samp><span class="option">--with-llsc</span></samp> and <samp><span class="option">--without-llsc</span></samp> 287respectively. <samp><span class="option">--with-llsc</span></samp> is the default for some 288configurations; see the installation documentation for details. 289 290 <br><dt><code>-mdsp</code><dt><code>-mno-dsp</code><dd><a name="index-mdsp-1668"></a><a name="index-mno_002ddsp-1669"></a>Use (do not use) revision 1 of the MIPS DSP ASE. 291See <a href="MIPS-DSP-Built_002din-Functions.html#MIPS-DSP-Built_002din-Functions">MIPS DSP Built-in Functions</a>. This option defines the 292preprocessor macro ‘<samp><span class="samp">__mips_dsp</span></samp>’. It also defines 293‘<samp><span class="samp">__mips_dsp_rev</span></samp>’ to 1. 294 295 <br><dt><code>-mdspr2</code><dt><code>-mno-dspr2</code><dd><a name="index-mdspr2-1670"></a><a name="index-mno_002ddspr2-1671"></a>Use (do not use) revision 2 of the MIPS DSP ASE. 296See <a href="MIPS-DSP-Built_002din-Functions.html#MIPS-DSP-Built_002din-Functions">MIPS DSP Built-in Functions</a>. This option defines the 297preprocessor macros ‘<samp><span class="samp">__mips_dsp</span></samp>’ and ‘<samp><span class="samp">__mips_dspr2</span></samp>’. 298It also defines ‘<samp><span class="samp">__mips_dsp_rev</span></samp>’ to 2. 299 300 <br><dt><code>-msmartmips</code><dt><code>-mno-smartmips</code><dd><a name="index-msmartmips-1672"></a><a name="index-mno_002dsmartmips-1673"></a>Use (do not use) the MIPS SmartMIPS ASE. 301 302 <br><dt><code>-mpaired-single</code><dt><code>-mno-paired-single</code><dd><a name="index-mpaired_002dsingle-1674"></a><a name="index-mno_002dpaired_002dsingle-1675"></a>Use (do not use) paired-single floating-point instructions. 303See <a href="MIPS-Paired_002dSingle-Support.html#MIPS-Paired_002dSingle-Support">MIPS Paired-Single Support</a>. This option requires 304hardware floating-point support to be enabled. 305 306 <br><dt><code>-mdmx</code><dt><code>-mno-mdmx</code><dd><a name="index-mdmx-1676"></a><a name="index-mno_002dmdmx-1677"></a>Use (do not use) MIPS Digital Media Extension instructions. 307This option can only be used when generating 64-bit code and requires 308hardware floating-point support to be enabled. 309 310 <br><dt><code>-mips3d</code><dt><code>-mno-mips3d</code><dd><a name="index-mips3d-1678"></a><a name="index-mno_002dmips3d-1679"></a>Use (do not use) the MIPS-3D ASE. See <a href="MIPS_002d3D-Built_002din-Functions.html#MIPS_002d3D-Built_002din-Functions">MIPS-3D Built-in Functions</a>. 311The option <samp><span class="option">-mips3d</span></samp> implies <samp><span class="option">-mpaired-single</span></samp>. 312 313 <br><dt><code>-mmt</code><dt><code>-mno-mt</code><dd><a name="index-mmt-1680"></a><a name="index-mno_002dmt-1681"></a>Use (do not use) MT Multithreading instructions. 314 315 <br><dt><code>-mlong64</code><dd><a name="index-mlong64-1682"></a>Force <code>long</code> types to be 64 bits wide. See <samp><span class="option">-mlong32</span></samp> for 316an explanation of the default and the way that the pointer size is 317determined. 318 319 <br><dt><code>-mlong32</code><dd><a name="index-mlong32-1683"></a>Force <code>long</code>, <code>int</code>, and pointer types to be 32 bits wide. 320 321 <p>The default size of <code>int</code>s, <code>long</code>s and pointers depends on 322the ABI. All the supported ABIs use 32-bit <code>int</code>s. The n64 ABI 323uses 64-bit <code>long</code>s, as does the 64-bit EABI; the others use 32432-bit <code>long</code>s. Pointers are the same size as <code>long</code>s, 325or the same size as integer registers, whichever is smaller. 326 327 <br><dt><code>-msym32</code><dt><code>-mno-sym32</code><dd><a name="index-msym32-1684"></a><a name="index-mno_002dsym32-1685"></a>Assume (do not assume) that all symbols have 32-bit values, regardless 328of the selected ABI. This option is useful in combination with 329<samp><span class="option">-mabi=64</span></samp> and <samp><span class="option">-mno-abicalls</span></samp> because it allows GCC 330to generate shorter and faster references to symbolic addresses. 331 332 <br><dt><code>-G </code><var>num</var><dd><a name="index-G-1686"></a>Put definitions of externally-visible data in a small data section 333if that data is no bigger than <var>num</var> bytes. GCC can then access 334the data more efficiently; see <samp><span class="option">-mgpopt</span></samp> for details. 335 336 <p>The default <samp><span class="option">-G</span></samp> option depends on the configuration. 337 338 <br><dt><code>-mlocal-sdata</code><dt><code>-mno-local-sdata</code><dd><a name="index-mlocal_002dsdata-1687"></a><a name="index-mno_002dlocal_002dsdata-1688"></a>Extend (do not extend) the <samp><span class="option">-G</span></samp> behavior to local data too, 339such as to static variables in C. <samp><span class="option">-mlocal-sdata</span></samp> is the 340default for all configurations. 341 342 <p>If the linker complains that an application is using too much small data, 343you might want to try rebuilding the less performance-critical parts with 344<samp><span class="option">-mno-local-sdata</span></samp>. You might also want to build large 345libraries with <samp><span class="option">-mno-local-sdata</span></samp>, so that the libraries leave 346more room for the main program. 347 348 <br><dt><code>-mextern-sdata</code><dt><code>-mno-extern-sdata</code><dd><a name="index-mextern_002dsdata-1689"></a><a name="index-mno_002dextern_002dsdata-1690"></a>Assume (do not assume) that externally-defined data will be in 349a small data section if that data is within the <samp><span class="option">-G</span></samp> limit. 350<samp><span class="option">-mextern-sdata</span></samp> is the default for all configurations. 351 352 <p>If you compile a module <var>Mod</var> with <samp><span class="option">-mextern-sdata</span></samp> <samp><span class="option">-G 353</span><var>num</var></samp> <samp><span class="option">-mgpopt</span></samp>, and <var>Mod</var> references a variable <var>Var</var> 354that is no bigger than <var>num</var> bytes, you must make sure that <var>Var</var> 355is placed in a small data section. If <var>Var</var> is defined by another 356module, you must either compile that module with a high-enough 357<samp><span class="option">-G</span></samp> setting or attach a <code>section</code> attribute to <var>Var</var>'s 358definition. If <var>Var</var> is common, you must link the application 359with a high-enough <samp><span class="option">-G</span></samp> setting. 360 361 <p>The easiest way of satisfying these restrictions is to compile 362and link every module with the same <samp><span class="option">-G</span></samp> option. However, 363you may wish to build a library that supports several different 364small data limits. You can do this by compiling the library with 365the highest supported <samp><span class="option">-G</span></samp> setting and additionally using 366<samp><span class="option">-mno-extern-sdata</span></samp> to stop the library from making assumptions 367about externally-defined data. 368 369 <br><dt><code>-mgpopt</code><dt><code>-mno-gpopt</code><dd><a name="index-mgpopt-1691"></a><a name="index-mno_002dgpopt-1692"></a>Use (do not use) GP-relative accesses for symbols that are known to be 370in a small data section; see <samp><span class="option">-G</span></samp>, <samp><span class="option">-mlocal-sdata</span></samp> and 371<samp><span class="option">-mextern-sdata</span></samp>. <samp><span class="option">-mgpopt</span></samp> is the default for all 372configurations. 373 374 <p><samp><span class="option">-mno-gpopt</span></samp> is useful for cases where the <code>$gp</code> register 375might not hold the value of <code>_gp</code>. For example, if the code is 376part of a library that might be used in a boot monitor, programs that 377call boot monitor routines will pass an unknown value in <code>$gp</code>. 378(In such situations, the boot monitor itself would usually be compiled 379with <samp><span class="option">-G0</span></samp>.) 380 381 <p><samp><span class="option">-mno-gpopt</span></samp> implies <samp><span class="option">-mno-local-sdata</span></samp> and 382<samp><span class="option">-mno-extern-sdata</span></samp>. 383 384 <br><dt><code>-membedded-data</code><dt><code>-mno-embedded-data</code><dd><a name="index-membedded_002ddata-1693"></a><a name="index-mno_002dembedded_002ddata-1694"></a>Allocate variables to the read-only data section first if possible, then 385next in the small data section if possible, otherwise in data. This gives 386slightly slower code than the default, but reduces the amount of RAM required 387when executing, and thus may be preferred for some embedded systems. 388 389 <br><dt><code>-muninit-const-in-rodata</code><dt><code>-mno-uninit-const-in-rodata</code><dd><a name="index-muninit_002dconst_002din_002drodata-1695"></a><a name="index-mno_002duninit_002dconst_002din_002drodata-1696"></a>Put uninitialized <code>const</code> variables in the read-only data section. 390This option is only meaningful in conjunction with <samp><span class="option">-membedded-data</span></samp>. 391 392 <br><dt><code>-mcode-readable=</code><var>setting</var><dd><a name="index-mcode_002dreadable-1697"></a>Specify whether GCC may generate code that reads from executable sections. 393There are three possible settings: 394 395 <dl> 396<dt><code>-mcode-readable=yes</code><dd>Instructions may freely access executable sections. This is the 397default setting. 398 399 <br><dt><code>-mcode-readable=pcrel</code><dd>MIPS16 PC-relative load instructions can access executable sections, 400but other instructions must not do so. This option is useful on 4KSc 401and 4KSd processors when the code TLBs have the Read Inhibit bit set. 402It is also useful on processors that can be configured to have a dual 403instruction/data SRAM interface and that, like the M4K, automatically 404redirect PC-relative loads to the instruction RAM. 405 406 <br><dt><code>-mcode-readable=no</code><dd>Instructions must not access executable sections. This option can be 407useful on targets that are configured to have a dual instruction/data 408SRAM interface but that (unlike the M4K) do not automatically redirect 409PC-relative loads to the instruction RAM. 410</dl> 411 412 <br><dt><code>-msplit-addresses</code><dt><code>-mno-split-addresses</code><dd><a name="index-msplit_002daddresses-1698"></a><a name="index-mno_002dsplit_002daddresses-1699"></a>Enable (disable) use of the <code>%hi()</code> and <code>%lo()</code> assembler 413relocation operators. This option has been superseded by 414<samp><span class="option">-mexplicit-relocs</span></samp> but is retained for backwards compatibility. 415 416 <br><dt><code>-mexplicit-relocs</code><dt><code>-mno-explicit-relocs</code><dd><a name="index-mexplicit_002drelocs-1700"></a><a name="index-mno_002dexplicit_002drelocs-1701"></a>Use (do not use) assembler relocation operators when dealing with symbolic 417addresses. The alternative, selected by <samp><span class="option">-mno-explicit-relocs</span></samp>, 418is to use assembler macros instead. 419 420 <p><samp><span class="option">-mexplicit-relocs</span></samp> is the default if GCC was configured 421to use an assembler that supports relocation operators. 422 423 <br><dt><code>-mcheck-zero-division</code><dt><code>-mno-check-zero-division</code><dd><a name="index-mcheck_002dzero_002ddivision-1702"></a><a name="index-mno_002dcheck_002dzero_002ddivision-1703"></a>Trap (do not trap) on integer division by zero. 424 425 <p>The default is <samp><span class="option">-mcheck-zero-division</span></samp>. 426 427 <br><dt><code>-mdivide-traps</code><dt><code>-mdivide-breaks</code><dd><a name="index-mdivide_002dtraps-1704"></a><a name="index-mdivide_002dbreaks-1705"></a>MIPS systems check for division by zero by generating either a 428conditional trap or a break instruction. Using traps results in 429smaller code, but is only supported on MIPS II and later. Also, some 430versions of the Linux kernel have a bug that prevents trap from 431generating the proper signal (<code>SIGFPE</code>). Use <samp><span class="option">-mdivide-traps</span></samp> to 432allow conditional traps on architectures that support them and 433<samp><span class="option">-mdivide-breaks</span></samp> to force the use of breaks. 434 435 <p>The default is usually <samp><span class="option">-mdivide-traps</span></samp>, but this can be 436overridden at configure time using <samp><span class="option">--with-divide=breaks</span></samp>. 437Divide-by-zero checks can be completely disabled using 438<samp><span class="option">-mno-check-zero-division</span></samp>. 439 440 <br><dt><code>-mmemcpy</code><dt><code>-mno-memcpy</code><dd><a name="index-mmemcpy-1706"></a><a name="index-mno_002dmemcpy-1707"></a>Force (do not force) the use of <code>memcpy()</code> for non-trivial block 441moves. The default is <samp><span class="option">-mno-memcpy</span></samp>, which allows GCC to inline 442most constant-sized copies. 443 444 <br><dt><code>-mlong-calls</code><dt><code>-mno-long-calls</code><dd><a name="index-mlong_002dcalls-1708"></a><a name="index-mno_002dlong_002dcalls-1709"></a>Disable (do not disable) use of the <code>jal</code> instruction. Calling 445functions using <code>jal</code> is more efficient but requires the caller 446and callee to be in the same 256 megabyte segment. 447 448 <p>This option has no effect on abicalls code. The default is 449<samp><span class="option">-mno-long-calls</span></samp>. 450 451 <br><dt><code>-mmad</code><dt><code>-mno-mad</code><dd><a name="index-mmad-1710"></a><a name="index-mno_002dmad-1711"></a>Enable (disable) use of the <code>mad</code>, <code>madu</code> and <code>mul</code> 452instructions, as provided by the R4650 ISA. 453 454 <br><dt><code>-mfused-madd</code><dt><code>-mno-fused-madd</code><dd><a name="index-mfused_002dmadd-1712"></a><a name="index-mno_002dfused_002dmadd-1713"></a>Enable (disable) use of the floating point multiply-accumulate 455instructions, when they are available. The default is 456<samp><span class="option">-mfused-madd</span></samp>. 457 458 <p>On the R8000 CPU when multiply-accumulate instructions are used, 459the intermediate product is calculated to infinite precision 460and is not subject to the FCSR Flush to Zero bit. This may be 461undesirable in some circumstances. On other processors the result 462is numerically identical to the equivalent computation using 463separate multiply, add, subtract and negate instructions. 464 465 <br><dt><code>-nocpp</code><dd><a name="index-nocpp-1714"></a>Tell the MIPS assembler to not run its preprocessor over user 466assembler files (with a ‘<samp><span class="samp">.s</span></samp>’ suffix) when assembling them. 467 468 <br><dt><code>-mfix-24k</code><br><dt><code>-mno-fix-24k</code><dd><a name="index-mfix_002d24k-1715"></a><a name="index-mno_002dfix_002d24k-1716"></a>Work around the 24K E48 (lost data on stores during refill) errata. 469The workarounds are implemented by the assembler rather than by GCC. 470 471 <br><dt><code>-mfix-r4000</code><dt><code>-mno-fix-r4000</code><dd><a name="index-mfix_002dr4000-1717"></a><a name="index-mno_002dfix_002dr4000-1718"></a>Work around certain R4000 CPU errata: 472 <ul> 473<li>A double-word or a variable shift may give an incorrect result if executed 474immediately after starting an integer division. 475<li>A double-word or a variable shift may give an incorrect result if executed 476while an integer multiplication is in progress. 477<li>An integer division may give an incorrect result if started in a delay slot 478of a taken branch or a jump. 479</ul> 480 481 <br><dt><code>-mfix-r4400</code><dt><code>-mno-fix-r4400</code><dd><a name="index-mfix_002dr4400-1719"></a><a name="index-mno_002dfix_002dr4400-1720"></a>Work around certain R4400 CPU errata: 482 <ul> 483<li>A double-word or a variable shift may give an incorrect result if executed 484immediately after starting an integer division. 485</ul> 486 487 <br><dt><code>-mfix-r10000</code><dt><code>-mno-fix-r10000</code><dd><a name="index-mfix_002dr10000-1721"></a><a name="index-mno_002dfix_002dr10000-1722"></a>Work around certain R10000 errata: 488 <ul> 489<li><code>ll</code>/<code>sc</code> sequences may not behave atomically on revisions 490prior to 3.0. They may deadlock on revisions 2.6 and earlier. 491</ul> 492 493 <p>This option can only be used if the target architecture supports 494branch-likely instructions. <samp><span class="option">-mfix-r10000</span></samp> is the default when 495<samp><span class="option">-march=r10000</span></samp> is used; <samp><span class="option">-mno-fix-r10000</span></samp> is the default 496otherwise. 497 498 <br><dt><code>-mfix-vr4120</code><dt><code>-mno-fix-vr4120</code><dd><a name="index-mfix_002dvr4120-1723"></a>Work around certain VR4120 errata: 499 <ul> 500<li><code>dmultu</code> does not always produce the correct result. 501<li><code>div</code> and <code>ddiv</code> do not always produce the correct result if one 502of the operands is negative. 503</ul> 504 The workarounds for the division errata rely on special functions in 505<samp><span class="file">libgcc.a</span></samp>. At present, these functions are only provided by 506the <code>mips64vr*-elf</code> configurations. 507 508 <p>Other VR4120 errata require a nop to be inserted between certain pairs of 509instructions. These errata are handled by the assembler, not by GCC itself. 510 511 <br><dt><code>-mfix-vr4130</code><dd><a name="index-mfix_002dvr4130-1724"></a>Work around the VR4130 <code>mflo</code>/<code>mfhi</code> errata. The 512workarounds are implemented by the assembler rather than by GCC, 513although GCC will avoid using <code>mflo</code> and <code>mfhi</code> if the 514VR4130 <code>macc</code>, <code>macchi</code>, <code>dmacc</code> and <code>dmacchi</code> 515instructions are available instead. 516 517 <br><dt><code>-mfix-sb1</code><dt><code>-mno-fix-sb1</code><dd><a name="index-mfix_002dsb1-1725"></a>Work around certain SB-1 CPU core errata. 518(This flag currently works around the SB-1 revision 2 519“F1” and “F2” floating point errata.) 520 521 <br><dt><code>-mr10k-cache-barrier=</code><var>setting</var><dd><a name="index-mr10k_002dcache_002dbarrier-1726"></a>Specify whether GCC should insert cache barriers to avoid the 522side-effects of speculation on R10K processors. 523 524 <p>In common with many processors, the R10K tries to predict the outcome 525of a conditional branch and speculatively executes instructions from 526the “taken” branch. It later aborts these instructions if the 527predicted outcome was wrong. However, on the R10K, even aborted 528instructions can have side effects. 529 530 <p>This problem only affects kernel stores and, depending on the system, 531kernel loads. As an example, a speculatively-executed store may load 532the target memory into cache and mark the cache line as dirty, even if 533the store itself is later aborted. If a DMA operation writes to the 534same area of memory before the “dirty” line is flushed, the cached 535data will overwrite the DMA-ed data. See the R10K processor manual 536for a full description, including other potential problems. 537 538 <p>One workaround is to insert cache barrier instructions before every memory 539access that might be speculatively executed and that might have side 540effects even if aborted. <samp><span class="option">-mr10k-cache-barrier=</span><var>setting</var></samp> 541controls GCC's implementation of this workaround. It assumes that 542aborted accesses to any byte in the following regions will not have 543side effects: 544 545 <ol type=1 start=1> 546<li>the memory occupied by the current function's stack frame; 547 548 <li>the memory occupied by an incoming stack argument; 549 550 <li>the memory occupied by an object with a link-time-constant address. 551 </ol> 552 553 <p>It is the kernel's responsibility to ensure that speculative 554accesses to these regions are indeed safe. 555 556 <p>If the input program contains a function declaration such as: 557 558 <pre class="smallexample"> void foo (void); 559</pre> 560 <p>then the implementation of <code>foo</code> must allow <code>j foo</code> and 561<code>jal foo</code> to be executed speculatively. GCC honors this 562restriction for functions it compiles itself. It expects non-GCC 563functions (such as hand-written assembly code) to do the same. 564 565 <p>The option has three forms: 566 567 <dl> 568<dt><code>-mr10k-cache-barrier=load-store</code><dd>Insert a cache barrier before a load or store that might be 569speculatively executed and that might have side effects even 570if aborted. 571 572 <br><dt><code>-mr10k-cache-barrier=store</code><dd>Insert a cache barrier before a store that might be speculatively 573executed and that might have side effects even if aborted. 574 575 <br><dt><code>-mr10k-cache-barrier=none</code><dd>Disable the insertion of cache barriers. This is the default setting. 576</dl> 577 578 <br><dt><code>-mflush-func=</code><var>func</var><dt><code>-mno-flush-func</code><dd><a name="index-mflush_002dfunc-1727"></a>Specifies the function to call to flush the I and D caches, or to not 579call any such function. If called, the function must take the same 580arguments as the common <code>_flush_func()</code>, that is, the address of the 581memory range for which the cache is being flushed, the size of the 582memory range, and the number 3 (to flush both caches). The default 583depends on the target GCC was configured for, but commonly is either 584‘<samp><span class="samp">_flush_func</span></samp>’ or ‘<samp><span class="samp">__cpu_flush</span></samp>’. 585 586 <br><dt><code>mbranch-cost=</code><var>num</var><dd><a name="index-mbranch_002dcost-1728"></a>Set the cost of branches to roughly <var>num</var> “simple” instructions. 587This cost is only a heuristic and is not guaranteed to produce 588consistent results across releases. A zero cost redundantly selects 589the default, which is based on the <samp><span class="option">-mtune</span></samp> setting. 590 591 <br><dt><code>-mbranch-likely</code><dt><code>-mno-branch-likely</code><dd><a name="index-mbranch_002dlikely-1729"></a><a name="index-mno_002dbranch_002dlikely-1730"></a>Enable or disable use of Branch Likely instructions, regardless of the 592default for the selected architecture. By default, Branch Likely 593instructions may be generated if they are supported by the selected 594architecture. An exception is for the MIPS32 and MIPS64 architectures 595and processors which implement those architectures; for those, Branch 596Likely instructions will not be generated by default because the MIPS32 597and MIPS64 architectures specifically deprecate their use. 598 599 <br><dt><code>-mfp-exceptions</code><dt><code>-mno-fp-exceptions</code><dd><a name="index-mfp_002dexceptions-1731"></a>Specifies whether FP exceptions are enabled. This affects how we schedule 600FP instructions for some processors. The default is that FP exceptions are 601enabled. 602 603 <p>For instance, on the SB-1, if FP exceptions are disabled, and we are emitting 60464-bit code, then we can use both FP pipes. Otherwise, we can only use one 605FP pipe. 606 607 <br><dt><code>-mvr4130-align</code><dt><code>-mno-vr4130-align</code><dd><a name="index-mvr4130_002dalign-1732"></a>The VR4130 pipeline is two-way superscalar, but can only issue two 608instructions together if the first one is 8-byte aligned. When this 609option is enabled, GCC will align pairs of instructions that it 610thinks should execute in parallel. 611 612 <p>This option only has an effect when optimizing for the VR4130. 613It normally makes code faster, but at the expense of making it bigger. 614It is enabled by default at optimization level <samp><span class="option">-O3</span></samp>. 615 616 <br><dt><code>-msynci</code><dt><code>-mno-synci</code><dd><a name="index-msynci-1733"></a>Enable (disable) generation of <code>synci</code> instructions on 617architectures that support it. The <code>synci</code> instructions (if 618enabled) will be generated when <code>__builtin___clear_cache()</code> is 619compiled. 620 621 <p>This option defaults to <code>-mno-synci</code>, but the default can be 622overridden by configuring with <code>--with-synci</code>. 623 624 <p>When compiling code for single processor systems, it is generally safe 625to use <code>synci</code>. However, on many multi-core (SMP) systems, it 626will not invalidate the instruction caches on all cores and may lead 627to undefined behavior. 628 629 <br><dt><code>-mrelax-pic-calls</code><dt><code>-mno-relax-pic-calls</code><dd><a name="index-mrelax_002dpic_002dcalls-1734"></a>Try to turn PIC calls that are normally dispatched via register 630<code>$25</code> into direct calls. This is only possible if the linker can 631resolve the destination at link-time and if the destination is within 632range for a direct call. 633 634 <p><samp><span class="option">-mrelax-pic-calls</span></samp> is the default if GCC was configured to use 635an assembler and a linker that supports the <code>.reloc</code> assembly 636directive and <code>-mexplicit-relocs</code> is in effect. With 637<code>-mno-explicit-relocs</code>, this optimization can be performed by the 638assembler and the linker alone without help from the compiler. 639 640 <br><dt><code>-mmcount-ra-address</code><dt><code>-mno-mcount-ra-address</code><dd><a name="index-mmcount_002dra_002daddress-1735"></a><a name="index-mno_002dmcount_002dra_002daddress-1736"></a>Emit (do not emit) code that allows <code>_mcount</code> to modify the 641calling function's return address. When enabled, this option extends 642the usual <code>_mcount</code> interface with a new <var>ra-address</var> 643parameter, which has type <code>intptr_t *</code> and is passed in register 644<code>$12</code>. <code>_mcount</code> can then modify the return address by 645doing both of the following: 646 <ul> 647<li>Returning the new address in register <code>$31</code>. 648<li>Storing the new address in <code>*</code><var>ra-address</var>, 649if <var>ra-address</var> is nonnull. 650</ul> 651 652 <p>The default is <samp><span class="option">-mno-mcount-ra-address</span></samp>. 653 654 </dl> 655 656 </body></html> 657 658