1<html lang="en"> 2<head> 3<title>ARM NEON Intrinsics - Using the GNU Compiler Collection (GCC)</title> 4<meta http-equiv="Content-Type" content="text/html"> 5<meta name="description" content="Using the GNU Compiler Collection (GCC)"> 6<meta name="generator" content="makeinfo 4.13"> 7<link title="Top" rel="start" href="index.html#Top"> 8<link rel="up" href="Target-Builtins.html#Target-Builtins" title="Target Builtins"> 9<link rel="prev" href="ARM-iWMMXt-Built_002din-Functions.html#ARM-iWMMXt-Built_002din-Functions" title="ARM iWMMXt Built-in Functions"> 10<link rel="next" href="Blackfin-Built_002din-Functions.html#Blackfin-Built_002din-Functions" title="Blackfin Built-in Functions"> 11<link href="http://www.gnu.org/software/texinfo/" rel="generator-home" title="Texinfo Homepage"> 12<!-- 13Copyright (C) 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 141998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 152010 Free Software Foundation, Inc. 16 17Permission is granted to copy, distribute and/or modify this document 18under the terms of the GNU Free Documentation License, Version 1.3 or 19any later version published by the Free Software Foundation; with the 20Invariant Sections being ``Funding Free Software'', the Front-Cover 21Texts being (a) (see below), and with the Back-Cover Texts being (b) 22(see below). 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href="ARM-iWMMXt-Built_002din-Functions.html#ARM-iWMMXt-Built_002din-Functions">ARM iWMMXt Built-in Functions</a>, 54Up: <a rel="up" accesskey="u" href="Target-Builtins.html#Target-Builtins">Target Builtins</a> 55<hr> 56</div> 57 58<h4 class="subsection">6.54.3 ARM NEON Intrinsics</h4> 59 60<p>These built-in intrinsics for the ARM Advanced SIMD extension are available 61when the <samp><span class="option">-mfpu=neon</span></samp> switch is used: 62 63<!-- Copyright (C) 2006 Free Software Foundation, Inc. --> 64<!-- This is part of the GCC manual. --> 65<!-- For copying conditions, see the file gcc.texi. --> 66<!-- This file is generated automatically using gcc/config/arm/neon-docgen.ml --> 67<!-- Please do not edit manually. --> 68<h5 class="subsubsection">6.54.3.1 Addition</h5> 69 70 <ul> 71<li>uint32x2_t vadd_u32 (uint32x2_t, uint32x2_t) 72<br><em>Form of expected instruction(s):</em> <code>vadd.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 73</ul> 74 75 <ul> 76<li>uint16x4_t vadd_u16 (uint16x4_t, uint16x4_t) 77<br><em>Form of expected instruction(s):</em> <code>vadd.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 78</ul> 79 80 <ul> 81<li>uint8x8_t vadd_u8 (uint8x8_t, uint8x8_t) 82<br><em>Form of expected instruction(s):</em> <code>vadd.i8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 83</ul> 84 85 <ul> 86<li>int32x2_t vadd_s32 (int32x2_t, int32x2_t) 87<br><em>Form of expected instruction(s):</em> <code>vadd.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 88</ul> 89 90 <ul> 91<li>int16x4_t vadd_s16 (int16x4_t, int16x4_t) 92<br><em>Form of expected instruction(s):</em> <code>vadd.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 93</ul> 94 95 <ul> 96<li>int8x8_t vadd_s8 (int8x8_t, int8x8_t) 97<br><em>Form of expected instruction(s):</em> <code>vadd.i8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 98</ul> 99 100 <ul> 101<li>float32x2_t vadd_f32 (float32x2_t, float32x2_t) 102<br><em>Form of expected instruction(s):</em> <code>vadd.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 103</ul> 104 105 <ul> 106<li>uint64x1_t vadd_u64 (uint64x1_t, uint64x1_t) 107</ul> 108 109 <ul> 110<li>int64x1_t vadd_s64 (int64x1_t, int64x1_t) 111</ul> 112 113 <ul> 114<li>uint32x4_t vaddq_u32 (uint32x4_t, uint32x4_t) 115<br><em>Form of expected instruction(s):</em> <code>vadd.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 116</ul> 117 118 <ul> 119<li>uint16x8_t vaddq_u16 (uint16x8_t, uint16x8_t) 120<br><em>Form of expected instruction(s):</em> <code>vadd.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 121</ul> 122 123 <ul> 124<li>uint8x16_t vaddq_u8 (uint8x16_t, uint8x16_t) 125<br><em>Form of expected instruction(s):</em> <code>vadd.i8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 126</ul> 127 128 <ul> 129<li>int32x4_t vaddq_s32 (int32x4_t, int32x4_t) 130<br><em>Form of expected instruction(s):</em> <code>vadd.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 131</ul> 132 133 <ul> 134<li>int16x8_t vaddq_s16 (int16x8_t, int16x8_t) 135<br><em>Form of expected instruction(s):</em> <code>vadd.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 136</ul> 137 138 <ul> 139<li>int8x16_t vaddq_s8 (int8x16_t, int8x16_t) 140<br><em>Form of expected instruction(s):</em> <code>vadd.i8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 141</ul> 142 143 <ul> 144<li>uint64x2_t vaddq_u64 (uint64x2_t, uint64x2_t) 145<br><em>Form of expected instruction(s):</em> <code>vadd.i64 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 146</ul> 147 148 <ul> 149<li>int64x2_t vaddq_s64 (int64x2_t, int64x2_t) 150<br><em>Form of expected instruction(s):</em> <code>vadd.i64 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 151</ul> 152 153 <ul> 154<li>float32x4_t vaddq_f32 (float32x4_t, float32x4_t) 155<br><em>Form of expected instruction(s):</em> <code>vadd.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 156</ul> 157 158 <ul> 159<li>uint64x2_t vaddl_u32 (uint32x2_t, uint32x2_t) 160<br><em>Form of expected instruction(s):</em> <code>vaddl.u32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 161</ul> 162 163 <ul> 164<li>uint32x4_t vaddl_u16 (uint16x4_t, uint16x4_t) 165<br><em>Form of expected instruction(s):</em> <code>vaddl.u16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 166</ul> 167 168 <ul> 169<li>uint16x8_t vaddl_u8 (uint8x8_t, uint8x8_t) 170<br><em>Form of expected instruction(s):</em> <code>vaddl.u8 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 171</ul> 172 173 <ul> 174<li>int64x2_t vaddl_s32 (int32x2_t, int32x2_t) 175<br><em>Form of expected instruction(s):</em> <code>vaddl.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 176</ul> 177 178 <ul> 179<li>int32x4_t vaddl_s16 (int16x4_t, int16x4_t) 180<br><em>Form of expected instruction(s):</em> <code>vaddl.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 181</ul> 182 183 <ul> 184<li>int16x8_t vaddl_s8 (int8x8_t, int8x8_t) 185<br><em>Form of expected instruction(s):</em> <code>vaddl.s8 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 186</ul> 187 188 <ul> 189<li>uint64x2_t vaddw_u32 (uint64x2_t, uint32x2_t) 190<br><em>Form of expected instruction(s):</em> <code>vaddw.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var> 191</ul> 192 193 <ul> 194<li>uint32x4_t vaddw_u16 (uint32x4_t, uint16x4_t) 195<br><em>Form of expected instruction(s):</em> <code>vaddw.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var> 196</ul> 197 198 <ul> 199<li>uint16x8_t vaddw_u8 (uint16x8_t, uint8x8_t) 200<br><em>Form of expected instruction(s):</em> <code>vaddw.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var> 201</ul> 202 203 <ul> 204<li>int64x2_t vaddw_s32 (int64x2_t, int32x2_t) 205<br><em>Form of expected instruction(s):</em> <code>vaddw.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var> 206</ul> 207 208 <ul> 209<li>int32x4_t vaddw_s16 (int32x4_t, int16x4_t) 210<br><em>Form of expected instruction(s):</em> <code>vaddw.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var> 211</ul> 212 213 <ul> 214<li>int16x8_t vaddw_s8 (int16x8_t, int8x8_t) 215<br><em>Form of expected instruction(s):</em> <code>vaddw.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var> 216</ul> 217 218 <ul> 219<li>uint32x2_t vhadd_u32 (uint32x2_t, uint32x2_t) 220<br><em>Form of expected instruction(s):</em> <code>vhadd.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 221</ul> 222 223 <ul> 224<li>uint16x4_t vhadd_u16 (uint16x4_t, uint16x4_t) 225<br><em>Form of expected instruction(s):</em> <code>vhadd.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 226</ul> 227 228 <ul> 229<li>uint8x8_t vhadd_u8 (uint8x8_t, uint8x8_t) 230<br><em>Form of expected instruction(s):</em> <code>vhadd.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 231</ul> 232 233 <ul> 234<li>int32x2_t vhadd_s32 (int32x2_t, int32x2_t) 235<br><em>Form of expected instruction(s):</em> <code>vhadd.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 236</ul> 237 238 <ul> 239<li>int16x4_t vhadd_s16 (int16x4_t, int16x4_t) 240<br><em>Form of expected instruction(s):</em> <code>vhadd.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 241</ul> 242 243 <ul> 244<li>int8x8_t vhadd_s8 (int8x8_t, int8x8_t) 245<br><em>Form of expected instruction(s):</em> <code>vhadd.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 246</ul> 247 248 <ul> 249<li>uint32x4_t vhaddq_u32 (uint32x4_t, uint32x4_t) 250<br><em>Form of expected instruction(s):</em> <code>vhadd.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 251</ul> 252 253 <ul> 254<li>uint16x8_t vhaddq_u16 (uint16x8_t, uint16x8_t) 255<br><em>Form of expected instruction(s):</em> <code>vhadd.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 256</ul> 257 258 <ul> 259<li>uint8x16_t vhaddq_u8 (uint8x16_t, uint8x16_t) 260<br><em>Form of expected instruction(s):</em> <code>vhadd.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 261</ul> 262 263 <ul> 264<li>int32x4_t vhaddq_s32 (int32x4_t, int32x4_t) 265<br><em>Form of expected instruction(s):</em> <code>vhadd.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 266</ul> 267 268 <ul> 269<li>int16x8_t vhaddq_s16 (int16x8_t, int16x8_t) 270<br><em>Form of expected instruction(s):</em> <code>vhadd.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 271</ul> 272 273 <ul> 274<li>int8x16_t vhaddq_s8 (int8x16_t, int8x16_t) 275<br><em>Form of expected instruction(s):</em> <code>vhadd.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 276</ul> 277 278 <ul> 279<li>uint32x2_t vrhadd_u32 (uint32x2_t, uint32x2_t) 280<br><em>Form of expected instruction(s):</em> <code>vrhadd.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 281</ul> 282 283 <ul> 284<li>uint16x4_t vrhadd_u16 (uint16x4_t, uint16x4_t) 285<br><em>Form of expected instruction(s):</em> <code>vrhadd.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 286</ul> 287 288 <ul> 289<li>uint8x8_t vrhadd_u8 (uint8x8_t, uint8x8_t) 290<br><em>Form of expected instruction(s):</em> <code>vrhadd.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 291</ul> 292 293 <ul> 294<li>int32x2_t vrhadd_s32 (int32x2_t, int32x2_t) 295<br><em>Form of expected instruction(s):</em> <code>vrhadd.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 296</ul> 297 298 <ul> 299<li>int16x4_t vrhadd_s16 (int16x4_t, int16x4_t) 300<br><em>Form of expected instruction(s):</em> <code>vrhadd.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 301</ul> 302 303 <ul> 304<li>int8x8_t vrhadd_s8 (int8x8_t, int8x8_t) 305<br><em>Form of expected instruction(s):</em> <code>vrhadd.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 306</ul> 307 308 <ul> 309<li>uint32x4_t vrhaddq_u32 (uint32x4_t, uint32x4_t) 310<br><em>Form of expected instruction(s):</em> <code>vrhadd.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 311</ul> 312 313 <ul> 314<li>uint16x8_t vrhaddq_u16 (uint16x8_t, uint16x8_t) 315<br><em>Form of expected instruction(s):</em> <code>vrhadd.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 316</ul> 317 318 <ul> 319<li>uint8x16_t vrhaddq_u8 (uint8x16_t, uint8x16_t) 320<br><em>Form of expected instruction(s):</em> <code>vrhadd.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 321</ul> 322 323 <ul> 324<li>int32x4_t vrhaddq_s32 (int32x4_t, int32x4_t) 325<br><em>Form of expected instruction(s):</em> <code>vrhadd.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 326</ul> 327 328 <ul> 329<li>int16x8_t vrhaddq_s16 (int16x8_t, int16x8_t) 330<br><em>Form of expected instruction(s):</em> <code>vrhadd.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 331</ul> 332 333 <ul> 334<li>int8x16_t vrhaddq_s8 (int8x16_t, int8x16_t) 335<br><em>Form of expected instruction(s):</em> <code>vrhadd.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 336</ul> 337 338 <ul> 339<li>uint32x2_t vqadd_u32 (uint32x2_t, uint32x2_t) 340<br><em>Form of expected instruction(s):</em> <code>vqadd.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 341</ul> 342 343 <ul> 344<li>uint16x4_t vqadd_u16 (uint16x4_t, uint16x4_t) 345<br><em>Form of expected instruction(s):</em> <code>vqadd.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 346</ul> 347 348 <ul> 349<li>uint8x8_t vqadd_u8 (uint8x8_t, uint8x8_t) 350<br><em>Form of expected instruction(s):</em> <code>vqadd.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 351</ul> 352 353 <ul> 354<li>int32x2_t vqadd_s32 (int32x2_t, int32x2_t) 355<br><em>Form of expected instruction(s):</em> <code>vqadd.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 356</ul> 357 358 <ul> 359<li>int16x4_t vqadd_s16 (int16x4_t, int16x4_t) 360<br><em>Form of expected instruction(s):</em> <code>vqadd.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 361</ul> 362 363 <ul> 364<li>int8x8_t vqadd_s8 (int8x8_t, int8x8_t) 365<br><em>Form of expected instruction(s):</em> <code>vqadd.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 366</ul> 367 368 <ul> 369<li>uint64x1_t vqadd_u64 (uint64x1_t, uint64x1_t) 370<br><em>Form of expected instruction(s):</em> <code>vqadd.u64 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 371</ul> 372 373 <ul> 374<li>int64x1_t vqadd_s64 (int64x1_t, int64x1_t) 375<br><em>Form of expected instruction(s):</em> <code>vqadd.s64 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 376</ul> 377 378 <ul> 379<li>uint32x4_t vqaddq_u32 (uint32x4_t, uint32x4_t) 380<br><em>Form of expected instruction(s):</em> <code>vqadd.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 381</ul> 382 383 <ul> 384<li>uint16x8_t vqaddq_u16 (uint16x8_t, uint16x8_t) 385<br><em>Form of expected instruction(s):</em> <code>vqadd.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 386</ul> 387 388 <ul> 389<li>uint8x16_t vqaddq_u8 (uint8x16_t, uint8x16_t) 390<br><em>Form of expected instruction(s):</em> <code>vqadd.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 391</ul> 392 393 <ul> 394<li>int32x4_t vqaddq_s32 (int32x4_t, int32x4_t) 395<br><em>Form of expected instruction(s):</em> <code>vqadd.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 396</ul> 397 398 <ul> 399<li>int16x8_t vqaddq_s16 (int16x8_t, int16x8_t) 400<br><em>Form of expected instruction(s):</em> <code>vqadd.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 401</ul> 402 403 <ul> 404<li>int8x16_t vqaddq_s8 (int8x16_t, int8x16_t) 405<br><em>Form of expected instruction(s):</em> <code>vqadd.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 406</ul> 407 408 <ul> 409<li>uint64x2_t vqaddq_u64 (uint64x2_t, uint64x2_t) 410<br><em>Form of expected instruction(s):</em> <code>vqadd.u64 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 411</ul> 412 413 <ul> 414<li>int64x2_t vqaddq_s64 (int64x2_t, int64x2_t) 415<br><em>Form of expected instruction(s):</em> <code>vqadd.s64 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 416</ul> 417 418 <ul> 419<li>uint32x2_t vaddhn_u64 (uint64x2_t, uint64x2_t) 420<br><em>Form of expected instruction(s):</em> <code>vaddhn.i64 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 421</ul> 422 423 <ul> 424<li>uint16x4_t vaddhn_u32 (uint32x4_t, uint32x4_t) 425<br><em>Form of expected instruction(s):</em> <code>vaddhn.i32 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 426</ul> 427 428 <ul> 429<li>uint8x8_t vaddhn_u16 (uint16x8_t, uint16x8_t) 430<br><em>Form of expected instruction(s):</em> <code>vaddhn.i16 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 431</ul> 432 433 <ul> 434<li>int32x2_t vaddhn_s64 (int64x2_t, int64x2_t) 435<br><em>Form of expected instruction(s):</em> <code>vaddhn.i64 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 436</ul> 437 438 <ul> 439<li>int16x4_t vaddhn_s32 (int32x4_t, int32x4_t) 440<br><em>Form of expected instruction(s):</em> <code>vaddhn.i32 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 441</ul> 442 443 <ul> 444<li>int8x8_t vaddhn_s16 (int16x8_t, int16x8_t) 445<br><em>Form of expected instruction(s):</em> <code>vaddhn.i16 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 446</ul> 447 448 <ul> 449<li>uint32x2_t vraddhn_u64 (uint64x2_t, uint64x2_t) 450<br><em>Form of expected instruction(s):</em> <code>vraddhn.i64 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 451</ul> 452 453 <ul> 454<li>uint16x4_t vraddhn_u32 (uint32x4_t, uint32x4_t) 455<br><em>Form of expected instruction(s):</em> <code>vraddhn.i32 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 456</ul> 457 458 <ul> 459<li>uint8x8_t vraddhn_u16 (uint16x8_t, uint16x8_t) 460<br><em>Form of expected instruction(s):</em> <code>vraddhn.i16 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 461</ul> 462 463 <ul> 464<li>int32x2_t vraddhn_s64 (int64x2_t, int64x2_t) 465<br><em>Form of expected instruction(s):</em> <code>vraddhn.i64 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 466</ul> 467 468 <ul> 469<li>int16x4_t vraddhn_s32 (int32x4_t, int32x4_t) 470<br><em>Form of expected instruction(s):</em> <code>vraddhn.i32 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 471</ul> 472 473 <ul> 474<li>int8x8_t vraddhn_s16 (int16x8_t, int16x8_t) 475<br><em>Form of expected instruction(s):</em> <code>vraddhn.i16 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 476</ul> 477 478<h5 class="subsubsection">6.54.3.2 Multiplication</h5> 479 480 <ul> 481<li>uint32x2_t vmul_u32 (uint32x2_t, uint32x2_t) 482<br><em>Form of expected instruction(s):</em> <code>vmul.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 483</ul> 484 485 <ul> 486<li>uint16x4_t vmul_u16 (uint16x4_t, uint16x4_t) 487<br><em>Form of expected instruction(s):</em> <code>vmul.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 488</ul> 489 490 <ul> 491<li>uint8x8_t vmul_u8 (uint8x8_t, uint8x8_t) 492<br><em>Form of expected instruction(s):</em> <code>vmul.i8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 493</ul> 494 495 <ul> 496<li>int32x2_t vmul_s32 (int32x2_t, int32x2_t) 497<br><em>Form of expected instruction(s):</em> <code>vmul.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 498</ul> 499 500 <ul> 501<li>int16x4_t vmul_s16 (int16x4_t, int16x4_t) 502<br><em>Form of expected instruction(s):</em> <code>vmul.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 503</ul> 504 505 <ul> 506<li>int8x8_t vmul_s8 (int8x8_t, int8x8_t) 507<br><em>Form of expected instruction(s):</em> <code>vmul.i8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 508</ul> 509 510 <ul> 511<li>float32x2_t vmul_f32 (float32x2_t, float32x2_t) 512<br><em>Form of expected instruction(s):</em> <code>vmul.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 513</ul> 514 515 <ul> 516<li>poly8x8_t vmul_p8 (poly8x8_t, poly8x8_t) 517<br><em>Form of expected instruction(s):</em> <code>vmul.p8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 518</ul> 519 520 <ul> 521<li>uint32x4_t vmulq_u32 (uint32x4_t, uint32x4_t) 522<br><em>Form of expected instruction(s):</em> <code>vmul.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 523</ul> 524 525 <ul> 526<li>uint16x8_t vmulq_u16 (uint16x8_t, uint16x8_t) 527<br><em>Form of expected instruction(s):</em> <code>vmul.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 528</ul> 529 530 <ul> 531<li>uint8x16_t vmulq_u8 (uint8x16_t, uint8x16_t) 532<br><em>Form of expected instruction(s):</em> <code>vmul.i8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 533</ul> 534 535 <ul> 536<li>int32x4_t vmulq_s32 (int32x4_t, int32x4_t) 537<br><em>Form of expected instruction(s):</em> <code>vmul.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 538</ul> 539 540 <ul> 541<li>int16x8_t vmulq_s16 (int16x8_t, int16x8_t) 542<br><em>Form of expected instruction(s):</em> <code>vmul.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 543</ul> 544 545 <ul> 546<li>int8x16_t vmulq_s8 (int8x16_t, int8x16_t) 547<br><em>Form of expected instruction(s):</em> <code>vmul.i8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 548</ul> 549 550 <ul> 551<li>float32x4_t vmulq_f32 (float32x4_t, float32x4_t) 552<br><em>Form of expected instruction(s):</em> <code>vmul.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 553</ul> 554 555 <ul> 556<li>poly8x16_t vmulq_p8 (poly8x16_t, poly8x16_t) 557<br><em>Form of expected instruction(s):</em> <code>vmul.p8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 558</ul> 559 560 <ul> 561<li>int32x2_t vqdmulh_s32 (int32x2_t, int32x2_t) 562<br><em>Form of expected instruction(s):</em> <code>vqdmulh.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 563</ul> 564 565 <ul> 566<li>int16x4_t vqdmulh_s16 (int16x4_t, int16x4_t) 567<br><em>Form of expected instruction(s):</em> <code>vqdmulh.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 568</ul> 569 570 <ul> 571<li>int32x4_t vqdmulhq_s32 (int32x4_t, int32x4_t) 572<br><em>Form of expected instruction(s):</em> <code>vqdmulh.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 573</ul> 574 575 <ul> 576<li>int16x8_t vqdmulhq_s16 (int16x8_t, int16x8_t) 577<br><em>Form of expected instruction(s):</em> <code>vqdmulh.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 578</ul> 579 580 <ul> 581<li>int32x2_t vqrdmulh_s32 (int32x2_t, int32x2_t) 582<br><em>Form of expected instruction(s):</em> <code>vqrdmulh.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 583</ul> 584 585 <ul> 586<li>int16x4_t vqrdmulh_s16 (int16x4_t, int16x4_t) 587<br><em>Form of expected instruction(s):</em> <code>vqrdmulh.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 588</ul> 589 590 <ul> 591<li>int32x4_t vqrdmulhq_s32 (int32x4_t, int32x4_t) 592<br><em>Form of expected instruction(s):</em> <code>vqrdmulh.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 593</ul> 594 595 <ul> 596<li>int16x8_t vqrdmulhq_s16 (int16x8_t, int16x8_t) 597<br><em>Form of expected instruction(s):</em> <code>vqrdmulh.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 598</ul> 599 600 <ul> 601<li>uint64x2_t vmull_u32 (uint32x2_t, uint32x2_t) 602<br><em>Form of expected instruction(s):</em> <code>vmull.u32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 603</ul> 604 605 <ul> 606<li>uint32x4_t vmull_u16 (uint16x4_t, uint16x4_t) 607<br><em>Form of expected instruction(s):</em> <code>vmull.u16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 608</ul> 609 610 <ul> 611<li>uint16x8_t vmull_u8 (uint8x8_t, uint8x8_t) 612<br><em>Form of expected instruction(s):</em> <code>vmull.u8 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 613</ul> 614 615 <ul> 616<li>int64x2_t vmull_s32 (int32x2_t, int32x2_t) 617<br><em>Form of expected instruction(s):</em> <code>vmull.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 618</ul> 619 620 <ul> 621<li>int32x4_t vmull_s16 (int16x4_t, int16x4_t) 622<br><em>Form of expected instruction(s):</em> <code>vmull.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 623</ul> 624 625 <ul> 626<li>int16x8_t vmull_s8 (int8x8_t, int8x8_t) 627<br><em>Form of expected instruction(s):</em> <code>vmull.s8 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 628</ul> 629 630 <ul> 631<li>poly16x8_t vmull_p8 (poly8x8_t, poly8x8_t) 632<br><em>Form of expected instruction(s):</em> <code>vmull.p8 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 633</ul> 634 635 <ul> 636<li>int64x2_t vqdmull_s32 (int32x2_t, int32x2_t) 637<br><em>Form of expected instruction(s):</em> <code>vqdmull.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 638</ul> 639 640 <ul> 641<li>int32x4_t vqdmull_s16 (int16x4_t, int16x4_t) 642<br><em>Form of expected instruction(s):</em> <code>vqdmull.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 643</ul> 644 645<h5 class="subsubsection">6.54.3.3 Multiply-accumulate</h5> 646 647 <ul> 648<li>uint32x2_t vmla_u32 (uint32x2_t, uint32x2_t, uint32x2_t) 649<br><em>Form of expected instruction(s):</em> <code>vmla.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 650</ul> 651 652 <ul> 653<li>uint16x4_t vmla_u16 (uint16x4_t, uint16x4_t, uint16x4_t) 654<br><em>Form of expected instruction(s):</em> <code>vmla.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 655</ul> 656 657 <ul> 658<li>uint8x8_t vmla_u8 (uint8x8_t, uint8x8_t, uint8x8_t) 659<br><em>Form of expected instruction(s):</em> <code>vmla.i8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 660</ul> 661 662 <ul> 663<li>int32x2_t vmla_s32 (int32x2_t, int32x2_t, int32x2_t) 664<br><em>Form of expected instruction(s):</em> <code>vmla.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 665</ul> 666 667 <ul> 668<li>int16x4_t vmla_s16 (int16x4_t, int16x4_t, int16x4_t) 669<br><em>Form of expected instruction(s):</em> <code>vmla.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 670</ul> 671 672 <ul> 673<li>int8x8_t vmla_s8 (int8x8_t, int8x8_t, int8x8_t) 674<br><em>Form of expected instruction(s):</em> <code>vmla.i8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 675</ul> 676 677 <ul> 678<li>float32x2_t vmla_f32 (float32x2_t, float32x2_t, float32x2_t) 679<br><em>Form of expected instruction(s):</em> <code>vmla.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 680</ul> 681 682 <ul> 683<li>uint32x4_t vmlaq_u32 (uint32x4_t, uint32x4_t, uint32x4_t) 684<br><em>Form of expected instruction(s):</em> <code>vmla.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 685</ul> 686 687 <ul> 688<li>uint16x8_t vmlaq_u16 (uint16x8_t, uint16x8_t, uint16x8_t) 689<br><em>Form of expected instruction(s):</em> <code>vmla.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 690</ul> 691 692 <ul> 693<li>uint8x16_t vmlaq_u8 (uint8x16_t, uint8x16_t, uint8x16_t) 694<br><em>Form of expected instruction(s):</em> <code>vmla.i8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 695</ul> 696 697 <ul> 698<li>int32x4_t vmlaq_s32 (int32x4_t, int32x4_t, int32x4_t) 699<br><em>Form of expected instruction(s):</em> <code>vmla.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 700</ul> 701 702 <ul> 703<li>int16x8_t vmlaq_s16 (int16x8_t, int16x8_t, int16x8_t) 704<br><em>Form of expected instruction(s):</em> <code>vmla.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 705</ul> 706 707 <ul> 708<li>int8x16_t vmlaq_s8 (int8x16_t, int8x16_t, int8x16_t) 709<br><em>Form of expected instruction(s):</em> <code>vmla.i8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 710</ul> 711 712 <ul> 713<li>float32x4_t vmlaq_f32 (float32x4_t, float32x4_t, float32x4_t) 714<br><em>Form of expected instruction(s):</em> <code>vmla.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 715</ul> 716 717 <ul> 718<li>uint64x2_t vmlal_u32 (uint64x2_t, uint32x2_t, uint32x2_t) 719<br><em>Form of expected instruction(s):</em> <code>vmlal.u32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 720</ul> 721 722 <ul> 723<li>uint32x4_t vmlal_u16 (uint32x4_t, uint16x4_t, uint16x4_t) 724<br><em>Form of expected instruction(s):</em> <code>vmlal.u16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 725</ul> 726 727 <ul> 728<li>uint16x8_t vmlal_u8 (uint16x8_t, uint8x8_t, uint8x8_t) 729<br><em>Form of expected instruction(s):</em> <code>vmlal.u8 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 730</ul> 731 732 <ul> 733<li>int64x2_t vmlal_s32 (int64x2_t, int32x2_t, int32x2_t) 734<br><em>Form of expected instruction(s):</em> <code>vmlal.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 735</ul> 736 737 <ul> 738<li>int32x4_t vmlal_s16 (int32x4_t, int16x4_t, int16x4_t) 739<br><em>Form of expected instruction(s):</em> <code>vmlal.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 740</ul> 741 742 <ul> 743<li>int16x8_t vmlal_s8 (int16x8_t, int8x8_t, int8x8_t) 744<br><em>Form of expected instruction(s):</em> <code>vmlal.s8 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 745</ul> 746 747 <ul> 748<li>int64x2_t vqdmlal_s32 (int64x2_t, int32x2_t, int32x2_t) 749<br><em>Form of expected instruction(s):</em> <code>vqdmlal.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 750</ul> 751 752 <ul> 753<li>int32x4_t vqdmlal_s16 (int32x4_t, int16x4_t, int16x4_t) 754<br><em>Form of expected instruction(s):</em> <code>vqdmlal.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 755</ul> 756 757<h5 class="subsubsection">6.54.3.4 Multiply-subtract</h5> 758 759 <ul> 760<li>uint32x2_t vmls_u32 (uint32x2_t, uint32x2_t, uint32x2_t) 761<br><em>Form of expected instruction(s):</em> <code>vmls.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 762</ul> 763 764 <ul> 765<li>uint16x4_t vmls_u16 (uint16x4_t, uint16x4_t, uint16x4_t) 766<br><em>Form of expected instruction(s):</em> <code>vmls.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 767</ul> 768 769 <ul> 770<li>uint8x8_t vmls_u8 (uint8x8_t, uint8x8_t, uint8x8_t) 771<br><em>Form of expected instruction(s):</em> <code>vmls.i8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 772</ul> 773 774 <ul> 775<li>int32x2_t vmls_s32 (int32x2_t, int32x2_t, int32x2_t) 776<br><em>Form of expected instruction(s):</em> <code>vmls.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 777</ul> 778 779 <ul> 780<li>int16x4_t vmls_s16 (int16x4_t, int16x4_t, int16x4_t) 781<br><em>Form of expected instruction(s):</em> <code>vmls.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 782</ul> 783 784 <ul> 785<li>int8x8_t vmls_s8 (int8x8_t, int8x8_t, int8x8_t) 786<br><em>Form of expected instruction(s):</em> <code>vmls.i8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 787</ul> 788 789 <ul> 790<li>float32x2_t vmls_f32 (float32x2_t, float32x2_t, float32x2_t) 791<br><em>Form of expected instruction(s):</em> <code>vmls.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 792</ul> 793 794 <ul> 795<li>uint32x4_t vmlsq_u32 (uint32x4_t, uint32x4_t, uint32x4_t) 796<br><em>Form of expected instruction(s):</em> <code>vmls.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 797</ul> 798 799 <ul> 800<li>uint16x8_t vmlsq_u16 (uint16x8_t, uint16x8_t, uint16x8_t) 801<br><em>Form of expected instruction(s):</em> <code>vmls.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 802</ul> 803 804 <ul> 805<li>uint8x16_t vmlsq_u8 (uint8x16_t, uint8x16_t, uint8x16_t) 806<br><em>Form of expected instruction(s):</em> <code>vmls.i8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 807</ul> 808 809 <ul> 810<li>int32x4_t vmlsq_s32 (int32x4_t, int32x4_t, int32x4_t) 811<br><em>Form of expected instruction(s):</em> <code>vmls.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 812</ul> 813 814 <ul> 815<li>int16x8_t vmlsq_s16 (int16x8_t, int16x8_t, int16x8_t) 816<br><em>Form of expected instruction(s):</em> <code>vmls.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 817</ul> 818 819 <ul> 820<li>int8x16_t vmlsq_s8 (int8x16_t, int8x16_t, int8x16_t) 821<br><em>Form of expected instruction(s):</em> <code>vmls.i8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 822</ul> 823 824 <ul> 825<li>float32x4_t vmlsq_f32 (float32x4_t, float32x4_t, float32x4_t) 826<br><em>Form of expected instruction(s):</em> <code>vmls.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 827</ul> 828 829 <ul> 830<li>uint64x2_t vmlsl_u32 (uint64x2_t, uint32x2_t, uint32x2_t) 831<br><em>Form of expected instruction(s):</em> <code>vmlsl.u32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 832</ul> 833 834 <ul> 835<li>uint32x4_t vmlsl_u16 (uint32x4_t, uint16x4_t, uint16x4_t) 836<br><em>Form of expected instruction(s):</em> <code>vmlsl.u16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 837</ul> 838 839 <ul> 840<li>uint16x8_t vmlsl_u8 (uint16x8_t, uint8x8_t, uint8x8_t) 841<br><em>Form of expected instruction(s):</em> <code>vmlsl.u8 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 842</ul> 843 844 <ul> 845<li>int64x2_t vmlsl_s32 (int64x2_t, int32x2_t, int32x2_t) 846<br><em>Form of expected instruction(s):</em> <code>vmlsl.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 847</ul> 848 849 <ul> 850<li>int32x4_t vmlsl_s16 (int32x4_t, int16x4_t, int16x4_t) 851<br><em>Form of expected instruction(s):</em> <code>vmlsl.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 852</ul> 853 854 <ul> 855<li>int16x8_t vmlsl_s8 (int16x8_t, int8x8_t, int8x8_t) 856<br><em>Form of expected instruction(s):</em> <code>vmlsl.s8 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 857</ul> 858 859 <ul> 860<li>int64x2_t vqdmlsl_s32 (int64x2_t, int32x2_t, int32x2_t) 861<br><em>Form of expected instruction(s):</em> <code>vqdmlsl.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 862</ul> 863 864 <ul> 865<li>int32x4_t vqdmlsl_s16 (int32x4_t, int16x4_t, int16x4_t) 866<br><em>Form of expected instruction(s):</em> <code>vqdmlsl.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 867</ul> 868 869<h5 class="subsubsection">6.54.3.5 Subtraction</h5> 870 871 <ul> 872<li>uint32x2_t vsub_u32 (uint32x2_t, uint32x2_t) 873<br><em>Form of expected instruction(s):</em> <code>vsub.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 874</ul> 875 876 <ul> 877<li>uint16x4_t vsub_u16 (uint16x4_t, uint16x4_t) 878<br><em>Form of expected instruction(s):</em> <code>vsub.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 879</ul> 880 881 <ul> 882<li>uint8x8_t vsub_u8 (uint8x8_t, uint8x8_t) 883<br><em>Form of expected instruction(s):</em> <code>vsub.i8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 884</ul> 885 886 <ul> 887<li>int32x2_t vsub_s32 (int32x2_t, int32x2_t) 888<br><em>Form of expected instruction(s):</em> <code>vsub.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 889</ul> 890 891 <ul> 892<li>int16x4_t vsub_s16 (int16x4_t, int16x4_t) 893<br><em>Form of expected instruction(s):</em> <code>vsub.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 894</ul> 895 896 <ul> 897<li>int8x8_t vsub_s8 (int8x8_t, int8x8_t) 898<br><em>Form of expected instruction(s):</em> <code>vsub.i8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 899</ul> 900 901 <ul> 902<li>float32x2_t vsub_f32 (float32x2_t, float32x2_t) 903<br><em>Form of expected instruction(s):</em> <code>vsub.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 904</ul> 905 906 <ul> 907<li>uint64x1_t vsub_u64 (uint64x1_t, uint64x1_t) 908</ul> 909 910 <ul> 911<li>int64x1_t vsub_s64 (int64x1_t, int64x1_t) 912</ul> 913 914 <ul> 915<li>uint32x4_t vsubq_u32 (uint32x4_t, uint32x4_t) 916<br><em>Form of expected instruction(s):</em> <code>vsub.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 917</ul> 918 919 <ul> 920<li>uint16x8_t vsubq_u16 (uint16x8_t, uint16x8_t) 921<br><em>Form of expected instruction(s):</em> <code>vsub.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 922</ul> 923 924 <ul> 925<li>uint8x16_t vsubq_u8 (uint8x16_t, uint8x16_t) 926<br><em>Form of expected instruction(s):</em> <code>vsub.i8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 927</ul> 928 929 <ul> 930<li>int32x4_t vsubq_s32 (int32x4_t, int32x4_t) 931<br><em>Form of expected instruction(s):</em> <code>vsub.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 932</ul> 933 934 <ul> 935<li>int16x8_t vsubq_s16 (int16x8_t, int16x8_t) 936<br><em>Form of expected instruction(s):</em> <code>vsub.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 937</ul> 938 939 <ul> 940<li>int8x16_t vsubq_s8 (int8x16_t, int8x16_t) 941<br><em>Form of expected instruction(s):</em> <code>vsub.i8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 942</ul> 943 944 <ul> 945<li>uint64x2_t vsubq_u64 (uint64x2_t, uint64x2_t) 946<br><em>Form of expected instruction(s):</em> <code>vsub.i64 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 947</ul> 948 949 <ul> 950<li>int64x2_t vsubq_s64 (int64x2_t, int64x2_t) 951<br><em>Form of expected instruction(s):</em> <code>vsub.i64 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 952</ul> 953 954 <ul> 955<li>float32x4_t vsubq_f32 (float32x4_t, float32x4_t) 956<br><em>Form of expected instruction(s):</em> <code>vsub.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 957</ul> 958 959 <ul> 960<li>uint64x2_t vsubl_u32 (uint32x2_t, uint32x2_t) 961<br><em>Form of expected instruction(s):</em> <code>vsubl.u32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 962</ul> 963 964 <ul> 965<li>uint32x4_t vsubl_u16 (uint16x4_t, uint16x4_t) 966<br><em>Form of expected instruction(s):</em> <code>vsubl.u16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 967</ul> 968 969 <ul> 970<li>uint16x8_t vsubl_u8 (uint8x8_t, uint8x8_t) 971<br><em>Form of expected instruction(s):</em> <code>vsubl.u8 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 972</ul> 973 974 <ul> 975<li>int64x2_t vsubl_s32 (int32x2_t, int32x2_t) 976<br><em>Form of expected instruction(s):</em> <code>vsubl.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 977</ul> 978 979 <ul> 980<li>int32x4_t vsubl_s16 (int16x4_t, int16x4_t) 981<br><em>Form of expected instruction(s):</em> <code>vsubl.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 982</ul> 983 984 <ul> 985<li>int16x8_t vsubl_s8 (int8x8_t, int8x8_t) 986<br><em>Form of expected instruction(s):</em> <code>vsubl.s8 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 987</ul> 988 989 <ul> 990<li>uint64x2_t vsubw_u32 (uint64x2_t, uint32x2_t) 991<br><em>Form of expected instruction(s):</em> <code>vsubw.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var> 992</ul> 993 994 <ul> 995<li>uint32x4_t vsubw_u16 (uint32x4_t, uint16x4_t) 996<br><em>Form of expected instruction(s):</em> <code>vsubw.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var> 997</ul> 998 999 <ul> 1000<li>uint16x8_t vsubw_u8 (uint16x8_t, uint8x8_t) 1001<br><em>Form of expected instruction(s):</em> <code>vsubw.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var> 1002</ul> 1003 1004 <ul> 1005<li>int64x2_t vsubw_s32 (int64x2_t, int32x2_t) 1006<br><em>Form of expected instruction(s):</em> <code>vsubw.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var> 1007</ul> 1008 1009 <ul> 1010<li>int32x4_t vsubw_s16 (int32x4_t, int16x4_t) 1011<br><em>Form of expected instruction(s):</em> <code>vsubw.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var> 1012</ul> 1013 1014 <ul> 1015<li>int16x8_t vsubw_s8 (int16x8_t, int8x8_t) 1016<br><em>Form of expected instruction(s):</em> <code>vsubw.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var> 1017</ul> 1018 1019 <ul> 1020<li>uint32x2_t vhsub_u32 (uint32x2_t, uint32x2_t) 1021<br><em>Form of expected instruction(s):</em> <code>vhsub.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1022</ul> 1023 1024 <ul> 1025<li>uint16x4_t vhsub_u16 (uint16x4_t, uint16x4_t) 1026<br><em>Form of expected instruction(s):</em> <code>vhsub.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1027</ul> 1028 1029 <ul> 1030<li>uint8x8_t vhsub_u8 (uint8x8_t, uint8x8_t) 1031<br><em>Form of expected instruction(s):</em> <code>vhsub.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1032</ul> 1033 1034 <ul> 1035<li>int32x2_t vhsub_s32 (int32x2_t, int32x2_t) 1036<br><em>Form of expected instruction(s):</em> <code>vhsub.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1037</ul> 1038 1039 <ul> 1040<li>int16x4_t vhsub_s16 (int16x4_t, int16x4_t) 1041<br><em>Form of expected instruction(s):</em> <code>vhsub.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1042</ul> 1043 1044 <ul> 1045<li>int8x8_t vhsub_s8 (int8x8_t, int8x8_t) 1046<br><em>Form of expected instruction(s):</em> <code>vhsub.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1047</ul> 1048 1049 <ul> 1050<li>uint32x4_t vhsubq_u32 (uint32x4_t, uint32x4_t) 1051<br><em>Form of expected instruction(s):</em> <code>vhsub.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1052</ul> 1053 1054 <ul> 1055<li>uint16x8_t vhsubq_u16 (uint16x8_t, uint16x8_t) 1056<br><em>Form of expected instruction(s):</em> <code>vhsub.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1057</ul> 1058 1059 <ul> 1060<li>uint8x16_t vhsubq_u8 (uint8x16_t, uint8x16_t) 1061<br><em>Form of expected instruction(s):</em> <code>vhsub.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1062</ul> 1063 1064 <ul> 1065<li>int32x4_t vhsubq_s32 (int32x4_t, int32x4_t) 1066<br><em>Form of expected instruction(s):</em> <code>vhsub.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1067</ul> 1068 1069 <ul> 1070<li>int16x8_t vhsubq_s16 (int16x8_t, int16x8_t) 1071<br><em>Form of expected instruction(s):</em> <code>vhsub.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1072</ul> 1073 1074 <ul> 1075<li>int8x16_t vhsubq_s8 (int8x16_t, int8x16_t) 1076<br><em>Form of expected instruction(s):</em> <code>vhsub.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1077</ul> 1078 1079 <ul> 1080<li>uint32x2_t vqsub_u32 (uint32x2_t, uint32x2_t) 1081<br><em>Form of expected instruction(s):</em> <code>vqsub.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1082</ul> 1083 1084 <ul> 1085<li>uint16x4_t vqsub_u16 (uint16x4_t, uint16x4_t) 1086<br><em>Form of expected instruction(s):</em> <code>vqsub.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1087</ul> 1088 1089 <ul> 1090<li>uint8x8_t vqsub_u8 (uint8x8_t, uint8x8_t) 1091<br><em>Form of expected instruction(s):</em> <code>vqsub.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1092</ul> 1093 1094 <ul> 1095<li>int32x2_t vqsub_s32 (int32x2_t, int32x2_t) 1096<br><em>Form of expected instruction(s):</em> <code>vqsub.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1097</ul> 1098 1099 <ul> 1100<li>int16x4_t vqsub_s16 (int16x4_t, int16x4_t) 1101<br><em>Form of expected instruction(s):</em> <code>vqsub.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1102</ul> 1103 1104 <ul> 1105<li>int8x8_t vqsub_s8 (int8x8_t, int8x8_t) 1106<br><em>Form of expected instruction(s):</em> <code>vqsub.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1107</ul> 1108 1109 <ul> 1110<li>uint64x1_t vqsub_u64 (uint64x1_t, uint64x1_t) 1111<br><em>Form of expected instruction(s):</em> <code>vqsub.u64 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1112</ul> 1113 1114 <ul> 1115<li>int64x1_t vqsub_s64 (int64x1_t, int64x1_t) 1116<br><em>Form of expected instruction(s):</em> <code>vqsub.s64 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1117</ul> 1118 1119 <ul> 1120<li>uint32x4_t vqsubq_u32 (uint32x4_t, uint32x4_t) 1121<br><em>Form of expected instruction(s):</em> <code>vqsub.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1122</ul> 1123 1124 <ul> 1125<li>uint16x8_t vqsubq_u16 (uint16x8_t, uint16x8_t) 1126<br><em>Form of expected instruction(s):</em> <code>vqsub.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1127</ul> 1128 1129 <ul> 1130<li>uint8x16_t vqsubq_u8 (uint8x16_t, uint8x16_t) 1131<br><em>Form of expected instruction(s):</em> <code>vqsub.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1132</ul> 1133 1134 <ul> 1135<li>int32x4_t vqsubq_s32 (int32x4_t, int32x4_t) 1136<br><em>Form of expected instruction(s):</em> <code>vqsub.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1137</ul> 1138 1139 <ul> 1140<li>int16x8_t vqsubq_s16 (int16x8_t, int16x8_t) 1141<br><em>Form of expected instruction(s):</em> <code>vqsub.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1142</ul> 1143 1144 <ul> 1145<li>int8x16_t vqsubq_s8 (int8x16_t, int8x16_t) 1146<br><em>Form of expected instruction(s):</em> <code>vqsub.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1147</ul> 1148 1149 <ul> 1150<li>uint64x2_t vqsubq_u64 (uint64x2_t, uint64x2_t) 1151<br><em>Form of expected instruction(s):</em> <code>vqsub.u64 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1152</ul> 1153 1154 <ul> 1155<li>int64x2_t vqsubq_s64 (int64x2_t, int64x2_t) 1156<br><em>Form of expected instruction(s):</em> <code>vqsub.s64 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1157</ul> 1158 1159 <ul> 1160<li>uint32x2_t vsubhn_u64 (uint64x2_t, uint64x2_t) 1161<br><em>Form of expected instruction(s):</em> <code>vsubhn.i64 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1162</ul> 1163 1164 <ul> 1165<li>uint16x4_t vsubhn_u32 (uint32x4_t, uint32x4_t) 1166<br><em>Form of expected instruction(s):</em> <code>vsubhn.i32 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1167</ul> 1168 1169 <ul> 1170<li>uint8x8_t vsubhn_u16 (uint16x8_t, uint16x8_t) 1171<br><em>Form of expected instruction(s):</em> <code>vsubhn.i16 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1172</ul> 1173 1174 <ul> 1175<li>int32x2_t vsubhn_s64 (int64x2_t, int64x2_t) 1176<br><em>Form of expected instruction(s):</em> <code>vsubhn.i64 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1177</ul> 1178 1179 <ul> 1180<li>int16x4_t vsubhn_s32 (int32x4_t, int32x4_t) 1181<br><em>Form of expected instruction(s):</em> <code>vsubhn.i32 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1182</ul> 1183 1184 <ul> 1185<li>int8x8_t vsubhn_s16 (int16x8_t, int16x8_t) 1186<br><em>Form of expected instruction(s):</em> <code>vsubhn.i16 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1187</ul> 1188 1189 <ul> 1190<li>uint32x2_t vrsubhn_u64 (uint64x2_t, uint64x2_t) 1191<br><em>Form of expected instruction(s):</em> <code>vrsubhn.i64 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1192</ul> 1193 1194 <ul> 1195<li>uint16x4_t vrsubhn_u32 (uint32x4_t, uint32x4_t) 1196<br><em>Form of expected instruction(s):</em> <code>vrsubhn.i32 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1197</ul> 1198 1199 <ul> 1200<li>uint8x8_t vrsubhn_u16 (uint16x8_t, uint16x8_t) 1201<br><em>Form of expected instruction(s):</em> <code>vrsubhn.i16 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1202</ul> 1203 1204 <ul> 1205<li>int32x2_t vrsubhn_s64 (int64x2_t, int64x2_t) 1206<br><em>Form of expected instruction(s):</em> <code>vrsubhn.i64 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1207</ul> 1208 1209 <ul> 1210<li>int16x4_t vrsubhn_s32 (int32x4_t, int32x4_t) 1211<br><em>Form of expected instruction(s):</em> <code>vrsubhn.i32 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1212</ul> 1213 1214 <ul> 1215<li>int8x8_t vrsubhn_s16 (int16x8_t, int16x8_t) 1216<br><em>Form of expected instruction(s):</em> <code>vrsubhn.i16 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1217</ul> 1218 1219<h5 class="subsubsection">6.54.3.6 Comparison (equal-to)</h5> 1220 1221 <ul> 1222<li>uint32x2_t vceq_u32 (uint32x2_t, uint32x2_t) 1223<br><em>Form of expected instruction(s):</em> <code>vceq.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1224</ul> 1225 1226 <ul> 1227<li>uint16x4_t vceq_u16 (uint16x4_t, uint16x4_t) 1228<br><em>Form of expected instruction(s):</em> <code>vceq.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1229</ul> 1230 1231 <ul> 1232<li>uint8x8_t vceq_u8 (uint8x8_t, uint8x8_t) 1233<br><em>Form of expected instruction(s):</em> <code>vceq.i8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1234</ul> 1235 1236 <ul> 1237<li>uint32x2_t vceq_s32 (int32x2_t, int32x2_t) 1238<br><em>Form of expected instruction(s):</em> <code>vceq.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1239</ul> 1240 1241 <ul> 1242<li>uint16x4_t vceq_s16 (int16x4_t, int16x4_t) 1243<br><em>Form of expected instruction(s):</em> <code>vceq.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1244</ul> 1245 1246 <ul> 1247<li>uint8x8_t vceq_s8 (int8x8_t, int8x8_t) 1248<br><em>Form of expected instruction(s):</em> <code>vceq.i8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1249</ul> 1250 1251 <ul> 1252<li>uint32x2_t vceq_f32 (float32x2_t, float32x2_t) 1253<br><em>Form of expected instruction(s):</em> <code>vceq.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1254</ul> 1255 1256 <ul> 1257<li>uint8x8_t vceq_p8 (poly8x8_t, poly8x8_t) 1258<br><em>Form of expected instruction(s):</em> <code>vceq.i8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1259</ul> 1260 1261 <ul> 1262<li>uint32x4_t vceqq_u32 (uint32x4_t, uint32x4_t) 1263<br><em>Form of expected instruction(s):</em> <code>vceq.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1264</ul> 1265 1266 <ul> 1267<li>uint16x8_t vceqq_u16 (uint16x8_t, uint16x8_t) 1268<br><em>Form of expected instruction(s):</em> <code>vceq.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1269</ul> 1270 1271 <ul> 1272<li>uint8x16_t vceqq_u8 (uint8x16_t, uint8x16_t) 1273<br><em>Form of expected instruction(s):</em> <code>vceq.i8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1274</ul> 1275 1276 <ul> 1277<li>uint32x4_t vceqq_s32 (int32x4_t, int32x4_t) 1278<br><em>Form of expected instruction(s):</em> <code>vceq.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1279</ul> 1280 1281 <ul> 1282<li>uint16x8_t vceqq_s16 (int16x8_t, int16x8_t) 1283<br><em>Form of expected instruction(s):</em> <code>vceq.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1284</ul> 1285 1286 <ul> 1287<li>uint8x16_t vceqq_s8 (int8x16_t, int8x16_t) 1288<br><em>Form of expected instruction(s):</em> <code>vceq.i8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1289</ul> 1290 1291 <ul> 1292<li>uint32x4_t vceqq_f32 (float32x4_t, float32x4_t) 1293<br><em>Form of expected instruction(s):</em> <code>vceq.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1294</ul> 1295 1296 <ul> 1297<li>uint8x16_t vceqq_p8 (poly8x16_t, poly8x16_t) 1298<br><em>Form of expected instruction(s):</em> <code>vceq.i8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1299</ul> 1300 1301<h5 class="subsubsection">6.54.3.7 Comparison (greater-than-or-equal-to)</h5> 1302 1303 <ul> 1304<li>uint32x2_t vcge_u32 (uint32x2_t, uint32x2_t) 1305<br><em>Form of expected instruction(s):</em> <code>vcge.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1306</ul> 1307 1308 <ul> 1309<li>uint16x4_t vcge_u16 (uint16x4_t, uint16x4_t) 1310<br><em>Form of expected instruction(s):</em> <code>vcge.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1311</ul> 1312 1313 <ul> 1314<li>uint8x8_t vcge_u8 (uint8x8_t, uint8x8_t) 1315<br><em>Form of expected instruction(s):</em> <code>vcge.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1316</ul> 1317 1318 <ul> 1319<li>uint32x2_t vcge_s32 (int32x2_t, int32x2_t) 1320<br><em>Form of expected instruction(s):</em> <code>vcge.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1321</ul> 1322 1323 <ul> 1324<li>uint16x4_t vcge_s16 (int16x4_t, int16x4_t) 1325<br><em>Form of expected instruction(s):</em> <code>vcge.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1326</ul> 1327 1328 <ul> 1329<li>uint8x8_t vcge_s8 (int8x8_t, int8x8_t) 1330<br><em>Form of expected instruction(s):</em> <code>vcge.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1331</ul> 1332 1333 <ul> 1334<li>uint32x2_t vcge_f32 (float32x2_t, float32x2_t) 1335<br><em>Form of expected instruction(s):</em> <code>vcge.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1336</ul> 1337 1338 <ul> 1339<li>uint32x4_t vcgeq_u32 (uint32x4_t, uint32x4_t) 1340<br><em>Form of expected instruction(s):</em> <code>vcge.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1341</ul> 1342 1343 <ul> 1344<li>uint16x8_t vcgeq_u16 (uint16x8_t, uint16x8_t) 1345<br><em>Form of expected instruction(s):</em> <code>vcge.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1346</ul> 1347 1348 <ul> 1349<li>uint8x16_t vcgeq_u8 (uint8x16_t, uint8x16_t) 1350<br><em>Form of expected instruction(s):</em> <code>vcge.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1351</ul> 1352 1353 <ul> 1354<li>uint32x4_t vcgeq_s32 (int32x4_t, int32x4_t) 1355<br><em>Form of expected instruction(s):</em> <code>vcge.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1356</ul> 1357 1358 <ul> 1359<li>uint16x8_t vcgeq_s16 (int16x8_t, int16x8_t) 1360<br><em>Form of expected instruction(s):</em> <code>vcge.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1361</ul> 1362 1363 <ul> 1364<li>uint8x16_t vcgeq_s8 (int8x16_t, int8x16_t) 1365<br><em>Form of expected instruction(s):</em> <code>vcge.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1366</ul> 1367 1368 <ul> 1369<li>uint32x4_t vcgeq_f32 (float32x4_t, float32x4_t) 1370<br><em>Form of expected instruction(s):</em> <code>vcge.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1371</ul> 1372 1373<h5 class="subsubsection">6.54.3.8 Comparison (less-than-or-equal-to)</h5> 1374 1375 <ul> 1376<li>uint32x2_t vcle_u32 (uint32x2_t, uint32x2_t) 1377<br><em>Form of expected instruction(s):</em> <code>vcge.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1378</ul> 1379 1380 <ul> 1381<li>uint16x4_t vcle_u16 (uint16x4_t, uint16x4_t) 1382<br><em>Form of expected instruction(s):</em> <code>vcge.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1383</ul> 1384 1385 <ul> 1386<li>uint8x8_t vcle_u8 (uint8x8_t, uint8x8_t) 1387<br><em>Form of expected instruction(s):</em> <code>vcge.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1388</ul> 1389 1390 <ul> 1391<li>uint32x2_t vcle_s32 (int32x2_t, int32x2_t) 1392<br><em>Form of expected instruction(s):</em> <code>vcge.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1393</ul> 1394 1395 <ul> 1396<li>uint16x4_t vcle_s16 (int16x4_t, int16x4_t) 1397<br><em>Form of expected instruction(s):</em> <code>vcge.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1398</ul> 1399 1400 <ul> 1401<li>uint8x8_t vcle_s8 (int8x8_t, int8x8_t) 1402<br><em>Form of expected instruction(s):</em> <code>vcge.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1403</ul> 1404 1405 <ul> 1406<li>uint32x2_t vcle_f32 (float32x2_t, float32x2_t) 1407<br><em>Form of expected instruction(s):</em> <code>vcge.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1408</ul> 1409 1410 <ul> 1411<li>uint32x4_t vcleq_u32 (uint32x4_t, uint32x4_t) 1412<br><em>Form of expected instruction(s):</em> <code>vcge.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1413</ul> 1414 1415 <ul> 1416<li>uint16x8_t vcleq_u16 (uint16x8_t, uint16x8_t) 1417<br><em>Form of expected instruction(s):</em> <code>vcge.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1418</ul> 1419 1420 <ul> 1421<li>uint8x16_t vcleq_u8 (uint8x16_t, uint8x16_t) 1422<br><em>Form of expected instruction(s):</em> <code>vcge.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1423</ul> 1424 1425 <ul> 1426<li>uint32x4_t vcleq_s32 (int32x4_t, int32x4_t) 1427<br><em>Form of expected instruction(s):</em> <code>vcge.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1428</ul> 1429 1430 <ul> 1431<li>uint16x8_t vcleq_s16 (int16x8_t, int16x8_t) 1432<br><em>Form of expected instruction(s):</em> <code>vcge.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1433</ul> 1434 1435 <ul> 1436<li>uint8x16_t vcleq_s8 (int8x16_t, int8x16_t) 1437<br><em>Form of expected instruction(s):</em> <code>vcge.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1438</ul> 1439 1440 <ul> 1441<li>uint32x4_t vcleq_f32 (float32x4_t, float32x4_t) 1442<br><em>Form of expected instruction(s):</em> <code>vcge.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1443</ul> 1444 1445<h5 class="subsubsection">6.54.3.9 Comparison (greater-than)</h5> 1446 1447 <ul> 1448<li>uint32x2_t vcgt_u32 (uint32x2_t, uint32x2_t) 1449<br><em>Form of expected instruction(s):</em> <code>vcgt.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1450</ul> 1451 1452 <ul> 1453<li>uint16x4_t vcgt_u16 (uint16x4_t, uint16x4_t) 1454<br><em>Form of expected instruction(s):</em> <code>vcgt.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1455</ul> 1456 1457 <ul> 1458<li>uint8x8_t vcgt_u8 (uint8x8_t, uint8x8_t) 1459<br><em>Form of expected instruction(s):</em> <code>vcgt.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1460</ul> 1461 1462 <ul> 1463<li>uint32x2_t vcgt_s32 (int32x2_t, int32x2_t) 1464<br><em>Form of expected instruction(s):</em> <code>vcgt.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1465</ul> 1466 1467 <ul> 1468<li>uint16x4_t vcgt_s16 (int16x4_t, int16x4_t) 1469<br><em>Form of expected instruction(s):</em> <code>vcgt.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1470</ul> 1471 1472 <ul> 1473<li>uint8x8_t vcgt_s8 (int8x8_t, int8x8_t) 1474<br><em>Form of expected instruction(s):</em> <code>vcgt.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1475</ul> 1476 1477 <ul> 1478<li>uint32x2_t vcgt_f32 (float32x2_t, float32x2_t) 1479<br><em>Form of expected instruction(s):</em> <code>vcgt.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1480</ul> 1481 1482 <ul> 1483<li>uint32x4_t vcgtq_u32 (uint32x4_t, uint32x4_t) 1484<br><em>Form of expected instruction(s):</em> <code>vcgt.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1485</ul> 1486 1487 <ul> 1488<li>uint16x8_t vcgtq_u16 (uint16x8_t, uint16x8_t) 1489<br><em>Form of expected instruction(s):</em> <code>vcgt.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1490</ul> 1491 1492 <ul> 1493<li>uint8x16_t vcgtq_u8 (uint8x16_t, uint8x16_t) 1494<br><em>Form of expected instruction(s):</em> <code>vcgt.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1495</ul> 1496 1497 <ul> 1498<li>uint32x4_t vcgtq_s32 (int32x4_t, int32x4_t) 1499<br><em>Form of expected instruction(s):</em> <code>vcgt.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1500</ul> 1501 1502 <ul> 1503<li>uint16x8_t vcgtq_s16 (int16x8_t, int16x8_t) 1504<br><em>Form of expected instruction(s):</em> <code>vcgt.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1505</ul> 1506 1507 <ul> 1508<li>uint8x16_t vcgtq_s8 (int8x16_t, int8x16_t) 1509<br><em>Form of expected instruction(s):</em> <code>vcgt.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1510</ul> 1511 1512 <ul> 1513<li>uint32x4_t vcgtq_f32 (float32x4_t, float32x4_t) 1514<br><em>Form of expected instruction(s):</em> <code>vcgt.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1515</ul> 1516 1517<h5 class="subsubsection">6.54.3.10 Comparison (less-than)</h5> 1518 1519 <ul> 1520<li>uint32x2_t vclt_u32 (uint32x2_t, uint32x2_t) 1521<br><em>Form of expected instruction(s):</em> <code>vcgt.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1522</ul> 1523 1524 <ul> 1525<li>uint16x4_t vclt_u16 (uint16x4_t, uint16x4_t) 1526<br><em>Form of expected instruction(s):</em> <code>vcgt.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1527</ul> 1528 1529 <ul> 1530<li>uint8x8_t vclt_u8 (uint8x8_t, uint8x8_t) 1531<br><em>Form of expected instruction(s):</em> <code>vcgt.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1532</ul> 1533 1534 <ul> 1535<li>uint32x2_t vclt_s32 (int32x2_t, int32x2_t) 1536<br><em>Form of expected instruction(s):</em> <code>vcgt.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1537</ul> 1538 1539 <ul> 1540<li>uint16x4_t vclt_s16 (int16x4_t, int16x4_t) 1541<br><em>Form of expected instruction(s):</em> <code>vcgt.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1542</ul> 1543 1544 <ul> 1545<li>uint8x8_t vclt_s8 (int8x8_t, int8x8_t) 1546<br><em>Form of expected instruction(s):</em> <code>vcgt.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1547</ul> 1548 1549 <ul> 1550<li>uint32x2_t vclt_f32 (float32x2_t, float32x2_t) 1551<br><em>Form of expected instruction(s):</em> <code>vcgt.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1552</ul> 1553 1554 <ul> 1555<li>uint32x4_t vcltq_u32 (uint32x4_t, uint32x4_t) 1556<br><em>Form of expected instruction(s):</em> <code>vcgt.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1557</ul> 1558 1559 <ul> 1560<li>uint16x8_t vcltq_u16 (uint16x8_t, uint16x8_t) 1561<br><em>Form of expected instruction(s):</em> <code>vcgt.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1562</ul> 1563 1564 <ul> 1565<li>uint8x16_t vcltq_u8 (uint8x16_t, uint8x16_t) 1566<br><em>Form of expected instruction(s):</em> <code>vcgt.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1567</ul> 1568 1569 <ul> 1570<li>uint32x4_t vcltq_s32 (int32x4_t, int32x4_t) 1571<br><em>Form of expected instruction(s):</em> <code>vcgt.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1572</ul> 1573 1574 <ul> 1575<li>uint16x8_t vcltq_s16 (int16x8_t, int16x8_t) 1576<br><em>Form of expected instruction(s):</em> <code>vcgt.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1577</ul> 1578 1579 <ul> 1580<li>uint8x16_t vcltq_s8 (int8x16_t, int8x16_t) 1581<br><em>Form of expected instruction(s):</em> <code>vcgt.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1582</ul> 1583 1584 <ul> 1585<li>uint32x4_t vcltq_f32 (float32x4_t, float32x4_t) 1586<br><em>Form of expected instruction(s):</em> <code>vcgt.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1587</ul> 1588 1589<h5 class="subsubsection">6.54.3.11 Comparison (absolute greater-than-or-equal-to)</h5> 1590 1591 <ul> 1592<li>uint32x2_t vcage_f32 (float32x2_t, float32x2_t) 1593<br><em>Form of expected instruction(s):</em> <code>vacge.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1594</ul> 1595 1596 <ul> 1597<li>uint32x4_t vcageq_f32 (float32x4_t, float32x4_t) 1598<br><em>Form of expected instruction(s):</em> <code>vacge.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1599</ul> 1600 1601<h5 class="subsubsection">6.54.3.12 Comparison (absolute less-than-or-equal-to)</h5> 1602 1603 <ul> 1604<li>uint32x2_t vcale_f32 (float32x2_t, float32x2_t) 1605<br><em>Form of expected instruction(s):</em> <code>vacge.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1606</ul> 1607 1608 <ul> 1609<li>uint32x4_t vcaleq_f32 (float32x4_t, float32x4_t) 1610<br><em>Form of expected instruction(s):</em> <code>vacge.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1611</ul> 1612 1613<h5 class="subsubsection">6.54.3.13 Comparison (absolute greater-than)</h5> 1614 1615 <ul> 1616<li>uint32x2_t vcagt_f32 (float32x2_t, float32x2_t) 1617<br><em>Form of expected instruction(s):</em> <code>vacgt.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1618</ul> 1619 1620 <ul> 1621<li>uint32x4_t vcagtq_f32 (float32x4_t, float32x4_t) 1622<br><em>Form of expected instruction(s):</em> <code>vacgt.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1623</ul> 1624 1625<h5 class="subsubsection">6.54.3.14 Comparison (absolute less-than)</h5> 1626 1627 <ul> 1628<li>uint32x2_t vcalt_f32 (float32x2_t, float32x2_t) 1629<br><em>Form of expected instruction(s):</em> <code>vacgt.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1630</ul> 1631 1632 <ul> 1633<li>uint32x4_t vcaltq_f32 (float32x4_t, float32x4_t) 1634<br><em>Form of expected instruction(s):</em> <code>vacgt.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1635</ul> 1636 1637<h5 class="subsubsection">6.54.3.15 Test bits</h5> 1638 1639 <ul> 1640<li>uint32x2_t vtst_u32 (uint32x2_t, uint32x2_t) 1641<br><em>Form of expected instruction(s):</em> <code>vtst.32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1642</ul> 1643 1644 <ul> 1645<li>uint16x4_t vtst_u16 (uint16x4_t, uint16x4_t) 1646<br><em>Form of expected instruction(s):</em> <code>vtst.16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1647</ul> 1648 1649 <ul> 1650<li>uint8x8_t vtst_u8 (uint8x8_t, uint8x8_t) 1651<br><em>Form of expected instruction(s):</em> <code>vtst.8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1652</ul> 1653 1654 <ul> 1655<li>uint32x2_t vtst_s32 (int32x2_t, int32x2_t) 1656<br><em>Form of expected instruction(s):</em> <code>vtst.32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1657</ul> 1658 1659 <ul> 1660<li>uint16x4_t vtst_s16 (int16x4_t, int16x4_t) 1661<br><em>Form of expected instruction(s):</em> <code>vtst.16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1662</ul> 1663 1664 <ul> 1665<li>uint8x8_t vtst_s8 (int8x8_t, int8x8_t) 1666<br><em>Form of expected instruction(s):</em> <code>vtst.8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1667</ul> 1668 1669 <ul> 1670<li>uint8x8_t vtst_p8 (poly8x8_t, poly8x8_t) 1671<br><em>Form of expected instruction(s):</em> <code>vtst.8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1672</ul> 1673 1674 <ul> 1675<li>uint32x4_t vtstq_u32 (uint32x4_t, uint32x4_t) 1676<br><em>Form of expected instruction(s):</em> <code>vtst.32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1677</ul> 1678 1679 <ul> 1680<li>uint16x8_t vtstq_u16 (uint16x8_t, uint16x8_t) 1681<br><em>Form of expected instruction(s):</em> <code>vtst.16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1682</ul> 1683 1684 <ul> 1685<li>uint8x16_t vtstq_u8 (uint8x16_t, uint8x16_t) 1686<br><em>Form of expected instruction(s):</em> <code>vtst.8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1687</ul> 1688 1689 <ul> 1690<li>uint32x4_t vtstq_s32 (int32x4_t, int32x4_t) 1691<br><em>Form of expected instruction(s):</em> <code>vtst.32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1692</ul> 1693 1694 <ul> 1695<li>uint16x8_t vtstq_s16 (int16x8_t, int16x8_t) 1696<br><em>Form of expected instruction(s):</em> <code>vtst.16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1697</ul> 1698 1699 <ul> 1700<li>uint8x16_t vtstq_s8 (int8x16_t, int8x16_t) 1701<br><em>Form of expected instruction(s):</em> <code>vtst.8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1702</ul> 1703 1704 <ul> 1705<li>uint8x16_t vtstq_p8 (poly8x16_t, poly8x16_t) 1706<br><em>Form of expected instruction(s):</em> <code>vtst.8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1707</ul> 1708 1709<h5 class="subsubsection">6.54.3.16 Absolute difference</h5> 1710 1711 <ul> 1712<li>uint32x2_t vabd_u32 (uint32x2_t, uint32x2_t) 1713<br><em>Form of expected instruction(s):</em> <code>vabd.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1714</ul> 1715 1716 <ul> 1717<li>uint16x4_t vabd_u16 (uint16x4_t, uint16x4_t) 1718<br><em>Form of expected instruction(s):</em> <code>vabd.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1719</ul> 1720 1721 <ul> 1722<li>uint8x8_t vabd_u8 (uint8x8_t, uint8x8_t) 1723<br><em>Form of expected instruction(s):</em> <code>vabd.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1724</ul> 1725 1726 <ul> 1727<li>int32x2_t vabd_s32 (int32x2_t, int32x2_t) 1728<br><em>Form of expected instruction(s):</em> <code>vabd.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1729</ul> 1730 1731 <ul> 1732<li>int16x4_t vabd_s16 (int16x4_t, int16x4_t) 1733<br><em>Form of expected instruction(s):</em> <code>vabd.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1734</ul> 1735 1736 <ul> 1737<li>int8x8_t vabd_s8 (int8x8_t, int8x8_t) 1738<br><em>Form of expected instruction(s):</em> <code>vabd.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1739</ul> 1740 1741 <ul> 1742<li>float32x2_t vabd_f32 (float32x2_t, float32x2_t) 1743<br><em>Form of expected instruction(s):</em> <code>vabd.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1744</ul> 1745 1746 <ul> 1747<li>uint32x4_t vabdq_u32 (uint32x4_t, uint32x4_t) 1748<br><em>Form of expected instruction(s):</em> <code>vabd.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1749</ul> 1750 1751 <ul> 1752<li>uint16x8_t vabdq_u16 (uint16x8_t, uint16x8_t) 1753<br><em>Form of expected instruction(s):</em> <code>vabd.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1754</ul> 1755 1756 <ul> 1757<li>uint8x16_t vabdq_u8 (uint8x16_t, uint8x16_t) 1758<br><em>Form of expected instruction(s):</em> <code>vabd.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1759</ul> 1760 1761 <ul> 1762<li>int32x4_t vabdq_s32 (int32x4_t, int32x4_t) 1763<br><em>Form of expected instruction(s):</em> <code>vabd.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1764</ul> 1765 1766 <ul> 1767<li>int16x8_t vabdq_s16 (int16x8_t, int16x8_t) 1768<br><em>Form of expected instruction(s):</em> <code>vabd.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1769</ul> 1770 1771 <ul> 1772<li>int8x16_t vabdq_s8 (int8x16_t, int8x16_t) 1773<br><em>Form of expected instruction(s):</em> <code>vabd.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1774</ul> 1775 1776 <ul> 1777<li>float32x4_t vabdq_f32 (float32x4_t, float32x4_t) 1778<br><em>Form of expected instruction(s):</em> <code>vabd.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1779</ul> 1780 1781 <ul> 1782<li>uint64x2_t vabdl_u32 (uint32x2_t, uint32x2_t) 1783<br><em>Form of expected instruction(s):</em> <code>vabdl.u32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1784</ul> 1785 1786 <ul> 1787<li>uint32x4_t vabdl_u16 (uint16x4_t, uint16x4_t) 1788<br><em>Form of expected instruction(s):</em> <code>vabdl.u16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1789</ul> 1790 1791 <ul> 1792<li>uint16x8_t vabdl_u8 (uint8x8_t, uint8x8_t) 1793<br><em>Form of expected instruction(s):</em> <code>vabdl.u8 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1794</ul> 1795 1796 <ul> 1797<li>int64x2_t vabdl_s32 (int32x2_t, int32x2_t) 1798<br><em>Form of expected instruction(s):</em> <code>vabdl.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1799</ul> 1800 1801 <ul> 1802<li>int32x4_t vabdl_s16 (int16x4_t, int16x4_t) 1803<br><em>Form of expected instruction(s):</em> <code>vabdl.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1804</ul> 1805 1806 <ul> 1807<li>int16x8_t vabdl_s8 (int8x8_t, int8x8_t) 1808<br><em>Form of expected instruction(s):</em> <code>vabdl.s8 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1809</ul> 1810 1811<h5 class="subsubsection">6.54.3.17 Absolute difference and accumulate</h5> 1812 1813 <ul> 1814<li>uint32x2_t vaba_u32 (uint32x2_t, uint32x2_t, uint32x2_t) 1815<br><em>Form of expected instruction(s):</em> <code>vaba.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1816</ul> 1817 1818 <ul> 1819<li>uint16x4_t vaba_u16 (uint16x4_t, uint16x4_t, uint16x4_t) 1820<br><em>Form of expected instruction(s):</em> <code>vaba.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1821</ul> 1822 1823 <ul> 1824<li>uint8x8_t vaba_u8 (uint8x8_t, uint8x8_t, uint8x8_t) 1825<br><em>Form of expected instruction(s):</em> <code>vaba.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1826</ul> 1827 1828 <ul> 1829<li>int32x2_t vaba_s32 (int32x2_t, int32x2_t, int32x2_t) 1830<br><em>Form of expected instruction(s):</em> <code>vaba.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1831</ul> 1832 1833 <ul> 1834<li>int16x4_t vaba_s16 (int16x4_t, int16x4_t, int16x4_t) 1835<br><em>Form of expected instruction(s):</em> <code>vaba.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1836</ul> 1837 1838 <ul> 1839<li>int8x8_t vaba_s8 (int8x8_t, int8x8_t, int8x8_t) 1840<br><em>Form of expected instruction(s):</em> <code>vaba.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1841</ul> 1842 1843 <ul> 1844<li>uint32x4_t vabaq_u32 (uint32x4_t, uint32x4_t, uint32x4_t) 1845<br><em>Form of expected instruction(s):</em> <code>vaba.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1846</ul> 1847 1848 <ul> 1849<li>uint16x8_t vabaq_u16 (uint16x8_t, uint16x8_t, uint16x8_t) 1850<br><em>Form of expected instruction(s):</em> <code>vaba.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1851</ul> 1852 1853 <ul> 1854<li>uint8x16_t vabaq_u8 (uint8x16_t, uint8x16_t, uint8x16_t) 1855<br><em>Form of expected instruction(s):</em> <code>vaba.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1856</ul> 1857 1858 <ul> 1859<li>int32x4_t vabaq_s32 (int32x4_t, int32x4_t, int32x4_t) 1860<br><em>Form of expected instruction(s):</em> <code>vaba.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1861</ul> 1862 1863 <ul> 1864<li>int16x8_t vabaq_s16 (int16x8_t, int16x8_t, int16x8_t) 1865<br><em>Form of expected instruction(s):</em> <code>vaba.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1866</ul> 1867 1868 <ul> 1869<li>int8x16_t vabaq_s8 (int8x16_t, int8x16_t, int8x16_t) 1870<br><em>Form of expected instruction(s):</em> <code>vaba.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1871</ul> 1872 1873 <ul> 1874<li>uint64x2_t vabal_u32 (uint64x2_t, uint32x2_t, uint32x2_t) 1875<br><em>Form of expected instruction(s):</em> <code>vabal.u32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1876</ul> 1877 1878 <ul> 1879<li>uint32x4_t vabal_u16 (uint32x4_t, uint16x4_t, uint16x4_t) 1880<br><em>Form of expected instruction(s):</em> <code>vabal.u16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1881</ul> 1882 1883 <ul> 1884<li>uint16x8_t vabal_u8 (uint16x8_t, uint8x8_t, uint8x8_t) 1885<br><em>Form of expected instruction(s):</em> <code>vabal.u8 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1886</ul> 1887 1888 <ul> 1889<li>int64x2_t vabal_s32 (int64x2_t, int32x2_t, int32x2_t) 1890<br><em>Form of expected instruction(s):</em> <code>vabal.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1891</ul> 1892 1893 <ul> 1894<li>int32x4_t vabal_s16 (int32x4_t, int16x4_t, int16x4_t) 1895<br><em>Form of expected instruction(s):</em> <code>vabal.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1896</ul> 1897 1898 <ul> 1899<li>int16x8_t vabal_s8 (int16x8_t, int8x8_t, int8x8_t) 1900<br><em>Form of expected instruction(s):</em> <code>vabal.s8 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1901</ul> 1902 1903<h5 class="subsubsection">6.54.3.18 Maximum</h5> 1904 1905 <ul> 1906<li>uint32x2_t vmax_u32 (uint32x2_t, uint32x2_t) 1907<br><em>Form of expected instruction(s):</em> <code>vmax.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1908</ul> 1909 1910 <ul> 1911<li>uint16x4_t vmax_u16 (uint16x4_t, uint16x4_t) 1912<br><em>Form of expected instruction(s):</em> <code>vmax.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1913</ul> 1914 1915 <ul> 1916<li>uint8x8_t vmax_u8 (uint8x8_t, uint8x8_t) 1917<br><em>Form of expected instruction(s):</em> <code>vmax.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1918</ul> 1919 1920 <ul> 1921<li>int32x2_t vmax_s32 (int32x2_t, int32x2_t) 1922<br><em>Form of expected instruction(s):</em> <code>vmax.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1923</ul> 1924 1925 <ul> 1926<li>int16x4_t vmax_s16 (int16x4_t, int16x4_t) 1927<br><em>Form of expected instruction(s):</em> <code>vmax.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1928</ul> 1929 1930 <ul> 1931<li>int8x8_t vmax_s8 (int8x8_t, int8x8_t) 1932<br><em>Form of expected instruction(s):</em> <code>vmax.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1933</ul> 1934 1935 <ul> 1936<li>float32x2_t vmax_f32 (float32x2_t, float32x2_t) 1937<br><em>Form of expected instruction(s):</em> <code>vmax.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1938</ul> 1939 1940 <ul> 1941<li>uint32x4_t vmaxq_u32 (uint32x4_t, uint32x4_t) 1942<br><em>Form of expected instruction(s):</em> <code>vmax.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1943</ul> 1944 1945 <ul> 1946<li>uint16x8_t vmaxq_u16 (uint16x8_t, uint16x8_t) 1947<br><em>Form of expected instruction(s):</em> <code>vmax.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1948</ul> 1949 1950 <ul> 1951<li>uint8x16_t vmaxq_u8 (uint8x16_t, uint8x16_t) 1952<br><em>Form of expected instruction(s):</em> <code>vmax.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1953</ul> 1954 1955 <ul> 1956<li>int32x4_t vmaxq_s32 (int32x4_t, int32x4_t) 1957<br><em>Form of expected instruction(s):</em> <code>vmax.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1958</ul> 1959 1960 <ul> 1961<li>int16x8_t vmaxq_s16 (int16x8_t, int16x8_t) 1962<br><em>Form of expected instruction(s):</em> <code>vmax.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1963</ul> 1964 1965 <ul> 1966<li>int8x16_t vmaxq_s8 (int8x16_t, int8x16_t) 1967<br><em>Form of expected instruction(s):</em> <code>vmax.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1968</ul> 1969 1970 <ul> 1971<li>float32x4_t vmaxq_f32 (float32x4_t, float32x4_t) 1972<br><em>Form of expected instruction(s):</em> <code>vmax.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 1973</ul> 1974 1975<h5 class="subsubsection">6.54.3.19 Minimum</h5> 1976 1977 <ul> 1978<li>uint32x2_t vmin_u32 (uint32x2_t, uint32x2_t) 1979<br><em>Form of expected instruction(s):</em> <code>vmin.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1980</ul> 1981 1982 <ul> 1983<li>uint16x4_t vmin_u16 (uint16x4_t, uint16x4_t) 1984<br><em>Form of expected instruction(s):</em> <code>vmin.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1985</ul> 1986 1987 <ul> 1988<li>uint8x8_t vmin_u8 (uint8x8_t, uint8x8_t) 1989<br><em>Form of expected instruction(s):</em> <code>vmin.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1990</ul> 1991 1992 <ul> 1993<li>int32x2_t vmin_s32 (int32x2_t, int32x2_t) 1994<br><em>Form of expected instruction(s):</em> <code>vmin.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 1995</ul> 1996 1997 <ul> 1998<li>int16x4_t vmin_s16 (int16x4_t, int16x4_t) 1999<br><em>Form of expected instruction(s):</em> <code>vmin.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2000</ul> 2001 2002 <ul> 2003<li>int8x8_t vmin_s8 (int8x8_t, int8x8_t) 2004<br><em>Form of expected instruction(s):</em> <code>vmin.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2005</ul> 2006 2007 <ul> 2008<li>float32x2_t vmin_f32 (float32x2_t, float32x2_t) 2009<br><em>Form of expected instruction(s):</em> <code>vmin.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2010</ul> 2011 2012 <ul> 2013<li>uint32x4_t vminq_u32 (uint32x4_t, uint32x4_t) 2014<br><em>Form of expected instruction(s):</em> <code>vmin.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2015</ul> 2016 2017 <ul> 2018<li>uint16x8_t vminq_u16 (uint16x8_t, uint16x8_t) 2019<br><em>Form of expected instruction(s):</em> <code>vmin.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2020</ul> 2021 2022 <ul> 2023<li>uint8x16_t vminq_u8 (uint8x16_t, uint8x16_t) 2024<br><em>Form of expected instruction(s):</em> <code>vmin.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2025</ul> 2026 2027 <ul> 2028<li>int32x4_t vminq_s32 (int32x4_t, int32x4_t) 2029<br><em>Form of expected instruction(s):</em> <code>vmin.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2030</ul> 2031 2032 <ul> 2033<li>int16x8_t vminq_s16 (int16x8_t, int16x8_t) 2034<br><em>Form of expected instruction(s):</em> <code>vmin.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2035</ul> 2036 2037 <ul> 2038<li>int8x16_t vminq_s8 (int8x16_t, int8x16_t) 2039<br><em>Form of expected instruction(s):</em> <code>vmin.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2040</ul> 2041 2042 <ul> 2043<li>float32x4_t vminq_f32 (float32x4_t, float32x4_t) 2044<br><em>Form of expected instruction(s):</em> <code>vmin.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2045</ul> 2046 2047<h5 class="subsubsection">6.54.3.20 Pairwise add</h5> 2048 2049 <ul> 2050<li>uint32x2_t vpadd_u32 (uint32x2_t, uint32x2_t) 2051<br><em>Form of expected instruction(s):</em> <code>vpadd.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2052</ul> 2053 2054 <ul> 2055<li>uint16x4_t vpadd_u16 (uint16x4_t, uint16x4_t) 2056<br><em>Form of expected instruction(s):</em> <code>vpadd.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2057</ul> 2058 2059 <ul> 2060<li>uint8x8_t vpadd_u8 (uint8x8_t, uint8x8_t) 2061<br><em>Form of expected instruction(s):</em> <code>vpadd.i8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2062</ul> 2063 2064 <ul> 2065<li>int32x2_t vpadd_s32 (int32x2_t, int32x2_t) 2066<br><em>Form of expected instruction(s):</em> <code>vpadd.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2067</ul> 2068 2069 <ul> 2070<li>int16x4_t vpadd_s16 (int16x4_t, int16x4_t) 2071<br><em>Form of expected instruction(s):</em> <code>vpadd.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2072</ul> 2073 2074 <ul> 2075<li>int8x8_t vpadd_s8 (int8x8_t, int8x8_t) 2076<br><em>Form of expected instruction(s):</em> <code>vpadd.i8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2077</ul> 2078 2079 <ul> 2080<li>float32x2_t vpadd_f32 (float32x2_t, float32x2_t) 2081<br><em>Form of expected instruction(s):</em> <code>vpadd.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2082</ul> 2083 2084 <ul> 2085<li>uint64x1_t vpaddl_u32 (uint32x2_t) 2086<br><em>Form of expected instruction(s):</em> <code>vpaddl.u32 </code><var>d0</var><code>, </code><var>d0</var> 2087</ul> 2088 2089 <ul> 2090<li>uint32x2_t vpaddl_u16 (uint16x4_t) 2091<br><em>Form of expected instruction(s):</em> <code>vpaddl.u16 </code><var>d0</var><code>, </code><var>d0</var> 2092</ul> 2093 2094 <ul> 2095<li>uint16x4_t vpaddl_u8 (uint8x8_t) 2096<br><em>Form of expected instruction(s):</em> <code>vpaddl.u8 </code><var>d0</var><code>, </code><var>d0</var> 2097</ul> 2098 2099 <ul> 2100<li>int64x1_t vpaddl_s32 (int32x2_t) 2101<br><em>Form of expected instruction(s):</em> <code>vpaddl.s32 </code><var>d0</var><code>, </code><var>d0</var> 2102</ul> 2103 2104 <ul> 2105<li>int32x2_t vpaddl_s16 (int16x4_t) 2106<br><em>Form of expected instruction(s):</em> <code>vpaddl.s16 </code><var>d0</var><code>, </code><var>d0</var> 2107</ul> 2108 2109 <ul> 2110<li>int16x4_t vpaddl_s8 (int8x8_t) 2111<br><em>Form of expected instruction(s):</em> <code>vpaddl.s8 </code><var>d0</var><code>, </code><var>d0</var> 2112</ul> 2113 2114 <ul> 2115<li>uint64x2_t vpaddlq_u32 (uint32x4_t) 2116<br><em>Form of expected instruction(s):</em> <code>vpaddl.u32 </code><var>q0</var><code>, </code><var>q0</var> 2117</ul> 2118 2119 <ul> 2120<li>uint32x4_t vpaddlq_u16 (uint16x8_t) 2121<br><em>Form of expected instruction(s):</em> <code>vpaddl.u16 </code><var>q0</var><code>, </code><var>q0</var> 2122</ul> 2123 2124 <ul> 2125<li>uint16x8_t vpaddlq_u8 (uint8x16_t) 2126<br><em>Form of expected instruction(s):</em> <code>vpaddl.u8 </code><var>q0</var><code>, </code><var>q0</var> 2127</ul> 2128 2129 <ul> 2130<li>int64x2_t vpaddlq_s32 (int32x4_t) 2131<br><em>Form of expected instruction(s):</em> <code>vpaddl.s32 </code><var>q0</var><code>, </code><var>q0</var> 2132</ul> 2133 2134 <ul> 2135<li>int32x4_t vpaddlq_s16 (int16x8_t) 2136<br><em>Form of expected instruction(s):</em> <code>vpaddl.s16 </code><var>q0</var><code>, </code><var>q0</var> 2137</ul> 2138 2139 <ul> 2140<li>int16x8_t vpaddlq_s8 (int8x16_t) 2141<br><em>Form of expected instruction(s):</em> <code>vpaddl.s8 </code><var>q0</var><code>, </code><var>q0</var> 2142</ul> 2143 2144<h5 class="subsubsection">6.54.3.21 Pairwise add, single_opcode widen and accumulate</h5> 2145 2146 <ul> 2147<li>uint64x1_t vpadal_u32 (uint64x1_t, uint32x2_t) 2148<br><em>Form of expected instruction(s):</em> <code>vpadal.u32 </code><var>d0</var><code>, </code><var>d0</var> 2149</ul> 2150 2151 <ul> 2152<li>uint32x2_t vpadal_u16 (uint32x2_t, uint16x4_t) 2153<br><em>Form of expected instruction(s):</em> <code>vpadal.u16 </code><var>d0</var><code>, </code><var>d0</var> 2154</ul> 2155 2156 <ul> 2157<li>uint16x4_t vpadal_u8 (uint16x4_t, uint8x8_t) 2158<br><em>Form of expected instruction(s):</em> <code>vpadal.u8 </code><var>d0</var><code>, </code><var>d0</var> 2159</ul> 2160 2161 <ul> 2162<li>int64x1_t vpadal_s32 (int64x1_t, int32x2_t) 2163<br><em>Form of expected instruction(s):</em> <code>vpadal.s32 </code><var>d0</var><code>, </code><var>d0</var> 2164</ul> 2165 2166 <ul> 2167<li>int32x2_t vpadal_s16 (int32x2_t, int16x4_t) 2168<br><em>Form of expected instruction(s):</em> <code>vpadal.s16 </code><var>d0</var><code>, </code><var>d0</var> 2169</ul> 2170 2171 <ul> 2172<li>int16x4_t vpadal_s8 (int16x4_t, int8x8_t) 2173<br><em>Form of expected instruction(s):</em> <code>vpadal.s8 </code><var>d0</var><code>, </code><var>d0</var> 2174</ul> 2175 2176 <ul> 2177<li>uint64x2_t vpadalq_u32 (uint64x2_t, uint32x4_t) 2178<br><em>Form of expected instruction(s):</em> <code>vpadal.u32 </code><var>q0</var><code>, </code><var>q0</var> 2179</ul> 2180 2181 <ul> 2182<li>uint32x4_t vpadalq_u16 (uint32x4_t, uint16x8_t) 2183<br><em>Form of expected instruction(s):</em> <code>vpadal.u16 </code><var>q0</var><code>, </code><var>q0</var> 2184</ul> 2185 2186 <ul> 2187<li>uint16x8_t vpadalq_u8 (uint16x8_t, uint8x16_t) 2188<br><em>Form of expected instruction(s):</em> <code>vpadal.u8 </code><var>q0</var><code>, </code><var>q0</var> 2189</ul> 2190 2191 <ul> 2192<li>int64x2_t vpadalq_s32 (int64x2_t, int32x4_t) 2193<br><em>Form of expected instruction(s):</em> <code>vpadal.s32 </code><var>q0</var><code>, </code><var>q0</var> 2194</ul> 2195 2196 <ul> 2197<li>int32x4_t vpadalq_s16 (int32x4_t, int16x8_t) 2198<br><em>Form of expected instruction(s):</em> <code>vpadal.s16 </code><var>q0</var><code>, </code><var>q0</var> 2199</ul> 2200 2201 <ul> 2202<li>int16x8_t vpadalq_s8 (int16x8_t, int8x16_t) 2203<br><em>Form of expected instruction(s):</em> <code>vpadal.s8 </code><var>q0</var><code>, </code><var>q0</var> 2204</ul> 2205 2206<h5 class="subsubsection">6.54.3.22 Folding maximum</h5> 2207 2208 <ul> 2209<li>uint32x2_t vpmax_u32 (uint32x2_t, uint32x2_t) 2210<br><em>Form of expected instruction(s):</em> <code>vpmax.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2211</ul> 2212 2213 <ul> 2214<li>uint16x4_t vpmax_u16 (uint16x4_t, uint16x4_t) 2215<br><em>Form of expected instruction(s):</em> <code>vpmax.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2216</ul> 2217 2218 <ul> 2219<li>uint8x8_t vpmax_u8 (uint8x8_t, uint8x8_t) 2220<br><em>Form of expected instruction(s):</em> <code>vpmax.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2221</ul> 2222 2223 <ul> 2224<li>int32x2_t vpmax_s32 (int32x2_t, int32x2_t) 2225<br><em>Form of expected instruction(s):</em> <code>vpmax.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2226</ul> 2227 2228 <ul> 2229<li>int16x4_t vpmax_s16 (int16x4_t, int16x4_t) 2230<br><em>Form of expected instruction(s):</em> <code>vpmax.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2231</ul> 2232 2233 <ul> 2234<li>int8x8_t vpmax_s8 (int8x8_t, int8x8_t) 2235<br><em>Form of expected instruction(s):</em> <code>vpmax.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2236</ul> 2237 2238 <ul> 2239<li>float32x2_t vpmax_f32 (float32x2_t, float32x2_t) 2240<br><em>Form of expected instruction(s):</em> <code>vpmax.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2241</ul> 2242 2243<h5 class="subsubsection">6.54.3.23 Folding minimum</h5> 2244 2245 <ul> 2246<li>uint32x2_t vpmin_u32 (uint32x2_t, uint32x2_t) 2247<br><em>Form of expected instruction(s):</em> <code>vpmin.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2248</ul> 2249 2250 <ul> 2251<li>uint16x4_t vpmin_u16 (uint16x4_t, uint16x4_t) 2252<br><em>Form of expected instruction(s):</em> <code>vpmin.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2253</ul> 2254 2255 <ul> 2256<li>uint8x8_t vpmin_u8 (uint8x8_t, uint8x8_t) 2257<br><em>Form of expected instruction(s):</em> <code>vpmin.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2258</ul> 2259 2260 <ul> 2261<li>int32x2_t vpmin_s32 (int32x2_t, int32x2_t) 2262<br><em>Form of expected instruction(s):</em> <code>vpmin.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2263</ul> 2264 2265 <ul> 2266<li>int16x4_t vpmin_s16 (int16x4_t, int16x4_t) 2267<br><em>Form of expected instruction(s):</em> <code>vpmin.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2268</ul> 2269 2270 <ul> 2271<li>int8x8_t vpmin_s8 (int8x8_t, int8x8_t) 2272<br><em>Form of expected instruction(s):</em> <code>vpmin.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2273</ul> 2274 2275 <ul> 2276<li>float32x2_t vpmin_f32 (float32x2_t, float32x2_t) 2277<br><em>Form of expected instruction(s):</em> <code>vpmin.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2278</ul> 2279 2280<h5 class="subsubsection">6.54.3.24 Reciprocal step</h5> 2281 2282 <ul> 2283<li>float32x2_t vrecps_f32 (float32x2_t, float32x2_t) 2284<br><em>Form of expected instruction(s):</em> <code>vrecps.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2285</ul> 2286 2287 <ul> 2288<li>float32x4_t vrecpsq_f32 (float32x4_t, float32x4_t) 2289<br><em>Form of expected instruction(s):</em> <code>vrecps.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2290</ul> 2291 2292 <ul> 2293<li>float32x2_t vrsqrts_f32 (float32x2_t, float32x2_t) 2294<br><em>Form of expected instruction(s):</em> <code>vrsqrts.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2295</ul> 2296 2297 <ul> 2298<li>float32x4_t vrsqrtsq_f32 (float32x4_t, float32x4_t) 2299<br><em>Form of expected instruction(s):</em> <code>vrsqrts.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2300</ul> 2301 2302<h5 class="subsubsection">6.54.3.25 Vector shift left</h5> 2303 2304 <ul> 2305<li>uint32x2_t vshl_u32 (uint32x2_t, int32x2_t) 2306<br><em>Form of expected instruction(s):</em> <code>vshl.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2307</ul> 2308 2309 <ul> 2310<li>uint16x4_t vshl_u16 (uint16x4_t, int16x4_t) 2311<br><em>Form of expected instruction(s):</em> <code>vshl.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2312</ul> 2313 2314 <ul> 2315<li>uint8x8_t vshl_u8 (uint8x8_t, int8x8_t) 2316<br><em>Form of expected instruction(s):</em> <code>vshl.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2317</ul> 2318 2319 <ul> 2320<li>int32x2_t vshl_s32 (int32x2_t, int32x2_t) 2321<br><em>Form of expected instruction(s):</em> <code>vshl.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2322</ul> 2323 2324 <ul> 2325<li>int16x4_t vshl_s16 (int16x4_t, int16x4_t) 2326<br><em>Form of expected instruction(s):</em> <code>vshl.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2327</ul> 2328 2329 <ul> 2330<li>int8x8_t vshl_s8 (int8x8_t, int8x8_t) 2331<br><em>Form of expected instruction(s):</em> <code>vshl.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2332</ul> 2333 2334 <ul> 2335<li>uint64x1_t vshl_u64 (uint64x1_t, int64x1_t) 2336<br><em>Form of expected instruction(s):</em> <code>vshl.u64 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2337</ul> 2338 2339 <ul> 2340<li>int64x1_t vshl_s64 (int64x1_t, int64x1_t) 2341<br><em>Form of expected instruction(s):</em> <code>vshl.s64 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2342</ul> 2343 2344 <ul> 2345<li>uint32x4_t vshlq_u32 (uint32x4_t, int32x4_t) 2346<br><em>Form of expected instruction(s):</em> <code>vshl.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2347</ul> 2348 2349 <ul> 2350<li>uint16x8_t vshlq_u16 (uint16x8_t, int16x8_t) 2351<br><em>Form of expected instruction(s):</em> <code>vshl.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2352</ul> 2353 2354 <ul> 2355<li>uint8x16_t vshlq_u8 (uint8x16_t, int8x16_t) 2356<br><em>Form of expected instruction(s):</em> <code>vshl.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2357</ul> 2358 2359 <ul> 2360<li>int32x4_t vshlq_s32 (int32x4_t, int32x4_t) 2361<br><em>Form of expected instruction(s):</em> <code>vshl.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2362</ul> 2363 2364 <ul> 2365<li>int16x8_t vshlq_s16 (int16x8_t, int16x8_t) 2366<br><em>Form of expected instruction(s):</em> <code>vshl.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2367</ul> 2368 2369 <ul> 2370<li>int8x16_t vshlq_s8 (int8x16_t, int8x16_t) 2371<br><em>Form of expected instruction(s):</em> <code>vshl.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2372</ul> 2373 2374 <ul> 2375<li>uint64x2_t vshlq_u64 (uint64x2_t, int64x2_t) 2376<br><em>Form of expected instruction(s):</em> <code>vshl.u64 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2377</ul> 2378 2379 <ul> 2380<li>int64x2_t vshlq_s64 (int64x2_t, int64x2_t) 2381<br><em>Form of expected instruction(s):</em> <code>vshl.s64 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2382</ul> 2383 2384 <ul> 2385<li>uint32x2_t vrshl_u32 (uint32x2_t, int32x2_t) 2386<br><em>Form of expected instruction(s):</em> <code>vrshl.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2387</ul> 2388 2389 <ul> 2390<li>uint16x4_t vrshl_u16 (uint16x4_t, int16x4_t) 2391<br><em>Form of expected instruction(s):</em> <code>vrshl.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2392</ul> 2393 2394 <ul> 2395<li>uint8x8_t vrshl_u8 (uint8x8_t, int8x8_t) 2396<br><em>Form of expected instruction(s):</em> <code>vrshl.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2397</ul> 2398 2399 <ul> 2400<li>int32x2_t vrshl_s32 (int32x2_t, int32x2_t) 2401<br><em>Form of expected instruction(s):</em> <code>vrshl.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2402</ul> 2403 2404 <ul> 2405<li>int16x4_t vrshl_s16 (int16x4_t, int16x4_t) 2406<br><em>Form of expected instruction(s):</em> <code>vrshl.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2407</ul> 2408 2409 <ul> 2410<li>int8x8_t vrshl_s8 (int8x8_t, int8x8_t) 2411<br><em>Form of expected instruction(s):</em> <code>vrshl.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2412</ul> 2413 2414 <ul> 2415<li>uint64x1_t vrshl_u64 (uint64x1_t, int64x1_t) 2416<br><em>Form of expected instruction(s):</em> <code>vrshl.u64 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2417</ul> 2418 2419 <ul> 2420<li>int64x1_t vrshl_s64 (int64x1_t, int64x1_t) 2421<br><em>Form of expected instruction(s):</em> <code>vrshl.s64 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2422</ul> 2423 2424 <ul> 2425<li>uint32x4_t vrshlq_u32 (uint32x4_t, int32x4_t) 2426<br><em>Form of expected instruction(s):</em> <code>vrshl.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2427</ul> 2428 2429 <ul> 2430<li>uint16x8_t vrshlq_u16 (uint16x8_t, int16x8_t) 2431<br><em>Form of expected instruction(s):</em> <code>vrshl.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2432</ul> 2433 2434 <ul> 2435<li>uint8x16_t vrshlq_u8 (uint8x16_t, int8x16_t) 2436<br><em>Form of expected instruction(s):</em> <code>vrshl.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2437</ul> 2438 2439 <ul> 2440<li>int32x4_t vrshlq_s32 (int32x4_t, int32x4_t) 2441<br><em>Form of expected instruction(s):</em> <code>vrshl.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2442</ul> 2443 2444 <ul> 2445<li>int16x8_t vrshlq_s16 (int16x8_t, int16x8_t) 2446<br><em>Form of expected instruction(s):</em> <code>vrshl.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2447</ul> 2448 2449 <ul> 2450<li>int8x16_t vrshlq_s8 (int8x16_t, int8x16_t) 2451<br><em>Form of expected instruction(s):</em> <code>vrshl.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2452</ul> 2453 2454 <ul> 2455<li>uint64x2_t vrshlq_u64 (uint64x2_t, int64x2_t) 2456<br><em>Form of expected instruction(s):</em> <code>vrshl.u64 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2457</ul> 2458 2459 <ul> 2460<li>int64x2_t vrshlq_s64 (int64x2_t, int64x2_t) 2461<br><em>Form of expected instruction(s):</em> <code>vrshl.s64 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2462</ul> 2463 2464 <ul> 2465<li>uint32x2_t vqshl_u32 (uint32x2_t, int32x2_t) 2466<br><em>Form of expected instruction(s):</em> <code>vqshl.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2467</ul> 2468 2469 <ul> 2470<li>uint16x4_t vqshl_u16 (uint16x4_t, int16x4_t) 2471<br><em>Form of expected instruction(s):</em> <code>vqshl.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2472</ul> 2473 2474 <ul> 2475<li>uint8x8_t vqshl_u8 (uint8x8_t, int8x8_t) 2476<br><em>Form of expected instruction(s):</em> <code>vqshl.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2477</ul> 2478 2479 <ul> 2480<li>int32x2_t vqshl_s32 (int32x2_t, int32x2_t) 2481<br><em>Form of expected instruction(s):</em> <code>vqshl.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2482</ul> 2483 2484 <ul> 2485<li>int16x4_t vqshl_s16 (int16x4_t, int16x4_t) 2486<br><em>Form of expected instruction(s):</em> <code>vqshl.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2487</ul> 2488 2489 <ul> 2490<li>int8x8_t vqshl_s8 (int8x8_t, int8x8_t) 2491<br><em>Form of expected instruction(s):</em> <code>vqshl.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2492</ul> 2493 2494 <ul> 2495<li>uint64x1_t vqshl_u64 (uint64x1_t, int64x1_t) 2496<br><em>Form of expected instruction(s):</em> <code>vqshl.u64 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2497</ul> 2498 2499 <ul> 2500<li>int64x1_t vqshl_s64 (int64x1_t, int64x1_t) 2501<br><em>Form of expected instruction(s):</em> <code>vqshl.s64 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2502</ul> 2503 2504 <ul> 2505<li>uint32x4_t vqshlq_u32 (uint32x4_t, int32x4_t) 2506<br><em>Form of expected instruction(s):</em> <code>vqshl.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2507</ul> 2508 2509 <ul> 2510<li>uint16x8_t vqshlq_u16 (uint16x8_t, int16x8_t) 2511<br><em>Form of expected instruction(s):</em> <code>vqshl.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2512</ul> 2513 2514 <ul> 2515<li>uint8x16_t vqshlq_u8 (uint8x16_t, int8x16_t) 2516<br><em>Form of expected instruction(s):</em> <code>vqshl.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2517</ul> 2518 2519 <ul> 2520<li>int32x4_t vqshlq_s32 (int32x4_t, int32x4_t) 2521<br><em>Form of expected instruction(s):</em> <code>vqshl.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2522</ul> 2523 2524 <ul> 2525<li>int16x8_t vqshlq_s16 (int16x8_t, int16x8_t) 2526<br><em>Form of expected instruction(s):</em> <code>vqshl.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2527</ul> 2528 2529 <ul> 2530<li>int8x16_t vqshlq_s8 (int8x16_t, int8x16_t) 2531<br><em>Form of expected instruction(s):</em> <code>vqshl.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2532</ul> 2533 2534 <ul> 2535<li>uint64x2_t vqshlq_u64 (uint64x2_t, int64x2_t) 2536<br><em>Form of expected instruction(s):</em> <code>vqshl.u64 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2537</ul> 2538 2539 <ul> 2540<li>int64x2_t vqshlq_s64 (int64x2_t, int64x2_t) 2541<br><em>Form of expected instruction(s):</em> <code>vqshl.s64 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2542</ul> 2543 2544 <ul> 2545<li>uint32x2_t vqrshl_u32 (uint32x2_t, int32x2_t) 2546<br><em>Form of expected instruction(s):</em> <code>vqrshl.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2547</ul> 2548 2549 <ul> 2550<li>uint16x4_t vqrshl_u16 (uint16x4_t, int16x4_t) 2551<br><em>Form of expected instruction(s):</em> <code>vqrshl.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2552</ul> 2553 2554 <ul> 2555<li>uint8x8_t vqrshl_u8 (uint8x8_t, int8x8_t) 2556<br><em>Form of expected instruction(s):</em> <code>vqrshl.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2557</ul> 2558 2559 <ul> 2560<li>int32x2_t vqrshl_s32 (int32x2_t, int32x2_t) 2561<br><em>Form of expected instruction(s):</em> <code>vqrshl.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2562</ul> 2563 2564 <ul> 2565<li>int16x4_t vqrshl_s16 (int16x4_t, int16x4_t) 2566<br><em>Form of expected instruction(s):</em> <code>vqrshl.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2567</ul> 2568 2569 <ul> 2570<li>int8x8_t vqrshl_s8 (int8x8_t, int8x8_t) 2571<br><em>Form of expected instruction(s):</em> <code>vqrshl.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2572</ul> 2573 2574 <ul> 2575<li>uint64x1_t vqrshl_u64 (uint64x1_t, int64x1_t) 2576<br><em>Form of expected instruction(s):</em> <code>vqrshl.u64 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2577</ul> 2578 2579 <ul> 2580<li>int64x1_t vqrshl_s64 (int64x1_t, int64x1_t) 2581<br><em>Form of expected instruction(s):</em> <code>vqrshl.s64 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 2582</ul> 2583 2584 <ul> 2585<li>uint32x4_t vqrshlq_u32 (uint32x4_t, int32x4_t) 2586<br><em>Form of expected instruction(s):</em> <code>vqrshl.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2587</ul> 2588 2589 <ul> 2590<li>uint16x8_t vqrshlq_u16 (uint16x8_t, int16x8_t) 2591<br><em>Form of expected instruction(s):</em> <code>vqrshl.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2592</ul> 2593 2594 <ul> 2595<li>uint8x16_t vqrshlq_u8 (uint8x16_t, int8x16_t) 2596<br><em>Form of expected instruction(s):</em> <code>vqrshl.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2597</ul> 2598 2599 <ul> 2600<li>int32x4_t vqrshlq_s32 (int32x4_t, int32x4_t) 2601<br><em>Form of expected instruction(s):</em> <code>vqrshl.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2602</ul> 2603 2604 <ul> 2605<li>int16x8_t vqrshlq_s16 (int16x8_t, int16x8_t) 2606<br><em>Form of expected instruction(s):</em> <code>vqrshl.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2607</ul> 2608 2609 <ul> 2610<li>int8x16_t vqrshlq_s8 (int8x16_t, int8x16_t) 2611<br><em>Form of expected instruction(s):</em> <code>vqrshl.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2612</ul> 2613 2614 <ul> 2615<li>uint64x2_t vqrshlq_u64 (uint64x2_t, int64x2_t) 2616<br><em>Form of expected instruction(s):</em> <code>vqrshl.u64 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2617</ul> 2618 2619 <ul> 2620<li>int64x2_t vqrshlq_s64 (int64x2_t, int64x2_t) 2621<br><em>Form of expected instruction(s):</em> <code>vqrshl.s64 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 2622</ul> 2623 2624<h5 class="subsubsection">6.54.3.26 Vector shift left by constant</h5> 2625 2626 <ul> 2627<li>uint32x2_t vshl_n_u32 (uint32x2_t, const int) 2628<br><em>Form of expected instruction(s):</em> <code>vshl.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2629</ul> 2630 2631 <ul> 2632<li>uint16x4_t vshl_n_u16 (uint16x4_t, const int) 2633<br><em>Form of expected instruction(s):</em> <code>vshl.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2634</ul> 2635 2636 <ul> 2637<li>uint8x8_t vshl_n_u8 (uint8x8_t, const int) 2638<br><em>Form of expected instruction(s):</em> <code>vshl.i8 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2639</ul> 2640 2641 <ul> 2642<li>int32x2_t vshl_n_s32 (int32x2_t, const int) 2643<br><em>Form of expected instruction(s):</em> <code>vshl.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2644</ul> 2645 2646 <ul> 2647<li>int16x4_t vshl_n_s16 (int16x4_t, const int) 2648<br><em>Form of expected instruction(s):</em> <code>vshl.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2649</ul> 2650 2651 <ul> 2652<li>int8x8_t vshl_n_s8 (int8x8_t, const int) 2653<br><em>Form of expected instruction(s):</em> <code>vshl.i8 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2654</ul> 2655 2656 <ul> 2657<li>uint64x1_t vshl_n_u64 (uint64x1_t, const int) 2658<br><em>Form of expected instruction(s):</em> <code>vshl.i64 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2659</ul> 2660 2661 <ul> 2662<li>int64x1_t vshl_n_s64 (int64x1_t, const int) 2663<br><em>Form of expected instruction(s):</em> <code>vshl.i64 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2664</ul> 2665 2666 <ul> 2667<li>uint32x4_t vshlq_n_u32 (uint32x4_t, const int) 2668<br><em>Form of expected instruction(s):</em> <code>vshl.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 2669</ul> 2670 2671 <ul> 2672<li>uint16x8_t vshlq_n_u16 (uint16x8_t, const int) 2673<br><em>Form of expected instruction(s):</em> <code>vshl.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 2674</ul> 2675 2676 <ul> 2677<li>uint8x16_t vshlq_n_u8 (uint8x16_t, const int) 2678<br><em>Form of expected instruction(s):</em> <code>vshl.i8 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 2679</ul> 2680 2681 <ul> 2682<li>int32x4_t vshlq_n_s32 (int32x4_t, const int) 2683<br><em>Form of expected instruction(s):</em> <code>vshl.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 2684</ul> 2685 2686 <ul> 2687<li>int16x8_t vshlq_n_s16 (int16x8_t, const int) 2688<br><em>Form of expected instruction(s):</em> <code>vshl.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 2689</ul> 2690 2691 <ul> 2692<li>int8x16_t vshlq_n_s8 (int8x16_t, const int) 2693<br><em>Form of expected instruction(s):</em> <code>vshl.i8 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 2694</ul> 2695 2696 <ul> 2697<li>uint64x2_t vshlq_n_u64 (uint64x2_t, const int) 2698<br><em>Form of expected instruction(s):</em> <code>vshl.i64 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 2699</ul> 2700 2701 <ul> 2702<li>int64x2_t vshlq_n_s64 (int64x2_t, const int) 2703<br><em>Form of expected instruction(s):</em> <code>vshl.i64 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 2704</ul> 2705 2706 <ul> 2707<li>uint32x2_t vqshl_n_u32 (uint32x2_t, const int) 2708<br><em>Form of expected instruction(s):</em> <code>vqshl.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2709</ul> 2710 2711 <ul> 2712<li>uint16x4_t vqshl_n_u16 (uint16x4_t, const int) 2713<br><em>Form of expected instruction(s):</em> <code>vqshl.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2714</ul> 2715 2716 <ul> 2717<li>uint8x8_t vqshl_n_u8 (uint8x8_t, const int) 2718<br><em>Form of expected instruction(s):</em> <code>vqshl.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2719</ul> 2720 2721 <ul> 2722<li>int32x2_t vqshl_n_s32 (int32x2_t, const int) 2723<br><em>Form of expected instruction(s):</em> <code>vqshl.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2724</ul> 2725 2726 <ul> 2727<li>int16x4_t vqshl_n_s16 (int16x4_t, const int) 2728<br><em>Form of expected instruction(s):</em> <code>vqshl.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2729</ul> 2730 2731 <ul> 2732<li>int8x8_t vqshl_n_s8 (int8x8_t, const int) 2733<br><em>Form of expected instruction(s):</em> <code>vqshl.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2734</ul> 2735 2736 <ul> 2737<li>uint64x1_t vqshl_n_u64 (uint64x1_t, const int) 2738<br><em>Form of expected instruction(s):</em> <code>vqshl.u64 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2739</ul> 2740 2741 <ul> 2742<li>int64x1_t vqshl_n_s64 (int64x1_t, const int) 2743<br><em>Form of expected instruction(s):</em> <code>vqshl.s64 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2744</ul> 2745 2746 <ul> 2747<li>uint32x4_t vqshlq_n_u32 (uint32x4_t, const int) 2748<br><em>Form of expected instruction(s):</em> <code>vqshl.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 2749</ul> 2750 2751 <ul> 2752<li>uint16x8_t vqshlq_n_u16 (uint16x8_t, const int) 2753<br><em>Form of expected instruction(s):</em> <code>vqshl.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 2754</ul> 2755 2756 <ul> 2757<li>uint8x16_t vqshlq_n_u8 (uint8x16_t, const int) 2758<br><em>Form of expected instruction(s):</em> <code>vqshl.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 2759</ul> 2760 2761 <ul> 2762<li>int32x4_t vqshlq_n_s32 (int32x4_t, const int) 2763<br><em>Form of expected instruction(s):</em> <code>vqshl.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 2764</ul> 2765 2766 <ul> 2767<li>int16x8_t vqshlq_n_s16 (int16x8_t, const int) 2768<br><em>Form of expected instruction(s):</em> <code>vqshl.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 2769</ul> 2770 2771 <ul> 2772<li>int8x16_t vqshlq_n_s8 (int8x16_t, const int) 2773<br><em>Form of expected instruction(s):</em> <code>vqshl.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 2774</ul> 2775 2776 <ul> 2777<li>uint64x2_t vqshlq_n_u64 (uint64x2_t, const int) 2778<br><em>Form of expected instruction(s):</em> <code>vqshl.u64 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 2779</ul> 2780 2781 <ul> 2782<li>int64x2_t vqshlq_n_s64 (int64x2_t, const int) 2783<br><em>Form of expected instruction(s):</em> <code>vqshl.s64 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 2784</ul> 2785 2786 <ul> 2787<li>uint64x1_t vqshlu_n_s64 (int64x1_t, const int) 2788<br><em>Form of expected instruction(s):</em> <code>vqshlu.s64 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2789</ul> 2790 2791 <ul> 2792<li>uint32x2_t vqshlu_n_s32 (int32x2_t, const int) 2793<br><em>Form of expected instruction(s):</em> <code>vqshlu.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2794</ul> 2795 2796 <ul> 2797<li>uint16x4_t vqshlu_n_s16 (int16x4_t, const int) 2798<br><em>Form of expected instruction(s):</em> <code>vqshlu.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2799</ul> 2800 2801 <ul> 2802<li>uint8x8_t vqshlu_n_s8 (int8x8_t, const int) 2803<br><em>Form of expected instruction(s):</em> <code>vqshlu.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2804</ul> 2805 2806 <ul> 2807<li>uint64x2_t vqshluq_n_s64 (int64x2_t, const int) 2808<br><em>Form of expected instruction(s):</em> <code>vqshlu.s64 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 2809</ul> 2810 2811 <ul> 2812<li>uint32x4_t vqshluq_n_s32 (int32x4_t, const int) 2813<br><em>Form of expected instruction(s):</em> <code>vqshlu.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 2814</ul> 2815 2816 <ul> 2817<li>uint16x8_t vqshluq_n_s16 (int16x8_t, const int) 2818<br><em>Form of expected instruction(s):</em> <code>vqshlu.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 2819</ul> 2820 2821 <ul> 2822<li>uint8x16_t vqshluq_n_s8 (int8x16_t, const int) 2823<br><em>Form of expected instruction(s):</em> <code>vqshlu.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 2824</ul> 2825 2826 <ul> 2827<li>uint64x2_t vshll_n_u32 (uint32x2_t, const int) 2828<br><em>Form of expected instruction(s):</em> <code>vshll.u32 </code><var>q0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2829</ul> 2830 2831 <ul> 2832<li>uint32x4_t vshll_n_u16 (uint16x4_t, const int) 2833<br><em>Form of expected instruction(s):</em> <code>vshll.u16 </code><var>q0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2834</ul> 2835 2836 <ul> 2837<li>uint16x8_t vshll_n_u8 (uint8x8_t, const int) 2838<br><em>Form of expected instruction(s):</em> <code>vshll.u8 </code><var>q0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2839</ul> 2840 2841 <ul> 2842<li>int64x2_t vshll_n_s32 (int32x2_t, const int) 2843<br><em>Form of expected instruction(s):</em> <code>vshll.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2844</ul> 2845 2846 <ul> 2847<li>int32x4_t vshll_n_s16 (int16x4_t, const int) 2848<br><em>Form of expected instruction(s):</em> <code>vshll.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2849</ul> 2850 2851 <ul> 2852<li>int16x8_t vshll_n_s8 (int8x8_t, const int) 2853<br><em>Form of expected instruction(s):</em> <code>vshll.s8 </code><var>q0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2854</ul> 2855 2856<h5 class="subsubsection">6.54.3.27 Vector shift right by constant</h5> 2857 2858 <ul> 2859<li>uint32x2_t vshr_n_u32 (uint32x2_t, const int) 2860<br><em>Form of expected instruction(s):</em> <code>vshr.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2861</ul> 2862 2863 <ul> 2864<li>uint16x4_t vshr_n_u16 (uint16x4_t, const int) 2865<br><em>Form of expected instruction(s):</em> <code>vshr.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2866</ul> 2867 2868 <ul> 2869<li>uint8x8_t vshr_n_u8 (uint8x8_t, const int) 2870<br><em>Form of expected instruction(s):</em> <code>vshr.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2871</ul> 2872 2873 <ul> 2874<li>int32x2_t vshr_n_s32 (int32x2_t, const int) 2875<br><em>Form of expected instruction(s):</em> <code>vshr.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2876</ul> 2877 2878 <ul> 2879<li>int16x4_t vshr_n_s16 (int16x4_t, const int) 2880<br><em>Form of expected instruction(s):</em> <code>vshr.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2881</ul> 2882 2883 <ul> 2884<li>int8x8_t vshr_n_s8 (int8x8_t, const int) 2885<br><em>Form of expected instruction(s):</em> <code>vshr.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2886</ul> 2887 2888 <ul> 2889<li>uint64x1_t vshr_n_u64 (uint64x1_t, const int) 2890<br><em>Form of expected instruction(s):</em> <code>vshr.u64 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2891</ul> 2892 2893 <ul> 2894<li>int64x1_t vshr_n_s64 (int64x1_t, const int) 2895<br><em>Form of expected instruction(s):</em> <code>vshr.s64 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2896</ul> 2897 2898 <ul> 2899<li>uint32x4_t vshrq_n_u32 (uint32x4_t, const int) 2900<br><em>Form of expected instruction(s):</em> <code>vshr.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 2901</ul> 2902 2903 <ul> 2904<li>uint16x8_t vshrq_n_u16 (uint16x8_t, const int) 2905<br><em>Form of expected instruction(s):</em> <code>vshr.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 2906</ul> 2907 2908 <ul> 2909<li>uint8x16_t vshrq_n_u8 (uint8x16_t, const int) 2910<br><em>Form of expected instruction(s):</em> <code>vshr.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 2911</ul> 2912 2913 <ul> 2914<li>int32x4_t vshrq_n_s32 (int32x4_t, const int) 2915<br><em>Form of expected instruction(s):</em> <code>vshr.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 2916</ul> 2917 2918 <ul> 2919<li>int16x8_t vshrq_n_s16 (int16x8_t, const int) 2920<br><em>Form of expected instruction(s):</em> <code>vshr.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 2921</ul> 2922 2923 <ul> 2924<li>int8x16_t vshrq_n_s8 (int8x16_t, const int) 2925<br><em>Form of expected instruction(s):</em> <code>vshr.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 2926</ul> 2927 2928 <ul> 2929<li>uint64x2_t vshrq_n_u64 (uint64x2_t, const int) 2930<br><em>Form of expected instruction(s):</em> <code>vshr.u64 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 2931</ul> 2932 2933 <ul> 2934<li>int64x2_t vshrq_n_s64 (int64x2_t, const int) 2935<br><em>Form of expected instruction(s):</em> <code>vshr.s64 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 2936</ul> 2937 2938 <ul> 2939<li>uint32x2_t vrshr_n_u32 (uint32x2_t, const int) 2940<br><em>Form of expected instruction(s):</em> <code>vrshr.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2941</ul> 2942 2943 <ul> 2944<li>uint16x4_t vrshr_n_u16 (uint16x4_t, const int) 2945<br><em>Form of expected instruction(s):</em> <code>vrshr.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2946</ul> 2947 2948 <ul> 2949<li>uint8x8_t vrshr_n_u8 (uint8x8_t, const int) 2950<br><em>Form of expected instruction(s):</em> <code>vrshr.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2951</ul> 2952 2953 <ul> 2954<li>int32x2_t vrshr_n_s32 (int32x2_t, const int) 2955<br><em>Form of expected instruction(s):</em> <code>vrshr.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2956</ul> 2957 2958 <ul> 2959<li>int16x4_t vrshr_n_s16 (int16x4_t, const int) 2960<br><em>Form of expected instruction(s):</em> <code>vrshr.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2961</ul> 2962 2963 <ul> 2964<li>int8x8_t vrshr_n_s8 (int8x8_t, const int) 2965<br><em>Form of expected instruction(s):</em> <code>vrshr.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2966</ul> 2967 2968 <ul> 2969<li>uint64x1_t vrshr_n_u64 (uint64x1_t, const int) 2970<br><em>Form of expected instruction(s):</em> <code>vrshr.u64 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2971</ul> 2972 2973 <ul> 2974<li>int64x1_t vrshr_n_s64 (int64x1_t, const int) 2975<br><em>Form of expected instruction(s):</em> <code>vrshr.s64 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 2976</ul> 2977 2978 <ul> 2979<li>uint32x4_t vrshrq_n_u32 (uint32x4_t, const int) 2980<br><em>Form of expected instruction(s):</em> <code>vrshr.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 2981</ul> 2982 2983 <ul> 2984<li>uint16x8_t vrshrq_n_u16 (uint16x8_t, const int) 2985<br><em>Form of expected instruction(s):</em> <code>vrshr.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 2986</ul> 2987 2988 <ul> 2989<li>uint8x16_t vrshrq_n_u8 (uint8x16_t, const int) 2990<br><em>Form of expected instruction(s):</em> <code>vrshr.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 2991</ul> 2992 2993 <ul> 2994<li>int32x4_t vrshrq_n_s32 (int32x4_t, const int) 2995<br><em>Form of expected instruction(s):</em> <code>vrshr.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 2996</ul> 2997 2998 <ul> 2999<li>int16x8_t vrshrq_n_s16 (int16x8_t, const int) 3000<br><em>Form of expected instruction(s):</em> <code>vrshr.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3001</ul> 3002 3003 <ul> 3004<li>int8x16_t vrshrq_n_s8 (int8x16_t, const int) 3005<br><em>Form of expected instruction(s):</em> <code>vrshr.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3006</ul> 3007 3008 <ul> 3009<li>uint64x2_t vrshrq_n_u64 (uint64x2_t, const int) 3010<br><em>Form of expected instruction(s):</em> <code>vrshr.u64 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3011</ul> 3012 3013 <ul> 3014<li>int64x2_t vrshrq_n_s64 (int64x2_t, const int) 3015<br><em>Form of expected instruction(s):</em> <code>vrshr.s64 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3016</ul> 3017 3018 <ul> 3019<li>uint32x2_t vshrn_n_u64 (uint64x2_t, const int) 3020<br><em>Form of expected instruction(s):</em> <code>vshrn.i64 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3021</ul> 3022 3023 <ul> 3024<li>uint16x4_t vshrn_n_u32 (uint32x4_t, const int) 3025<br><em>Form of expected instruction(s):</em> <code>vshrn.i32 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3026</ul> 3027 3028 <ul> 3029<li>uint8x8_t vshrn_n_u16 (uint16x8_t, const int) 3030<br><em>Form of expected instruction(s):</em> <code>vshrn.i16 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3031</ul> 3032 3033 <ul> 3034<li>int32x2_t vshrn_n_s64 (int64x2_t, const int) 3035<br><em>Form of expected instruction(s):</em> <code>vshrn.i64 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3036</ul> 3037 3038 <ul> 3039<li>int16x4_t vshrn_n_s32 (int32x4_t, const int) 3040<br><em>Form of expected instruction(s):</em> <code>vshrn.i32 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3041</ul> 3042 3043 <ul> 3044<li>int8x8_t vshrn_n_s16 (int16x8_t, const int) 3045<br><em>Form of expected instruction(s):</em> <code>vshrn.i16 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3046</ul> 3047 3048 <ul> 3049<li>uint32x2_t vrshrn_n_u64 (uint64x2_t, const int) 3050<br><em>Form of expected instruction(s):</em> <code>vrshrn.i64 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3051</ul> 3052 3053 <ul> 3054<li>uint16x4_t vrshrn_n_u32 (uint32x4_t, const int) 3055<br><em>Form of expected instruction(s):</em> <code>vrshrn.i32 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3056</ul> 3057 3058 <ul> 3059<li>uint8x8_t vrshrn_n_u16 (uint16x8_t, const int) 3060<br><em>Form of expected instruction(s):</em> <code>vrshrn.i16 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3061</ul> 3062 3063 <ul> 3064<li>int32x2_t vrshrn_n_s64 (int64x2_t, const int) 3065<br><em>Form of expected instruction(s):</em> <code>vrshrn.i64 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3066</ul> 3067 3068 <ul> 3069<li>int16x4_t vrshrn_n_s32 (int32x4_t, const int) 3070<br><em>Form of expected instruction(s):</em> <code>vrshrn.i32 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3071</ul> 3072 3073 <ul> 3074<li>int8x8_t vrshrn_n_s16 (int16x8_t, const int) 3075<br><em>Form of expected instruction(s):</em> <code>vrshrn.i16 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3076</ul> 3077 3078 <ul> 3079<li>uint32x2_t vqshrn_n_u64 (uint64x2_t, const int) 3080<br><em>Form of expected instruction(s):</em> <code>vqshrn.u64 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3081</ul> 3082 3083 <ul> 3084<li>uint16x4_t vqshrn_n_u32 (uint32x4_t, const int) 3085<br><em>Form of expected instruction(s):</em> <code>vqshrn.u32 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3086</ul> 3087 3088 <ul> 3089<li>uint8x8_t vqshrn_n_u16 (uint16x8_t, const int) 3090<br><em>Form of expected instruction(s):</em> <code>vqshrn.u16 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3091</ul> 3092 3093 <ul> 3094<li>int32x2_t vqshrn_n_s64 (int64x2_t, const int) 3095<br><em>Form of expected instruction(s):</em> <code>vqshrn.s64 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3096</ul> 3097 3098 <ul> 3099<li>int16x4_t vqshrn_n_s32 (int32x4_t, const int) 3100<br><em>Form of expected instruction(s):</em> <code>vqshrn.s32 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3101</ul> 3102 3103 <ul> 3104<li>int8x8_t vqshrn_n_s16 (int16x8_t, const int) 3105<br><em>Form of expected instruction(s):</em> <code>vqshrn.s16 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3106</ul> 3107 3108 <ul> 3109<li>uint32x2_t vqrshrn_n_u64 (uint64x2_t, const int) 3110<br><em>Form of expected instruction(s):</em> <code>vqrshrn.u64 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3111</ul> 3112 3113 <ul> 3114<li>uint16x4_t vqrshrn_n_u32 (uint32x4_t, const int) 3115<br><em>Form of expected instruction(s):</em> <code>vqrshrn.u32 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3116</ul> 3117 3118 <ul> 3119<li>uint8x8_t vqrshrn_n_u16 (uint16x8_t, const int) 3120<br><em>Form of expected instruction(s):</em> <code>vqrshrn.u16 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3121</ul> 3122 3123 <ul> 3124<li>int32x2_t vqrshrn_n_s64 (int64x2_t, const int) 3125<br><em>Form of expected instruction(s):</em> <code>vqrshrn.s64 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3126</ul> 3127 3128 <ul> 3129<li>int16x4_t vqrshrn_n_s32 (int32x4_t, const int) 3130<br><em>Form of expected instruction(s):</em> <code>vqrshrn.s32 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3131</ul> 3132 3133 <ul> 3134<li>int8x8_t vqrshrn_n_s16 (int16x8_t, const int) 3135<br><em>Form of expected instruction(s):</em> <code>vqrshrn.s16 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3136</ul> 3137 3138 <ul> 3139<li>uint32x2_t vqshrun_n_s64 (int64x2_t, const int) 3140<br><em>Form of expected instruction(s):</em> <code>vqshrun.s64 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3141</ul> 3142 3143 <ul> 3144<li>uint16x4_t vqshrun_n_s32 (int32x4_t, const int) 3145<br><em>Form of expected instruction(s):</em> <code>vqshrun.s32 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3146</ul> 3147 3148 <ul> 3149<li>uint8x8_t vqshrun_n_s16 (int16x8_t, const int) 3150<br><em>Form of expected instruction(s):</em> <code>vqshrun.s16 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3151</ul> 3152 3153 <ul> 3154<li>uint32x2_t vqrshrun_n_s64 (int64x2_t, const int) 3155<br><em>Form of expected instruction(s):</em> <code>vqrshrun.s64 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3156</ul> 3157 3158 <ul> 3159<li>uint16x4_t vqrshrun_n_s32 (int32x4_t, const int) 3160<br><em>Form of expected instruction(s):</em> <code>vqrshrun.s32 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3161</ul> 3162 3163 <ul> 3164<li>uint8x8_t vqrshrun_n_s16 (int16x8_t, const int) 3165<br><em>Form of expected instruction(s):</em> <code>vqrshrun.s16 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3166</ul> 3167 3168<h5 class="subsubsection">6.54.3.28 Vector shift right by constant and accumulate</h5> 3169 3170 <ul> 3171<li>uint32x2_t vsra_n_u32 (uint32x2_t, uint32x2_t, const int) 3172<br><em>Form of expected instruction(s):</em> <code>vsra.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 3173</ul> 3174 3175 <ul> 3176<li>uint16x4_t vsra_n_u16 (uint16x4_t, uint16x4_t, const int) 3177<br><em>Form of expected instruction(s):</em> <code>vsra.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 3178</ul> 3179 3180 <ul> 3181<li>uint8x8_t vsra_n_u8 (uint8x8_t, uint8x8_t, const int) 3182<br><em>Form of expected instruction(s):</em> <code>vsra.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 3183</ul> 3184 3185 <ul> 3186<li>int32x2_t vsra_n_s32 (int32x2_t, int32x2_t, const int) 3187<br><em>Form of expected instruction(s):</em> <code>vsra.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 3188</ul> 3189 3190 <ul> 3191<li>int16x4_t vsra_n_s16 (int16x4_t, int16x4_t, const int) 3192<br><em>Form of expected instruction(s):</em> <code>vsra.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 3193</ul> 3194 3195 <ul> 3196<li>int8x8_t vsra_n_s8 (int8x8_t, int8x8_t, const int) 3197<br><em>Form of expected instruction(s):</em> <code>vsra.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 3198</ul> 3199 3200 <ul> 3201<li>uint64x1_t vsra_n_u64 (uint64x1_t, uint64x1_t, const int) 3202<br><em>Form of expected instruction(s):</em> <code>vsra.u64 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 3203</ul> 3204 3205 <ul> 3206<li>int64x1_t vsra_n_s64 (int64x1_t, int64x1_t, const int) 3207<br><em>Form of expected instruction(s):</em> <code>vsra.s64 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 3208</ul> 3209 3210 <ul> 3211<li>uint32x4_t vsraq_n_u32 (uint32x4_t, uint32x4_t, const int) 3212<br><em>Form of expected instruction(s):</em> <code>vsra.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3213</ul> 3214 3215 <ul> 3216<li>uint16x8_t vsraq_n_u16 (uint16x8_t, uint16x8_t, const int) 3217<br><em>Form of expected instruction(s):</em> <code>vsra.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3218</ul> 3219 3220 <ul> 3221<li>uint8x16_t vsraq_n_u8 (uint8x16_t, uint8x16_t, const int) 3222<br><em>Form of expected instruction(s):</em> <code>vsra.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3223</ul> 3224 3225 <ul> 3226<li>int32x4_t vsraq_n_s32 (int32x4_t, int32x4_t, const int) 3227<br><em>Form of expected instruction(s):</em> <code>vsra.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3228</ul> 3229 3230 <ul> 3231<li>int16x8_t vsraq_n_s16 (int16x8_t, int16x8_t, const int) 3232<br><em>Form of expected instruction(s):</em> <code>vsra.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3233</ul> 3234 3235 <ul> 3236<li>int8x16_t vsraq_n_s8 (int8x16_t, int8x16_t, const int) 3237<br><em>Form of expected instruction(s):</em> <code>vsra.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3238</ul> 3239 3240 <ul> 3241<li>uint64x2_t vsraq_n_u64 (uint64x2_t, uint64x2_t, const int) 3242<br><em>Form of expected instruction(s):</em> <code>vsra.u64 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3243</ul> 3244 3245 <ul> 3246<li>int64x2_t vsraq_n_s64 (int64x2_t, int64x2_t, const int) 3247<br><em>Form of expected instruction(s):</em> <code>vsra.s64 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3248</ul> 3249 3250 <ul> 3251<li>uint32x2_t vrsra_n_u32 (uint32x2_t, uint32x2_t, const int) 3252<br><em>Form of expected instruction(s):</em> <code>vrsra.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 3253</ul> 3254 3255 <ul> 3256<li>uint16x4_t vrsra_n_u16 (uint16x4_t, uint16x4_t, const int) 3257<br><em>Form of expected instruction(s):</em> <code>vrsra.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 3258</ul> 3259 3260 <ul> 3261<li>uint8x8_t vrsra_n_u8 (uint8x8_t, uint8x8_t, const int) 3262<br><em>Form of expected instruction(s):</em> <code>vrsra.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 3263</ul> 3264 3265 <ul> 3266<li>int32x2_t vrsra_n_s32 (int32x2_t, int32x2_t, const int) 3267<br><em>Form of expected instruction(s):</em> <code>vrsra.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 3268</ul> 3269 3270 <ul> 3271<li>int16x4_t vrsra_n_s16 (int16x4_t, int16x4_t, const int) 3272<br><em>Form of expected instruction(s):</em> <code>vrsra.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 3273</ul> 3274 3275 <ul> 3276<li>int8x8_t vrsra_n_s8 (int8x8_t, int8x8_t, const int) 3277<br><em>Form of expected instruction(s):</em> <code>vrsra.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 3278</ul> 3279 3280 <ul> 3281<li>uint64x1_t vrsra_n_u64 (uint64x1_t, uint64x1_t, const int) 3282<br><em>Form of expected instruction(s):</em> <code>vrsra.u64 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 3283</ul> 3284 3285 <ul> 3286<li>int64x1_t vrsra_n_s64 (int64x1_t, int64x1_t, const int) 3287<br><em>Form of expected instruction(s):</em> <code>vrsra.s64 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 3288</ul> 3289 3290 <ul> 3291<li>uint32x4_t vrsraq_n_u32 (uint32x4_t, uint32x4_t, const int) 3292<br><em>Form of expected instruction(s):</em> <code>vrsra.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3293</ul> 3294 3295 <ul> 3296<li>uint16x8_t vrsraq_n_u16 (uint16x8_t, uint16x8_t, const int) 3297<br><em>Form of expected instruction(s):</em> <code>vrsra.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3298</ul> 3299 3300 <ul> 3301<li>uint8x16_t vrsraq_n_u8 (uint8x16_t, uint8x16_t, const int) 3302<br><em>Form of expected instruction(s):</em> <code>vrsra.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3303</ul> 3304 3305 <ul> 3306<li>int32x4_t vrsraq_n_s32 (int32x4_t, int32x4_t, const int) 3307<br><em>Form of expected instruction(s):</em> <code>vrsra.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3308</ul> 3309 3310 <ul> 3311<li>int16x8_t vrsraq_n_s16 (int16x8_t, int16x8_t, const int) 3312<br><em>Form of expected instruction(s):</em> <code>vrsra.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3313</ul> 3314 3315 <ul> 3316<li>int8x16_t vrsraq_n_s8 (int8x16_t, int8x16_t, const int) 3317<br><em>Form of expected instruction(s):</em> <code>vrsra.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3318</ul> 3319 3320 <ul> 3321<li>uint64x2_t vrsraq_n_u64 (uint64x2_t, uint64x2_t, const int) 3322<br><em>Form of expected instruction(s):</em> <code>vrsra.u64 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3323</ul> 3324 3325 <ul> 3326<li>int64x2_t vrsraq_n_s64 (int64x2_t, int64x2_t, const int) 3327<br><em>Form of expected instruction(s):</em> <code>vrsra.s64 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3328</ul> 3329 3330<h5 class="subsubsection">6.54.3.29 Vector shift right and insert</h5> 3331 3332 <ul> 3333<li>uint32x2_t vsri_n_u32 (uint32x2_t, uint32x2_t, const int) 3334<br><em>Form of expected instruction(s):</em> <code>vsri.32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 3335</ul> 3336 3337 <ul> 3338<li>uint16x4_t vsri_n_u16 (uint16x4_t, uint16x4_t, const int) 3339<br><em>Form of expected instruction(s):</em> <code>vsri.16 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 3340</ul> 3341 3342 <ul> 3343<li>uint8x8_t vsri_n_u8 (uint8x8_t, uint8x8_t, const int) 3344<br><em>Form of expected instruction(s):</em> <code>vsri.8 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 3345</ul> 3346 3347 <ul> 3348<li>int32x2_t vsri_n_s32 (int32x2_t, int32x2_t, const int) 3349<br><em>Form of expected instruction(s):</em> <code>vsri.32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 3350</ul> 3351 3352 <ul> 3353<li>int16x4_t vsri_n_s16 (int16x4_t, int16x4_t, const int) 3354<br><em>Form of expected instruction(s):</em> <code>vsri.16 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 3355</ul> 3356 3357 <ul> 3358<li>int8x8_t vsri_n_s8 (int8x8_t, int8x8_t, const int) 3359<br><em>Form of expected instruction(s):</em> <code>vsri.8 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 3360</ul> 3361 3362 <ul> 3363<li>uint64x1_t vsri_n_u64 (uint64x1_t, uint64x1_t, const int) 3364<br><em>Form of expected instruction(s):</em> <code>vsri.64 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 3365</ul> 3366 3367 <ul> 3368<li>int64x1_t vsri_n_s64 (int64x1_t, int64x1_t, const int) 3369<br><em>Form of expected instruction(s):</em> <code>vsri.64 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 3370</ul> 3371 3372 <ul> 3373<li>poly16x4_t vsri_n_p16 (poly16x4_t, poly16x4_t, const int) 3374<br><em>Form of expected instruction(s):</em> <code>vsri.16 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 3375</ul> 3376 3377 <ul> 3378<li>poly8x8_t vsri_n_p8 (poly8x8_t, poly8x8_t, const int) 3379<br><em>Form of expected instruction(s):</em> <code>vsri.8 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 3380</ul> 3381 3382 <ul> 3383<li>uint32x4_t vsriq_n_u32 (uint32x4_t, uint32x4_t, const int) 3384<br><em>Form of expected instruction(s):</em> <code>vsri.32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3385</ul> 3386 3387 <ul> 3388<li>uint16x8_t vsriq_n_u16 (uint16x8_t, uint16x8_t, const int) 3389<br><em>Form of expected instruction(s):</em> <code>vsri.16 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3390</ul> 3391 3392 <ul> 3393<li>uint8x16_t vsriq_n_u8 (uint8x16_t, uint8x16_t, const int) 3394<br><em>Form of expected instruction(s):</em> <code>vsri.8 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3395</ul> 3396 3397 <ul> 3398<li>int32x4_t vsriq_n_s32 (int32x4_t, int32x4_t, const int) 3399<br><em>Form of expected instruction(s):</em> <code>vsri.32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3400</ul> 3401 3402 <ul> 3403<li>int16x8_t vsriq_n_s16 (int16x8_t, int16x8_t, const int) 3404<br><em>Form of expected instruction(s):</em> <code>vsri.16 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3405</ul> 3406 3407 <ul> 3408<li>int8x16_t vsriq_n_s8 (int8x16_t, int8x16_t, const int) 3409<br><em>Form of expected instruction(s):</em> <code>vsri.8 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3410</ul> 3411 3412 <ul> 3413<li>uint64x2_t vsriq_n_u64 (uint64x2_t, uint64x2_t, const int) 3414<br><em>Form of expected instruction(s):</em> <code>vsri.64 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3415</ul> 3416 3417 <ul> 3418<li>int64x2_t vsriq_n_s64 (int64x2_t, int64x2_t, const int) 3419<br><em>Form of expected instruction(s):</em> <code>vsri.64 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3420</ul> 3421 3422 <ul> 3423<li>poly16x8_t vsriq_n_p16 (poly16x8_t, poly16x8_t, const int) 3424<br><em>Form of expected instruction(s):</em> <code>vsri.16 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3425</ul> 3426 3427 <ul> 3428<li>poly8x16_t vsriq_n_p8 (poly8x16_t, poly8x16_t, const int) 3429<br><em>Form of expected instruction(s):</em> <code>vsri.8 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3430</ul> 3431 3432<h5 class="subsubsection">6.54.3.30 Vector shift left and insert</h5> 3433 3434 <ul> 3435<li>uint32x2_t vsli_n_u32 (uint32x2_t, uint32x2_t, const int) 3436<br><em>Form of expected instruction(s):</em> <code>vsli.32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 3437</ul> 3438 3439 <ul> 3440<li>uint16x4_t vsli_n_u16 (uint16x4_t, uint16x4_t, const int) 3441<br><em>Form of expected instruction(s):</em> <code>vsli.16 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 3442</ul> 3443 3444 <ul> 3445<li>uint8x8_t vsli_n_u8 (uint8x8_t, uint8x8_t, const int) 3446<br><em>Form of expected instruction(s):</em> <code>vsli.8 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 3447</ul> 3448 3449 <ul> 3450<li>int32x2_t vsli_n_s32 (int32x2_t, int32x2_t, const int) 3451<br><em>Form of expected instruction(s):</em> <code>vsli.32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 3452</ul> 3453 3454 <ul> 3455<li>int16x4_t vsli_n_s16 (int16x4_t, int16x4_t, const int) 3456<br><em>Form of expected instruction(s):</em> <code>vsli.16 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 3457</ul> 3458 3459 <ul> 3460<li>int8x8_t vsli_n_s8 (int8x8_t, int8x8_t, const int) 3461<br><em>Form of expected instruction(s):</em> <code>vsli.8 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 3462</ul> 3463 3464 <ul> 3465<li>uint64x1_t vsli_n_u64 (uint64x1_t, uint64x1_t, const int) 3466<br><em>Form of expected instruction(s):</em> <code>vsli.64 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 3467</ul> 3468 3469 <ul> 3470<li>int64x1_t vsli_n_s64 (int64x1_t, int64x1_t, const int) 3471<br><em>Form of expected instruction(s):</em> <code>vsli.64 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 3472</ul> 3473 3474 <ul> 3475<li>poly16x4_t vsli_n_p16 (poly16x4_t, poly16x4_t, const int) 3476<br><em>Form of expected instruction(s):</em> <code>vsli.16 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 3477</ul> 3478 3479 <ul> 3480<li>poly8x8_t vsli_n_p8 (poly8x8_t, poly8x8_t, const int) 3481<br><em>Form of expected instruction(s):</em> <code>vsli.8 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 3482</ul> 3483 3484 <ul> 3485<li>uint32x4_t vsliq_n_u32 (uint32x4_t, uint32x4_t, const int) 3486<br><em>Form of expected instruction(s):</em> <code>vsli.32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3487</ul> 3488 3489 <ul> 3490<li>uint16x8_t vsliq_n_u16 (uint16x8_t, uint16x8_t, const int) 3491<br><em>Form of expected instruction(s):</em> <code>vsli.16 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3492</ul> 3493 3494 <ul> 3495<li>uint8x16_t vsliq_n_u8 (uint8x16_t, uint8x16_t, const int) 3496<br><em>Form of expected instruction(s):</em> <code>vsli.8 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3497</ul> 3498 3499 <ul> 3500<li>int32x4_t vsliq_n_s32 (int32x4_t, int32x4_t, const int) 3501<br><em>Form of expected instruction(s):</em> <code>vsli.32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3502</ul> 3503 3504 <ul> 3505<li>int16x8_t vsliq_n_s16 (int16x8_t, int16x8_t, const int) 3506<br><em>Form of expected instruction(s):</em> <code>vsli.16 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3507</ul> 3508 3509 <ul> 3510<li>int8x16_t vsliq_n_s8 (int8x16_t, int8x16_t, const int) 3511<br><em>Form of expected instruction(s):</em> <code>vsli.8 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3512</ul> 3513 3514 <ul> 3515<li>uint64x2_t vsliq_n_u64 (uint64x2_t, uint64x2_t, const int) 3516<br><em>Form of expected instruction(s):</em> <code>vsli.64 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3517</ul> 3518 3519 <ul> 3520<li>int64x2_t vsliq_n_s64 (int64x2_t, int64x2_t, const int) 3521<br><em>Form of expected instruction(s):</em> <code>vsli.64 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3522</ul> 3523 3524 <ul> 3525<li>poly16x8_t vsliq_n_p16 (poly16x8_t, poly16x8_t, const int) 3526<br><em>Form of expected instruction(s):</em> <code>vsli.16 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3527</ul> 3528 3529 <ul> 3530<li>poly8x16_t vsliq_n_p8 (poly8x16_t, poly8x16_t, const int) 3531<br><em>Form of expected instruction(s):</em> <code>vsli.8 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 3532</ul> 3533 3534<h5 class="subsubsection">6.54.3.31 Absolute value</h5> 3535 3536 <ul> 3537<li>float32x2_t vabs_f32 (float32x2_t) 3538<br><em>Form of expected instruction(s):</em> <code>vabs.f32 </code><var>d0</var><code>, </code><var>d0</var> 3539</ul> 3540 3541 <ul> 3542<li>int32x2_t vabs_s32 (int32x2_t) 3543<br><em>Form of expected instruction(s):</em> <code>vabs.s32 </code><var>d0</var><code>, </code><var>d0</var> 3544</ul> 3545 3546 <ul> 3547<li>int16x4_t vabs_s16 (int16x4_t) 3548<br><em>Form of expected instruction(s):</em> <code>vabs.s16 </code><var>d0</var><code>, </code><var>d0</var> 3549</ul> 3550 3551 <ul> 3552<li>int8x8_t vabs_s8 (int8x8_t) 3553<br><em>Form of expected instruction(s):</em> <code>vabs.s8 </code><var>d0</var><code>, </code><var>d0</var> 3554</ul> 3555 3556 <ul> 3557<li>float32x4_t vabsq_f32 (float32x4_t) 3558<br><em>Form of expected instruction(s):</em> <code>vabs.f32 </code><var>q0</var><code>, </code><var>q0</var> 3559</ul> 3560 3561 <ul> 3562<li>int32x4_t vabsq_s32 (int32x4_t) 3563<br><em>Form of expected instruction(s):</em> <code>vabs.s32 </code><var>q0</var><code>, </code><var>q0</var> 3564</ul> 3565 3566 <ul> 3567<li>int16x8_t vabsq_s16 (int16x8_t) 3568<br><em>Form of expected instruction(s):</em> <code>vabs.s16 </code><var>q0</var><code>, </code><var>q0</var> 3569</ul> 3570 3571 <ul> 3572<li>int8x16_t vabsq_s8 (int8x16_t) 3573<br><em>Form of expected instruction(s):</em> <code>vabs.s8 </code><var>q0</var><code>, </code><var>q0</var> 3574</ul> 3575 3576 <ul> 3577<li>int32x2_t vqabs_s32 (int32x2_t) 3578<br><em>Form of expected instruction(s):</em> <code>vqabs.s32 </code><var>d0</var><code>, </code><var>d0</var> 3579</ul> 3580 3581 <ul> 3582<li>int16x4_t vqabs_s16 (int16x4_t) 3583<br><em>Form of expected instruction(s):</em> <code>vqabs.s16 </code><var>d0</var><code>, </code><var>d0</var> 3584</ul> 3585 3586 <ul> 3587<li>int8x8_t vqabs_s8 (int8x8_t) 3588<br><em>Form of expected instruction(s):</em> <code>vqabs.s8 </code><var>d0</var><code>, </code><var>d0</var> 3589</ul> 3590 3591 <ul> 3592<li>int32x4_t vqabsq_s32 (int32x4_t) 3593<br><em>Form of expected instruction(s):</em> <code>vqabs.s32 </code><var>q0</var><code>, </code><var>q0</var> 3594</ul> 3595 3596 <ul> 3597<li>int16x8_t vqabsq_s16 (int16x8_t) 3598<br><em>Form of expected instruction(s):</em> <code>vqabs.s16 </code><var>q0</var><code>, </code><var>q0</var> 3599</ul> 3600 3601 <ul> 3602<li>int8x16_t vqabsq_s8 (int8x16_t) 3603<br><em>Form of expected instruction(s):</em> <code>vqabs.s8 </code><var>q0</var><code>, </code><var>q0</var> 3604</ul> 3605 3606<h5 class="subsubsection">6.54.3.32 Negation</h5> 3607 3608 <ul> 3609<li>float32x2_t vneg_f32 (float32x2_t) 3610<br><em>Form of expected instruction(s):</em> <code>vneg.f32 </code><var>d0</var><code>, </code><var>d0</var> 3611</ul> 3612 3613 <ul> 3614<li>int32x2_t vneg_s32 (int32x2_t) 3615<br><em>Form of expected instruction(s):</em> <code>vneg.s32 </code><var>d0</var><code>, </code><var>d0</var> 3616</ul> 3617 3618 <ul> 3619<li>int16x4_t vneg_s16 (int16x4_t) 3620<br><em>Form of expected instruction(s):</em> <code>vneg.s16 </code><var>d0</var><code>, </code><var>d0</var> 3621</ul> 3622 3623 <ul> 3624<li>int8x8_t vneg_s8 (int8x8_t) 3625<br><em>Form of expected instruction(s):</em> <code>vneg.s8 </code><var>d0</var><code>, </code><var>d0</var> 3626</ul> 3627 3628 <ul> 3629<li>float32x4_t vnegq_f32 (float32x4_t) 3630<br><em>Form of expected instruction(s):</em> <code>vneg.f32 </code><var>q0</var><code>, </code><var>q0</var> 3631</ul> 3632 3633 <ul> 3634<li>int32x4_t vnegq_s32 (int32x4_t) 3635<br><em>Form of expected instruction(s):</em> <code>vneg.s32 </code><var>q0</var><code>, </code><var>q0</var> 3636</ul> 3637 3638 <ul> 3639<li>int16x8_t vnegq_s16 (int16x8_t) 3640<br><em>Form of expected instruction(s):</em> <code>vneg.s16 </code><var>q0</var><code>, </code><var>q0</var> 3641</ul> 3642 3643 <ul> 3644<li>int8x16_t vnegq_s8 (int8x16_t) 3645<br><em>Form of expected instruction(s):</em> <code>vneg.s8 </code><var>q0</var><code>, </code><var>q0</var> 3646</ul> 3647 3648 <ul> 3649<li>int32x2_t vqneg_s32 (int32x2_t) 3650<br><em>Form of expected instruction(s):</em> <code>vqneg.s32 </code><var>d0</var><code>, </code><var>d0</var> 3651</ul> 3652 3653 <ul> 3654<li>int16x4_t vqneg_s16 (int16x4_t) 3655<br><em>Form of expected instruction(s):</em> <code>vqneg.s16 </code><var>d0</var><code>, </code><var>d0</var> 3656</ul> 3657 3658 <ul> 3659<li>int8x8_t vqneg_s8 (int8x8_t) 3660<br><em>Form of expected instruction(s):</em> <code>vqneg.s8 </code><var>d0</var><code>, </code><var>d0</var> 3661</ul> 3662 3663 <ul> 3664<li>int32x4_t vqnegq_s32 (int32x4_t) 3665<br><em>Form of expected instruction(s):</em> <code>vqneg.s32 </code><var>q0</var><code>, </code><var>q0</var> 3666</ul> 3667 3668 <ul> 3669<li>int16x8_t vqnegq_s16 (int16x8_t) 3670<br><em>Form of expected instruction(s):</em> <code>vqneg.s16 </code><var>q0</var><code>, </code><var>q0</var> 3671</ul> 3672 3673 <ul> 3674<li>int8x16_t vqnegq_s8 (int8x16_t) 3675<br><em>Form of expected instruction(s):</em> <code>vqneg.s8 </code><var>q0</var><code>, </code><var>q0</var> 3676</ul> 3677 3678<h5 class="subsubsection">6.54.3.33 Bitwise not</h5> 3679 3680 <ul> 3681<li>uint32x2_t vmvn_u32 (uint32x2_t) 3682<br><em>Form of expected instruction(s):</em> <code>vmvn </code><var>d0</var><code>, </code><var>d0</var> 3683</ul> 3684 3685 <ul> 3686<li>uint16x4_t vmvn_u16 (uint16x4_t) 3687<br><em>Form of expected instruction(s):</em> <code>vmvn </code><var>d0</var><code>, </code><var>d0</var> 3688</ul> 3689 3690 <ul> 3691<li>uint8x8_t vmvn_u8 (uint8x8_t) 3692<br><em>Form of expected instruction(s):</em> <code>vmvn </code><var>d0</var><code>, </code><var>d0</var> 3693</ul> 3694 3695 <ul> 3696<li>int32x2_t vmvn_s32 (int32x2_t) 3697<br><em>Form of expected instruction(s):</em> <code>vmvn </code><var>d0</var><code>, </code><var>d0</var> 3698</ul> 3699 3700 <ul> 3701<li>int16x4_t vmvn_s16 (int16x4_t) 3702<br><em>Form of expected instruction(s):</em> <code>vmvn </code><var>d0</var><code>, </code><var>d0</var> 3703</ul> 3704 3705 <ul> 3706<li>int8x8_t vmvn_s8 (int8x8_t) 3707<br><em>Form of expected instruction(s):</em> <code>vmvn </code><var>d0</var><code>, </code><var>d0</var> 3708</ul> 3709 3710 <ul> 3711<li>poly8x8_t vmvn_p8 (poly8x8_t) 3712<br><em>Form of expected instruction(s):</em> <code>vmvn </code><var>d0</var><code>, </code><var>d0</var> 3713</ul> 3714 3715 <ul> 3716<li>uint32x4_t vmvnq_u32 (uint32x4_t) 3717<br><em>Form of expected instruction(s):</em> <code>vmvn </code><var>q0</var><code>, </code><var>q0</var> 3718</ul> 3719 3720 <ul> 3721<li>uint16x8_t vmvnq_u16 (uint16x8_t) 3722<br><em>Form of expected instruction(s):</em> <code>vmvn </code><var>q0</var><code>, </code><var>q0</var> 3723</ul> 3724 3725 <ul> 3726<li>uint8x16_t vmvnq_u8 (uint8x16_t) 3727<br><em>Form of expected instruction(s):</em> <code>vmvn </code><var>q0</var><code>, </code><var>q0</var> 3728</ul> 3729 3730 <ul> 3731<li>int32x4_t vmvnq_s32 (int32x4_t) 3732<br><em>Form of expected instruction(s):</em> <code>vmvn </code><var>q0</var><code>, </code><var>q0</var> 3733</ul> 3734 3735 <ul> 3736<li>int16x8_t vmvnq_s16 (int16x8_t) 3737<br><em>Form of expected instruction(s):</em> <code>vmvn </code><var>q0</var><code>, </code><var>q0</var> 3738</ul> 3739 3740 <ul> 3741<li>int8x16_t vmvnq_s8 (int8x16_t) 3742<br><em>Form of expected instruction(s):</em> <code>vmvn </code><var>q0</var><code>, </code><var>q0</var> 3743</ul> 3744 3745 <ul> 3746<li>poly8x16_t vmvnq_p8 (poly8x16_t) 3747<br><em>Form of expected instruction(s):</em> <code>vmvn </code><var>q0</var><code>, </code><var>q0</var> 3748</ul> 3749 3750<h5 class="subsubsection">6.54.3.34 Count leading sign bits</h5> 3751 3752 <ul> 3753<li>int32x2_t vcls_s32 (int32x2_t) 3754<br><em>Form of expected instruction(s):</em> <code>vcls.s32 </code><var>d0</var><code>, </code><var>d0</var> 3755</ul> 3756 3757 <ul> 3758<li>int16x4_t vcls_s16 (int16x4_t) 3759<br><em>Form of expected instruction(s):</em> <code>vcls.s16 </code><var>d0</var><code>, </code><var>d0</var> 3760</ul> 3761 3762 <ul> 3763<li>int8x8_t vcls_s8 (int8x8_t) 3764<br><em>Form of expected instruction(s):</em> <code>vcls.s8 </code><var>d0</var><code>, </code><var>d0</var> 3765</ul> 3766 3767 <ul> 3768<li>int32x4_t vclsq_s32 (int32x4_t) 3769<br><em>Form of expected instruction(s):</em> <code>vcls.s32 </code><var>q0</var><code>, </code><var>q0</var> 3770</ul> 3771 3772 <ul> 3773<li>int16x8_t vclsq_s16 (int16x8_t) 3774<br><em>Form of expected instruction(s):</em> <code>vcls.s16 </code><var>q0</var><code>, </code><var>q0</var> 3775</ul> 3776 3777 <ul> 3778<li>int8x16_t vclsq_s8 (int8x16_t) 3779<br><em>Form of expected instruction(s):</em> <code>vcls.s8 </code><var>q0</var><code>, </code><var>q0</var> 3780</ul> 3781 3782<h5 class="subsubsection">6.54.3.35 Count leading zeros</h5> 3783 3784 <ul> 3785<li>uint32x2_t vclz_u32 (uint32x2_t) 3786<br><em>Form of expected instruction(s):</em> <code>vclz.i32 </code><var>d0</var><code>, </code><var>d0</var> 3787</ul> 3788 3789 <ul> 3790<li>uint16x4_t vclz_u16 (uint16x4_t) 3791<br><em>Form of expected instruction(s):</em> <code>vclz.i16 </code><var>d0</var><code>, </code><var>d0</var> 3792</ul> 3793 3794 <ul> 3795<li>uint8x8_t vclz_u8 (uint8x8_t) 3796<br><em>Form of expected instruction(s):</em> <code>vclz.i8 </code><var>d0</var><code>, </code><var>d0</var> 3797</ul> 3798 3799 <ul> 3800<li>int32x2_t vclz_s32 (int32x2_t) 3801<br><em>Form of expected instruction(s):</em> <code>vclz.i32 </code><var>d0</var><code>, </code><var>d0</var> 3802</ul> 3803 3804 <ul> 3805<li>int16x4_t vclz_s16 (int16x4_t) 3806<br><em>Form of expected instruction(s):</em> <code>vclz.i16 </code><var>d0</var><code>, </code><var>d0</var> 3807</ul> 3808 3809 <ul> 3810<li>int8x8_t vclz_s8 (int8x8_t) 3811<br><em>Form of expected instruction(s):</em> <code>vclz.i8 </code><var>d0</var><code>, </code><var>d0</var> 3812</ul> 3813 3814 <ul> 3815<li>uint32x4_t vclzq_u32 (uint32x4_t) 3816<br><em>Form of expected instruction(s):</em> <code>vclz.i32 </code><var>q0</var><code>, </code><var>q0</var> 3817</ul> 3818 3819 <ul> 3820<li>uint16x8_t vclzq_u16 (uint16x8_t) 3821<br><em>Form of expected instruction(s):</em> <code>vclz.i16 </code><var>q0</var><code>, </code><var>q0</var> 3822</ul> 3823 3824 <ul> 3825<li>uint8x16_t vclzq_u8 (uint8x16_t) 3826<br><em>Form of expected instruction(s):</em> <code>vclz.i8 </code><var>q0</var><code>, </code><var>q0</var> 3827</ul> 3828 3829 <ul> 3830<li>int32x4_t vclzq_s32 (int32x4_t) 3831<br><em>Form of expected instruction(s):</em> <code>vclz.i32 </code><var>q0</var><code>, </code><var>q0</var> 3832</ul> 3833 3834 <ul> 3835<li>int16x8_t vclzq_s16 (int16x8_t) 3836<br><em>Form of expected instruction(s):</em> <code>vclz.i16 </code><var>q0</var><code>, </code><var>q0</var> 3837</ul> 3838 3839 <ul> 3840<li>int8x16_t vclzq_s8 (int8x16_t) 3841<br><em>Form of expected instruction(s):</em> <code>vclz.i8 </code><var>q0</var><code>, </code><var>q0</var> 3842</ul> 3843 3844<h5 class="subsubsection">6.54.3.36 Count number of set bits</h5> 3845 3846 <ul> 3847<li>uint8x8_t vcnt_u8 (uint8x8_t) 3848<br><em>Form of expected instruction(s):</em> <code>vcnt.8 </code><var>d0</var><code>, </code><var>d0</var> 3849</ul> 3850 3851 <ul> 3852<li>int8x8_t vcnt_s8 (int8x8_t) 3853<br><em>Form of expected instruction(s):</em> <code>vcnt.8 </code><var>d0</var><code>, </code><var>d0</var> 3854</ul> 3855 3856 <ul> 3857<li>poly8x8_t vcnt_p8 (poly8x8_t) 3858<br><em>Form of expected instruction(s):</em> <code>vcnt.8 </code><var>d0</var><code>, </code><var>d0</var> 3859</ul> 3860 3861 <ul> 3862<li>uint8x16_t vcntq_u8 (uint8x16_t) 3863<br><em>Form of expected instruction(s):</em> <code>vcnt.8 </code><var>q0</var><code>, </code><var>q0</var> 3864</ul> 3865 3866 <ul> 3867<li>int8x16_t vcntq_s8 (int8x16_t) 3868<br><em>Form of expected instruction(s):</em> <code>vcnt.8 </code><var>q0</var><code>, </code><var>q0</var> 3869</ul> 3870 3871 <ul> 3872<li>poly8x16_t vcntq_p8 (poly8x16_t) 3873<br><em>Form of expected instruction(s):</em> <code>vcnt.8 </code><var>q0</var><code>, </code><var>q0</var> 3874</ul> 3875 3876<h5 class="subsubsection">6.54.3.37 Reciprocal estimate</h5> 3877 3878 <ul> 3879<li>float32x2_t vrecpe_f32 (float32x2_t) 3880<br><em>Form of expected instruction(s):</em> <code>vrecpe.f32 </code><var>d0</var><code>, </code><var>d0</var> 3881</ul> 3882 3883 <ul> 3884<li>uint32x2_t vrecpe_u32 (uint32x2_t) 3885<br><em>Form of expected instruction(s):</em> <code>vrecpe.u32 </code><var>d0</var><code>, </code><var>d0</var> 3886</ul> 3887 3888 <ul> 3889<li>float32x4_t vrecpeq_f32 (float32x4_t) 3890<br><em>Form of expected instruction(s):</em> <code>vrecpe.f32 </code><var>q0</var><code>, </code><var>q0</var> 3891</ul> 3892 3893 <ul> 3894<li>uint32x4_t vrecpeq_u32 (uint32x4_t) 3895<br><em>Form of expected instruction(s):</em> <code>vrecpe.u32 </code><var>q0</var><code>, </code><var>q0</var> 3896</ul> 3897 3898<h5 class="subsubsection">6.54.3.38 Reciprocal square-root estimate</h5> 3899 3900 <ul> 3901<li>float32x2_t vrsqrte_f32 (float32x2_t) 3902<br><em>Form of expected instruction(s):</em> <code>vrsqrte.f32 </code><var>d0</var><code>, </code><var>d0</var> 3903</ul> 3904 3905 <ul> 3906<li>uint32x2_t vrsqrte_u32 (uint32x2_t) 3907<br><em>Form of expected instruction(s):</em> <code>vrsqrte.u32 </code><var>d0</var><code>, </code><var>d0</var> 3908</ul> 3909 3910 <ul> 3911<li>float32x4_t vrsqrteq_f32 (float32x4_t) 3912<br><em>Form of expected instruction(s):</em> <code>vrsqrte.f32 </code><var>q0</var><code>, </code><var>q0</var> 3913</ul> 3914 3915 <ul> 3916<li>uint32x4_t vrsqrteq_u32 (uint32x4_t) 3917<br><em>Form of expected instruction(s):</em> <code>vrsqrte.u32 </code><var>q0</var><code>, </code><var>q0</var> 3918</ul> 3919 3920<h5 class="subsubsection">6.54.3.39 Get lanes from a vector</h5> 3921 3922 <ul> 3923<li>uint32_t vget_lane_u32 (uint32x2_t, const int) 3924<br><em>Form of expected instruction(s):</em> <code>vmov.32 </code><var>r0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 3925</ul> 3926 3927 <ul> 3928<li>uint16_t vget_lane_u16 (uint16x4_t, const int) 3929<br><em>Form of expected instruction(s):</em> <code>vmov.u16 </code><var>r0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 3930</ul> 3931 3932 <ul> 3933<li>uint8_t vget_lane_u8 (uint8x8_t, const int) 3934<br><em>Form of expected instruction(s):</em> <code>vmov.u8 </code><var>r0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 3935</ul> 3936 3937 <ul> 3938<li>int32_t vget_lane_s32 (int32x2_t, const int) 3939<br><em>Form of expected instruction(s):</em> <code>vmov.32 </code><var>r0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 3940</ul> 3941 3942 <ul> 3943<li>int16_t vget_lane_s16 (int16x4_t, const int) 3944<br><em>Form of expected instruction(s):</em> <code>vmov.s16 </code><var>r0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 3945</ul> 3946 3947 <ul> 3948<li>int8_t vget_lane_s8 (int8x8_t, const int) 3949<br><em>Form of expected instruction(s):</em> <code>vmov.s8 </code><var>r0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 3950</ul> 3951 3952 <ul> 3953<li>float32_t vget_lane_f32 (float32x2_t, const int) 3954<br><em>Form of expected instruction(s):</em> <code>vmov.32 </code><var>r0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 3955</ul> 3956 3957 <ul> 3958<li>poly16_t vget_lane_p16 (poly16x4_t, const int) 3959<br><em>Form of expected instruction(s):</em> <code>vmov.u16 </code><var>r0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 3960</ul> 3961 3962 <ul> 3963<li>poly8_t vget_lane_p8 (poly8x8_t, const int) 3964<br><em>Form of expected instruction(s):</em> <code>vmov.u8 </code><var>r0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 3965</ul> 3966 3967 <ul> 3968<li>uint64_t vget_lane_u64 (uint64x1_t, const int) 3969</ul> 3970 3971 <ul> 3972<li>int64_t vget_lane_s64 (int64x1_t, const int) 3973</ul> 3974 3975 <ul> 3976<li>uint32_t vgetq_lane_u32 (uint32x4_t, const int) 3977<br><em>Form of expected instruction(s):</em> <code>vmov.32 </code><var>r0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 3978</ul> 3979 3980 <ul> 3981<li>uint16_t vgetq_lane_u16 (uint16x8_t, const int) 3982<br><em>Form of expected instruction(s):</em> <code>vmov.u16 </code><var>r0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 3983</ul> 3984 3985 <ul> 3986<li>uint8_t vgetq_lane_u8 (uint8x16_t, const int) 3987<br><em>Form of expected instruction(s):</em> <code>vmov.u8 </code><var>r0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 3988</ul> 3989 3990 <ul> 3991<li>int32_t vgetq_lane_s32 (int32x4_t, const int) 3992<br><em>Form of expected instruction(s):</em> <code>vmov.32 </code><var>r0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 3993</ul> 3994 3995 <ul> 3996<li>int16_t vgetq_lane_s16 (int16x8_t, const int) 3997<br><em>Form of expected instruction(s):</em> <code>vmov.s16 </code><var>r0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 3998</ul> 3999 4000 <ul> 4001<li>int8_t vgetq_lane_s8 (int8x16_t, const int) 4002<br><em>Form of expected instruction(s):</em> <code>vmov.s8 </code><var>r0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 4003</ul> 4004 4005 <ul> 4006<li>float32_t vgetq_lane_f32 (float32x4_t, const int) 4007<br><em>Form of expected instruction(s):</em> <code>vmov.32 </code><var>r0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 4008</ul> 4009 4010 <ul> 4011<li>poly16_t vgetq_lane_p16 (poly16x8_t, const int) 4012<br><em>Form of expected instruction(s):</em> <code>vmov.u16 </code><var>r0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 4013</ul> 4014 4015 <ul> 4016<li>poly8_t vgetq_lane_p8 (poly8x16_t, const int) 4017<br><em>Form of expected instruction(s):</em> <code>vmov.u8 </code><var>r0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 4018</ul> 4019 4020 <ul> 4021<li>uint64_t vgetq_lane_u64 (uint64x2_t, const int) 4022<br><em>Form of expected instruction(s):</em> <code>vmov </code><var>r0</var><code>, </code><var>r0</var><code>, </code><var>d0</var> 4023</ul> 4024 4025 <ul> 4026<li>int64_t vgetq_lane_s64 (int64x2_t, const int) 4027<br><em>Form of expected instruction(s):</em> <code>vmov </code><var>r0</var><code>, </code><var>r0</var><code>, </code><var>d0</var> 4028</ul> 4029 4030<h5 class="subsubsection">6.54.3.40 Set lanes in a vector</h5> 4031 4032 <ul> 4033<li>uint32x2_t vset_lane_u32 (uint32_t, uint32x2_t, const int) 4034<br><em>Form of expected instruction(s):</em> <code>vmov.32 </code><var>d0</var><code>[</code><var>0</var><code>], </code><var>r0</var> 4035</ul> 4036 4037 <ul> 4038<li>uint16x4_t vset_lane_u16 (uint16_t, uint16x4_t, const int) 4039<br><em>Form of expected instruction(s):</em> <code>vmov.16 </code><var>d0</var><code>[</code><var>0</var><code>], </code><var>r0</var> 4040</ul> 4041 4042 <ul> 4043<li>uint8x8_t vset_lane_u8 (uint8_t, uint8x8_t, const int) 4044<br><em>Form of expected instruction(s):</em> <code>vmov.8 </code><var>d0</var><code>[</code><var>0</var><code>], </code><var>r0</var> 4045</ul> 4046 4047 <ul> 4048<li>int32x2_t vset_lane_s32 (int32_t, int32x2_t, const int) 4049<br><em>Form of expected instruction(s):</em> <code>vmov.32 </code><var>d0</var><code>[</code><var>0</var><code>], </code><var>r0</var> 4050</ul> 4051 4052 <ul> 4053<li>int16x4_t vset_lane_s16 (int16_t, int16x4_t, const int) 4054<br><em>Form of expected instruction(s):</em> <code>vmov.16 </code><var>d0</var><code>[</code><var>0</var><code>], </code><var>r0</var> 4055</ul> 4056 4057 <ul> 4058<li>int8x8_t vset_lane_s8 (int8_t, int8x8_t, const int) 4059<br><em>Form of expected instruction(s):</em> <code>vmov.8 </code><var>d0</var><code>[</code><var>0</var><code>], </code><var>r0</var> 4060</ul> 4061 4062 <ul> 4063<li>float32x2_t vset_lane_f32 (float32_t, float32x2_t, const int) 4064<br><em>Form of expected instruction(s):</em> <code>vmov.32 </code><var>d0</var><code>[</code><var>0</var><code>], </code><var>r0</var> 4065</ul> 4066 4067 <ul> 4068<li>poly16x4_t vset_lane_p16 (poly16_t, poly16x4_t, const int) 4069<br><em>Form of expected instruction(s):</em> <code>vmov.16 </code><var>d0</var><code>[</code><var>0</var><code>], </code><var>r0</var> 4070</ul> 4071 4072 <ul> 4073<li>poly8x8_t vset_lane_p8 (poly8_t, poly8x8_t, const int) 4074<br><em>Form of expected instruction(s):</em> <code>vmov.8 </code><var>d0</var><code>[</code><var>0</var><code>], </code><var>r0</var> 4075</ul> 4076 4077 <ul> 4078<li>uint64x1_t vset_lane_u64 (uint64_t, uint64x1_t, const int) 4079</ul> 4080 4081 <ul> 4082<li>int64x1_t vset_lane_s64 (int64_t, int64x1_t, const int) 4083</ul> 4084 4085 <ul> 4086<li>uint32x4_t vsetq_lane_u32 (uint32_t, uint32x4_t, const int) 4087<br><em>Form of expected instruction(s):</em> <code>vmov.32 </code><var>d0</var><code>[</code><var>0</var><code>], </code><var>r0</var> 4088</ul> 4089 4090 <ul> 4091<li>uint16x8_t vsetq_lane_u16 (uint16_t, uint16x8_t, const int) 4092<br><em>Form of expected instruction(s):</em> <code>vmov.16 </code><var>d0</var><code>[</code><var>0</var><code>], </code><var>r0</var> 4093</ul> 4094 4095 <ul> 4096<li>uint8x16_t vsetq_lane_u8 (uint8_t, uint8x16_t, const int) 4097<br><em>Form of expected instruction(s):</em> <code>vmov.8 </code><var>d0</var><code>[</code><var>0</var><code>], </code><var>r0</var> 4098</ul> 4099 4100 <ul> 4101<li>int32x4_t vsetq_lane_s32 (int32_t, int32x4_t, const int) 4102<br><em>Form of expected instruction(s):</em> <code>vmov.32 </code><var>d0</var><code>[</code><var>0</var><code>], </code><var>r0</var> 4103</ul> 4104 4105 <ul> 4106<li>int16x8_t vsetq_lane_s16 (int16_t, int16x8_t, const int) 4107<br><em>Form of expected instruction(s):</em> <code>vmov.16 </code><var>d0</var><code>[</code><var>0</var><code>], </code><var>r0</var> 4108</ul> 4109 4110 <ul> 4111<li>int8x16_t vsetq_lane_s8 (int8_t, int8x16_t, const int) 4112<br><em>Form of expected instruction(s):</em> <code>vmov.8 </code><var>d0</var><code>[</code><var>0</var><code>], </code><var>r0</var> 4113</ul> 4114 4115 <ul> 4116<li>float32x4_t vsetq_lane_f32 (float32_t, float32x4_t, const int) 4117<br><em>Form of expected instruction(s):</em> <code>vmov.32 </code><var>d0</var><code>[</code><var>0</var><code>], </code><var>r0</var> 4118</ul> 4119 4120 <ul> 4121<li>poly16x8_t vsetq_lane_p16 (poly16_t, poly16x8_t, const int) 4122<br><em>Form of expected instruction(s):</em> <code>vmov.16 </code><var>d0</var><code>[</code><var>0</var><code>], </code><var>r0</var> 4123</ul> 4124 4125 <ul> 4126<li>poly8x16_t vsetq_lane_p8 (poly8_t, poly8x16_t, const int) 4127<br><em>Form of expected instruction(s):</em> <code>vmov.8 </code><var>d0</var><code>[</code><var>0</var><code>], </code><var>r0</var> 4128</ul> 4129 4130 <ul> 4131<li>uint64x2_t vsetq_lane_u64 (uint64_t, uint64x2_t, const int) 4132<br><em>Form of expected instruction(s):</em> <code>vmov </code><var>d0</var><code>, </code><var>r0</var><code>, </code><var>r0</var> 4133</ul> 4134 4135 <ul> 4136<li>int64x2_t vsetq_lane_s64 (int64_t, int64x2_t, const int) 4137<br><em>Form of expected instruction(s):</em> <code>vmov </code><var>d0</var><code>, </code><var>r0</var><code>, </code><var>r0</var> 4138</ul> 4139 4140<h5 class="subsubsection">6.54.3.41 Create vector from literal bit pattern</h5> 4141 4142 <ul> 4143<li>uint32x2_t vcreate_u32 (uint64_t) 4144</ul> 4145 4146 <ul> 4147<li>uint16x4_t vcreate_u16 (uint64_t) 4148</ul> 4149 4150 <ul> 4151<li>uint8x8_t vcreate_u8 (uint64_t) 4152</ul> 4153 4154 <ul> 4155<li>int32x2_t vcreate_s32 (uint64_t) 4156</ul> 4157 4158 <ul> 4159<li>int16x4_t vcreate_s16 (uint64_t) 4160</ul> 4161 4162 <ul> 4163<li>int8x8_t vcreate_s8 (uint64_t) 4164</ul> 4165 4166 <ul> 4167<li>uint64x1_t vcreate_u64 (uint64_t) 4168</ul> 4169 4170 <ul> 4171<li>int64x1_t vcreate_s64 (uint64_t) 4172</ul> 4173 4174 <ul> 4175<li>float32x2_t vcreate_f32 (uint64_t) 4176</ul> 4177 4178 <ul> 4179<li>poly16x4_t vcreate_p16 (uint64_t) 4180</ul> 4181 4182 <ul> 4183<li>poly8x8_t vcreate_p8 (uint64_t) 4184</ul> 4185 4186<h5 class="subsubsection">6.54.3.42 Set all lanes to the same value</h5> 4187 4188 <ul> 4189<li>uint32x2_t vdup_n_u32 (uint32_t) 4190<br><em>Form of expected instruction(s):</em> <code>vdup.32 </code><var>d0</var><code>, </code><var>r0</var> 4191</ul> 4192 4193 <ul> 4194<li>uint16x4_t vdup_n_u16 (uint16_t) 4195<br><em>Form of expected instruction(s):</em> <code>vdup.16 </code><var>d0</var><code>, </code><var>r0</var> 4196</ul> 4197 4198 <ul> 4199<li>uint8x8_t vdup_n_u8 (uint8_t) 4200<br><em>Form of expected instruction(s):</em> <code>vdup.8 </code><var>d0</var><code>, </code><var>r0</var> 4201</ul> 4202 4203 <ul> 4204<li>int32x2_t vdup_n_s32 (int32_t) 4205<br><em>Form of expected instruction(s):</em> <code>vdup.32 </code><var>d0</var><code>, </code><var>r0</var> 4206</ul> 4207 4208 <ul> 4209<li>int16x4_t vdup_n_s16 (int16_t) 4210<br><em>Form of expected instruction(s):</em> <code>vdup.16 </code><var>d0</var><code>, </code><var>r0</var> 4211</ul> 4212 4213 <ul> 4214<li>int8x8_t vdup_n_s8 (int8_t) 4215<br><em>Form of expected instruction(s):</em> <code>vdup.8 </code><var>d0</var><code>, </code><var>r0</var> 4216</ul> 4217 4218 <ul> 4219<li>float32x2_t vdup_n_f32 (float32_t) 4220<br><em>Form of expected instruction(s):</em> <code>vdup.32 </code><var>d0</var><code>, </code><var>r0</var> 4221</ul> 4222 4223 <ul> 4224<li>poly16x4_t vdup_n_p16 (poly16_t) 4225<br><em>Form of expected instruction(s):</em> <code>vdup.16 </code><var>d0</var><code>, </code><var>r0</var> 4226</ul> 4227 4228 <ul> 4229<li>poly8x8_t vdup_n_p8 (poly8_t) 4230<br><em>Form of expected instruction(s):</em> <code>vdup.8 </code><var>d0</var><code>, </code><var>r0</var> 4231</ul> 4232 4233 <ul> 4234<li>uint64x1_t vdup_n_u64 (uint64_t) 4235</ul> 4236 4237 <ul> 4238<li>int64x1_t vdup_n_s64 (int64_t) 4239</ul> 4240 4241 <ul> 4242<li>uint32x4_t vdupq_n_u32 (uint32_t) 4243<br><em>Form of expected instruction(s):</em> <code>vdup.32 </code><var>q0</var><code>, </code><var>r0</var> 4244</ul> 4245 4246 <ul> 4247<li>uint16x8_t vdupq_n_u16 (uint16_t) 4248<br><em>Form of expected instruction(s):</em> <code>vdup.16 </code><var>q0</var><code>, </code><var>r0</var> 4249</ul> 4250 4251 <ul> 4252<li>uint8x16_t vdupq_n_u8 (uint8_t) 4253<br><em>Form of expected instruction(s):</em> <code>vdup.8 </code><var>q0</var><code>, </code><var>r0</var> 4254</ul> 4255 4256 <ul> 4257<li>int32x4_t vdupq_n_s32 (int32_t) 4258<br><em>Form of expected instruction(s):</em> <code>vdup.32 </code><var>q0</var><code>, </code><var>r0</var> 4259</ul> 4260 4261 <ul> 4262<li>int16x8_t vdupq_n_s16 (int16_t) 4263<br><em>Form of expected instruction(s):</em> <code>vdup.16 </code><var>q0</var><code>, </code><var>r0</var> 4264</ul> 4265 4266 <ul> 4267<li>int8x16_t vdupq_n_s8 (int8_t) 4268<br><em>Form of expected instruction(s):</em> <code>vdup.8 </code><var>q0</var><code>, </code><var>r0</var> 4269</ul> 4270 4271 <ul> 4272<li>float32x4_t vdupq_n_f32 (float32_t) 4273<br><em>Form of expected instruction(s):</em> <code>vdup.32 </code><var>q0</var><code>, </code><var>r0</var> 4274</ul> 4275 4276 <ul> 4277<li>poly16x8_t vdupq_n_p16 (poly16_t) 4278<br><em>Form of expected instruction(s):</em> <code>vdup.16 </code><var>q0</var><code>, </code><var>r0</var> 4279</ul> 4280 4281 <ul> 4282<li>poly8x16_t vdupq_n_p8 (poly8_t) 4283<br><em>Form of expected instruction(s):</em> <code>vdup.8 </code><var>q0</var><code>, </code><var>r0</var> 4284</ul> 4285 4286 <ul> 4287<li>uint64x2_t vdupq_n_u64 (uint64_t) 4288</ul> 4289 4290 <ul> 4291<li>int64x2_t vdupq_n_s64 (int64_t) 4292</ul> 4293 4294 <ul> 4295<li>uint32x2_t vmov_n_u32 (uint32_t) 4296<br><em>Form of expected instruction(s):</em> <code>vdup.32 </code><var>d0</var><code>, </code><var>r0</var> 4297</ul> 4298 4299 <ul> 4300<li>uint16x4_t vmov_n_u16 (uint16_t) 4301<br><em>Form of expected instruction(s):</em> <code>vdup.16 </code><var>d0</var><code>, </code><var>r0</var> 4302</ul> 4303 4304 <ul> 4305<li>uint8x8_t vmov_n_u8 (uint8_t) 4306<br><em>Form of expected instruction(s):</em> <code>vdup.8 </code><var>d0</var><code>, </code><var>r0</var> 4307</ul> 4308 4309 <ul> 4310<li>int32x2_t vmov_n_s32 (int32_t) 4311<br><em>Form of expected instruction(s):</em> <code>vdup.32 </code><var>d0</var><code>, </code><var>r0</var> 4312</ul> 4313 4314 <ul> 4315<li>int16x4_t vmov_n_s16 (int16_t) 4316<br><em>Form of expected instruction(s):</em> <code>vdup.16 </code><var>d0</var><code>, </code><var>r0</var> 4317</ul> 4318 4319 <ul> 4320<li>int8x8_t vmov_n_s8 (int8_t) 4321<br><em>Form of expected instruction(s):</em> <code>vdup.8 </code><var>d0</var><code>, </code><var>r0</var> 4322</ul> 4323 4324 <ul> 4325<li>float32x2_t vmov_n_f32 (float32_t) 4326<br><em>Form of expected instruction(s):</em> <code>vdup.32 </code><var>d0</var><code>, </code><var>r0</var> 4327</ul> 4328 4329 <ul> 4330<li>poly16x4_t vmov_n_p16 (poly16_t) 4331<br><em>Form of expected instruction(s):</em> <code>vdup.16 </code><var>d0</var><code>, </code><var>r0</var> 4332</ul> 4333 4334 <ul> 4335<li>poly8x8_t vmov_n_p8 (poly8_t) 4336<br><em>Form of expected instruction(s):</em> <code>vdup.8 </code><var>d0</var><code>, </code><var>r0</var> 4337</ul> 4338 4339 <ul> 4340<li>uint64x1_t vmov_n_u64 (uint64_t) 4341</ul> 4342 4343 <ul> 4344<li>int64x1_t vmov_n_s64 (int64_t) 4345</ul> 4346 4347 <ul> 4348<li>uint32x4_t vmovq_n_u32 (uint32_t) 4349<br><em>Form of expected instruction(s):</em> <code>vdup.32 </code><var>q0</var><code>, </code><var>r0</var> 4350</ul> 4351 4352 <ul> 4353<li>uint16x8_t vmovq_n_u16 (uint16_t) 4354<br><em>Form of expected instruction(s):</em> <code>vdup.16 </code><var>q0</var><code>, </code><var>r0</var> 4355</ul> 4356 4357 <ul> 4358<li>uint8x16_t vmovq_n_u8 (uint8_t) 4359<br><em>Form of expected instruction(s):</em> <code>vdup.8 </code><var>q0</var><code>, </code><var>r0</var> 4360</ul> 4361 4362 <ul> 4363<li>int32x4_t vmovq_n_s32 (int32_t) 4364<br><em>Form of expected instruction(s):</em> <code>vdup.32 </code><var>q0</var><code>, </code><var>r0</var> 4365</ul> 4366 4367 <ul> 4368<li>int16x8_t vmovq_n_s16 (int16_t) 4369<br><em>Form of expected instruction(s):</em> <code>vdup.16 </code><var>q0</var><code>, </code><var>r0</var> 4370</ul> 4371 4372 <ul> 4373<li>int8x16_t vmovq_n_s8 (int8_t) 4374<br><em>Form of expected instruction(s):</em> <code>vdup.8 </code><var>q0</var><code>, </code><var>r0</var> 4375</ul> 4376 4377 <ul> 4378<li>float32x4_t vmovq_n_f32 (float32_t) 4379<br><em>Form of expected instruction(s):</em> <code>vdup.32 </code><var>q0</var><code>, </code><var>r0</var> 4380</ul> 4381 4382 <ul> 4383<li>poly16x8_t vmovq_n_p16 (poly16_t) 4384<br><em>Form of expected instruction(s):</em> <code>vdup.16 </code><var>q0</var><code>, </code><var>r0</var> 4385</ul> 4386 4387 <ul> 4388<li>poly8x16_t vmovq_n_p8 (poly8_t) 4389<br><em>Form of expected instruction(s):</em> <code>vdup.8 </code><var>q0</var><code>, </code><var>r0</var> 4390</ul> 4391 4392 <ul> 4393<li>uint64x2_t vmovq_n_u64 (uint64_t) 4394</ul> 4395 4396 <ul> 4397<li>int64x2_t vmovq_n_s64 (int64_t) 4398</ul> 4399 4400 <ul> 4401<li>uint32x2_t vdup_lane_u32 (uint32x2_t, const int) 4402<br><em>Form of expected instruction(s):</em> <code>vdup.32 </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 4403</ul> 4404 4405 <ul> 4406<li>uint16x4_t vdup_lane_u16 (uint16x4_t, const int) 4407<br><em>Form of expected instruction(s):</em> <code>vdup.16 </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 4408</ul> 4409 4410 <ul> 4411<li>uint8x8_t vdup_lane_u8 (uint8x8_t, const int) 4412<br><em>Form of expected instruction(s):</em> <code>vdup.8 </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 4413</ul> 4414 4415 <ul> 4416<li>int32x2_t vdup_lane_s32 (int32x2_t, const int) 4417<br><em>Form of expected instruction(s):</em> <code>vdup.32 </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 4418</ul> 4419 4420 <ul> 4421<li>int16x4_t vdup_lane_s16 (int16x4_t, const int) 4422<br><em>Form of expected instruction(s):</em> <code>vdup.16 </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 4423</ul> 4424 4425 <ul> 4426<li>int8x8_t vdup_lane_s8 (int8x8_t, const int) 4427<br><em>Form of expected instruction(s):</em> <code>vdup.8 </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 4428</ul> 4429 4430 <ul> 4431<li>float32x2_t vdup_lane_f32 (float32x2_t, const int) 4432<br><em>Form of expected instruction(s):</em> <code>vdup.32 </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 4433</ul> 4434 4435 <ul> 4436<li>poly16x4_t vdup_lane_p16 (poly16x4_t, const int) 4437<br><em>Form of expected instruction(s):</em> <code>vdup.16 </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 4438</ul> 4439 4440 <ul> 4441<li>poly8x8_t vdup_lane_p8 (poly8x8_t, const int) 4442<br><em>Form of expected instruction(s):</em> <code>vdup.8 </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 4443</ul> 4444 4445 <ul> 4446<li>uint64x1_t vdup_lane_u64 (uint64x1_t, const int) 4447</ul> 4448 4449 <ul> 4450<li>int64x1_t vdup_lane_s64 (int64x1_t, const int) 4451</ul> 4452 4453 <ul> 4454<li>uint32x4_t vdupq_lane_u32 (uint32x2_t, const int) 4455<br><em>Form of expected instruction(s):</em> <code>vdup.32 </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 4456</ul> 4457 4458 <ul> 4459<li>uint16x8_t vdupq_lane_u16 (uint16x4_t, const int) 4460<br><em>Form of expected instruction(s):</em> <code>vdup.16 </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 4461</ul> 4462 4463 <ul> 4464<li>uint8x16_t vdupq_lane_u8 (uint8x8_t, const int) 4465<br><em>Form of expected instruction(s):</em> <code>vdup.8 </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 4466</ul> 4467 4468 <ul> 4469<li>int32x4_t vdupq_lane_s32 (int32x2_t, const int) 4470<br><em>Form of expected instruction(s):</em> <code>vdup.32 </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 4471</ul> 4472 4473 <ul> 4474<li>int16x8_t vdupq_lane_s16 (int16x4_t, const int) 4475<br><em>Form of expected instruction(s):</em> <code>vdup.16 </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 4476</ul> 4477 4478 <ul> 4479<li>int8x16_t vdupq_lane_s8 (int8x8_t, const int) 4480<br><em>Form of expected instruction(s):</em> <code>vdup.8 </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 4481</ul> 4482 4483 <ul> 4484<li>float32x4_t vdupq_lane_f32 (float32x2_t, const int) 4485<br><em>Form of expected instruction(s):</em> <code>vdup.32 </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 4486</ul> 4487 4488 <ul> 4489<li>poly16x8_t vdupq_lane_p16 (poly16x4_t, const int) 4490<br><em>Form of expected instruction(s):</em> <code>vdup.16 </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 4491</ul> 4492 4493 <ul> 4494<li>poly8x16_t vdupq_lane_p8 (poly8x8_t, const int) 4495<br><em>Form of expected instruction(s):</em> <code>vdup.8 </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 4496</ul> 4497 4498 <ul> 4499<li>uint64x2_t vdupq_lane_u64 (uint64x1_t, const int) 4500</ul> 4501 4502 <ul> 4503<li>int64x2_t vdupq_lane_s64 (int64x1_t, const int) 4504</ul> 4505 4506<h5 class="subsubsection">6.54.3.43 Combining vectors</h5> 4507 4508 <ul> 4509<li>uint32x4_t vcombine_u32 (uint32x2_t, uint32x2_t) 4510</ul> 4511 4512 <ul> 4513<li>uint16x8_t vcombine_u16 (uint16x4_t, uint16x4_t) 4514</ul> 4515 4516 <ul> 4517<li>uint8x16_t vcombine_u8 (uint8x8_t, uint8x8_t) 4518</ul> 4519 4520 <ul> 4521<li>int32x4_t vcombine_s32 (int32x2_t, int32x2_t) 4522</ul> 4523 4524 <ul> 4525<li>int16x8_t vcombine_s16 (int16x4_t, int16x4_t) 4526</ul> 4527 4528 <ul> 4529<li>int8x16_t vcombine_s8 (int8x8_t, int8x8_t) 4530</ul> 4531 4532 <ul> 4533<li>uint64x2_t vcombine_u64 (uint64x1_t, uint64x1_t) 4534</ul> 4535 4536 <ul> 4537<li>int64x2_t vcombine_s64 (int64x1_t, int64x1_t) 4538</ul> 4539 4540 <ul> 4541<li>float32x4_t vcombine_f32 (float32x2_t, float32x2_t) 4542</ul> 4543 4544 <ul> 4545<li>poly16x8_t vcombine_p16 (poly16x4_t, poly16x4_t) 4546</ul> 4547 4548 <ul> 4549<li>poly8x16_t vcombine_p8 (poly8x8_t, poly8x8_t) 4550</ul> 4551 4552<h5 class="subsubsection">6.54.3.44 Splitting vectors</h5> 4553 4554 <ul> 4555<li>uint32x2_t vget_high_u32 (uint32x4_t) 4556</ul> 4557 4558 <ul> 4559<li>uint16x4_t vget_high_u16 (uint16x8_t) 4560</ul> 4561 4562 <ul> 4563<li>uint8x8_t vget_high_u8 (uint8x16_t) 4564</ul> 4565 4566 <ul> 4567<li>int32x2_t vget_high_s32 (int32x4_t) 4568</ul> 4569 4570 <ul> 4571<li>int16x4_t vget_high_s16 (int16x8_t) 4572</ul> 4573 4574 <ul> 4575<li>int8x8_t vget_high_s8 (int8x16_t) 4576</ul> 4577 4578 <ul> 4579<li>uint64x1_t vget_high_u64 (uint64x2_t) 4580</ul> 4581 4582 <ul> 4583<li>int64x1_t vget_high_s64 (int64x2_t) 4584</ul> 4585 4586 <ul> 4587<li>float32x2_t vget_high_f32 (float32x4_t) 4588</ul> 4589 4590 <ul> 4591<li>poly16x4_t vget_high_p16 (poly16x8_t) 4592</ul> 4593 4594 <ul> 4595<li>poly8x8_t vget_high_p8 (poly8x16_t) 4596</ul> 4597 4598 <ul> 4599<li>uint32x2_t vget_low_u32 (uint32x4_t) 4600<br><em>Form of expected instruction(s):</em> <code>vmov </code><var>d0</var><code>, </code><var>d0</var> 4601</ul> 4602 4603 <ul> 4604<li>uint16x4_t vget_low_u16 (uint16x8_t) 4605<br><em>Form of expected instruction(s):</em> <code>vmov </code><var>d0</var><code>, </code><var>d0</var> 4606</ul> 4607 4608 <ul> 4609<li>uint8x8_t vget_low_u8 (uint8x16_t) 4610<br><em>Form of expected instruction(s):</em> <code>vmov </code><var>d0</var><code>, </code><var>d0</var> 4611</ul> 4612 4613 <ul> 4614<li>int32x2_t vget_low_s32 (int32x4_t) 4615<br><em>Form of expected instruction(s):</em> <code>vmov </code><var>d0</var><code>, </code><var>d0</var> 4616</ul> 4617 4618 <ul> 4619<li>int16x4_t vget_low_s16 (int16x8_t) 4620<br><em>Form of expected instruction(s):</em> <code>vmov </code><var>d0</var><code>, </code><var>d0</var> 4621</ul> 4622 4623 <ul> 4624<li>int8x8_t vget_low_s8 (int8x16_t) 4625<br><em>Form of expected instruction(s):</em> <code>vmov </code><var>d0</var><code>, </code><var>d0</var> 4626</ul> 4627 4628 <ul> 4629<li>float32x2_t vget_low_f32 (float32x4_t) 4630<br><em>Form of expected instruction(s):</em> <code>vmov </code><var>d0</var><code>, </code><var>d0</var> 4631</ul> 4632 4633 <ul> 4634<li>poly16x4_t vget_low_p16 (poly16x8_t) 4635<br><em>Form of expected instruction(s):</em> <code>vmov </code><var>d0</var><code>, </code><var>d0</var> 4636</ul> 4637 4638 <ul> 4639<li>poly8x8_t vget_low_p8 (poly8x16_t) 4640<br><em>Form of expected instruction(s):</em> <code>vmov </code><var>d0</var><code>, </code><var>d0</var> 4641</ul> 4642 4643 <ul> 4644<li>uint64x1_t vget_low_u64 (uint64x2_t) 4645</ul> 4646 4647 <ul> 4648<li>int64x1_t vget_low_s64 (int64x2_t) 4649</ul> 4650 4651<h5 class="subsubsection">6.54.3.45 Conversions</h5> 4652 4653 <ul> 4654<li>float32x2_t vcvt_f32_u32 (uint32x2_t) 4655<br><em>Form of expected instruction(s):</em> <code>vcvt.f32.u32 </code><var>d0</var><code>, </code><var>d0</var> 4656</ul> 4657 4658 <ul> 4659<li>float32x2_t vcvt_f32_s32 (int32x2_t) 4660<br><em>Form of expected instruction(s):</em> <code>vcvt.f32.s32 </code><var>d0</var><code>, </code><var>d0</var> 4661</ul> 4662 4663 <ul> 4664<li>uint32x2_t vcvt_u32_f32 (float32x2_t) 4665<br><em>Form of expected instruction(s):</em> <code>vcvt.u32.f32 </code><var>d0</var><code>, </code><var>d0</var> 4666</ul> 4667 4668 <ul> 4669<li>int32x2_t vcvt_s32_f32 (float32x2_t) 4670<br><em>Form of expected instruction(s):</em> <code>vcvt.s32.f32 </code><var>d0</var><code>, </code><var>d0</var> 4671</ul> 4672 4673 <ul> 4674<li>float32x4_t vcvtq_f32_u32 (uint32x4_t) 4675<br><em>Form of expected instruction(s):</em> <code>vcvt.f32.u32 </code><var>q0</var><code>, </code><var>q0</var> 4676</ul> 4677 4678 <ul> 4679<li>float32x4_t vcvtq_f32_s32 (int32x4_t) 4680<br><em>Form of expected instruction(s):</em> <code>vcvt.f32.s32 </code><var>q0</var><code>, </code><var>q0</var> 4681</ul> 4682 4683 <ul> 4684<li>uint32x4_t vcvtq_u32_f32 (float32x4_t) 4685<br><em>Form of expected instruction(s):</em> <code>vcvt.u32.f32 </code><var>q0</var><code>, </code><var>q0</var> 4686</ul> 4687 4688 <ul> 4689<li>int32x4_t vcvtq_s32_f32 (float32x4_t) 4690<br><em>Form of expected instruction(s):</em> <code>vcvt.s32.f32 </code><var>q0</var><code>, </code><var>q0</var> 4691</ul> 4692 4693 <ul> 4694<li>float32x2_t vcvt_n_f32_u32 (uint32x2_t, const int) 4695<br><em>Form of expected instruction(s):</em> <code>vcvt.f32.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 4696</ul> 4697 4698 <ul> 4699<li>float32x2_t vcvt_n_f32_s32 (int32x2_t, const int) 4700<br><em>Form of expected instruction(s):</em> <code>vcvt.f32.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 4701</ul> 4702 4703 <ul> 4704<li>uint32x2_t vcvt_n_u32_f32 (float32x2_t, const int) 4705<br><em>Form of expected instruction(s):</em> <code>vcvt.u32.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 4706</ul> 4707 4708 <ul> 4709<li>int32x2_t vcvt_n_s32_f32 (float32x2_t, const int) 4710<br><em>Form of expected instruction(s):</em> <code>vcvt.s32.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 4711</ul> 4712 4713 <ul> 4714<li>float32x4_t vcvtq_n_f32_u32 (uint32x4_t, const int) 4715<br><em>Form of expected instruction(s):</em> <code>vcvt.f32.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 4716</ul> 4717 4718 <ul> 4719<li>float32x4_t vcvtq_n_f32_s32 (int32x4_t, const int) 4720<br><em>Form of expected instruction(s):</em> <code>vcvt.f32.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 4721</ul> 4722 4723 <ul> 4724<li>uint32x4_t vcvtq_n_u32_f32 (float32x4_t, const int) 4725<br><em>Form of expected instruction(s):</em> <code>vcvt.u32.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 4726</ul> 4727 4728 <ul> 4729<li>int32x4_t vcvtq_n_s32_f32 (float32x4_t, const int) 4730<br><em>Form of expected instruction(s):</em> <code>vcvt.s32.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 4731</ul> 4732 4733<h5 class="subsubsection">6.54.3.46 Move, single_opcode narrowing</h5> 4734 4735 <ul> 4736<li>uint32x2_t vmovn_u64 (uint64x2_t) 4737<br><em>Form of expected instruction(s):</em> <code>vmovn.i64 </code><var>d0</var><code>, </code><var>q0</var> 4738</ul> 4739 4740 <ul> 4741<li>uint16x4_t vmovn_u32 (uint32x4_t) 4742<br><em>Form of expected instruction(s):</em> <code>vmovn.i32 </code><var>d0</var><code>, </code><var>q0</var> 4743</ul> 4744 4745 <ul> 4746<li>uint8x8_t vmovn_u16 (uint16x8_t) 4747<br><em>Form of expected instruction(s):</em> <code>vmovn.i16 </code><var>d0</var><code>, </code><var>q0</var> 4748</ul> 4749 4750 <ul> 4751<li>int32x2_t vmovn_s64 (int64x2_t) 4752<br><em>Form of expected instruction(s):</em> <code>vmovn.i64 </code><var>d0</var><code>, </code><var>q0</var> 4753</ul> 4754 4755 <ul> 4756<li>int16x4_t vmovn_s32 (int32x4_t) 4757<br><em>Form of expected instruction(s):</em> <code>vmovn.i32 </code><var>d0</var><code>, </code><var>q0</var> 4758</ul> 4759 4760 <ul> 4761<li>int8x8_t vmovn_s16 (int16x8_t) 4762<br><em>Form of expected instruction(s):</em> <code>vmovn.i16 </code><var>d0</var><code>, </code><var>q0</var> 4763</ul> 4764 4765 <ul> 4766<li>uint32x2_t vqmovn_u64 (uint64x2_t) 4767<br><em>Form of expected instruction(s):</em> <code>vqmovn.u64 </code><var>d0</var><code>, </code><var>q0</var> 4768</ul> 4769 4770 <ul> 4771<li>uint16x4_t vqmovn_u32 (uint32x4_t) 4772<br><em>Form of expected instruction(s):</em> <code>vqmovn.u32 </code><var>d0</var><code>, </code><var>q0</var> 4773</ul> 4774 4775 <ul> 4776<li>uint8x8_t vqmovn_u16 (uint16x8_t) 4777<br><em>Form of expected instruction(s):</em> <code>vqmovn.u16 </code><var>d0</var><code>, </code><var>q0</var> 4778</ul> 4779 4780 <ul> 4781<li>int32x2_t vqmovn_s64 (int64x2_t) 4782<br><em>Form of expected instruction(s):</em> <code>vqmovn.s64 </code><var>d0</var><code>, </code><var>q0</var> 4783</ul> 4784 4785 <ul> 4786<li>int16x4_t vqmovn_s32 (int32x4_t) 4787<br><em>Form of expected instruction(s):</em> <code>vqmovn.s32 </code><var>d0</var><code>, </code><var>q0</var> 4788</ul> 4789 4790 <ul> 4791<li>int8x8_t vqmovn_s16 (int16x8_t) 4792<br><em>Form of expected instruction(s):</em> <code>vqmovn.s16 </code><var>d0</var><code>, </code><var>q0</var> 4793</ul> 4794 4795 <ul> 4796<li>uint32x2_t vqmovun_s64 (int64x2_t) 4797<br><em>Form of expected instruction(s):</em> <code>vqmovun.s64 </code><var>d0</var><code>, </code><var>q0</var> 4798</ul> 4799 4800 <ul> 4801<li>uint16x4_t vqmovun_s32 (int32x4_t) 4802<br><em>Form of expected instruction(s):</em> <code>vqmovun.s32 </code><var>d0</var><code>, </code><var>q0</var> 4803</ul> 4804 4805 <ul> 4806<li>uint8x8_t vqmovun_s16 (int16x8_t) 4807<br><em>Form of expected instruction(s):</em> <code>vqmovun.s16 </code><var>d0</var><code>, </code><var>q0</var> 4808</ul> 4809 4810<h5 class="subsubsection">6.54.3.47 Move, single_opcode long</h5> 4811 4812 <ul> 4813<li>uint64x2_t vmovl_u32 (uint32x2_t) 4814<br><em>Form of expected instruction(s):</em> <code>vmovl.u32 </code><var>q0</var><code>, </code><var>d0</var> 4815</ul> 4816 4817 <ul> 4818<li>uint32x4_t vmovl_u16 (uint16x4_t) 4819<br><em>Form of expected instruction(s):</em> <code>vmovl.u16 </code><var>q0</var><code>, </code><var>d0</var> 4820</ul> 4821 4822 <ul> 4823<li>uint16x8_t vmovl_u8 (uint8x8_t) 4824<br><em>Form of expected instruction(s):</em> <code>vmovl.u8 </code><var>q0</var><code>, </code><var>d0</var> 4825</ul> 4826 4827 <ul> 4828<li>int64x2_t vmovl_s32 (int32x2_t) 4829<br><em>Form of expected instruction(s):</em> <code>vmovl.s32 </code><var>q0</var><code>, </code><var>d0</var> 4830</ul> 4831 4832 <ul> 4833<li>int32x4_t vmovl_s16 (int16x4_t) 4834<br><em>Form of expected instruction(s):</em> <code>vmovl.s16 </code><var>q0</var><code>, </code><var>d0</var> 4835</ul> 4836 4837 <ul> 4838<li>int16x8_t vmovl_s8 (int8x8_t) 4839<br><em>Form of expected instruction(s):</em> <code>vmovl.s8 </code><var>q0</var><code>, </code><var>d0</var> 4840</ul> 4841 4842<h5 class="subsubsection">6.54.3.48 Table lookup</h5> 4843 4844 <ul> 4845<li>poly8x8_t vtbl1_p8 (poly8x8_t, uint8x8_t) 4846<br><em>Form of expected instruction(s):</em> <code>vtbl.8 </code><var>d0</var><code>, {</code><var>d0</var><code>}, </code><var>d0</var> 4847</ul> 4848 4849 <ul> 4850<li>int8x8_t vtbl1_s8 (int8x8_t, int8x8_t) 4851<br><em>Form of expected instruction(s):</em> <code>vtbl.8 </code><var>d0</var><code>, {</code><var>d0</var><code>}, </code><var>d0</var> 4852</ul> 4853 4854 <ul> 4855<li>uint8x8_t vtbl1_u8 (uint8x8_t, uint8x8_t) 4856<br><em>Form of expected instruction(s):</em> <code>vtbl.8 </code><var>d0</var><code>, {</code><var>d0</var><code>}, </code><var>d0</var> 4857</ul> 4858 4859 <ul> 4860<li>poly8x8_t vtbl2_p8 (poly8x8x2_t, uint8x8_t) 4861<br><em>Form of expected instruction(s):</em> <code>vtbl.8 </code><var>d0</var><code>, {</code><var>d0</var><code>, </code><var>d1</var><code>}, </code><var>d0</var> 4862</ul> 4863 4864 <ul> 4865<li>int8x8_t vtbl2_s8 (int8x8x2_t, int8x8_t) 4866<br><em>Form of expected instruction(s):</em> <code>vtbl.8 </code><var>d0</var><code>, {</code><var>d0</var><code>, </code><var>d1</var><code>}, </code><var>d0</var> 4867</ul> 4868 4869 <ul> 4870<li>uint8x8_t vtbl2_u8 (uint8x8x2_t, uint8x8_t) 4871<br><em>Form of expected instruction(s):</em> <code>vtbl.8 </code><var>d0</var><code>, {</code><var>d0</var><code>, </code><var>d1</var><code>}, </code><var>d0</var> 4872</ul> 4873 4874 <ul> 4875<li>poly8x8_t vtbl3_p8 (poly8x8x3_t, uint8x8_t) 4876<br><em>Form of expected instruction(s):</em> <code>vtbl.8 </code><var>d0</var><code>, {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, </code><var>d0</var> 4877</ul> 4878 4879 <ul> 4880<li>int8x8_t vtbl3_s8 (int8x8x3_t, int8x8_t) 4881<br><em>Form of expected instruction(s):</em> <code>vtbl.8 </code><var>d0</var><code>, {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, </code><var>d0</var> 4882</ul> 4883 4884 <ul> 4885<li>uint8x8_t vtbl3_u8 (uint8x8x3_t, uint8x8_t) 4886<br><em>Form of expected instruction(s):</em> <code>vtbl.8 </code><var>d0</var><code>, {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, </code><var>d0</var> 4887</ul> 4888 4889 <ul> 4890<li>poly8x8_t vtbl4_p8 (poly8x8x4_t, uint8x8_t) 4891<br><em>Form of expected instruction(s):</em> <code>vtbl.8 </code><var>d0</var><code>, {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, </code><var>d0</var> 4892</ul> 4893 4894 <ul> 4895<li>int8x8_t vtbl4_s8 (int8x8x4_t, int8x8_t) 4896<br><em>Form of expected instruction(s):</em> <code>vtbl.8 </code><var>d0</var><code>, {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, </code><var>d0</var> 4897</ul> 4898 4899 <ul> 4900<li>uint8x8_t vtbl4_u8 (uint8x8x4_t, uint8x8_t) 4901<br><em>Form of expected instruction(s):</em> <code>vtbl.8 </code><var>d0</var><code>, {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, </code><var>d0</var> 4902</ul> 4903 4904<h5 class="subsubsection">6.54.3.49 Extended table lookup</h5> 4905 4906 <ul> 4907<li>poly8x8_t vtbx1_p8 (poly8x8_t, poly8x8_t, uint8x8_t) 4908<br><em>Form of expected instruction(s):</em> <code>vtbx.8 </code><var>d0</var><code>, {</code><var>d0</var><code>}, </code><var>d0</var> 4909</ul> 4910 4911 <ul> 4912<li>int8x8_t vtbx1_s8 (int8x8_t, int8x8_t, int8x8_t) 4913<br><em>Form of expected instruction(s):</em> <code>vtbx.8 </code><var>d0</var><code>, {</code><var>d0</var><code>}, </code><var>d0</var> 4914</ul> 4915 4916 <ul> 4917<li>uint8x8_t vtbx1_u8 (uint8x8_t, uint8x8_t, uint8x8_t) 4918<br><em>Form of expected instruction(s):</em> <code>vtbx.8 </code><var>d0</var><code>, {</code><var>d0</var><code>}, </code><var>d0</var> 4919</ul> 4920 4921 <ul> 4922<li>poly8x8_t vtbx2_p8 (poly8x8_t, poly8x8x2_t, uint8x8_t) 4923<br><em>Form of expected instruction(s):</em> <code>vtbx.8 </code><var>d0</var><code>, {</code><var>d0</var><code>, </code><var>d1</var><code>}, </code><var>d0</var> 4924</ul> 4925 4926 <ul> 4927<li>int8x8_t vtbx2_s8 (int8x8_t, int8x8x2_t, int8x8_t) 4928<br><em>Form of expected instruction(s):</em> <code>vtbx.8 </code><var>d0</var><code>, {</code><var>d0</var><code>, </code><var>d1</var><code>}, </code><var>d0</var> 4929</ul> 4930 4931 <ul> 4932<li>uint8x8_t vtbx2_u8 (uint8x8_t, uint8x8x2_t, uint8x8_t) 4933<br><em>Form of expected instruction(s):</em> <code>vtbx.8 </code><var>d0</var><code>, {</code><var>d0</var><code>, </code><var>d1</var><code>}, </code><var>d0</var> 4934</ul> 4935 4936 <ul> 4937<li>poly8x8_t vtbx3_p8 (poly8x8_t, poly8x8x3_t, uint8x8_t) 4938<br><em>Form of expected instruction(s):</em> <code>vtbx.8 </code><var>d0</var><code>, {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, </code><var>d0</var> 4939</ul> 4940 4941 <ul> 4942<li>int8x8_t vtbx3_s8 (int8x8_t, int8x8x3_t, int8x8_t) 4943<br><em>Form of expected instruction(s):</em> <code>vtbx.8 </code><var>d0</var><code>, {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, </code><var>d0</var> 4944</ul> 4945 4946 <ul> 4947<li>uint8x8_t vtbx3_u8 (uint8x8_t, uint8x8x3_t, uint8x8_t) 4948<br><em>Form of expected instruction(s):</em> <code>vtbx.8 </code><var>d0</var><code>, {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, </code><var>d0</var> 4949</ul> 4950 4951 <ul> 4952<li>poly8x8_t vtbx4_p8 (poly8x8_t, poly8x8x4_t, uint8x8_t) 4953<br><em>Form of expected instruction(s):</em> <code>vtbx.8 </code><var>d0</var><code>, {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, </code><var>d0</var> 4954</ul> 4955 4956 <ul> 4957<li>int8x8_t vtbx4_s8 (int8x8_t, int8x8x4_t, int8x8_t) 4958<br><em>Form of expected instruction(s):</em> <code>vtbx.8 </code><var>d0</var><code>, {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, </code><var>d0</var> 4959</ul> 4960 4961 <ul> 4962<li>uint8x8_t vtbx4_u8 (uint8x8_t, uint8x8x4_t, uint8x8_t) 4963<br><em>Form of expected instruction(s):</em> <code>vtbx.8 </code><var>d0</var><code>, {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, </code><var>d0</var> 4964</ul> 4965 4966<h5 class="subsubsection">6.54.3.50 Multiply, lane</h5> 4967 4968 <ul> 4969<li>float32x2_t vmul_lane_f32 (float32x2_t, float32x2_t, const int) 4970<br><em>Form of expected instruction(s):</em> <code>vmul.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 4971</ul> 4972 4973 <ul> 4974<li>uint32x2_t vmul_lane_u32 (uint32x2_t, uint32x2_t, const int) 4975<br><em>Form of expected instruction(s):</em> <code>vmul.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 4976</ul> 4977 4978 <ul> 4979<li>uint16x4_t vmul_lane_u16 (uint16x4_t, uint16x4_t, const int) 4980<br><em>Form of expected instruction(s):</em> <code>vmul.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 4981</ul> 4982 4983 <ul> 4984<li>int32x2_t vmul_lane_s32 (int32x2_t, int32x2_t, const int) 4985<br><em>Form of expected instruction(s):</em> <code>vmul.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 4986</ul> 4987 4988 <ul> 4989<li>int16x4_t vmul_lane_s16 (int16x4_t, int16x4_t, const int) 4990<br><em>Form of expected instruction(s):</em> <code>vmul.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 4991</ul> 4992 4993 <ul> 4994<li>float32x4_t vmulq_lane_f32 (float32x4_t, float32x2_t, const int) 4995<br><em>Form of expected instruction(s):</em> <code>vmul.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 4996</ul> 4997 4998 <ul> 4999<li>uint32x4_t vmulq_lane_u32 (uint32x4_t, uint32x2_t, const int) 5000<br><em>Form of expected instruction(s):</em> <code>vmul.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5001</ul> 5002 5003 <ul> 5004<li>uint16x8_t vmulq_lane_u16 (uint16x8_t, uint16x4_t, const int) 5005<br><em>Form of expected instruction(s):</em> <code>vmul.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5006</ul> 5007 5008 <ul> 5009<li>int32x4_t vmulq_lane_s32 (int32x4_t, int32x2_t, const int) 5010<br><em>Form of expected instruction(s):</em> <code>vmul.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5011</ul> 5012 5013 <ul> 5014<li>int16x8_t vmulq_lane_s16 (int16x8_t, int16x4_t, const int) 5015<br><em>Form of expected instruction(s):</em> <code>vmul.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5016</ul> 5017 5018<h5 class="subsubsection">6.54.3.51 Long multiply, lane</h5> 5019 5020 <ul> 5021<li>uint64x2_t vmull_lane_u32 (uint32x2_t, uint32x2_t, const int) 5022<br><em>Form of expected instruction(s):</em> <code>vmull.u32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5023</ul> 5024 5025 <ul> 5026<li>uint32x4_t vmull_lane_u16 (uint16x4_t, uint16x4_t, const int) 5027<br><em>Form of expected instruction(s):</em> <code>vmull.u16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5028</ul> 5029 5030 <ul> 5031<li>int64x2_t vmull_lane_s32 (int32x2_t, int32x2_t, const int) 5032<br><em>Form of expected instruction(s):</em> <code>vmull.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5033</ul> 5034 5035 <ul> 5036<li>int32x4_t vmull_lane_s16 (int16x4_t, int16x4_t, const int) 5037<br><em>Form of expected instruction(s):</em> <code>vmull.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5038</ul> 5039 5040<h5 class="subsubsection">6.54.3.52 Saturating doubling long multiply, lane</h5> 5041 5042 <ul> 5043<li>int64x2_t vqdmull_lane_s32 (int32x2_t, int32x2_t, const int) 5044<br><em>Form of expected instruction(s):</em> <code>vqdmull.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5045</ul> 5046 5047 <ul> 5048<li>int32x4_t vqdmull_lane_s16 (int16x4_t, int16x4_t, const int) 5049<br><em>Form of expected instruction(s):</em> <code>vqdmull.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5050</ul> 5051 5052<h5 class="subsubsection">6.54.3.53 Saturating doubling multiply high, lane</h5> 5053 5054 <ul> 5055<li>int32x4_t vqdmulhq_lane_s32 (int32x4_t, int32x2_t, const int) 5056<br><em>Form of expected instruction(s):</em> <code>vqdmulh.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5057</ul> 5058 5059 <ul> 5060<li>int16x8_t vqdmulhq_lane_s16 (int16x8_t, int16x4_t, const int) 5061<br><em>Form of expected instruction(s):</em> <code>vqdmulh.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5062</ul> 5063 5064 <ul> 5065<li>int32x2_t vqdmulh_lane_s32 (int32x2_t, int32x2_t, const int) 5066<br><em>Form of expected instruction(s):</em> <code>vqdmulh.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5067</ul> 5068 5069 <ul> 5070<li>int16x4_t vqdmulh_lane_s16 (int16x4_t, int16x4_t, const int) 5071<br><em>Form of expected instruction(s):</em> <code>vqdmulh.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5072</ul> 5073 5074 <ul> 5075<li>int32x4_t vqrdmulhq_lane_s32 (int32x4_t, int32x2_t, const int) 5076<br><em>Form of expected instruction(s):</em> <code>vqrdmulh.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5077</ul> 5078 5079 <ul> 5080<li>int16x8_t vqrdmulhq_lane_s16 (int16x8_t, int16x4_t, const int) 5081<br><em>Form of expected instruction(s):</em> <code>vqrdmulh.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5082</ul> 5083 5084 <ul> 5085<li>int32x2_t vqrdmulh_lane_s32 (int32x2_t, int32x2_t, const int) 5086<br><em>Form of expected instruction(s):</em> <code>vqrdmulh.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5087</ul> 5088 5089 <ul> 5090<li>int16x4_t vqrdmulh_lane_s16 (int16x4_t, int16x4_t, const int) 5091<br><em>Form of expected instruction(s):</em> <code>vqrdmulh.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5092</ul> 5093 5094<h5 class="subsubsection">6.54.3.54 Multiply-accumulate, lane</h5> 5095 5096 <ul> 5097<li>float32x2_t vmla_lane_f32 (float32x2_t, float32x2_t, float32x2_t, const int) 5098<br><em>Form of expected instruction(s):</em> <code>vmla.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5099</ul> 5100 5101 <ul> 5102<li>uint32x2_t vmla_lane_u32 (uint32x2_t, uint32x2_t, uint32x2_t, const int) 5103<br><em>Form of expected instruction(s):</em> <code>vmla.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5104</ul> 5105 5106 <ul> 5107<li>uint16x4_t vmla_lane_u16 (uint16x4_t, uint16x4_t, uint16x4_t, const int) 5108<br><em>Form of expected instruction(s):</em> <code>vmla.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5109</ul> 5110 5111 <ul> 5112<li>int32x2_t vmla_lane_s32 (int32x2_t, int32x2_t, int32x2_t, const int) 5113<br><em>Form of expected instruction(s):</em> <code>vmla.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5114</ul> 5115 5116 <ul> 5117<li>int16x4_t vmla_lane_s16 (int16x4_t, int16x4_t, int16x4_t, const int) 5118<br><em>Form of expected instruction(s):</em> <code>vmla.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5119</ul> 5120 5121 <ul> 5122<li>float32x4_t vmlaq_lane_f32 (float32x4_t, float32x4_t, float32x2_t, const int) 5123<br><em>Form of expected instruction(s):</em> <code>vmla.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5124</ul> 5125 5126 <ul> 5127<li>uint32x4_t vmlaq_lane_u32 (uint32x4_t, uint32x4_t, uint32x2_t, const int) 5128<br><em>Form of expected instruction(s):</em> <code>vmla.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5129</ul> 5130 5131 <ul> 5132<li>uint16x8_t vmlaq_lane_u16 (uint16x8_t, uint16x8_t, uint16x4_t, const int) 5133<br><em>Form of expected instruction(s):</em> <code>vmla.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5134</ul> 5135 5136 <ul> 5137<li>int32x4_t vmlaq_lane_s32 (int32x4_t, int32x4_t, int32x2_t, const int) 5138<br><em>Form of expected instruction(s):</em> <code>vmla.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5139</ul> 5140 5141 <ul> 5142<li>int16x8_t vmlaq_lane_s16 (int16x8_t, int16x8_t, int16x4_t, const int) 5143<br><em>Form of expected instruction(s):</em> <code>vmla.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5144</ul> 5145 5146 <ul> 5147<li>uint64x2_t vmlal_lane_u32 (uint64x2_t, uint32x2_t, uint32x2_t, const int) 5148<br><em>Form of expected instruction(s):</em> <code>vmlal.u32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5149</ul> 5150 5151 <ul> 5152<li>uint32x4_t vmlal_lane_u16 (uint32x4_t, uint16x4_t, uint16x4_t, const int) 5153<br><em>Form of expected instruction(s):</em> <code>vmlal.u16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5154</ul> 5155 5156 <ul> 5157<li>int64x2_t vmlal_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int) 5158<br><em>Form of expected instruction(s):</em> <code>vmlal.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5159</ul> 5160 5161 <ul> 5162<li>int32x4_t vmlal_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int) 5163<br><em>Form of expected instruction(s):</em> <code>vmlal.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5164</ul> 5165 5166 <ul> 5167<li>int64x2_t vqdmlal_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int) 5168<br><em>Form of expected instruction(s):</em> <code>vqdmlal.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5169</ul> 5170 5171 <ul> 5172<li>int32x4_t vqdmlal_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int) 5173<br><em>Form of expected instruction(s):</em> <code>vqdmlal.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5174</ul> 5175 5176<h5 class="subsubsection">6.54.3.55 Multiply-subtract, lane</h5> 5177 5178 <ul> 5179<li>float32x2_t vmls_lane_f32 (float32x2_t, float32x2_t, float32x2_t, const int) 5180<br><em>Form of expected instruction(s):</em> <code>vmls.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5181</ul> 5182 5183 <ul> 5184<li>uint32x2_t vmls_lane_u32 (uint32x2_t, uint32x2_t, uint32x2_t, const int) 5185<br><em>Form of expected instruction(s):</em> <code>vmls.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5186</ul> 5187 5188 <ul> 5189<li>uint16x4_t vmls_lane_u16 (uint16x4_t, uint16x4_t, uint16x4_t, const int) 5190<br><em>Form of expected instruction(s):</em> <code>vmls.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5191</ul> 5192 5193 <ul> 5194<li>int32x2_t vmls_lane_s32 (int32x2_t, int32x2_t, int32x2_t, const int) 5195<br><em>Form of expected instruction(s):</em> <code>vmls.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5196</ul> 5197 5198 <ul> 5199<li>int16x4_t vmls_lane_s16 (int16x4_t, int16x4_t, int16x4_t, const int) 5200<br><em>Form of expected instruction(s):</em> <code>vmls.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5201</ul> 5202 5203 <ul> 5204<li>float32x4_t vmlsq_lane_f32 (float32x4_t, float32x4_t, float32x2_t, const int) 5205<br><em>Form of expected instruction(s):</em> <code>vmls.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5206</ul> 5207 5208 <ul> 5209<li>uint32x4_t vmlsq_lane_u32 (uint32x4_t, uint32x4_t, uint32x2_t, const int) 5210<br><em>Form of expected instruction(s):</em> <code>vmls.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5211</ul> 5212 5213 <ul> 5214<li>uint16x8_t vmlsq_lane_u16 (uint16x8_t, uint16x8_t, uint16x4_t, const int) 5215<br><em>Form of expected instruction(s):</em> <code>vmls.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5216</ul> 5217 5218 <ul> 5219<li>int32x4_t vmlsq_lane_s32 (int32x4_t, int32x4_t, int32x2_t, const int) 5220<br><em>Form of expected instruction(s):</em> <code>vmls.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5221</ul> 5222 5223 <ul> 5224<li>int16x8_t vmlsq_lane_s16 (int16x8_t, int16x8_t, int16x4_t, const int) 5225<br><em>Form of expected instruction(s):</em> <code>vmls.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5226</ul> 5227 5228 <ul> 5229<li>uint64x2_t vmlsl_lane_u32 (uint64x2_t, uint32x2_t, uint32x2_t, const int) 5230<br><em>Form of expected instruction(s):</em> <code>vmlsl.u32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5231</ul> 5232 5233 <ul> 5234<li>uint32x4_t vmlsl_lane_u16 (uint32x4_t, uint16x4_t, uint16x4_t, const int) 5235<br><em>Form of expected instruction(s):</em> <code>vmlsl.u16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5236</ul> 5237 5238 <ul> 5239<li>int64x2_t vmlsl_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int) 5240<br><em>Form of expected instruction(s):</em> <code>vmlsl.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5241</ul> 5242 5243 <ul> 5244<li>int32x4_t vmlsl_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int) 5245<br><em>Form of expected instruction(s):</em> <code>vmlsl.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5246</ul> 5247 5248 <ul> 5249<li>int64x2_t vqdmlsl_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int) 5250<br><em>Form of expected instruction(s):</em> <code>vqdmlsl.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5251</ul> 5252 5253 <ul> 5254<li>int32x4_t vqdmlsl_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int) 5255<br><em>Form of expected instruction(s):</em> <code>vqdmlsl.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5256</ul> 5257 5258<h5 class="subsubsection">6.54.3.56 Vector multiply by scalar</h5> 5259 5260 <ul> 5261<li>float32x2_t vmul_n_f32 (float32x2_t, float32_t) 5262<br><em>Form of expected instruction(s):</em> <code>vmul.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5263</ul> 5264 5265 <ul> 5266<li>uint32x2_t vmul_n_u32 (uint32x2_t, uint32_t) 5267<br><em>Form of expected instruction(s):</em> <code>vmul.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5268</ul> 5269 5270 <ul> 5271<li>uint16x4_t vmul_n_u16 (uint16x4_t, uint16_t) 5272<br><em>Form of expected instruction(s):</em> <code>vmul.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5273</ul> 5274 5275 <ul> 5276<li>int32x2_t vmul_n_s32 (int32x2_t, int32_t) 5277<br><em>Form of expected instruction(s):</em> <code>vmul.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5278</ul> 5279 5280 <ul> 5281<li>int16x4_t vmul_n_s16 (int16x4_t, int16_t) 5282<br><em>Form of expected instruction(s):</em> <code>vmul.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5283</ul> 5284 5285 <ul> 5286<li>float32x4_t vmulq_n_f32 (float32x4_t, float32_t) 5287<br><em>Form of expected instruction(s):</em> <code>vmul.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5288</ul> 5289 5290 <ul> 5291<li>uint32x4_t vmulq_n_u32 (uint32x4_t, uint32_t) 5292<br><em>Form of expected instruction(s):</em> <code>vmul.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5293</ul> 5294 5295 <ul> 5296<li>uint16x8_t vmulq_n_u16 (uint16x8_t, uint16_t) 5297<br><em>Form of expected instruction(s):</em> <code>vmul.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5298</ul> 5299 5300 <ul> 5301<li>int32x4_t vmulq_n_s32 (int32x4_t, int32_t) 5302<br><em>Form of expected instruction(s):</em> <code>vmul.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5303</ul> 5304 5305 <ul> 5306<li>int16x8_t vmulq_n_s16 (int16x8_t, int16_t) 5307<br><em>Form of expected instruction(s):</em> <code>vmul.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5308</ul> 5309 5310<h5 class="subsubsection">6.54.3.57 Vector long multiply by scalar</h5> 5311 5312 <ul> 5313<li>uint64x2_t vmull_n_u32 (uint32x2_t, uint32_t) 5314<br><em>Form of expected instruction(s):</em> <code>vmull.u32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5315</ul> 5316 5317 <ul> 5318<li>uint32x4_t vmull_n_u16 (uint16x4_t, uint16_t) 5319<br><em>Form of expected instruction(s):</em> <code>vmull.u16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5320</ul> 5321 5322 <ul> 5323<li>int64x2_t vmull_n_s32 (int32x2_t, int32_t) 5324<br><em>Form of expected instruction(s):</em> <code>vmull.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5325</ul> 5326 5327 <ul> 5328<li>int32x4_t vmull_n_s16 (int16x4_t, int16_t) 5329<br><em>Form of expected instruction(s):</em> <code>vmull.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5330</ul> 5331 5332<h5 class="subsubsection">6.54.3.58 Vector saturating doubling long multiply by scalar</h5> 5333 5334 <ul> 5335<li>int64x2_t vqdmull_n_s32 (int32x2_t, int32_t) 5336<br><em>Form of expected instruction(s):</em> <code>vqdmull.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5337</ul> 5338 5339 <ul> 5340<li>int32x4_t vqdmull_n_s16 (int16x4_t, int16_t) 5341<br><em>Form of expected instruction(s):</em> <code>vqdmull.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5342</ul> 5343 5344<h5 class="subsubsection">6.54.3.59 Vector saturating doubling multiply high by scalar</h5> 5345 5346 <ul> 5347<li>int32x4_t vqdmulhq_n_s32 (int32x4_t, int32_t) 5348<br><em>Form of expected instruction(s):</em> <code>vqdmulh.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5349</ul> 5350 5351 <ul> 5352<li>int16x8_t vqdmulhq_n_s16 (int16x8_t, int16_t) 5353<br><em>Form of expected instruction(s):</em> <code>vqdmulh.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5354</ul> 5355 5356 <ul> 5357<li>int32x2_t vqdmulh_n_s32 (int32x2_t, int32_t) 5358<br><em>Form of expected instruction(s):</em> <code>vqdmulh.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5359</ul> 5360 5361 <ul> 5362<li>int16x4_t vqdmulh_n_s16 (int16x4_t, int16_t) 5363<br><em>Form of expected instruction(s):</em> <code>vqdmulh.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5364</ul> 5365 5366 <ul> 5367<li>int32x4_t vqrdmulhq_n_s32 (int32x4_t, int32_t) 5368<br><em>Form of expected instruction(s):</em> <code>vqrdmulh.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5369</ul> 5370 5371 <ul> 5372<li>int16x8_t vqrdmulhq_n_s16 (int16x8_t, int16_t) 5373<br><em>Form of expected instruction(s):</em> <code>vqrdmulh.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5374</ul> 5375 5376 <ul> 5377<li>int32x2_t vqrdmulh_n_s32 (int32x2_t, int32_t) 5378<br><em>Form of expected instruction(s):</em> <code>vqrdmulh.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5379</ul> 5380 5381 <ul> 5382<li>int16x4_t vqrdmulh_n_s16 (int16x4_t, int16_t) 5383<br><em>Form of expected instruction(s):</em> <code>vqrdmulh.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5384</ul> 5385 5386<h5 class="subsubsection">6.54.3.60 Vector multiply-accumulate by scalar</h5> 5387 5388 <ul> 5389<li>float32x2_t vmla_n_f32 (float32x2_t, float32x2_t, float32_t) 5390<br><em>Form of expected instruction(s):</em> <code>vmla.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5391</ul> 5392 5393 <ul> 5394<li>uint32x2_t vmla_n_u32 (uint32x2_t, uint32x2_t, uint32_t) 5395<br><em>Form of expected instruction(s):</em> <code>vmla.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5396</ul> 5397 5398 <ul> 5399<li>uint16x4_t vmla_n_u16 (uint16x4_t, uint16x4_t, uint16_t) 5400<br><em>Form of expected instruction(s):</em> <code>vmla.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5401</ul> 5402 5403 <ul> 5404<li>int32x2_t vmla_n_s32 (int32x2_t, int32x2_t, int32_t) 5405<br><em>Form of expected instruction(s):</em> <code>vmla.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5406</ul> 5407 5408 <ul> 5409<li>int16x4_t vmla_n_s16 (int16x4_t, int16x4_t, int16_t) 5410<br><em>Form of expected instruction(s):</em> <code>vmla.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5411</ul> 5412 5413 <ul> 5414<li>float32x4_t vmlaq_n_f32 (float32x4_t, float32x4_t, float32_t) 5415<br><em>Form of expected instruction(s):</em> <code>vmla.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5416</ul> 5417 5418 <ul> 5419<li>uint32x4_t vmlaq_n_u32 (uint32x4_t, uint32x4_t, uint32_t) 5420<br><em>Form of expected instruction(s):</em> <code>vmla.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5421</ul> 5422 5423 <ul> 5424<li>uint16x8_t vmlaq_n_u16 (uint16x8_t, uint16x8_t, uint16_t) 5425<br><em>Form of expected instruction(s):</em> <code>vmla.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5426</ul> 5427 5428 <ul> 5429<li>int32x4_t vmlaq_n_s32 (int32x4_t, int32x4_t, int32_t) 5430<br><em>Form of expected instruction(s):</em> <code>vmla.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5431</ul> 5432 5433 <ul> 5434<li>int16x8_t vmlaq_n_s16 (int16x8_t, int16x8_t, int16_t) 5435<br><em>Form of expected instruction(s):</em> <code>vmla.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5436</ul> 5437 5438 <ul> 5439<li>uint64x2_t vmlal_n_u32 (uint64x2_t, uint32x2_t, uint32_t) 5440<br><em>Form of expected instruction(s):</em> <code>vmlal.u32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5441</ul> 5442 5443 <ul> 5444<li>uint32x4_t vmlal_n_u16 (uint32x4_t, uint16x4_t, uint16_t) 5445<br><em>Form of expected instruction(s):</em> <code>vmlal.u16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5446</ul> 5447 5448 <ul> 5449<li>int64x2_t vmlal_n_s32 (int64x2_t, int32x2_t, int32_t) 5450<br><em>Form of expected instruction(s):</em> <code>vmlal.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5451</ul> 5452 5453 <ul> 5454<li>int32x4_t vmlal_n_s16 (int32x4_t, int16x4_t, int16_t) 5455<br><em>Form of expected instruction(s):</em> <code>vmlal.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5456</ul> 5457 5458 <ul> 5459<li>int64x2_t vqdmlal_n_s32 (int64x2_t, int32x2_t, int32_t) 5460<br><em>Form of expected instruction(s):</em> <code>vqdmlal.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5461</ul> 5462 5463 <ul> 5464<li>int32x4_t vqdmlal_n_s16 (int32x4_t, int16x4_t, int16_t) 5465<br><em>Form of expected instruction(s):</em> <code>vqdmlal.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5466</ul> 5467 5468<h5 class="subsubsection">6.54.3.61 Vector multiply-subtract by scalar</h5> 5469 5470 <ul> 5471<li>float32x2_t vmls_n_f32 (float32x2_t, float32x2_t, float32_t) 5472<br><em>Form of expected instruction(s):</em> <code>vmls.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5473</ul> 5474 5475 <ul> 5476<li>uint32x2_t vmls_n_u32 (uint32x2_t, uint32x2_t, uint32_t) 5477<br><em>Form of expected instruction(s):</em> <code>vmls.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5478</ul> 5479 5480 <ul> 5481<li>uint16x4_t vmls_n_u16 (uint16x4_t, uint16x4_t, uint16_t) 5482<br><em>Form of expected instruction(s):</em> <code>vmls.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5483</ul> 5484 5485 <ul> 5486<li>int32x2_t vmls_n_s32 (int32x2_t, int32x2_t, int32_t) 5487<br><em>Form of expected instruction(s):</em> <code>vmls.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5488</ul> 5489 5490 <ul> 5491<li>int16x4_t vmls_n_s16 (int16x4_t, int16x4_t, int16_t) 5492<br><em>Form of expected instruction(s):</em> <code>vmls.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5493</ul> 5494 5495 <ul> 5496<li>float32x4_t vmlsq_n_f32 (float32x4_t, float32x4_t, float32_t) 5497<br><em>Form of expected instruction(s):</em> <code>vmls.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5498</ul> 5499 5500 <ul> 5501<li>uint32x4_t vmlsq_n_u32 (uint32x4_t, uint32x4_t, uint32_t) 5502<br><em>Form of expected instruction(s):</em> <code>vmls.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5503</ul> 5504 5505 <ul> 5506<li>uint16x8_t vmlsq_n_u16 (uint16x8_t, uint16x8_t, uint16_t) 5507<br><em>Form of expected instruction(s):</em> <code>vmls.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5508</ul> 5509 5510 <ul> 5511<li>int32x4_t vmlsq_n_s32 (int32x4_t, int32x4_t, int32_t) 5512<br><em>Form of expected instruction(s):</em> <code>vmls.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5513</ul> 5514 5515 <ul> 5516<li>int16x8_t vmlsq_n_s16 (int16x8_t, int16x8_t, int16_t) 5517<br><em>Form of expected instruction(s):</em> <code>vmls.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5518</ul> 5519 5520 <ul> 5521<li>uint64x2_t vmlsl_n_u32 (uint64x2_t, uint32x2_t, uint32_t) 5522<br><em>Form of expected instruction(s):</em> <code>vmlsl.u32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5523</ul> 5524 5525 <ul> 5526<li>uint32x4_t vmlsl_n_u16 (uint32x4_t, uint16x4_t, uint16_t) 5527<br><em>Form of expected instruction(s):</em> <code>vmlsl.u16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5528</ul> 5529 5530 <ul> 5531<li>int64x2_t vmlsl_n_s32 (int64x2_t, int32x2_t, int32_t) 5532<br><em>Form of expected instruction(s):</em> <code>vmlsl.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5533</ul> 5534 5535 <ul> 5536<li>int32x4_t vmlsl_n_s16 (int32x4_t, int16x4_t, int16_t) 5537<br><em>Form of expected instruction(s):</em> <code>vmlsl.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5538</ul> 5539 5540 <ul> 5541<li>int64x2_t vqdmlsl_n_s32 (int64x2_t, int32x2_t, int32_t) 5542<br><em>Form of expected instruction(s):</em> <code>vqdmlsl.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5543</ul> 5544 5545 <ul> 5546<li>int32x4_t vqdmlsl_n_s16 (int32x4_t, int16x4_t, int16_t) 5547<br><em>Form of expected instruction(s):</em> <code>vqdmlsl.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code> 5548</ul> 5549 5550<h5 class="subsubsection">6.54.3.62 Vector extract</h5> 5551 5552 <ul> 5553<li>uint32x2_t vext_u32 (uint32x2_t, uint32x2_t, const int) 5554<br><em>Form of expected instruction(s):</em> <code>vext.32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 5555</ul> 5556 5557 <ul> 5558<li>uint16x4_t vext_u16 (uint16x4_t, uint16x4_t, const int) 5559<br><em>Form of expected instruction(s):</em> <code>vext.16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 5560</ul> 5561 5562 <ul> 5563<li>uint8x8_t vext_u8 (uint8x8_t, uint8x8_t, const int) 5564<br><em>Form of expected instruction(s):</em> <code>vext.8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 5565</ul> 5566 5567 <ul> 5568<li>int32x2_t vext_s32 (int32x2_t, int32x2_t, const int) 5569<br><em>Form of expected instruction(s):</em> <code>vext.32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 5570</ul> 5571 5572 <ul> 5573<li>int16x4_t vext_s16 (int16x4_t, int16x4_t, const int) 5574<br><em>Form of expected instruction(s):</em> <code>vext.16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 5575</ul> 5576 5577 <ul> 5578<li>int8x8_t vext_s8 (int8x8_t, int8x8_t, const int) 5579<br><em>Form of expected instruction(s):</em> <code>vext.8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 5580</ul> 5581 5582 <ul> 5583<li>uint64x1_t vext_u64 (uint64x1_t, uint64x1_t, const int) 5584<br><em>Form of expected instruction(s):</em> <code>vext.64 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 5585</ul> 5586 5587 <ul> 5588<li>int64x1_t vext_s64 (int64x1_t, int64x1_t, const int) 5589<br><em>Form of expected instruction(s):</em> <code>vext.64 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 5590</ul> 5591 5592 <ul> 5593<li>float32x2_t vext_f32 (float32x2_t, float32x2_t, const int) 5594<br><em>Form of expected instruction(s):</em> <code>vext.32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 5595</ul> 5596 5597 <ul> 5598<li>poly16x4_t vext_p16 (poly16x4_t, poly16x4_t, const int) 5599<br><em>Form of expected instruction(s):</em> <code>vext.16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 5600</ul> 5601 5602 <ul> 5603<li>poly8x8_t vext_p8 (poly8x8_t, poly8x8_t, const int) 5604<br><em>Form of expected instruction(s):</em> <code>vext.8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var> 5605</ul> 5606 5607 <ul> 5608<li>uint32x4_t vextq_u32 (uint32x4_t, uint32x4_t, const int) 5609<br><em>Form of expected instruction(s):</em> <code>vext.32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 5610</ul> 5611 5612 <ul> 5613<li>uint16x8_t vextq_u16 (uint16x8_t, uint16x8_t, const int) 5614<br><em>Form of expected instruction(s):</em> <code>vext.16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 5615</ul> 5616 5617 <ul> 5618<li>uint8x16_t vextq_u8 (uint8x16_t, uint8x16_t, const int) 5619<br><em>Form of expected instruction(s):</em> <code>vext.8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 5620</ul> 5621 5622 <ul> 5623<li>int32x4_t vextq_s32 (int32x4_t, int32x4_t, const int) 5624<br><em>Form of expected instruction(s):</em> <code>vext.32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 5625</ul> 5626 5627 <ul> 5628<li>int16x8_t vextq_s16 (int16x8_t, int16x8_t, const int) 5629<br><em>Form of expected instruction(s):</em> <code>vext.16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 5630</ul> 5631 5632 <ul> 5633<li>int8x16_t vextq_s8 (int8x16_t, int8x16_t, const int) 5634<br><em>Form of expected instruction(s):</em> <code>vext.8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 5635</ul> 5636 5637 <ul> 5638<li>uint64x2_t vextq_u64 (uint64x2_t, uint64x2_t, const int) 5639<br><em>Form of expected instruction(s):</em> <code>vext.64 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 5640</ul> 5641 5642 <ul> 5643<li>int64x2_t vextq_s64 (int64x2_t, int64x2_t, const int) 5644<br><em>Form of expected instruction(s):</em> <code>vext.64 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 5645</ul> 5646 5647 <ul> 5648<li>float32x4_t vextq_f32 (float32x4_t, float32x4_t, const int) 5649<br><em>Form of expected instruction(s):</em> <code>vext.32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 5650</ul> 5651 5652 <ul> 5653<li>poly16x8_t vextq_p16 (poly16x8_t, poly16x8_t, const int) 5654<br><em>Form of expected instruction(s):</em> <code>vext.16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 5655</ul> 5656 5657 <ul> 5658<li>poly8x16_t vextq_p8 (poly8x16_t, poly8x16_t, const int) 5659<br><em>Form of expected instruction(s):</em> <code>vext.8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var> 5660</ul> 5661 5662<h5 class="subsubsection">6.54.3.63 Reverse elements</h5> 5663 5664 <ul> 5665<li>uint32x2_t vrev64_u32 (uint32x2_t) 5666<br><em>Form of expected instruction(s):</em> <code>vrev64.32 </code><var>d0</var><code>, </code><var>d0</var> 5667</ul> 5668 5669 <ul> 5670<li>uint16x4_t vrev64_u16 (uint16x4_t) 5671<br><em>Form of expected instruction(s):</em> <code>vrev64.16 </code><var>d0</var><code>, </code><var>d0</var> 5672</ul> 5673 5674 <ul> 5675<li>uint8x8_t vrev64_u8 (uint8x8_t) 5676<br><em>Form of expected instruction(s):</em> <code>vrev64.8 </code><var>d0</var><code>, </code><var>d0</var> 5677</ul> 5678 5679 <ul> 5680<li>int32x2_t vrev64_s32 (int32x2_t) 5681<br><em>Form of expected instruction(s):</em> <code>vrev64.32 </code><var>d0</var><code>, </code><var>d0</var> 5682</ul> 5683 5684 <ul> 5685<li>int16x4_t vrev64_s16 (int16x4_t) 5686<br><em>Form of expected instruction(s):</em> <code>vrev64.16 </code><var>d0</var><code>, </code><var>d0</var> 5687</ul> 5688 5689 <ul> 5690<li>int8x8_t vrev64_s8 (int8x8_t) 5691<br><em>Form of expected instruction(s):</em> <code>vrev64.8 </code><var>d0</var><code>, </code><var>d0</var> 5692</ul> 5693 5694 <ul> 5695<li>float32x2_t vrev64_f32 (float32x2_t) 5696<br><em>Form of expected instruction(s):</em> <code>vrev64.32 </code><var>d0</var><code>, </code><var>d0</var> 5697</ul> 5698 5699 <ul> 5700<li>poly16x4_t vrev64_p16 (poly16x4_t) 5701<br><em>Form of expected instruction(s):</em> <code>vrev64.16 </code><var>d0</var><code>, </code><var>d0</var> 5702</ul> 5703 5704 <ul> 5705<li>poly8x8_t vrev64_p8 (poly8x8_t) 5706<br><em>Form of expected instruction(s):</em> <code>vrev64.8 </code><var>d0</var><code>, </code><var>d0</var> 5707</ul> 5708 5709 <ul> 5710<li>uint32x4_t vrev64q_u32 (uint32x4_t) 5711<br><em>Form of expected instruction(s):</em> <code>vrev64.32 </code><var>q0</var><code>, </code><var>q0</var> 5712</ul> 5713 5714 <ul> 5715<li>uint16x8_t vrev64q_u16 (uint16x8_t) 5716<br><em>Form of expected instruction(s):</em> <code>vrev64.16 </code><var>q0</var><code>, </code><var>q0</var> 5717</ul> 5718 5719 <ul> 5720<li>uint8x16_t vrev64q_u8 (uint8x16_t) 5721<br><em>Form of expected instruction(s):</em> <code>vrev64.8 </code><var>q0</var><code>, </code><var>q0</var> 5722</ul> 5723 5724 <ul> 5725<li>int32x4_t vrev64q_s32 (int32x4_t) 5726<br><em>Form of expected instruction(s):</em> <code>vrev64.32 </code><var>q0</var><code>, </code><var>q0</var> 5727</ul> 5728 5729 <ul> 5730<li>int16x8_t vrev64q_s16 (int16x8_t) 5731<br><em>Form of expected instruction(s):</em> <code>vrev64.16 </code><var>q0</var><code>, </code><var>q0</var> 5732</ul> 5733 5734 <ul> 5735<li>int8x16_t vrev64q_s8 (int8x16_t) 5736<br><em>Form of expected instruction(s):</em> <code>vrev64.8 </code><var>q0</var><code>, </code><var>q0</var> 5737</ul> 5738 5739 <ul> 5740<li>float32x4_t vrev64q_f32 (float32x4_t) 5741<br><em>Form of expected instruction(s):</em> <code>vrev64.32 </code><var>q0</var><code>, </code><var>q0</var> 5742</ul> 5743 5744 <ul> 5745<li>poly16x8_t vrev64q_p16 (poly16x8_t) 5746<br><em>Form of expected instruction(s):</em> <code>vrev64.16 </code><var>q0</var><code>, </code><var>q0</var> 5747</ul> 5748 5749 <ul> 5750<li>poly8x16_t vrev64q_p8 (poly8x16_t) 5751<br><em>Form of expected instruction(s):</em> <code>vrev64.8 </code><var>q0</var><code>, </code><var>q0</var> 5752</ul> 5753 5754 <ul> 5755<li>uint16x4_t vrev32_u16 (uint16x4_t) 5756<br><em>Form of expected instruction(s):</em> <code>vrev32.16 </code><var>d0</var><code>, </code><var>d0</var> 5757</ul> 5758 5759 <ul> 5760<li>int16x4_t vrev32_s16 (int16x4_t) 5761<br><em>Form of expected instruction(s):</em> <code>vrev32.16 </code><var>d0</var><code>, </code><var>d0</var> 5762</ul> 5763 5764 <ul> 5765<li>uint8x8_t vrev32_u8 (uint8x8_t) 5766<br><em>Form of expected instruction(s):</em> <code>vrev32.8 </code><var>d0</var><code>, </code><var>d0</var> 5767</ul> 5768 5769 <ul> 5770<li>int8x8_t vrev32_s8 (int8x8_t) 5771<br><em>Form of expected instruction(s):</em> <code>vrev32.8 </code><var>d0</var><code>, </code><var>d0</var> 5772</ul> 5773 5774 <ul> 5775<li>poly16x4_t vrev32_p16 (poly16x4_t) 5776<br><em>Form of expected instruction(s):</em> <code>vrev32.16 </code><var>d0</var><code>, </code><var>d0</var> 5777</ul> 5778 5779 <ul> 5780<li>poly8x8_t vrev32_p8 (poly8x8_t) 5781<br><em>Form of expected instruction(s):</em> <code>vrev32.8 </code><var>d0</var><code>, </code><var>d0</var> 5782</ul> 5783 5784 <ul> 5785<li>uint16x8_t vrev32q_u16 (uint16x8_t) 5786<br><em>Form of expected instruction(s):</em> <code>vrev32.16 </code><var>q0</var><code>, </code><var>q0</var> 5787</ul> 5788 5789 <ul> 5790<li>int16x8_t vrev32q_s16 (int16x8_t) 5791<br><em>Form of expected instruction(s):</em> <code>vrev32.16 </code><var>q0</var><code>, </code><var>q0</var> 5792</ul> 5793 5794 <ul> 5795<li>uint8x16_t vrev32q_u8 (uint8x16_t) 5796<br><em>Form of expected instruction(s):</em> <code>vrev32.8 </code><var>q0</var><code>, </code><var>q0</var> 5797</ul> 5798 5799 <ul> 5800<li>int8x16_t vrev32q_s8 (int8x16_t) 5801<br><em>Form of expected instruction(s):</em> <code>vrev32.8 </code><var>q0</var><code>, </code><var>q0</var> 5802</ul> 5803 5804 <ul> 5805<li>poly16x8_t vrev32q_p16 (poly16x8_t) 5806<br><em>Form of expected instruction(s):</em> <code>vrev32.16 </code><var>q0</var><code>, </code><var>q0</var> 5807</ul> 5808 5809 <ul> 5810<li>poly8x16_t vrev32q_p8 (poly8x16_t) 5811<br><em>Form of expected instruction(s):</em> <code>vrev32.8 </code><var>q0</var><code>, </code><var>q0</var> 5812</ul> 5813 5814 <ul> 5815<li>uint8x8_t vrev16_u8 (uint8x8_t) 5816<br><em>Form of expected instruction(s):</em> <code>vrev16.8 </code><var>d0</var><code>, </code><var>d0</var> 5817</ul> 5818 5819 <ul> 5820<li>int8x8_t vrev16_s8 (int8x8_t) 5821<br><em>Form of expected instruction(s):</em> <code>vrev16.8 </code><var>d0</var><code>, </code><var>d0</var> 5822</ul> 5823 5824 <ul> 5825<li>poly8x8_t vrev16_p8 (poly8x8_t) 5826<br><em>Form of expected instruction(s):</em> <code>vrev16.8 </code><var>d0</var><code>, </code><var>d0</var> 5827</ul> 5828 5829 <ul> 5830<li>uint8x16_t vrev16q_u8 (uint8x16_t) 5831<br><em>Form of expected instruction(s):</em> <code>vrev16.8 </code><var>q0</var><code>, </code><var>q0</var> 5832</ul> 5833 5834 <ul> 5835<li>int8x16_t vrev16q_s8 (int8x16_t) 5836<br><em>Form of expected instruction(s):</em> <code>vrev16.8 </code><var>q0</var><code>, </code><var>q0</var> 5837</ul> 5838 5839 <ul> 5840<li>poly8x16_t vrev16q_p8 (poly8x16_t) 5841<br><em>Form of expected instruction(s):</em> <code>vrev16.8 </code><var>q0</var><code>, </code><var>q0</var> 5842</ul> 5843 5844<h5 class="subsubsection">6.54.3.64 Bit selection</h5> 5845 5846 <ul> 5847<li>uint32x2_t vbsl_u32 (uint32x2_t, uint32x2_t, uint32x2_t) 5848<br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbit </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbif </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 5849</ul> 5850 5851 <ul> 5852<li>uint16x4_t vbsl_u16 (uint16x4_t, uint16x4_t, uint16x4_t) 5853<br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbit </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbif </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 5854</ul> 5855 5856 <ul> 5857<li>uint8x8_t vbsl_u8 (uint8x8_t, uint8x8_t, uint8x8_t) 5858<br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbit </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbif </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 5859</ul> 5860 5861 <ul> 5862<li>int32x2_t vbsl_s32 (uint32x2_t, int32x2_t, int32x2_t) 5863<br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbit </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbif </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 5864</ul> 5865 5866 <ul> 5867<li>int16x4_t vbsl_s16 (uint16x4_t, int16x4_t, int16x4_t) 5868<br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbit </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbif </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 5869</ul> 5870 5871 <ul> 5872<li>int8x8_t vbsl_s8 (uint8x8_t, int8x8_t, int8x8_t) 5873<br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbit </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbif </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 5874</ul> 5875 5876 <ul> 5877<li>uint64x1_t vbsl_u64 (uint64x1_t, uint64x1_t, uint64x1_t) 5878<br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbit </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbif </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 5879</ul> 5880 5881 <ul> 5882<li>int64x1_t vbsl_s64 (uint64x1_t, int64x1_t, int64x1_t) 5883<br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbit </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbif </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 5884</ul> 5885 5886 <ul> 5887<li>float32x2_t vbsl_f32 (uint32x2_t, float32x2_t, float32x2_t) 5888<br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbit </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbif </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 5889</ul> 5890 5891 <ul> 5892<li>poly16x4_t vbsl_p16 (uint16x4_t, poly16x4_t, poly16x4_t) 5893<br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbit </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbif </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 5894</ul> 5895 5896 <ul> 5897<li>poly8x8_t vbsl_p8 (uint8x8_t, poly8x8_t, poly8x8_t) 5898<br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbit </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbif </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 5899</ul> 5900 5901 <ul> 5902<li>uint32x4_t vbslq_u32 (uint32x4_t, uint32x4_t, uint32x4_t) 5903<br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbit </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbif </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 5904</ul> 5905 5906 <ul> 5907<li>uint16x8_t vbslq_u16 (uint16x8_t, uint16x8_t, uint16x8_t) 5908<br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbit </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbif </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 5909</ul> 5910 5911 <ul> 5912<li>uint8x16_t vbslq_u8 (uint8x16_t, uint8x16_t, uint8x16_t) 5913<br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbit </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbif </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 5914</ul> 5915 5916 <ul> 5917<li>int32x4_t vbslq_s32 (uint32x4_t, int32x4_t, int32x4_t) 5918<br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbit </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbif </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 5919</ul> 5920 5921 <ul> 5922<li>int16x8_t vbslq_s16 (uint16x8_t, int16x8_t, int16x8_t) 5923<br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbit </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbif </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 5924</ul> 5925 5926 <ul> 5927<li>int8x16_t vbslq_s8 (uint8x16_t, int8x16_t, int8x16_t) 5928<br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbit </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbif </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 5929</ul> 5930 5931 <ul> 5932<li>uint64x2_t vbslq_u64 (uint64x2_t, uint64x2_t, uint64x2_t) 5933<br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbit </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbif </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 5934</ul> 5935 5936 <ul> 5937<li>int64x2_t vbslq_s64 (uint64x2_t, int64x2_t, int64x2_t) 5938<br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbit </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbif </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 5939</ul> 5940 5941 <ul> 5942<li>float32x4_t vbslq_f32 (uint32x4_t, float32x4_t, float32x4_t) 5943<br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbit </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbif </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 5944</ul> 5945 5946 <ul> 5947<li>poly16x8_t vbslq_p16 (uint16x8_t, poly16x8_t, poly16x8_t) 5948<br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbit </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbif </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 5949</ul> 5950 5951 <ul> 5952<li>poly8x16_t vbslq_p8 (uint8x16_t, poly8x16_t, poly8x16_t) 5953<br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbit </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbif </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 5954</ul> 5955 5956<h5 class="subsubsection">6.54.3.65 Transpose elements</h5> 5957 5958 <ul> 5959<li>uint32x2x2_t vtrn_u32 (uint32x2_t, uint32x2_t) 5960<br><em>Form of expected instruction(s):</em> <code>vtrn.32 </code><var>d0</var><code>, </code><var>d1</var> 5961</ul> 5962 5963 <ul> 5964<li>uint16x4x2_t vtrn_u16 (uint16x4_t, uint16x4_t) 5965<br><em>Form of expected instruction(s):</em> <code>vtrn.16 </code><var>d0</var><code>, </code><var>d1</var> 5966</ul> 5967 5968 <ul> 5969<li>uint8x8x2_t vtrn_u8 (uint8x8_t, uint8x8_t) 5970<br><em>Form of expected instruction(s):</em> <code>vtrn.8 </code><var>d0</var><code>, </code><var>d1</var> 5971</ul> 5972 5973 <ul> 5974<li>int32x2x2_t vtrn_s32 (int32x2_t, int32x2_t) 5975<br><em>Form of expected instruction(s):</em> <code>vtrn.32 </code><var>d0</var><code>, </code><var>d1</var> 5976</ul> 5977 5978 <ul> 5979<li>int16x4x2_t vtrn_s16 (int16x4_t, int16x4_t) 5980<br><em>Form of expected instruction(s):</em> <code>vtrn.16 </code><var>d0</var><code>, </code><var>d1</var> 5981</ul> 5982 5983 <ul> 5984<li>int8x8x2_t vtrn_s8 (int8x8_t, int8x8_t) 5985<br><em>Form of expected instruction(s):</em> <code>vtrn.8 </code><var>d0</var><code>, </code><var>d1</var> 5986</ul> 5987 5988 <ul> 5989<li>float32x2x2_t vtrn_f32 (float32x2_t, float32x2_t) 5990<br><em>Form of expected instruction(s):</em> <code>vtrn.32 </code><var>d0</var><code>, </code><var>d1</var> 5991</ul> 5992 5993 <ul> 5994<li>poly16x4x2_t vtrn_p16 (poly16x4_t, poly16x4_t) 5995<br><em>Form of expected instruction(s):</em> <code>vtrn.16 </code><var>d0</var><code>, </code><var>d1</var> 5996</ul> 5997 5998 <ul> 5999<li>poly8x8x2_t vtrn_p8 (poly8x8_t, poly8x8_t) 6000<br><em>Form of expected instruction(s):</em> <code>vtrn.8 </code><var>d0</var><code>, </code><var>d1</var> 6001</ul> 6002 6003 <ul> 6004<li>uint32x4x2_t vtrnq_u32 (uint32x4_t, uint32x4_t) 6005<br><em>Form of expected instruction(s):</em> <code>vtrn.32 </code><var>q0</var><code>, </code><var>q1</var> 6006</ul> 6007 6008 <ul> 6009<li>uint16x8x2_t vtrnq_u16 (uint16x8_t, uint16x8_t) 6010<br><em>Form of expected instruction(s):</em> <code>vtrn.16 </code><var>q0</var><code>, </code><var>q1</var> 6011</ul> 6012 6013 <ul> 6014<li>uint8x16x2_t vtrnq_u8 (uint8x16_t, uint8x16_t) 6015<br><em>Form of expected instruction(s):</em> <code>vtrn.8 </code><var>q0</var><code>, </code><var>q1</var> 6016</ul> 6017 6018 <ul> 6019<li>int32x4x2_t vtrnq_s32 (int32x4_t, int32x4_t) 6020<br><em>Form of expected instruction(s):</em> <code>vtrn.32 </code><var>q0</var><code>, </code><var>q1</var> 6021</ul> 6022 6023 <ul> 6024<li>int16x8x2_t vtrnq_s16 (int16x8_t, int16x8_t) 6025<br><em>Form of expected instruction(s):</em> <code>vtrn.16 </code><var>q0</var><code>, </code><var>q1</var> 6026</ul> 6027 6028 <ul> 6029<li>int8x16x2_t vtrnq_s8 (int8x16_t, int8x16_t) 6030<br><em>Form of expected instruction(s):</em> <code>vtrn.8 </code><var>q0</var><code>, </code><var>q1</var> 6031</ul> 6032 6033 <ul> 6034<li>float32x4x2_t vtrnq_f32 (float32x4_t, float32x4_t) 6035<br><em>Form of expected instruction(s):</em> <code>vtrn.32 </code><var>q0</var><code>, </code><var>q1</var> 6036</ul> 6037 6038 <ul> 6039<li>poly16x8x2_t vtrnq_p16 (poly16x8_t, poly16x8_t) 6040<br><em>Form of expected instruction(s):</em> <code>vtrn.16 </code><var>q0</var><code>, </code><var>q1</var> 6041</ul> 6042 6043 <ul> 6044<li>poly8x16x2_t vtrnq_p8 (poly8x16_t, poly8x16_t) 6045<br><em>Form of expected instruction(s):</em> <code>vtrn.8 </code><var>q0</var><code>, </code><var>q1</var> 6046</ul> 6047 6048<h5 class="subsubsection">6.54.3.66 Zip elements</h5> 6049 6050 <ul> 6051<li>uint32x2x2_t vzip_u32 (uint32x2_t, uint32x2_t) 6052<br><em>Form of expected instruction(s):</em> <code>vzip.32 </code><var>d0</var><code>, </code><var>d1</var> 6053</ul> 6054 6055 <ul> 6056<li>uint16x4x2_t vzip_u16 (uint16x4_t, uint16x4_t) 6057<br><em>Form of expected instruction(s):</em> <code>vzip.16 </code><var>d0</var><code>, </code><var>d1</var> 6058</ul> 6059 6060 <ul> 6061<li>uint8x8x2_t vzip_u8 (uint8x8_t, uint8x8_t) 6062<br><em>Form of expected instruction(s):</em> <code>vzip.8 </code><var>d0</var><code>, </code><var>d1</var> 6063</ul> 6064 6065 <ul> 6066<li>int32x2x2_t vzip_s32 (int32x2_t, int32x2_t) 6067<br><em>Form of expected instruction(s):</em> <code>vzip.32 </code><var>d0</var><code>, </code><var>d1</var> 6068</ul> 6069 6070 <ul> 6071<li>int16x4x2_t vzip_s16 (int16x4_t, int16x4_t) 6072<br><em>Form of expected instruction(s):</em> <code>vzip.16 </code><var>d0</var><code>, </code><var>d1</var> 6073</ul> 6074 6075 <ul> 6076<li>int8x8x2_t vzip_s8 (int8x8_t, int8x8_t) 6077<br><em>Form of expected instruction(s):</em> <code>vzip.8 </code><var>d0</var><code>, </code><var>d1</var> 6078</ul> 6079 6080 <ul> 6081<li>float32x2x2_t vzip_f32 (float32x2_t, float32x2_t) 6082<br><em>Form of expected instruction(s):</em> <code>vzip.32 </code><var>d0</var><code>, </code><var>d1</var> 6083</ul> 6084 6085 <ul> 6086<li>poly16x4x2_t vzip_p16 (poly16x4_t, poly16x4_t) 6087<br><em>Form of expected instruction(s):</em> <code>vzip.16 </code><var>d0</var><code>, </code><var>d1</var> 6088</ul> 6089 6090 <ul> 6091<li>poly8x8x2_t vzip_p8 (poly8x8_t, poly8x8_t) 6092<br><em>Form of expected instruction(s):</em> <code>vzip.8 </code><var>d0</var><code>, </code><var>d1</var> 6093</ul> 6094 6095 <ul> 6096<li>uint32x4x2_t vzipq_u32 (uint32x4_t, uint32x4_t) 6097<br><em>Form of expected instruction(s):</em> <code>vzip.32 </code><var>q0</var><code>, </code><var>q1</var> 6098</ul> 6099 6100 <ul> 6101<li>uint16x8x2_t vzipq_u16 (uint16x8_t, uint16x8_t) 6102<br><em>Form of expected instruction(s):</em> <code>vzip.16 </code><var>q0</var><code>, </code><var>q1</var> 6103</ul> 6104 6105 <ul> 6106<li>uint8x16x2_t vzipq_u8 (uint8x16_t, uint8x16_t) 6107<br><em>Form of expected instruction(s):</em> <code>vzip.8 </code><var>q0</var><code>, </code><var>q1</var> 6108</ul> 6109 6110 <ul> 6111<li>int32x4x2_t vzipq_s32 (int32x4_t, int32x4_t) 6112<br><em>Form of expected instruction(s):</em> <code>vzip.32 </code><var>q0</var><code>, </code><var>q1</var> 6113</ul> 6114 6115 <ul> 6116<li>int16x8x2_t vzipq_s16 (int16x8_t, int16x8_t) 6117<br><em>Form of expected instruction(s):</em> <code>vzip.16 </code><var>q0</var><code>, </code><var>q1</var> 6118</ul> 6119 6120 <ul> 6121<li>int8x16x2_t vzipq_s8 (int8x16_t, int8x16_t) 6122<br><em>Form of expected instruction(s):</em> <code>vzip.8 </code><var>q0</var><code>, </code><var>q1</var> 6123</ul> 6124 6125 <ul> 6126<li>float32x4x2_t vzipq_f32 (float32x4_t, float32x4_t) 6127<br><em>Form of expected instruction(s):</em> <code>vzip.32 </code><var>q0</var><code>, </code><var>q1</var> 6128</ul> 6129 6130 <ul> 6131<li>poly16x8x2_t vzipq_p16 (poly16x8_t, poly16x8_t) 6132<br><em>Form of expected instruction(s):</em> <code>vzip.16 </code><var>q0</var><code>, </code><var>q1</var> 6133</ul> 6134 6135 <ul> 6136<li>poly8x16x2_t vzipq_p8 (poly8x16_t, poly8x16_t) 6137<br><em>Form of expected instruction(s):</em> <code>vzip.8 </code><var>q0</var><code>, </code><var>q1</var> 6138</ul> 6139 6140<h5 class="subsubsection">6.54.3.67 Unzip elements</h5> 6141 6142 <ul> 6143<li>uint32x2x2_t vuzp_u32 (uint32x2_t, uint32x2_t) 6144<br><em>Form of expected instruction(s):</em> <code>vuzp.32 </code><var>d0</var><code>, </code><var>d1</var> 6145</ul> 6146 6147 <ul> 6148<li>uint16x4x2_t vuzp_u16 (uint16x4_t, uint16x4_t) 6149<br><em>Form of expected instruction(s):</em> <code>vuzp.16 </code><var>d0</var><code>, </code><var>d1</var> 6150</ul> 6151 6152 <ul> 6153<li>uint8x8x2_t vuzp_u8 (uint8x8_t, uint8x8_t) 6154<br><em>Form of expected instruction(s):</em> <code>vuzp.8 </code><var>d0</var><code>, </code><var>d1</var> 6155</ul> 6156 6157 <ul> 6158<li>int32x2x2_t vuzp_s32 (int32x2_t, int32x2_t) 6159<br><em>Form of expected instruction(s):</em> <code>vuzp.32 </code><var>d0</var><code>, </code><var>d1</var> 6160</ul> 6161 6162 <ul> 6163<li>int16x4x2_t vuzp_s16 (int16x4_t, int16x4_t) 6164<br><em>Form of expected instruction(s):</em> <code>vuzp.16 </code><var>d0</var><code>, </code><var>d1</var> 6165</ul> 6166 6167 <ul> 6168<li>int8x8x2_t vuzp_s8 (int8x8_t, int8x8_t) 6169<br><em>Form of expected instruction(s):</em> <code>vuzp.8 </code><var>d0</var><code>, </code><var>d1</var> 6170</ul> 6171 6172 <ul> 6173<li>float32x2x2_t vuzp_f32 (float32x2_t, float32x2_t) 6174<br><em>Form of expected instruction(s):</em> <code>vuzp.32 </code><var>d0</var><code>, </code><var>d1</var> 6175</ul> 6176 6177 <ul> 6178<li>poly16x4x2_t vuzp_p16 (poly16x4_t, poly16x4_t) 6179<br><em>Form of expected instruction(s):</em> <code>vuzp.16 </code><var>d0</var><code>, </code><var>d1</var> 6180</ul> 6181 6182 <ul> 6183<li>poly8x8x2_t vuzp_p8 (poly8x8_t, poly8x8_t) 6184<br><em>Form of expected instruction(s):</em> <code>vuzp.8 </code><var>d0</var><code>, </code><var>d1</var> 6185</ul> 6186 6187 <ul> 6188<li>uint32x4x2_t vuzpq_u32 (uint32x4_t, uint32x4_t) 6189<br><em>Form of expected instruction(s):</em> <code>vuzp.32 </code><var>q0</var><code>, </code><var>q1</var> 6190</ul> 6191 6192 <ul> 6193<li>uint16x8x2_t vuzpq_u16 (uint16x8_t, uint16x8_t) 6194<br><em>Form of expected instruction(s):</em> <code>vuzp.16 </code><var>q0</var><code>, </code><var>q1</var> 6195</ul> 6196 6197 <ul> 6198<li>uint8x16x2_t vuzpq_u8 (uint8x16_t, uint8x16_t) 6199<br><em>Form of expected instruction(s):</em> <code>vuzp.8 </code><var>q0</var><code>, </code><var>q1</var> 6200</ul> 6201 6202 <ul> 6203<li>int32x4x2_t vuzpq_s32 (int32x4_t, int32x4_t) 6204<br><em>Form of expected instruction(s):</em> <code>vuzp.32 </code><var>q0</var><code>, </code><var>q1</var> 6205</ul> 6206 6207 <ul> 6208<li>int16x8x2_t vuzpq_s16 (int16x8_t, int16x8_t) 6209<br><em>Form of expected instruction(s):</em> <code>vuzp.16 </code><var>q0</var><code>, </code><var>q1</var> 6210</ul> 6211 6212 <ul> 6213<li>int8x16x2_t vuzpq_s8 (int8x16_t, int8x16_t) 6214<br><em>Form of expected instruction(s):</em> <code>vuzp.8 </code><var>q0</var><code>, </code><var>q1</var> 6215</ul> 6216 6217 <ul> 6218<li>float32x4x2_t vuzpq_f32 (float32x4_t, float32x4_t) 6219<br><em>Form of expected instruction(s):</em> <code>vuzp.32 </code><var>q0</var><code>, </code><var>q1</var> 6220</ul> 6221 6222 <ul> 6223<li>poly16x8x2_t vuzpq_p16 (poly16x8_t, poly16x8_t) 6224<br><em>Form of expected instruction(s):</em> <code>vuzp.16 </code><var>q0</var><code>, </code><var>q1</var> 6225</ul> 6226 6227 <ul> 6228<li>poly8x16x2_t vuzpq_p8 (poly8x16_t, poly8x16_t) 6229<br><em>Form of expected instruction(s):</em> <code>vuzp.8 </code><var>q0</var><code>, </code><var>q1</var> 6230</ul> 6231 6232<h5 class="subsubsection">6.54.3.68 Element/structure loads, VLD1 variants</h5> 6233 6234 <ul> 6235<li>uint32x2_t vld1_u32 (const uint32_t *) 6236<br><em>Form of expected instruction(s):</em> <code>vld1.32 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code> 6237</ul> 6238 6239 <ul> 6240<li>uint16x4_t vld1_u16 (const uint16_t *) 6241<br><em>Form of expected instruction(s):</em> <code>vld1.16 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code> 6242</ul> 6243 6244 <ul> 6245<li>uint8x8_t vld1_u8 (const uint8_t *) 6246<br><em>Form of expected instruction(s):</em> <code>vld1.8 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code> 6247</ul> 6248 6249 <ul> 6250<li>int32x2_t vld1_s32 (const int32_t *) 6251<br><em>Form of expected instruction(s):</em> <code>vld1.32 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code> 6252</ul> 6253 6254 <ul> 6255<li>int16x4_t vld1_s16 (const int16_t *) 6256<br><em>Form of expected instruction(s):</em> <code>vld1.16 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code> 6257</ul> 6258 6259 <ul> 6260<li>int8x8_t vld1_s8 (const int8_t *) 6261<br><em>Form of expected instruction(s):</em> <code>vld1.8 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code> 6262</ul> 6263 6264 <ul> 6265<li>uint64x1_t vld1_u64 (const uint64_t *) 6266<br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code> 6267</ul> 6268 6269 <ul> 6270<li>int64x1_t vld1_s64 (const int64_t *) 6271<br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code> 6272</ul> 6273 6274 <ul> 6275<li>float32x2_t vld1_f32 (const float32_t *) 6276<br><em>Form of expected instruction(s):</em> <code>vld1.32 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code> 6277</ul> 6278 6279 <ul> 6280<li>poly16x4_t vld1_p16 (const poly16_t *) 6281<br><em>Form of expected instruction(s):</em> <code>vld1.16 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code> 6282</ul> 6283 6284 <ul> 6285<li>poly8x8_t vld1_p8 (const poly8_t *) 6286<br><em>Form of expected instruction(s):</em> <code>vld1.8 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code> 6287</ul> 6288 6289 <ul> 6290<li>uint32x4_t vld1q_u32 (const uint32_t *) 6291<br><em>Form of expected instruction(s):</em> <code>vld1.32 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6292</ul> 6293 6294 <ul> 6295<li>uint16x8_t vld1q_u16 (const uint16_t *) 6296<br><em>Form of expected instruction(s):</em> <code>vld1.16 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6297</ul> 6298 6299 <ul> 6300<li>uint8x16_t vld1q_u8 (const uint8_t *) 6301<br><em>Form of expected instruction(s):</em> <code>vld1.8 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6302</ul> 6303 6304 <ul> 6305<li>int32x4_t vld1q_s32 (const int32_t *) 6306<br><em>Form of expected instruction(s):</em> <code>vld1.32 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6307</ul> 6308 6309 <ul> 6310<li>int16x8_t vld1q_s16 (const int16_t *) 6311<br><em>Form of expected instruction(s):</em> <code>vld1.16 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6312</ul> 6313 6314 <ul> 6315<li>int8x16_t vld1q_s8 (const int8_t *) 6316<br><em>Form of expected instruction(s):</em> <code>vld1.8 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6317</ul> 6318 6319 <ul> 6320<li>uint64x2_t vld1q_u64 (const uint64_t *) 6321<br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6322</ul> 6323 6324 <ul> 6325<li>int64x2_t vld1q_s64 (const int64_t *) 6326<br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6327</ul> 6328 6329 <ul> 6330<li>float32x4_t vld1q_f32 (const float32_t *) 6331<br><em>Form of expected instruction(s):</em> <code>vld1.32 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6332</ul> 6333 6334 <ul> 6335<li>poly16x8_t vld1q_p16 (const poly16_t *) 6336<br><em>Form of expected instruction(s):</em> <code>vld1.16 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6337</ul> 6338 6339 <ul> 6340<li>poly8x16_t vld1q_p8 (const poly8_t *) 6341<br><em>Form of expected instruction(s):</em> <code>vld1.8 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6342</ul> 6343 6344 <ul> 6345<li>uint32x2_t vld1_lane_u32 (const uint32_t *, uint32x2_t, const int) 6346<br><em>Form of expected instruction(s):</em> <code>vld1.32 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6347</ul> 6348 6349 <ul> 6350<li>uint16x4_t vld1_lane_u16 (const uint16_t *, uint16x4_t, const int) 6351<br><em>Form of expected instruction(s):</em> <code>vld1.16 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6352</ul> 6353 6354 <ul> 6355<li>uint8x8_t vld1_lane_u8 (const uint8_t *, uint8x8_t, const int) 6356<br><em>Form of expected instruction(s):</em> <code>vld1.8 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6357</ul> 6358 6359 <ul> 6360<li>int32x2_t vld1_lane_s32 (const int32_t *, int32x2_t, const int) 6361<br><em>Form of expected instruction(s):</em> <code>vld1.32 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6362</ul> 6363 6364 <ul> 6365<li>int16x4_t vld1_lane_s16 (const int16_t *, int16x4_t, const int) 6366<br><em>Form of expected instruction(s):</em> <code>vld1.16 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6367</ul> 6368 6369 <ul> 6370<li>int8x8_t vld1_lane_s8 (const int8_t *, int8x8_t, const int) 6371<br><em>Form of expected instruction(s):</em> <code>vld1.8 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6372</ul> 6373 6374 <ul> 6375<li>float32x2_t vld1_lane_f32 (const float32_t *, float32x2_t, const int) 6376<br><em>Form of expected instruction(s):</em> <code>vld1.32 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6377</ul> 6378 6379 <ul> 6380<li>poly16x4_t vld1_lane_p16 (const poly16_t *, poly16x4_t, const int) 6381<br><em>Form of expected instruction(s):</em> <code>vld1.16 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6382</ul> 6383 6384 <ul> 6385<li>poly8x8_t vld1_lane_p8 (const poly8_t *, poly8x8_t, const int) 6386<br><em>Form of expected instruction(s):</em> <code>vld1.8 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6387</ul> 6388 6389 <ul> 6390<li>uint64x1_t vld1_lane_u64 (const uint64_t *, uint64x1_t, const int) 6391<br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code> 6392</ul> 6393 6394 <ul> 6395<li>int64x1_t vld1_lane_s64 (const int64_t *, int64x1_t, const int) 6396<br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code> 6397</ul> 6398 6399 <ul> 6400<li>uint32x4_t vld1q_lane_u32 (const uint32_t *, uint32x4_t, const int) 6401<br><em>Form of expected instruction(s):</em> <code>vld1.32 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6402</ul> 6403 6404 <ul> 6405<li>uint16x8_t vld1q_lane_u16 (const uint16_t *, uint16x8_t, const int) 6406<br><em>Form of expected instruction(s):</em> <code>vld1.16 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6407</ul> 6408 6409 <ul> 6410<li>uint8x16_t vld1q_lane_u8 (const uint8_t *, uint8x16_t, const int) 6411<br><em>Form of expected instruction(s):</em> <code>vld1.8 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6412</ul> 6413 6414 <ul> 6415<li>int32x4_t vld1q_lane_s32 (const int32_t *, int32x4_t, const int) 6416<br><em>Form of expected instruction(s):</em> <code>vld1.32 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6417</ul> 6418 6419 <ul> 6420<li>int16x8_t vld1q_lane_s16 (const int16_t *, int16x8_t, const int) 6421<br><em>Form of expected instruction(s):</em> <code>vld1.16 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6422</ul> 6423 6424 <ul> 6425<li>int8x16_t vld1q_lane_s8 (const int8_t *, int8x16_t, const int) 6426<br><em>Form of expected instruction(s):</em> <code>vld1.8 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6427</ul> 6428 6429 <ul> 6430<li>float32x4_t vld1q_lane_f32 (const float32_t *, float32x4_t, const int) 6431<br><em>Form of expected instruction(s):</em> <code>vld1.32 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6432</ul> 6433 6434 <ul> 6435<li>poly16x8_t vld1q_lane_p16 (const poly16_t *, poly16x8_t, const int) 6436<br><em>Form of expected instruction(s):</em> <code>vld1.16 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6437</ul> 6438 6439 <ul> 6440<li>poly8x16_t vld1q_lane_p8 (const poly8_t *, poly8x16_t, const int) 6441<br><em>Form of expected instruction(s):</em> <code>vld1.8 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6442</ul> 6443 6444 <ul> 6445<li>uint64x2_t vld1q_lane_u64 (const uint64_t *, uint64x2_t, const int) 6446<br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code> 6447</ul> 6448 6449 <ul> 6450<li>int64x2_t vld1q_lane_s64 (const int64_t *, int64x2_t, const int) 6451<br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code> 6452</ul> 6453 6454 <ul> 6455<li>uint32x2_t vld1_dup_u32 (const uint32_t *) 6456<br><em>Form of expected instruction(s):</em> <code>vld1.32 {</code><var>d0</var><code>[]}, [</code><var>r0</var><code>]</code> 6457</ul> 6458 6459 <ul> 6460<li>uint16x4_t vld1_dup_u16 (const uint16_t *) 6461<br><em>Form of expected instruction(s):</em> <code>vld1.16 {</code><var>d0</var><code>[]}, [</code><var>r0</var><code>]</code> 6462</ul> 6463 6464 <ul> 6465<li>uint8x8_t vld1_dup_u8 (const uint8_t *) 6466<br><em>Form of expected instruction(s):</em> <code>vld1.8 {</code><var>d0</var><code>[]}, [</code><var>r0</var><code>]</code> 6467</ul> 6468 6469 <ul> 6470<li>int32x2_t vld1_dup_s32 (const int32_t *) 6471<br><em>Form of expected instruction(s):</em> <code>vld1.32 {</code><var>d0</var><code>[]}, [</code><var>r0</var><code>]</code> 6472</ul> 6473 6474 <ul> 6475<li>int16x4_t vld1_dup_s16 (const int16_t *) 6476<br><em>Form of expected instruction(s):</em> <code>vld1.16 {</code><var>d0</var><code>[]}, [</code><var>r0</var><code>]</code> 6477</ul> 6478 6479 <ul> 6480<li>int8x8_t vld1_dup_s8 (const int8_t *) 6481<br><em>Form of expected instruction(s):</em> <code>vld1.8 {</code><var>d0</var><code>[]}, [</code><var>r0</var><code>]</code> 6482</ul> 6483 6484 <ul> 6485<li>float32x2_t vld1_dup_f32 (const float32_t *) 6486<br><em>Form of expected instruction(s):</em> <code>vld1.32 {</code><var>d0</var><code>[]}, [</code><var>r0</var><code>]</code> 6487</ul> 6488 6489 <ul> 6490<li>poly16x4_t vld1_dup_p16 (const poly16_t *) 6491<br><em>Form of expected instruction(s):</em> <code>vld1.16 {</code><var>d0</var><code>[]}, [</code><var>r0</var><code>]</code> 6492</ul> 6493 6494 <ul> 6495<li>poly8x8_t vld1_dup_p8 (const poly8_t *) 6496<br><em>Form of expected instruction(s):</em> <code>vld1.8 {</code><var>d0</var><code>[]}, [</code><var>r0</var><code>]</code> 6497</ul> 6498 6499 <ul> 6500<li>uint64x1_t vld1_dup_u64 (const uint64_t *) 6501<br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code> 6502</ul> 6503 6504 <ul> 6505<li>int64x1_t vld1_dup_s64 (const int64_t *) 6506<br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code> 6507</ul> 6508 6509 <ul> 6510<li>uint32x4_t vld1q_dup_u32 (const uint32_t *) 6511<br><em>Form of expected instruction(s):</em> <code>vld1.32 {</code><var>d0</var><code>[], </code><var>d1</var><code>[]}, [</code><var>r0</var><code>]</code> 6512</ul> 6513 6514 <ul> 6515<li>uint16x8_t vld1q_dup_u16 (const uint16_t *) 6516<br><em>Form of expected instruction(s):</em> <code>vld1.16 {</code><var>d0</var><code>[], </code><var>d1</var><code>[]}, [</code><var>r0</var><code>]</code> 6517</ul> 6518 6519 <ul> 6520<li>uint8x16_t vld1q_dup_u8 (const uint8_t *) 6521<br><em>Form of expected instruction(s):</em> <code>vld1.8 {</code><var>d0</var><code>[], </code><var>d1</var><code>[]}, [</code><var>r0</var><code>]</code> 6522</ul> 6523 6524 <ul> 6525<li>int32x4_t vld1q_dup_s32 (const int32_t *) 6526<br><em>Form of expected instruction(s):</em> <code>vld1.32 {</code><var>d0</var><code>[], </code><var>d1</var><code>[]}, [</code><var>r0</var><code>]</code> 6527</ul> 6528 6529 <ul> 6530<li>int16x8_t vld1q_dup_s16 (const int16_t *) 6531<br><em>Form of expected instruction(s):</em> <code>vld1.16 {</code><var>d0</var><code>[], </code><var>d1</var><code>[]}, [</code><var>r0</var><code>]</code> 6532</ul> 6533 6534 <ul> 6535<li>int8x16_t vld1q_dup_s8 (const int8_t *) 6536<br><em>Form of expected instruction(s):</em> <code>vld1.8 {</code><var>d0</var><code>[], </code><var>d1</var><code>[]}, [</code><var>r0</var><code>]</code> 6537</ul> 6538 6539 <ul> 6540<li>float32x4_t vld1q_dup_f32 (const float32_t *) 6541<br><em>Form of expected instruction(s):</em> <code>vld1.32 {</code><var>d0</var><code>[], </code><var>d1</var><code>[]}, [</code><var>r0</var><code>]</code> 6542</ul> 6543 6544 <ul> 6545<li>poly16x8_t vld1q_dup_p16 (const poly16_t *) 6546<br><em>Form of expected instruction(s):</em> <code>vld1.16 {</code><var>d0</var><code>[], </code><var>d1</var><code>[]}, [</code><var>r0</var><code>]</code> 6547</ul> 6548 6549 <ul> 6550<li>poly8x16_t vld1q_dup_p8 (const poly8_t *) 6551<br><em>Form of expected instruction(s):</em> <code>vld1.8 {</code><var>d0</var><code>[], </code><var>d1</var><code>[]}, [</code><var>r0</var><code>]</code> 6552</ul> 6553 6554 <ul> 6555<li>uint64x2_t vld1q_dup_u64 (const uint64_t *) 6556<br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6557</ul> 6558 6559 <ul> 6560<li>int64x2_t vld1q_dup_s64 (const int64_t *) 6561<br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6562</ul> 6563 6564<h5 class="subsubsection">6.54.3.69 Element/structure stores, VST1 variants</h5> 6565 6566 <ul> 6567<li>void vst1_u32 (uint32_t *, uint32x2_t) 6568<br><em>Form of expected instruction(s):</em> <code>vst1.32 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code> 6569</ul> 6570 6571 <ul> 6572<li>void vst1_u16 (uint16_t *, uint16x4_t) 6573<br><em>Form of expected instruction(s):</em> <code>vst1.16 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code> 6574</ul> 6575 6576 <ul> 6577<li>void vst1_u8 (uint8_t *, uint8x8_t) 6578<br><em>Form of expected instruction(s):</em> <code>vst1.8 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code> 6579</ul> 6580 6581 <ul> 6582<li>void vst1_s32 (int32_t *, int32x2_t) 6583<br><em>Form of expected instruction(s):</em> <code>vst1.32 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code> 6584</ul> 6585 6586 <ul> 6587<li>void vst1_s16 (int16_t *, int16x4_t) 6588<br><em>Form of expected instruction(s):</em> <code>vst1.16 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code> 6589</ul> 6590 6591 <ul> 6592<li>void vst1_s8 (int8_t *, int8x8_t) 6593<br><em>Form of expected instruction(s):</em> <code>vst1.8 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code> 6594</ul> 6595 6596 <ul> 6597<li>void vst1_u64 (uint64_t *, uint64x1_t) 6598<br><em>Form of expected instruction(s):</em> <code>vst1.64 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code> 6599</ul> 6600 6601 <ul> 6602<li>void vst1_s64 (int64_t *, int64x1_t) 6603<br><em>Form of expected instruction(s):</em> <code>vst1.64 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code> 6604</ul> 6605 6606 <ul> 6607<li>void vst1_f32 (float32_t *, float32x2_t) 6608<br><em>Form of expected instruction(s):</em> <code>vst1.32 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code> 6609</ul> 6610 6611 <ul> 6612<li>void vst1_p16 (poly16_t *, poly16x4_t) 6613<br><em>Form of expected instruction(s):</em> <code>vst1.16 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code> 6614</ul> 6615 6616 <ul> 6617<li>void vst1_p8 (poly8_t *, poly8x8_t) 6618<br><em>Form of expected instruction(s):</em> <code>vst1.8 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code> 6619</ul> 6620 6621 <ul> 6622<li>void vst1q_u32 (uint32_t *, uint32x4_t) 6623<br><em>Form of expected instruction(s):</em> <code>vst1.32 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6624</ul> 6625 6626 <ul> 6627<li>void vst1q_u16 (uint16_t *, uint16x8_t) 6628<br><em>Form of expected instruction(s):</em> <code>vst1.16 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6629</ul> 6630 6631 <ul> 6632<li>void vst1q_u8 (uint8_t *, uint8x16_t) 6633<br><em>Form of expected instruction(s):</em> <code>vst1.8 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6634</ul> 6635 6636 <ul> 6637<li>void vst1q_s32 (int32_t *, int32x4_t) 6638<br><em>Form of expected instruction(s):</em> <code>vst1.32 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6639</ul> 6640 6641 <ul> 6642<li>void vst1q_s16 (int16_t *, int16x8_t) 6643<br><em>Form of expected instruction(s):</em> <code>vst1.16 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6644</ul> 6645 6646 <ul> 6647<li>void vst1q_s8 (int8_t *, int8x16_t) 6648<br><em>Form of expected instruction(s):</em> <code>vst1.8 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6649</ul> 6650 6651 <ul> 6652<li>void vst1q_u64 (uint64_t *, uint64x2_t) 6653<br><em>Form of expected instruction(s):</em> <code>vst1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6654</ul> 6655 6656 <ul> 6657<li>void vst1q_s64 (int64_t *, int64x2_t) 6658<br><em>Form of expected instruction(s):</em> <code>vst1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6659</ul> 6660 6661 <ul> 6662<li>void vst1q_f32 (float32_t *, float32x4_t) 6663<br><em>Form of expected instruction(s):</em> <code>vst1.32 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6664</ul> 6665 6666 <ul> 6667<li>void vst1q_p16 (poly16_t *, poly16x8_t) 6668<br><em>Form of expected instruction(s):</em> <code>vst1.16 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6669</ul> 6670 6671 <ul> 6672<li>void vst1q_p8 (poly8_t *, poly8x16_t) 6673<br><em>Form of expected instruction(s):</em> <code>vst1.8 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6674</ul> 6675 6676 <ul> 6677<li>void vst1_lane_u32 (uint32_t *, uint32x2_t, const int) 6678<br><em>Form of expected instruction(s):</em> <code>vst1.32 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6679</ul> 6680 6681 <ul> 6682<li>void vst1_lane_u16 (uint16_t *, uint16x4_t, const int) 6683<br><em>Form of expected instruction(s):</em> <code>vst1.16 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6684</ul> 6685 6686 <ul> 6687<li>void vst1_lane_u8 (uint8_t *, uint8x8_t, const int) 6688<br><em>Form of expected instruction(s):</em> <code>vst1.8 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6689</ul> 6690 6691 <ul> 6692<li>void vst1_lane_s32 (int32_t *, int32x2_t, const int) 6693<br><em>Form of expected instruction(s):</em> <code>vst1.32 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6694</ul> 6695 6696 <ul> 6697<li>void vst1_lane_s16 (int16_t *, int16x4_t, const int) 6698<br><em>Form of expected instruction(s):</em> <code>vst1.16 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6699</ul> 6700 6701 <ul> 6702<li>void vst1_lane_s8 (int8_t *, int8x8_t, const int) 6703<br><em>Form of expected instruction(s):</em> <code>vst1.8 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6704</ul> 6705 6706 <ul> 6707<li>void vst1_lane_f32 (float32_t *, float32x2_t, const int) 6708<br><em>Form of expected instruction(s):</em> <code>vst1.32 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6709</ul> 6710 6711 <ul> 6712<li>void vst1_lane_p16 (poly16_t *, poly16x4_t, const int) 6713<br><em>Form of expected instruction(s):</em> <code>vst1.16 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6714</ul> 6715 6716 <ul> 6717<li>void vst1_lane_p8 (poly8_t *, poly8x8_t, const int) 6718<br><em>Form of expected instruction(s):</em> <code>vst1.8 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6719</ul> 6720 6721 <ul> 6722<li>void vst1_lane_s64 (int64_t *, int64x1_t, const int) 6723<br><em>Form of expected instruction(s):</em> <code>vst1.64 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code> 6724</ul> 6725 6726 <ul> 6727<li>void vst1_lane_u64 (uint64_t *, uint64x1_t, const int) 6728<br><em>Form of expected instruction(s):</em> <code>vst1.64 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code> 6729</ul> 6730 6731 <ul> 6732<li>void vst1q_lane_u32 (uint32_t *, uint32x4_t, const int) 6733<br><em>Form of expected instruction(s):</em> <code>vst1.32 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6734</ul> 6735 6736 <ul> 6737<li>void vst1q_lane_u16 (uint16_t *, uint16x8_t, const int) 6738<br><em>Form of expected instruction(s):</em> <code>vst1.16 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6739</ul> 6740 6741 <ul> 6742<li>void vst1q_lane_u8 (uint8_t *, uint8x16_t, const int) 6743<br><em>Form of expected instruction(s):</em> <code>vst1.8 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6744</ul> 6745 6746 <ul> 6747<li>void vst1q_lane_s32 (int32_t *, int32x4_t, const int) 6748<br><em>Form of expected instruction(s):</em> <code>vst1.32 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6749</ul> 6750 6751 <ul> 6752<li>void vst1q_lane_s16 (int16_t *, int16x8_t, const int) 6753<br><em>Form of expected instruction(s):</em> <code>vst1.16 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6754</ul> 6755 6756 <ul> 6757<li>void vst1q_lane_s8 (int8_t *, int8x16_t, const int) 6758<br><em>Form of expected instruction(s):</em> <code>vst1.8 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6759</ul> 6760 6761 <ul> 6762<li>void vst1q_lane_f32 (float32_t *, float32x4_t, const int) 6763<br><em>Form of expected instruction(s):</em> <code>vst1.32 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6764</ul> 6765 6766 <ul> 6767<li>void vst1q_lane_p16 (poly16_t *, poly16x8_t, const int) 6768<br><em>Form of expected instruction(s):</em> <code>vst1.16 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6769</ul> 6770 6771 <ul> 6772<li>void vst1q_lane_p8 (poly8_t *, poly8x16_t, const int) 6773<br><em>Form of expected instruction(s):</em> <code>vst1.8 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6774</ul> 6775 6776 <ul> 6777<li>void vst1q_lane_s64 (int64_t *, int64x2_t, const int) 6778<br><em>Form of expected instruction(s):</em> <code>vst1.64 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code> 6779</ul> 6780 6781 <ul> 6782<li>void vst1q_lane_u64 (uint64_t *, uint64x2_t, const int) 6783<br><em>Form of expected instruction(s):</em> <code>vst1.64 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code> 6784</ul> 6785 6786<h5 class="subsubsection">6.54.3.70 Element/structure loads, VLD2 variants</h5> 6787 6788 <ul> 6789<li>uint32x2x2_t vld2_u32 (const uint32_t *) 6790<br><em>Form of expected instruction(s):</em> <code>vld2.32 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6791</ul> 6792 6793 <ul> 6794<li>uint16x4x2_t vld2_u16 (const uint16_t *) 6795<br><em>Form of expected instruction(s):</em> <code>vld2.16 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6796</ul> 6797 6798 <ul> 6799<li>uint8x8x2_t vld2_u8 (const uint8_t *) 6800<br><em>Form of expected instruction(s):</em> <code>vld2.8 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6801</ul> 6802 6803 <ul> 6804<li>int32x2x2_t vld2_s32 (const int32_t *) 6805<br><em>Form of expected instruction(s):</em> <code>vld2.32 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6806</ul> 6807 6808 <ul> 6809<li>int16x4x2_t vld2_s16 (const int16_t *) 6810<br><em>Form of expected instruction(s):</em> <code>vld2.16 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6811</ul> 6812 6813 <ul> 6814<li>int8x8x2_t vld2_s8 (const int8_t *) 6815<br><em>Form of expected instruction(s):</em> <code>vld2.8 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6816</ul> 6817 6818 <ul> 6819<li>float32x2x2_t vld2_f32 (const float32_t *) 6820<br><em>Form of expected instruction(s):</em> <code>vld2.32 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6821</ul> 6822 6823 <ul> 6824<li>poly16x4x2_t vld2_p16 (const poly16_t *) 6825<br><em>Form of expected instruction(s):</em> <code>vld2.16 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6826</ul> 6827 6828 <ul> 6829<li>poly8x8x2_t vld2_p8 (const poly8_t *) 6830<br><em>Form of expected instruction(s):</em> <code>vld2.8 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6831</ul> 6832 6833 <ul> 6834<li>uint64x1x2_t vld2_u64 (const uint64_t *) 6835<br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6836</ul> 6837 6838 <ul> 6839<li>int64x1x2_t vld2_s64 (const int64_t *) 6840<br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6841</ul> 6842 6843 <ul> 6844<li>uint32x4x2_t vld2q_u32 (const uint32_t *) 6845<br><em>Form of expected instruction(s):</em> <code>vld2.32 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6846</ul> 6847 6848 <ul> 6849<li>uint16x8x2_t vld2q_u16 (const uint16_t *) 6850<br><em>Form of expected instruction(s):</em> <code>vld2.16 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6851</ul> 6852 6853 <ul> 6854<li>uint8x16x2_t vld2q_u8 (const uint8_t *) 6855<br><em>Form of expected instruction(s):</em> <code>vld2.8 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6856</ul> 6857 6858 <ul> 6859<li>int32x4x2_t vld2q_s32 (const int32_t *) 6860<br><em>Form of expected instruction(s):</em> <code>vld2.32 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6861</ul> 6862 6863 <ul> 6864<li>int16x8x2_t vld2q_s16 (const int16_t *) 6865<br><em>Form of expected instruction(s):</em> <code>vld2.16 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6866</ul> 6867 6868 <ul> 6869<li>int8x16x2_t vld2q_s8 (const int8_t *) 6870<br><em>Form of expected instruction(s):</em> <code>vld2.8 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6871</ul> 6872 6873 <ul> 6874<li>float32x4x2_t vld2q_f32 (const float32_t *) 6875<br><em>Form of expected instruction(s):</em> <code>vld2.32 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6876</ul> 6877 6878 <ul> 6879<li>poly16x8x2_t vld2q_p16 (const poly16_t *) 6880<br><em>Form of expected instruction(s):</em> <code>vld2.16 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6881</ul> 6882 6883 <ul> 6884<li>poly8x16x2_t vld2q_p8 (const poly8_t *) 6885<br><em>Form of expected instruction(s):</em> <code>vld2.8 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 6886</ul> 6887 6888 <ul> 6889<li>uint32x2x2_t vld2_lane_u32 (const uint32_t *, uint32x2x2_t, const int) 6890<br><em>Form of expected instruction(s):</em> <code>vld2.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6891</ul> 6892 6893 <ul> 6894<li>uint16x4x2_t vld2_lane_u16 (const uint16_t *, uint16x4x2_t, const int) 6895<br><em>Form of expected instruction(s):</em> <code>vld2.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6896</ul> 6897 6898 <ul> 6899<li>uint8x8x2_t vld2_lane_u8 (const uint8_t *, uint8x8x2_t, const int) 6900<br><em>Form of expected instruction(s):</em> <code>vld2.8 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6901</ul> 6902 6903 <ul> 6904<li>int32x2x2_t vld2_lane_s32 (const int32_t *, int32x2x2_t, const int) 6905<br><em>Form of expected instruction(s):</em> <code>vld2.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6906</ul> 6907 6908 <ul> 6909<li>int16x4x2_t vld2_lane_s16 (const int16_t *, int16x4x2_t, const int) 6910<br><em>Form of expected instruction(s):</em> <code>vld2.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6911</ul> 6912 6913 <ul> 6914<li>int8x8x2_t vld2_lane_s8 (const int8_t *, int8x8x2_t, const int) 6915<br><em>Form of expected instruction(s):</em> <code>vld2.8 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6916</ul> 6917 6918 <ul> 6919<li>float32x2x2_t vld2_lane_f32 (const float32_t *, float32x2x2_t, const int) 6920<br><em>Form of expected instruction(s):</em> <code>vld2.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6921</ul> 6922 6923 <ul> 6924<li>poly16x4x2_t vld2_lane_p16 (const poly16_t *, poly16x4x2_t, const int) 6925<br><em>Form of expected instruction(s):</em> <code>vld2.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6926</ul> 6927 6928 <ul> 6929<li>poly8x8x2_t vld2_lane_p8 (const poly8_t *, poly8x8x2_t, const int) 6930<br><em>Form of expected instruction(s):</em> <code>vld2.8 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6931</ul> 6932 6933 <ul> 6934<li>int32x4x2_t vld2q_lane_s32 (const int32_t *, int32x4x2_t, const int) 6935<br><em>Form of expected instruction(s):</em> <code>vld2.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6936</ul> 6937 6938 <ul> 6939<li>int16x8x2_t vld2q_lane_s16 (const int16_t *, int16x8x2_t, const int) 6940<br><em>Form of expected instruction(s):</em> <code>vld2.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6941</ul> 6942 6943 <ul> 6944<li>uint32x4x2_t vld2q_lane_u32 (const uint32_t *, uint32x4x2_t, const int) 6945<br><em>Form of expected instruction(s):</em> <code>vld2.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6946</ul> 6947 6948 <ul> 6949<li>uint16x8x2_t vld2q_lane_u16 (const uint16_t *, uint16x8x2_t, const int) 6950<br><em>Form of expected instruction(s):</em> <code>vld2.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6951</ul> 6952 6953 <ul> 6954<li>float32x4x2_t vld2q_lane_f32 (const float32_t *, float32x4x2_t, const int) 6955<br><em>Form of expected instruction(s):</em> <code>vld2.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6956</ul> 6957 6958 <ul> 6959<li>poly16x8x2_t vld2q_lane_p16 (const poly16_t *, poly16x8x2_t, const int) 6960<br><em>Form of expected instruction(s):</em> <code>vld2.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 6961</ul> 6962 6963 <ul> 6964<li>uint32x2x2_t vld2_dup_u32 (const uint32_t *) 6965<br><em>Form of expected instruction(s):</em> <code>vld2.32 {</code><var>d0</var><code>[], </code><var>d1</var><code>[]}, [</code><var>r0</var><code>]</code> 6966</ul> 6967 6968 <ul> 6969<li>uint16x4x2_t vld2_dup_u16 (const uint16_t *) 6970<br><em>Form of expected instruction(s):</em> <code>vld2.16 {</code><var>d0</var><code>[], </code><var>d1</var><code>[]}, [</code><var>r0</var><code>]</code> 6971</ul> 6972 6973 <ul> 6974<li>uint8x8x2_t vld2_dup_u8 (const uint8_t *) 6975<br><em>Form of expected instruction(s):</em> <code>vld2.8 {</code><var>d0</var><code>[], </code><var>d1</var><code>[]}, [</code><var>r0</var><code>]</code> 6976</ul> 6977 6978 <ul> 6979<li>int32x2x2_t vld2_dup_s32 (const int32_t *) 6980<br><em>Form of expected instruction(s):</em> <code>vld2.32 {</code><var>d0</var><code>[], </code><var>d1</var><code>[]}, [</code><var>r0</var><code>]</code> 6981</ul> 6982 6983 <ul> 6984<li>int16x4x2_t vld2_dup_s16 (const int16_t *) 6985<br><em>Form of expected instruction(s):</em> <code>vld2.16 {</code><var>d0</var><code>[], </code><var>d1</var><code>[]}, [</code><var>r0</var><code>]</code> 6986</ul> 6987 6988 <ul> 6989<li>int8x8x2_t vld2_dup_s8 (const int8_t *) 6990<br><em>Form of expected instruction(s):</em> <code>vld2.8 {</code><var>d0</var><code>[], </code><var>d1</var><code>[]}, [</code><var>r0</var><code>]</code> 6991</ul> 6992 6993 <ul> 6994<li>float32x2x2_t vld2_dup_f32 (const float32_t *) 6995<br><em>Form of expected instruction(s):</em> <code>vld2.32 {</code><var>d0</var><code>[], </code><var>d1</var><code>[]}, [</code><var>r0</var><code>]</code> 6996</ul> 6997 6998 <ul> 6999<li>poly16x4x2_t vld2_dup_p16 (const poly16_t *) 7000<br><em>Form of expected instruction(s):</em> <code>vld2.16 {</code><var>d0</var><code>[], </code><var>d1</var><code>[]}, [</code><var>r0</var><code>]</code> 7001</ul> 7002 7003 <ul> 7004<li>poly8x8x2_t vld2_dup_p8 (const poly8_t *) 7005<br><em>Form of expected instruction(s):</em> <code>vld2.8 {</code><var>d0</var><code>[], </code><var>d1</var><code>[]}, [</code><var>r0</var><code>]</code> 7006</ul> 7007 7008 <ul> 7009<li>uint64x1x2_t vld2_dup_u64 (const uint64_t *) 7010<br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 7011</ul> 7012 7013 <ul> 7014<li>int64x1x2_t vld2_dup_s64 (const int64_t *) 7015<br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 7016</ul> 7017 7018<h5 class="subsubsection">6.54.3.71 Element/structure stores, VST2 variants</h5> 7019 7020 <ul> 7021<li>void vst2_u32 (uint32_t *, uint32x2x2_t) 7022<br><em>Form of expected instruction(s):</em> <code>vst2.32 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 7023</ul> 7024 7025 <ul> 7026<li>void vst2_u16 (uint16_t *, uint16x4x2_t) 7027<br><em>Form of expected instruction(s):</em> <code>vst2.16 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 7028</ul> 7029 7030 <ul> 7031<li>void vst2_u8 (uint8_t *, uint8x8x2_t) 7032<br><em>Form of expected instruction(s):</em> <code>vst2.8 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 7033</ul> 7034 7035 <ul> 7036<li>void vst2_s32 (int32_t *, int32x2x2_t) 7037<br><em>Form of expected instruction(s):</em> <code>vst2.32 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 7038</ul> 7039 7040 <ul> 7041<li>void vst2_s16 (int16_t *, int16x4x2_t) 7042<br><em>Form of expected instruction(s):</em> <code>vst2.16 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 7043</ul> 7044 7045 <ul> 7046<li>void vst2_s8 (int8_t *, int8x8x2_t) 7047<br><em>Form of expected instruction(s):</em> <code>vst2.8 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 7048</ul> 7049 7050 <ul> 7051<li>void vst2_f32 (float32_t *, float32x2x2_t) 7052<br><em>Form of expected instruction(s):</em> <code>vst2.32 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 7053</ul> 7054 7055 <ul> 7056<li>void vst2_p16 (poly16_t *, poly16x4x2_t) 7057<br><em>Form of expected instruction(s):</em> <code>vst2.16 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 7058</ul> 7059 7060 <ul> 7061<li>void vst2_p8 (poly8_t *, poly8x8x2_t) 7062<br><em>Form of expected instruction(s):</em> <code>vst2.8 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 7063</ul> 7064 7065 <ul> 7066<li>void vst2_u64 (uint64_t *, uint64x1x2_t) 7067<br><em>Form of expected instruction(s):</em> <code>vst1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 7068</ul> 7069 7070 <ul> 7071<li>void vst2_s64 (int64_t *, int64x1x2_t) 7072<br><em>Form of expected instruction(s):</em> <code>vst1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 7073</ul> 7074 7075 <ul> 7076<li>void vst2q_u32 (uint32_t *, uint32x4x2_t) 7077<br><em>Form of expected instruction(s):</em> <code>vst2.32 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 7078</ul> 7079 7080 <ul> 7081<li>void vst2q_u16 (uint16_t *, uint16x8x2_t) 7082<br><em>Form of expected instruction(s):</em> <code>vst2.16 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 7083</ul> 7084 7085 <ul> 7086<li>void vst2q_u8 (uint8_t *, uint8x16x2_t) 7087<br><em>Form of expected instruction(s):</em> <code>vst2.8 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 7088</ul> 7089 7090 <ul> 7091<li>void vst2q_s32 (int32_t *, int32x4x2_t) 7092<br><em>Form of expected instruction(s):</em> <code>vst2.32 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 7093</ul> 7094 7095 <ul> 7096<li>void vst2q_s16 (int16_t *, int16x8x2_t) 7097<br><em>Form of expected instruction(s):</em> <code>vst2.16 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 7098</ul> 7099 7100 <ul> 7101<li>void vst2q_s8 (int8_t *, int8x16x2_t) 7102<br><em>Form of expected instruction(s):</em> <code>vst2.8 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 7103</ul> 7104 7105 <ul> 7106<li>void vst2q_f32 (float32_t *, float32x4x2_t) 7107<br><em>Form of expected instruction(s):</em> <code>vst2.32 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 7108</ul> 7109 7110 <ul> 7111<li>void vst2q_p16 (poly16_t *, poly16x8x2_t) 7112<br><em>Form of expected instruction(s):</em> <code>vst2.16 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 7113</ul> 7114 7115 <ul> 7116<li>void vst2q_p8 (poly8_t *, poly8x16x2_t) 7117<br><em>Form of expected instruction(s):</em> <code>vst2.8 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code> 7118</ul> 7119 7120 <ul> 7121<li>void vst2_lane_u32 (uint32_t *, uint32x2x2_t, const int) 7122<br><em>Form of expected instruction(s):</em> <code>vst2.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7123</ul> 7124 7125 <ul> 7126<li>void vst2_lane_u16 (uint16_t *, uint16x4x2_t, const int) 7127<br><em>Form of expected instruction(s):</em> <code>vst2.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7128</ul> 7129 7130 <ul> 7131<li>void vst2_lane_u8 (uint8_t *, uint8x8x2_t, const int) 7132<br><em>Form of expected instruction(s):</em> <code>vst2.8 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7133</ul> 7134 7135 <ul> 7136<li>void vst2_lane_s32 (int32_t *, int32x2x2_t, const int) 7137<br><em>Form of expected instruction(s):</em> <code>vst2.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7138</ul> 7139 7140 <ul> 7141<li>void vst2_lane_s16 (int16_t *, int16x4x2_t, const int) 7142<br><em>Form of expected instruction(s):</em> <code>vst2.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7143</ul> 7144 7145 <ul> 7146<li>void vst2_lane_s8 (int8_t *, int8x8x2_t, const int) 7147<br><em>Form of expected instruction(s):</em> <code>vst2.8 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7148</ul> 7149 7150 <ul> 7151<li>void vst2_lane_f32 (float32_t *, float32x2x2_t, const int) 7152<br><em>Form of expected instruction(s):</em> <code>vst2.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7153</ul> 7154 7155 <ul> 7156<li>void vst2_lane_p16 (poly16_t *, poly16x4x2_t, const int) 7157<br><em>Form of expected instruction(s):</em> <code>vst2.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7158</ul> 7159 7160 <ul> 7161<li>void vst2_lane_p8 (poly8_t *, poly8x8x2_t, const int) 7162<br><em>Form of expected instruction(s):</em> <code>vst2.8 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7163</ul> 7164 7165 <ul> 7166<li>void vst2q_lane_s32 (int32_t *, int32x4x2_t, const int) 7167<br><em>Form of expected instruction(s):</em> <code>vst2.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7168</ul> 7169 7170 <ul> 7171<li>void vst2q_lane_s16 (int16_t *, int16x8x2_t, const int) 7172<br><em>Form of expected instruction(s):</em> <code>vst2.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7173</ul> 7174 7175 <ul> 7176<li>void vst2q_lane_u32 (uint32_t *, uint32x4x2_t, const int) 7177<br><em>Form of expected instruction(s):</em> <code>vst2.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7178</ul> 7179 7180 <ul> 7181<li>void vst2q_lane_u16 (uint16_t *, uint16x8x2_t, const int) 7182<br><em>Form of expected instruction(s):</em> <code>vst2.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7183</ul> 7184 7185 <ul> 7186<li>void vst2q_lane_f32 (float32_t *, float32x4x2_t, const int) 7187<br><em>Form of expected instruction(s):</em> <code>vst2.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7188</ul> 7189 7190 <ul> 7191<li>void vst2q_lane_p16 (poly16_t *, poly16x8x2_t, const int) 7192<br><em>Form of expected instruction(s):</em> <code>vst2.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7193</ul> 7194 7195<h5 class="subsubsection">6.54.3.72 Element/structure loads, VLD3 variants</h5> 7196 7197 <ul> 7198<li>uint32x2x3_t vld3_u32 (const uint32_t *) 7199<br><em>Form of expected instruction(s):</em> <code>vld3.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code> 7200</ul> 7201 7202 <ul> 7203<li>uint16x4x3_t vld3_u16 (const uint16_t *) 7204<br><em>Form of expected instruction(s):</em> <code>vld3.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code> 7205</ul> 7206 7207 <ul> 7208<li>uint8x8x3_t vld3_u8 (const uint8_t *) 7209<br><em>Form of expected instruction(s):</em> <code>vld3.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code> 7210</ul> 7211 7212 <ul> 7213<li>int32x2x3_t vld3_s32 (const int32_t *) 7214<br><em>Form of expected instruction(s):</em> <code>vld3.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code> 7215</ul> 7216 7217 <ul> 7218<li>int16x4x3_t vld3_s16 (const int16_t *) 7219<br><em>Form of expected instruction(s):</em> <code>vld3.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code> 7220</ul> 7221 7222 <ul> 7223<li>int8x8x3_t vld3_s8 (const int8_t *) 7224<br><em>Form of expected instruction(s):</em> <code>vld3.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code> 7225</ul> 7226 7227 <ul> 7228<li>float32x2x3_t vld3_f32 (const float32_t *) 7229<br><em>Form of expected instruction(s):</em> <code>vld3.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code> 7230</ul> 7231 7232 <ul> 7233<li>poly16x4x3_t vld3_p16 (const poly16_t *) 7234<br><em>Form of expected instruction(s):</em> <code>vld3.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code> 7235</ul> 7236 7237 <ul> 7238<li>poly8x8x3_t vld3_p8 (const poly8_t *) 7239<br><em>Form of expected instruction(s):</em> <code>vld3.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code> 7240</ul> 7241 7242 <ul> 7243<li>uint64x1x3_t vld3_u64 (const uint64_t *) 7244<br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code> 7245</ul> 7246 7247 <ul> 7248<li>int64x1x3_t vld3_s64 (const int64_t *) 7249<br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code> 7250</ul> 7251 7252 <ul> 7253<li>uint32x4x3_t vld3q_u32 (const uint32_t *) 7254<br><em>Form of expected instruction(s):</em> <code>vld3.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code> 7255</ul> 7256 7257 <ul> 7258<li>uint16x8x3_t vld3q_u16 (const uint16_t *) 7259<br><em>Form of expected instruction(s):</em> <code>vld3.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code> 7260</ul> 7261 7262 <ul> 7263<li>uint8x16x3_t vld3q_u8 (const uint8_t *) 7264<br><em>Form of expected instruction(s):</em> <code>vld3.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code> 7265</ul> 7266 7267 <ul> 7268<li>int32x4x3_t vld3q_s32 (const int32_t *) 7269<br><em>Form of expected instruction(s):</em> <code>vld3.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code> 7270</ul> 7271 7272 <ul> 7273<li>int16x8x3_t vld3q_s16 (const int16_t *) 7274<br><em>Form of expected instruction(s):</em> <code>vld3.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code> 7275</ul> 7276 7277 <ul> 7278<li>int8x16x3_t vld3q_s8 (const int8_t *) 7279<br><em>Form of expected instruction(s):</em> <code>vld3.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code> 7280</ul> 7281 7282 <ul> 7283<li>float32x4x3_t vld3q_f32 (const float32_t *) 7284<br><em>Form of expected instruction(s):</em> <code>vld3.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code> 7285</ul> 7286 7287 <ul> 7288<li>poly16x8x3_t vld3q_p16 (const poly16_t *) 7289<br><em>Form of expected instruction(s):</em> <code>vld3.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code> 7290</ul> 7291 7292 <ul> 7293<li>poly8x16x3_t vld3q_p8 (const poly8_t *) 7294<br><em>Form of expected instruction(s):</em> <code>vld3.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code> 7295</ul> 7296 7297 <ul> 7298<li>uint32x2x3_t vld3_lane_u32 (const uint32_t *, uint32x2x3_t, const int) 7299<br><em>Form of expected instruction(s):</em> <code>vld3.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7300</ul> 7301 7302 <ul> 7303<li>uint16x4x3_t vld3_lane_u16 (const uint16_t *, uint16x4x3_t, const int) 7304<br><em>Form of expected instruction(s):</em> <code>vld3.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7305</ul> 7306 7307 <ul> 7308<li>uint8x8x3_t vld3_lane_u8 (const uint8_t *, uint8x8x3_t, const int) 7309<br><em>Form of expected instruction(s):</em> <code>vld3.8 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7310</ul> 7311 7312 <ul> 7313<li>int32x2x3_t vld3_lane_s32 (const int32_t *, int32x2x3_t, const int) 7314<br><em>Form of expected instruction(s):</em> <code>vld3.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7315</ul> 7316 7317 <ul> 7318<li>int16x4x3_t vld3_lane_s16 (const int16_t *, int16x4x3_t, const int) 7319<br><em>Form of expected instruction(s):</em> <code>vld3.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7320</ul> 7321 7322 <ul> 7323<li>int8x8x3_t vld3_lane_s8 (const int8_t *, int8x8x3_t, const int) 7324<br><em>Form of expected instruction(s):</em> <code>vld3.8 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7325</ul> 7326 7327 <ul> 7328<li>float32x2x3_t vld3_lane_f32 (const float32_t *, float32x2x3_t, const int) 7329<br><em>Form of expected instruction(s):</em> <code>vld3.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7330</ul> 7331 7332 <ul> 7333<li>poly16x4x3_t vld3_lane_p16 (const poly16_t *, poly16x4x3_t, const int) 7334<br><em>Form of expected instruction(s):</em> <code>vld3.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7335</ul> 7336 7337 <ul> 7338<li>poly8x8x3_t vld3_lane_p8 (const poly8_t *, poly8x8x3_t, const int) 7339<br><em>Form of expected instruction(s):</em> <code>vld3.8 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7340</ul> 7341 7342 <ul> 7343<li>int32x4x3_t vld3q_lane_s32 (const int32_t *, int32x4x3_t, const int) 7344<br><em>Form of expected instruction(s):</em> <code>vld3.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7345</ul> 7346 7347 <ul> 7348<li>int16x8x3_t vld3q_lane_s16 (const int16_t *, int16x8x3_t, const int) 7349<br><em>Form of expected instruction(s):</em> <code>vld3.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7350</ul> 7351 7352 <ul> 7353<li>uint32x4x3_t vld3q_lane_u32 (const uint32_t *, uint32x4x3_t, const int) 7354<br><em>Form of expected instruction(s):</em> <code>vld3.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7355</ul> 7356 7357 <ul> 7358<li>uint16x8x3_t vld3q_lane_u16 (const uint16_t *, uint16x8x3_t, const int) 7359<br><em>Form of expected instruction(s):</em> <code>vld3.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7360</ul> 7361 7362 <ul> 7363<li>float32x4x3_t vld3q_lane_f32 (const float32_t *, float32x4x3_t, const int) 7364<br><em>Form of expected instruction(s):</em> <code>vld3.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7365</ul> 7366 7367 <ul> 7368<li>poly16x8x3_t vld3q_lane_p16 (const poly16_t *, poly16x8x3_t, const int) 7369<br><em>Form of expected instruction(s):</em> <code>vld3.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7370</ul> 7371 7372 <ul> 7373<li>uint32x2x3_t vld3_dup_u32 (const uint32_t *) 7374<br><em>Form of expected instruction(s):</em> <code>vld3.32 {</code><var>d0</var><code>[], </code><var>d1</var><code>[], </code><var>d2</var><code>[]}, [</code><var>r0</var><code>]</code> 7375</ul> 7376 7377 <ul> 7378<li>uint16x4x3_t vld3_dup_u16 (const uint16_t *) 7379<br><em>Form of expected instruction(s):</em> <code>vld3.16 {</code><var>d0</var><code>[], </code><var>d1</var><code>[], </code><var>d2</var><code>[]}, [</code><var>r0</var><code>]</code> 7380</ul> 7381 7382 <ul> 7383<li>uint8x8x3_t vld3_dup_u8 (const uint8_t *) 7384<br><em>Form of expected instruction(s):</em> <code>vld3.8 {</code><var>d0</var><code>[], </code><var>d1</var><code>[], </code><var>d2</var><code>[]}, [</code><var>r0</var><code>]</code> 7385</ul> 7386 7387 <ul> 7388<li>int32x2x3_t vld3_dup_s32 (const int32_t *) 7389<br><em>Form of expected instruction(s):</em> <code>vld3.32 {</code><var>d0</var><code>[], </code><var>d1</var><code>[], </code><var>d2</var><code>[]}, [</code><var>r0</var><code>]</code> 7390</ul> 7391 7392 <ul> 7393<li>int16x4x3_t vld3_dup_s16 (const int16_t *) 7394<br><em>Form of expected instruction(s):</em> <code>vld3.16 {</code><var>d0</var><code>[], </code><var>d1</var><code>[], </code><var>d2</var><code>[]}, [</code><var>r0</var><code>]</code> 7395</ul> 7396 7397 <ul> 7398<li>int8x8x3_t vld3_dup_s8 (const int8_t *) 7399<br><em>Form of expected instruction(s):</em> <code>vld3.8 {</code><var>d0</var><code>[], </code><var>d1</var><code>[], </code><var>d2</var><code>[]}, [</code><var>r0</var><code>]</code> 7400</ul> 7401 7402 <ul> 7403<li>float32x2x3_t vld3_dup_f32 (const float32_t *) 7404<br><em>Form of expected instruction(s):</em> <code>vld3.32 {</code><var>d0</var><code>[], </code><var>d1</var><code>[], </code><var>d2</var><code>[]}, [</code><var>r0</var><code>]</code> 7405</ul> 7406 7407 <ul> 7408<li>poly16x4x3_t vld3_dup_p16 (const poly16_t *) 7409<br><em>Form of expected instruction(s):</em> <code>vld3.16 {</code><var>d0</var><code>[], </code><var>d1</var><code>[], </code><var>d2</var><code>[]}, [</code><var>r0</var><code>]</code> 7410</ul> 7411 7412 <ul> 7413<li>poly8x8x3_t vld3_dup_p8 (const poly8_t *) 7414<br><em>Form of expected instruction(s):</em> <code>vld3.8 {</code><var>d0</var><code>[], </code><var>d1</var><code>[], </code><var>d2</var><code>[]}, [</code><var>r0</var><code>]</code> 7415</ul> 7416 7417 <ul> 7418<li>uint64x1x3_t vld3_dup_u64 (const uint64_t *) 7419<br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code> 7420</ul> 7421 7422 <ul> 7423<li>int64x1x3_t vld3_dup_s64 (const int64_t *) 7424<br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code> 7425</ul> 7426 7427<h5 class="subsubsection">6.54.3.73 Element/structure stores, VST3 variants</h5> 7428 7429 <ul> 7430<li>void vst3_u32 (uint32_t *, uint32x2x3_t) 7431<br><em>Form of expected instruction(s):</em> <code>vst3.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7432</ul> 7433 7434 <ul> 7435<li>void vst3_u16 (uint16_t *, uint16x4x3_t) 7436<br><em>Form of expected instruction(s):</em> <code>vst3.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7437</ul> 7438 7439 <ul> 7440<li>void vst3_u8 (uint8_t *, uint8x8x3_t) 7441<br><em>Form of expected instruction(s):</em> <code>vst3.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7442</ul> 7443 7444 <ul> 7445<li>void vst3_s32 (int32_t *, int32x2x3_t) 7446<br><em>Form of expected instruction(s):</em> <code>vst3.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7447</ul> 7448 7449 <ul> 7450<li>void vst3_s16 (int16_t *, int16x4x3_t) 7451<br><em>Form of expected instruction(s):</em> <code>vst3.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7452</ul> 7453 7454 <ul> 7455<li>void vst3_s8 (int8_t *, int8x8x3_t) 7456<br><em>Form of expected instruction(s):</em> <code>vst3.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7457</ul> 7458 7459 <ul> 7460<li>void vst3_f32 (float32_t *, float32x2x3_t) 7461<br><em>Form of expected instruction(s):</em> <code>vst3.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7462</ul> 7463 7464 <ul> 7465<li>void vst3_p16 (poly16_t *, poly16x4x3_t) 7466<br><em>Form of expected instruction(s):</em> <code>vst3.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7467</ul> 7468 7469 <ul> 7470<li>void vst3_p8 (poly8_t *, poly8x8x3_t) 7471<br><em>Form of expected instruction(s):</em> <code>vst3.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7472</ul> 7473 7474 <ul> 7475<li>void vst3_u64 (uint64_t *, uint64x1x3_t) 7476<br><em>Form of expected instruction(s):</em> <code>vst1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7477</ul> 7478 7479 <ul> 7480<li>void vst3_s64 (int64_t *, int64x1x3_t) 7481<br><em>Form of expected instruction(s):</em> <code>vst1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7482</ul> 7483 7484 <ul> 7485<li>void vst3q_u32 (uint32_t *, uint32x4x3_t) 7486<br><em>Form of expected instruction(s):</em> <code>vst3.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code> 7487</ul> 7488 7489 <ul> 7490<li>void vst3q_u16 (uint16_t *, uint16x8x3_t) 7491<br><em>Form of expected instruction(s):</em> <code>vst3.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code> 7492</ul> 7493 7494 <ul> 7495<li>void vst3q_u8 (uint8_t *, uint8x16x3_t) 7496<br><em>Form of expected instruction(s):</em> <code>vst3.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code> 7497</ul> 7498 7499 <ul> 7500<li>void vst3q_s32 (int32_t *, int32x4x3_t) 7501<br><em>Form of expected instruction(s):</em> <code>vst3.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code> 7502</ul> 7503 7504 <ul> 7505<li>void vst3q_s16 (int16_t *, int16x8x3_t) 7506<br><em>Form of expected instruction(s):</em> <code>vst3.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code> 7507</ul> 7508 7509 <ul> 7510<li>void vst3q_s8 (int8_t *, int8x16x3_t) 7511<br><em>Form of expected instruction(s):</em> <code>vst3.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code> 7512</ul> 7513 7514 <ul> 7515<li>void vst3q_f32 (float32_t *, float32x4x3_t) 7516<br><em>Form of expected instruction(s):</em> <code>vst3.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code> 7517</ul> 7518 7519 <ul> 7520<li>void vst3q_p16 (poly16_t *, poly16x8x3_t) 7521<br><em>Form of expected instruction(s):</em> <code>vst3.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code> 7522</ul> 7523 7524 <ul> 7525<li>void vst3q_p8 (poly8_t *, poly8x16x3_t) 7526<br><em>Form of expected instruction(s):</em> <code>vst3.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code> 7527</ul> 7528 7529 <ul> 7530<li>void vst3_lane_u32 (uint32_t *, uint32x2x3_t, const int) 7531<br><em>Form of expected instruction(s):</em> <code>vst3.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7532</ul> 7533 7534 <ul> 7535<li>void vst3_lane_u16 (uint16_t *, uint16x4x3_t, const int) 7536<br><em>Form of expected instruction(s):</em> <code>vst3.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7537</ul> 7538 7539 <ul> 7540<li>void vst3_lane_u8 (uint8_t *, uint8x8x3_t, const int) 7541<br><em>Form of expected instruction(s):</em> <code>vst3.8 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7542</ul> 7543 7544 <ul> 7545<li>void vst3_lane_s32 (int32_t *, int32x2x3_t, const int) 7546<br><em>Form of expected instruction(s):</em> <code>vst3.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7547</ul> 7548 7549 <ul> 7550<li>void vst3_lane_s16 (int16_t *, int16x4x3_t, const int) 7551<br><em>Form of expected instruction(s):</em> <code>vst3.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7552</ul> 7553 7554 <ul> 7555<li>void vst3_lane_s8 (int8_t *, int8x8x3_t, const int) 7556<br><em>Form of expected instruction(s):</em> <code>vst3.8 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7557</ul> 7558 7559 <ul> 7560<li>void vst3_lane_f32 (float32_t *, float32x2x3_t, const int) 7561<br><em>Form of expected instruction(s):</em> <code>vst3.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7562</ul> 7563 7564 <ul> 7565<li>void vst3_lane_p16 (poly16_t *, poly16x4x3_t, const int) 7566<br><em>Form of expected instruction(s):</em> <code>vst3.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7567</ul> 7568 7569 <ul> 7570<li>void vst3_lane_p8 (poly8_t *, poly8x8x3_t, const int) 7571<br><em>Form of expected instruction(s):</em> <code>vst3.8 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7572</ul> 7573 7574 <ul> 7575<li>void vst3q_lane_s32 (int32_t *, int32x4x3_t, const int) 7576<br><em>Form of expected instruction(s):</em> <code>vst3.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7577</ul> 7578 7579 <ul> 7580<li>void vst3q_lane_s16 (int16_t *, int16x8x3_t, const int) 7581<br><em>Form of expected instruction(s):</em> <code>vst3.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7582</ul> 7583 7584 <ul> 7585<li>void vst3q_lane_u32 (uint32_t *, uint32x4x3_t, const int) 7586<br><em>Form of expected instruction(s):</em> <code>vst3.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7587</ul> 7588 7589 <ul> 7590<li>void vst3q_lane_u16 (uint16_t *, uint16x8x3_t, const int) 7591<br><em>Form of expected instruction(s):</em> <code>vst3.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7592</ul> 7593 7594 <ul> 7595<li>void vst3q_lane_f32 (float32_t *, float32x4x3_t, const int) 7596<br><em>Form of expected instruction(s):</em> <code>vst3.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7597</ul> 7598 7599 <ul> 7600<li>void vst3q_lane_p16 (poly16_t *, poly16x8x3_t, const int) 7601<br><em>Form of expected instruction(s):</em> <code>vst3.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7602</ul> 7603 7604<h5 class="subsubsection">6.54.3.74 Element/structure loads, VLD4 variants</h5> 7605 7606 <ul> 7607<li>uint32x2x4_t vld4_u32 (const uint32_t *) 7608<br><em>Form of expected instruction(s):</em> <code>vld4.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7609</ul> 7610 7611 <ul> 7612<li>uint16x4x4_t vld4_u16 (const uint16_t *) 7613<br><em>Form of expected instruction(s):</em> <code>vld4.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7614</ul> 7615 7616 <ul> 7617<li>uint8x8x4_t vld4_u8 (const uint8_t *) 7618<br><em>Form of expected instruction(s):</em> <code>vld4.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7619</ul> 7620 7621 <ul> 7622<li>int32x2x4_t vld4_s32 (const int32_t *) 7623<br><em>Form of expected instruction(s):</em> <code>vld4.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7624</ul> 7625 7626 <ul> 7627<li>int16x4x4_t vld4_s16 (const int16_t *) 7628<br><em>Form of expected instruction(s):</em> <code>vld4.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7629</ul> 7630 7631 <ul> 7632<li>int8x8x4_t vld4_s8 (const int8_t *) 7633<br><em>Form of expected instruction(s):</em> <code>vld4.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7634</ul> 7635 7636 <ul> 7637<li>float32x2x4_t vld4_f32 (const float32_t *) 7638<br><em>Form of expected instruction(s):</em> <code>vld4.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7639</ul> 7640 7641 <ul> 7642<li>poly16x4x4_t vld4_p16 (const poly16_t *) 7643<br><em>Form of expected instruction(s):</em> <code>vld4.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7644</ul> 7645 7646 <ul> 7647<li>poly8x8x4_t vld4_p8 (const poly8_t *) 7648<br><em>Form of expected instruction(s):</em> <code>vld4.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7649</ul> 7650 7651 <ul> 7652<li>uint64x1x4_t vld4_u64 (const uint64_t *) 7653<br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7654</ul> 7655 7656 <ul> 7657<li>int64x1x4_t vld4_s64 (const int64_t *) 7658<br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7659</ul> 7660 7661 <ul> 7662<li>uint32x4x4_t vld4q_u32 (const uint32_t *) 7663<br><em>Form of expected instruction(s):</em> <code>vld4.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7664</ul> 7665 7666 <ul> 7667<li>uint16x8x4_t vld4q_u16 (const uint16_t *) 7668<br><em>Form of expected instruction(s):</em> <code>vld4.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7669</ul> 7670 7671 <ul> 7672<li>uint8x16x4_t vld4q_u8 (const uint8_t *) 7673<br><em>Form of expected instruction(s):</em> <code>vld4.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7674</ul> 7675 7676 <ul> 7677<li>int32x4x4_t vld4q_s32 (const int32_t *) 7678<br><em>Form of expected instruction(s):</em> <code>vld4.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7679</ul> 7680 7681 <ul> 7682<li>int16x8x4_t vld4q_s16 (const int16_t *) 7683<br><em>Form of expected instruction(s):</em> <code>vld4.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7684</ul> 7685 7686 <ul> 7687<li>int8x16x4_t vld4q_s8 (const int8_t *) 7688<br><em>Form of expected instruction(s):</em> <code>vld4.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7689</ul> 7690 7691 <ul> 7692<li>float32x4x4_t vld4q_f32 (const float32_t *) 7693<br><em>Form of expected instruction(s):</em> <code>vld4.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7694</ul> 7695 7696 <ul> 7697<li>poly16x8x4_t vld4q_p16 (const poly16_t *) 7698<br><em>Form of expected instruction(s):</em> <code>vld4.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7699</ul> 7700 7701 <ul> 7702<li>poly8x16x4_t vld4q_p8 (const poly8_t *) 7703<br><em>Form of expected instruction(s):</em> <code>vld4.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7704</ul> 7705 7706 <ul> 7707<li>uint32x2x4_t vld4_lane_u32 (const uint32_t *, uint32x2x4_t, const int) 7708<br><em>Form of expected instruction(s):</em> <code>vld4.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7709</ul> 7710 7711 <ul> 7712<li>uint16x4x4_t vld4_lane_u16 (const uint16_t *, uint16x4x4_t, const int) 7713<br><em>Form of expected instruction(s):</em> <code>vld4.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7714</ul> 7715 7716 <ul> 7717<li>uint8x8x4_t vld4_lane_u8 (const uint8_t *, uint8x8x4_t, const int) 7718<br><em>Form of expected instruction(s):</em> <code>vld4.8 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7719</ul> 7720 7721 <ul> 7722<li>int32x2x4_t vld4_lane_s32 (const int32_t *, int32x2x4_t, const int) 7723<br><em>Form of expected instruction(s):</em> <code>vld4.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7724</ul> 7725 7726 <ul> 7727<li>int16x4x4_t vld4_lane_s16 (const int16_t *, int16x4x4_t, const int) 7728<br><em>Form of expected instruction(s):</em> <code>vld4.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7729</ul> 7730 7731 <ul> 7732<li>int8x8x4_t vld4_lane_s8 (const int8_t *, int8x8x4_t, const int) 7733<br><em>Form of expected instruction(s):</em> <code>vld4.8 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7734</ul> 7735 7736 <ul> 7737<li>float32x2x4_t vld4_lane_f32 (const float32_t *, float32x2x4_t, const int) 7738<br><em>Form of expected instruction(s):</em> <code>vld4.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7739</ul> 7740 7741 <ul> 7742<li>poly16x4x4_t vld4_lane_p16 (const poly16_t *, poly16x4x4_t, const int) 7743<br><em>Form of expected instruction(s):</em> <code>vld4.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7744</ul> 7745 7746 <ul> 7747<li>poly8x8x4_t vld4_lane_p8 (const poly8_t *, poly8x8x4_t, const int) 7748<br><em>Form of expected instruction(s):</em> <code>vld4.8 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7749</ul> 7750 7751 <ul> 7752<li>int32x4x4_t vld4q_lane_s32 (const int32_t *, int32x4x4_t, const int) 7753<br><em>Form of expected instruction(s):</em> <code>vld4.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7754</ul> 7755 7756 <ul> 7757<li>int16x8x4_t vld4q_lane_s16 (const int16_t *, int16x8x4_t, const int) 7758<br><em>Form of expected instruction(s):</em> <code>vld4.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7759</ul> 7760 7761 <ul> 7762<li>uint32x4x4_t vld4q_lane_u32 (const uint32_t *, uint32x4x4_t, const int) 7763<br><em>Form of expected instruction(s):</em> <code>vld4.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7764</ul> 7765 7766 <ul> 7767<li>uint16x8x4_t vld4q_lane_u16 (const uint16_t *, uint16x8x4_t, const int) 7768<br><em>Form of expected instruction(s):</em> <code>vld4.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7769</ul> 7770 7771 <ul> 7772<li>float32x4x4_t vld4q_lane_f32 (const float32_t *, float32x4x4_t, const int) 7773<br><em>Form of expected instruction(s):</em> <code>vld4.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7774</ul> 7775 7776 <ul> 7777<li>poly16x8x4_t vld4q_lane_p16 (const poly16_t *, poly16x8x4_t, const int) 7778<br><em>Form of expected instruction(s):</em> <code>vld4.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7779</ul> 7780 7781 <ul> 7782<li>uint32x2x4_t vld4_dup_u32 (const uint32_t *) 7783<br><em>Form of expected instruction(s):</em> <code>vld4.32 {</code><var>d0</var><code>[], </code><var>d1</var><code>[], </code><var>d2</var><code>[], </code><var>d3</var><code>[]}, [</code><var>r0</var><code>]</code> 7784</ul> 7785 7786 <ul> 7787<li>uint16x4x4_t vld4_dup_u16 (const uint16_t *) 7788<br><em>Form of expected instruction(s):</em> <code>vld4.16 {</code><var>d0</var><code>[], </code><var>d1</var><code>[], </code><var>d2</var><code>[], </code><var>d3</var><code>[]}, [</code><var>r0</var><code>]</code> 7789</ul> 7790 7791 <ul> 7792<li>uint8x8x4_t vld4_dup_u8 (const uint8_t *) 7793<br><em>Form of expected instruction(s):</em> <code>vld4.8 {</code><var>d0</var><code>[], </code><var>d1</var><code>[], </code><var>d2</var><code>[], </code><var>d3</var><code>[]}, [</code><var>r0</var><code>]</code> 7794</ul> 7795 7796 <ul> 7797<li>int32x2x4_t vld4_dup_s32 (const int32_t *) 7798<br><em>Form of expected instruction(s):</em> <code>vld4.32 {</code><var>d0</var><code>[], </code><var>d1</var><code>[], </code><var>d2</var><code>[], </code><var>d3</var><code>[]}, [</code><var>r0</var><code>]</code> 7799</ul> 7800 7801 <ul> 7802<li>int16x4x4_t vld4_dup_s16 (const int16_t *) 7803<br><em>Form of expected instruction(s):</em> <code>vld4.16 {</code><var>d0</var><code>[], </code><var>d1</var><code>[], </code><var>d2</var><code>[], </code><var>d3</var><code>[]}, [</code><var>r0</var><code>]</code> 7804</ul> 7805 7806 <ul> 7807<li>int8x8x4_t vld4_dup_s8 (const int8_t *) 7808<br><em>Form of expected instruction(s):</em> <code>vld4.8 {</code><var>d0</var><code>[], </code><var>d1</var><code>[], </code><var>d2</var><code>[], </code><var>d3</var><code>[]}, [</code><var>r0</var><code>]</code> 7809</ul> 7810 7811 <ul> 7812<li>float32x2x4_t vld4_dup_f32 (const float32_t *) 7813<br><em>Form of expected instruction(s):</em> <code>vld4.32 {</code><var>d0</var><code>[], </code><var>d1</var><code>[], </code><var>d2</var><code>[], </code><var>d3</var><code>[]}, [</code><var>r0</var><code>]</code> 7814</ul> 7815 7816 <ul> 7817<li>poly16x4x4_t vld4_dup_p16 (const poly16_t *) 7818<br><em>Form of expected instruction(s):</em> <code>vld4.16 {</code><var>d0</var><code>[], </code><var>d1</var><code>[], </code><var>d2</var><code>[], </code><var>d3</var><code>[]}, [</code><var>r0</var><code>]</code> 7819</ul> 7820 7821 <ul> 7822<li>poly8x8x4_t vld4_dup_p8 (const poly8_t *) 7823<br><em>Form of expected instruction(s):</em> <code>vld4.8 {</code><var>d0</var><code>[], </code><var>d1</var><code>[], </code><var>d2</var><code>[], </code><var>d3</var><code>[]}, [</code><var>r0</var><code>]</code> 7824</ul> 7825 7826 <ul> 7827<li>uint64x1x4_t vld4_dup_u64 (const uint64_t *) 7828<br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7829</ul> 7830 7831 <ul> 7832<li>int64x1x4_t vld4_dup_s64 (const int64_t *) 7833<br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7834</ul> 7835 7836<h5 class="subsubsection">6.54.3.75 Element/structure stores, VST4 variants</h5> 7837 7838 <ul> 7839<li>void vst4_u32 (uint32_t *, uint32x2x4_t) 7840<br><em>Form of expected instruction(s):</em> <code>vst4.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7841</ul> 7842 7843 <ul> 7844<li>void vst4_u16 (uint16_t *, uint16x4x4_t) 7845<br><em>Form of expected instruction(s):</em> <code>vst4.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7846</ul> 7847 7848 <ul> 7849<li>void vst4_u8 (uint8_t *, uint8x8x4_t) 7850<br><em>Form of expected instruction(s):</em> <code>vst4.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7851</ul> 7852 7853 <ul> 7854<li>void vst4_s32 (int32_t *, int32x2x4_t) 7855<br><em>Form of expected instruction(s):</em> <code>vst4.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7856</ul> 7857 7858 <ul> 7859<li>void vst4_s16 (int16_t *, int16x4x4_t) 7860<br><em>Form of expected instruction(s):</em> <code>vst4.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7861</ul> 7862 7863 <ul> 7864<li>void vst4_s8 (int8_t *, int8x8x4_t) 7865<br><em>Form of expected instruction(s):</em> <code>vst4.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7866</ul> 7867 7868 <ul> 7869<li>void vst4_f32 (float32_t *, float32x2x4_t) 7870<br><em>Form of expected instruction(s):</em> <code>vst4.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7871</ul> 7872 7873 <ul> 7874<li>void vst4_p16 (poly16_t *, poly16x4x4_t) 7875<br><em>Form of expected instruction(s):</em> <code>vst4.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7876</ul> 7877 7878 <ul> 7879<li>void vst4_p8 (poly8_t *, poly8x8x4_t) 7880<br><em>Form of expected instruction(s):</em> <code>vst4.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7881</ul> 7882 7883 <ul> 7884<li>void vst4_u64 (uint64_t *, uint64x1x4_t) 7885<br><em>Form of expected instruction(s):</em> <code>vst1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7886</ul> 7887 7888 <ul> 7889<li>void vst4_s64 (int64_t *, int64x1x4_t) 7890<br><em>Form of expected instruction(s):</em> <code>vst1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7891</ul> 7892 7893 <ul> 7894<li>void vst4q_u32 (uint32_t *, uint32x4x4_t) 7895<br><em>Form of expected instruction(s):</em> <code>vst4.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7896</ul> 7897 7898 <ul> 7899<li>void vst4q_u16 (uint16_t *, uint16x8x4_t) 7900<br><em>Form of expected instruction(s):</em> <code>vst4.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7901</ul> 7902 7903 <ul> 7904<li>void vst4q_u8 (uint8_t *, uint8x16x4_t) 7905<br><em>Form of expected instruction(s):</em> <code>vst4.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7906</ul> 7907 7908 <ul> 7909<li>void vst4q_s32 (int32_t *, int32x4x4_t) 7910<br><em>Form of expected instruction(s):</em> <code>vst4.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7911</ul> 7912 7913 <ul> 7914<li>void vst4q_s16 (int16_t *, int16x8x4_t) 7915<br><em>Form of expected instruction(s):</em> <code>vst4.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7916</ul> 7917 7918 <ul> 7919<li>void vst4q_s8 (int8_t *, int8x16x4_t) 7920<br><em>Form of expected instruction(s):</em> <code>vst4.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7921</ul> 7922 7923 <ul> 7924<li>void vst4q_f32 (float32_t *, float32x4x4_t) 7925<br><em>Form of expected instruction(s):</em> <code>vst4.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7926</ul> 7927 7928 <ul> 7929<li>void vst4q_p16 (poly16_t *, poly16x8x4_t) 7930<br><em>Form of expected instruction(s):</em> <code>vst4.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7931</ul> 7932 7933 <ul> 7934<li>void vst4q_p8 (poly8_t *, poly8x16x4_t) 7935<br><em>Form of expected instruction(s):</em> <code>vst4.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code> 7936</ul> 7937 7938 <ul> 7939<li>void vst4_lane_u32 (uint32_t *, uint32x2x4_t, const int) 7940<br><em>Form of expected instruction(s):</em> <code>vst4.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7941</ul> 7942 7943 <ul> 7944<li>void vst4_lane_u16 (uint16_t *, uint16x4x4_t, const int) 7945<br><em>Form of expected instruction(s):</em> <code>vst4.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7946</ul> 7947 7948 <ul> 7949<li>void vst4_lane_u8 (uint8_t *, uint8x8x4_t, const int) 7950<br><em>Form of expected instruction(s):</em> <code>vst4.8 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7951</ul> 7952 7953 <ul> 7954<li>void vst4_lane_s32 (int32_t *, int32x2x4_t, const int) 7955<br><em>Form of expected instruction(s):</em> <code>vst4.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7956</ul> 7957 7958 <ul> 7959<li>void vst4_lane_s16 (int16_t *, int16x4x4_t, const int) 7960<br><em>Form of expected instruction(s):</em> <code>vst4.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7961</ul> 7962 7963 <ul> 7964<li>void vst4_lane_s8 (int8_t *, int8x8x4_t, const int) 7965<br><em>Form of expected instruction(s):</em> <code>vst4.8 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7966</ul> 7967 7968 <ul> 7969<li>void vst4_lane_f32 (float32_t *, float32x2x4_t, const int) 7970<br><em>Form of expected instruction(s):</em> <code>vst4.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7971</ul> 7972 7973 <ul> 7974<li>void vst4_lane_p16 (poly16_t *, poly16x4x4_t, const int) 7975<br><em>Form of expected instruction(s):</em> <code>vst4.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7976</ul> 7977 7978 <ul> 7979<li>void vst4_lane_p8 (poly8_t *, poly8x8x4_t, const int) 7980<br><em>Form of expected instruction(s):</em> <code>vst4.8 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7981</ul> 7982 7983 <ul> 7984<li>void vst4q_lane_s32 (int32_t *, int32x4x4_t, const int) 7985<br><em>Form of expected instruction(s):</em> <code>vst4.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7986</ul> 7987 7988 <ul> 7989<li>void vst4q_lane_s16 (int16_t *, int16x8x4_t, const int) 7990<br><em>Form of expected instruction(s):</em> <code>vst4.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7991</ul> 7992 7993 <ul> 7994<li>void vst4q_lane_u32 (uint32_t *, uint32x4x4_t, const int) 7995<br><em>Form of expected instruction(s):</em> <code>vst4.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 7996</ul> 7997 7998 <ul> 7999<li>void vst4q_lane_u16 (uint16_t *, uint16x8x4_t, const int) 8000<br><em>Form of expected instruction(s):</em> <code>vst4.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 8001</ul> 8002 8003 <ul> 8004<li>void vst4q_lane_f32 (float32_t *, float32x4x4_t, const int) 8005<br><em>Form of expected instruction(s):</em> <code>vst4.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 8006</ul> 8007 8008 <ul> 8009<li>void vst4q_lane_p16 (poly16_t *, poly16x8x4_t, const int) 8010<br><em>Form of expected instruction(s):</em> <code>vst4.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code> 8011</ul> 8012 8013<h5 class="subsubsection">6.54.3.76 Logical operations (AND)</h5> 8014 8015 <ul> 8016<li>uint32x2_t vand_u32 (uint32x2_t, uint32x2_t) 8017<br><em>Form of expected instruction(s):</em> <code>vand </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 8018</ul> 8019 8020 <ul> 8021<li>uint16x4_t vand_u16 (uint16x4_t, uint16x4_t) 8022<br><em>Form of expected instruction(s):</em> <code>vand </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 8023</ul> 8024 8025 <ul> 8026<li>uint8x8_t vand_u8 (uint8x8_t, uint8x8_t) 8027<br><em>Form of expected instruction(s):</em> <code>vand </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 8028</ul> 8029 8030 <ul> 8031<li>int32x2_t vand_s32 (int32x2_t, int32x2_t) 8032<br><em>Form of expected instruction(s):</em> <code>vand </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 8033</ul> 8034 8035 <ul> 8036<li>int16x4_t vand_s16 (int16x4_t, int16x4_t) 8037<br><em>Form of expected instruction(s):</em> <code>vand </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 8038</ul> 8039 8040 <ul> 8041<li>int8x8_t vand_s8 (int8x8_t, int8x8_t) 8042<br><em>Form of expected instruction(s):</em> <code>vand </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 8043</ul> 8044 8045 <ul> 8046<li>uint64x1_t vand_u64 (uint64x1_t, uint64x1_t) 8047</ul> 8048 8049 <ul> 8050<li>int64x1_t vand_s64 (int64x1_t, int64x1_t) 8051</ul> 8052 8053 <ul> 8054<li>uint32x4_t vandq_u32 (uint32x4_t, uint32x4_t) 8055<br><em>Form of expected instruction(s):</em> <code>vand </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8056</ul> 8057 8058 <ul> 8059<li>uint16x8_t vandq_u16 (uint16x8_t, uint16x8_t) 8060<br><em>Form of expected instruction(s):</em> <code>vand </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8061</ul> 8062 8063 <ul> 8064<li>uint8x16_t vandq_u8 (uint8x16_t, uint8x16_t) 8065<br><em>Form of expected instruction(s):</em> <code>vand </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8066</ul> 8067 8068 <ul> 8069<li>int32x4_t vandq_s32 (int32x4_t, int32x4_t) 8070<br><em>Form of expected instruction(s):</em> <code>vand </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8071</ul> 8072 8073 <ul> 8074<li>int16x8_t vandq_s16 (int16x8_t, int16x8_t) 8075<br><em>Form of expected instruction(s):</em> <code>vand </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8076</ul> 8077 8078 <ul> 8079<li>int8x16_t vandq_s8 (int8x16_t, int8x16_t) 8080<br><em>Form of expected instruction(s):</em> <code>vand </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8081</ul> 8082 8083 <ul> 8084<li>uint64x2_t vandq_u64 (uint64x2_t, uint64x2_t) 8085<br><em>Form of expected instruction(s):</em> <code>vand </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8086</ul> 8087 8088 <ul> 8089<li>int64x2_t vandq_s64 (int64x2_t, int64x2_t) 8090<br><em>Form of expected instruction(s):</em> <code>vand </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8091</ul> 8092 8093<h5 class="subsubsection">6.54.3.77 Logical operations (OR)</h5> 8094 8095 <ul> 8096<li>uint32x2_t vorr_u32 (uint32x2_t, uint32x2_t) 8097<br><em>Form of expected instruction(s):</em> <code>vorr </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 8098</ul> 8099 8100 <ul> 8101<li>uint16x4_t vorr_u16 (uint16x4_t, uint16x4_t) 8102<br><em>Form of expected instruction(s):</em> <code>vorr </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 8103</ul> 8104 8105 <ul> 8106<li>uint8x8_t vorr_u8 (uint8x8_t, uint8x8_t) 8107<br><em>Form of expected instruction(s):</em> <code>vorr </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 8108</ul> 8109 8110 <ul> 8111<li>int32x2_t vorr_s32 (int32x2_t, int32x2_t) 8112<br><em>Form of expected instruction(s):</em> <code>vorr </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 8113</ul> 8114 8115 <ul> 8116<li>int16x4_t vorr_s16 (int16x4_t, int16x4_t) 8117<br><em>Form of expected instruction(s):</em> <code>vorr </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 8118</ul> 8119 8120 <ul> 8121<li>int8x8_t vorr_s8 (int8x8_t, int8x8_t) 8122<br><em>Form of expected instruction(s):</em> <code>vorr </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 8123</ul> 8124 8125 <ul> 8126<li>uint64x1_t vorr_u64 (uint64x1_t, uint64x1_t) 8127</ul> 8128 8129 <ul> 8130<li>int64x1_t vorr_s64 (int64x1_t, int64x1_t) 8131</ul> 8132 8133 <ul> 8134<li>uint32x4_t vorrq_u32 (uint32x4_t, uint32x4_t) 8135<br><em>Form of expected instruction(s):</em> <code>vorr </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8136</ul> 8137 8138 <ul> 8139<li>uint16x8_t vorrq_u16 (uint16x8_t, uint16x8_t) 8140<br><em>Form of expected instruction(s):</em> <code>vorr </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8141</ul> 8142 8143 <ul> 8144<li>uint8x16_t vorrq_u8 (uint8x16_t, uint8x16_t) 8145<br><em>Form of expected instruction(s):</em> <code>vorr </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8146</ul> 8147 8148 <ul> 8149<li>int32x4_t vorrq_s32 (int32x4_t, int32x4_t) 8150<br><em>Form of expected instruction(s):</em> <code>vorr </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8151</ul> 8152 8153 <ul> 8154<li>int16x8_t vorrq_s16 (int16x8_t, int16x8_t) 8155<br><em>Form of expected instruction(s):</em> <code>vorr </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8156</ul> 8157 8158 <ul> 8159<li>int8x16_t vorrq_s8 (int8x16_t, int8x16_t) 8160<br><em>Form of expected instruction(s):</em> <code>vorr </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8161</ul> 8162 8163 <ul> 8164<li>uint64x2_t vorrq_u64 (uint64x2_t, uint64x2_t) 8165<br><em>Form of expected instruction(s):</em> <code>vorr </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8166</ul> 8167 8168 <ul> 8169<li>int64x2_t vorrq_s64 (int64x2_t, int64x2_t) 8170<br><em>Form of expected instruction(s):</em> <code>vorr </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8171</ul> 8172 8173<h5 class="subsubsection">6.54.3.78 Logical operations (exclusive OR)</h5> 8174 8175 <ul> 8176<li>uint32x2_t veor_u32 (uint32x2_t, uint32x2_t) 8177<br><em>Form of expected instruction(s):</em> <code>veor </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 8178</ul> 8179 8180 <ul> 8181<li>uint16x4_t veor_u16 (uint16x4_t, uint16x4_t) 8182<br><em>Form of expected instruction(s):</em> <code>veor </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 8183</ul> 8184 8185 <ul> 8186<li>uint8x8_t veor_u8 (uint8x8_t, uint8x8_t) 8187<br><em>Form of expected instruction(s):</em> <code>veor </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 8188</ul> 8189 8190 <ul> 8191<li>int32x2_t veor_s32 (int32x2_t, int32x2_t) 8192<br><em>Form of expected instruction(s):</em> <code>veor </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 8193</ul> 8194 8195 <ul> 8196<li>int16x4_t veor_s16 (int16x4_t, int16x4_t) 8197<br><em>Form of expected instruction(s):</em> <code>veor </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 8198</ul> 8199 8200 <ul> 8201<li>int8x8_t veor_s8 (int8x8_t, int8x8_t) 8202<br><em>Form of expected instruction(s):</em> <code>veor </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 8203</ul> 8204 8205 <ul> 8206<li>uint64x1_t veor_u64 (uint64x1_t, uint64x1_t) 8207</ul> 8208 8209 <ul> 8210<li>int64x1_t veor_s64 (int64x1_t, int64x1_t) 8211</ul> 8212 8213 <ul> 8214<li>uint32x4_t veorq_u32 (uint32x4_t, uint32x4_t) 8215<br><em>Form of expected instruction(s):</em> <code>veor </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8216</ul> 8217 8218 <ul> 8219<li>uint16x8_t veorq_u16 (uint16x8_t, uint16x8_t) 8220<br><em>Form of expected instruction(s):</em> <code>veor </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8221</ul> 8222 8223 <ul> 8224<li>uint8x16_t veorq_u8 (uint8x16_t, uint8x16_t) 8225<br><em>Form of expected instruction(s):</em> <code>veor </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8226</ul> 8227 8228 <ul> 8229<li>int32x4_t veorq_s32 (int32x4_t, int32x4_t) 8230<br><em>Form of expected instruction(s):</em> <code>veor </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8231</ul> 8232 8233 <ul> 8234<li>int16x8_t veorq_s16 (int16x8_t, int16x8_t) 8235<br><em>Form of expected instruction(s):</em> <code>veor </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8236</ul> 8237 8238 <ul> 8239<li>int8x16_t veorq_s8 (int8x16_t, int8x16_t) 8240<br><em>Form of expected instruction(s):</em> <code>veor </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8241</ul> 8242 8243 <ul> 8244<li>uint64x2_t veorq_u64 (uint64x2_t, uint64x2_t) 8245<br><em>Form of expected instruction(s):</em> <code>veor </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8246</ul> 8247 8248 <ul> 8249<li>int64x2_t veorq_s64 (int64x2_t, int64x2_t) 8250<br><em>Form of expected instruction(s):</em> <code>veor </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8251</ul> 8252 8253<h5 class="subsubsection">6.54.3.79 Logical operations (AND-NOT)</h5> 8254 8255 <ul> 8256<li>uint32x2_t vbic_u32 (uint32x2_t, uint32x2_t) 8257<br><em>Form of expected instruction(s):</em> <code>vbic </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 8258</ul> 8259 8260 <ul> 8261<li>uint16x4_t vbic_u16 (uint16x4_t, uint16x4_t) 8262<br><em>Form of expected instruction(s):</em> <code>vbic </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 8263</ul> 8264 8265 <ul> 8266<li>uint8x8_t vbic_u8 (uint8x8_t, uint8x8_t) 8267<br><em>Form of expected instruction(s):</em> <code>vbic </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 8268</ul> 8269 8270 <ul> 8271<li>int32x2_t vbic_s32 (int32x2_t, int32x2_t) 8272<br><em>Form of expected instruction(s):</em> <code>vbic </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 8273</ul> 8274 8275 <ul> 8276<li>int16x4_t vbic_s16 (int16x4_t, int16x4_t) 8277<br><em>Form of expected instruction(s):</em> <code>vbic </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 8278</ul> 8279 8280 <ul> 8281<li>int8x8_t vbic_s8 (int8x8_t, int8x8_t) 8282<br><em>Form of expected instruction(s):</em> <code>vbic </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 8283</ul> 8284 8285 <ul> 8286<li>uint64x1_t vbic_u64 (uint64x1_t, uint64x1_t) 8287</ul> 8288 8289 <ul> 8290<li>int64x1_t vbic_s64 (int64x1_t, int64x1_t) 8291</ul> 8292 8293 <ul> 8294<li>uint32x4_t vbicq_u32 (uint32x4_t, uint32x4_t) 8295<br><em>Form of expected instruction(s):</em> <code>vbic </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8296</ul> 8297 8298 <ul> 8299<li>uint16x8_t vbicq_u16 (uint16x8_t, uint16x8_t) 8300<br><em>Form of expected instruction(s):</em> <code>vbic </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8301</ul> 8302 8303 <ul> 8304<li>uint8x16_t vbicq_u8 (uint8x16_t, uint8x16_t) 8305<br><em>Form of expected instruction(s):</em> <code>vbic </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8306</ul> 8307 8308 <ul> 8309<li>int32x4_t vbicq_s32 (int32x4_t, int32x4_t) 8310<br><em>Form of expected instruction(s):</em> <code>vbic </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8311</ul> 8312 8313 <ul> 8314<li>int16x8_t vbicq_s16 (int16x8_t, int16x8_t) 8315<br><em>Form of expected instruction(s):</em> <code>vbic </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8316</ul> 8317 8318 <ul> 8319<li>int8x16_t vbicq_s8 (int8x16_t, int8x16_t) 8320<br><em>Form of expected instruction(s):</em> <code>vbic </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8321</ul> 8322 8323 <ul> 8324<li>uint64x2_t vbicq_u64 (uint64x2_t, uint64x2_t) 8325<br><em>Form of expected instruction(s):</em> <code>vbic </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8326</ul> 8327 8328 <ul> 8329<li>int64x2_t vbicq_s64 (int64x2_t, int64x2_t) 8330<br><em>Form of expected instruction(s):</em> <code>vbic </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8331</ul> 8332 8333<h5 class="subsubsection">6.54.3.80 Logical operations (OR-NOT)</h5> 8334 8335 <ul> 8336<li>uint32x2_t vorn_u32 (uint32x2_t, uint32x2_t) 8337<br><em>Form of expected instruction(s):</em> <code>vorn </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 8338</ul> 8339 8340 <ul> 8341<li>uint16x4_t vorn_u16 (uint16x4_t, uint16x4_t) 8342<br><em>Form of expected instruction(s):</em> <code>vorn </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 8343</ul> 8344 8345 <ul> 8346<li>uint8x8_t vorn_u8 (uint8x8_t, uint8x8_t) 8347<br><em>Form of expected instruction(s):</em> <code>vorn </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 8348</ul> 8349 8350 <ul> 8351<li>int32x2_t vorn_s32 (int32x2_t, int32x2_t) 8352<br><em>Form of expected instruction(s):</em> <code>vorn </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 8353</ul> 8354 8355 <ul> 8356<li>int16x4_t vorn_s16 (int16x4_t, int16x4_t) 8357<br><em>Form of expected instruction(s):</em> <code>vorn </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 8358</ul> 8359 8360 <ul> 8361<li>int8x8_t vorn_s8 (int8x8_t, int8x8_t) 8362<br><em>Form of expected instruction(s):</em> <code>vorn </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> 8363</ul> 8364 8365 <ul> 8366<li>uint64x1_t vorn_u64 (uint64x1_t, uint64x1_t) 8367</ul> 8368 8369 <ul> 8370<li>int64x1_t vorn_s64 (int64x1_t, int64x1_t) 8371</ul> 8372 8373 <ul> 8374<li>uint32x4_t vornq_u32 (uint32x4_t, uint32x4_t) 8375<br><em>Form of expected instruction(s):</em> <code>vorn </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8376</ul> 8377 8378 <ul> 8379<li>uint16x8_t vornq_u16 (uint16x8_t, uint16x8_t) 8380<br><em>Form of expected instruction(s):</em> <code>vorn </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8381</ul> 8382 8383 <ul> 8384<li>uint8x16_t vornq_u8 (uint8x16_t, uint8x16_t) 8385<br><em>Form of expected instruction(s):</em> <code>vorn </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8386</ul> 8387 8388 <ul> 8389<li>int32x4_t vornq_s32 (int32x4_t, int32x4_t) 8390<br><em>Form of expected instruction(s):</em> <code>vorn </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8391</ul> 8392 8393 <ul> 8394<li>int16x8_t vornq_s16 (int16x8_t, int16x8_t) 8395<br><em>Form of expected instruction(s):</em> <code>vorn </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8396</ul> 8397 8398 <ul> 8399<li>int8x16_t vornq_s8 (int8x16_t, int8x16_t) 8400<br><em>Form of expected instruction(s):</em> <code>vorn </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8401</ul> 8402 8403 <ul> 8404<li>uint64x2_t vornq_u64 (uint64x2_t, uint64x2_t) 8405<br><em>Form of expected instruction(s):</em> <code>vorn </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8406</ul> 8407 8408 <ul> 8409<li>int64x2_t vornq_s64 (int64x2_t, int64x2_t) 8410<br><em>Form of expected instruction(s):</em> <code>vorn </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> 8411</ul> 8412 8413<h5 class="subsubsection">6.54.3.81 Reinterpret casts</h5> 8414 8415 <ul> 8416<li>poly8x8_t vreinterpret_p8_u32 (uint32x2_t) 8417</ul> 8418 8419 <ul> 8420<li>poly8x8_t vreinterpret_p8_u16 (uint16x4_t) 8421</ul> 8422 8423 <ul> 8424<li>poly8x8_t vreinterpret_p8_u8 (uint8x8_t) 8425</ul> 8426 8427 <ul> 8428<li>poly8x8_t vreinterpret_p8_s32 (int32x2_t) 8429</ul> 8430 8431 <ul> 8432<li>poly8x8_t vreinterpret_p8_s16 (int16x4_t) 8433</ul> 8434 8435 <ul> 8436<li>poly8x8_t vreinterpret_p8_s8 (int8x8_t) 8437</ul> 8438 8439 <ul> 8440<li>poly8x8_t vreinterpret_p8_u64 (uint64x1_t) 8441</ul> 8442 8443 <ul> 8444<li>poly8x8_t vreinterpret_p8_s64 (int64x1_t) 8445</ul> 8446 8447 <ul> 8448<li>poly8x8_t vreinterpret_p8_f32 (float32x2_t) 8449</ul> 8450 8451 <ul> 8452<li>poly8x8_t vreinterpret_p8_p16 (poly16x4_t) 8453</ul> 8454 8455 <ul> 8456<li>poly8x16_t vreinterpretq_p8_u32 (uint32x4_t) 8457</ul> 8458 8459 <ul> 8460<li>poly8x16_t vreinterpretq_p8_u16 (uint16x8_t) 8461</ul> 8462 8463 <ul> 8464<li>poly8x16_t vreinterpretq_p8_u8 (uint8x16_t) 8465</ul> 8466 8467 <ul> 8468<li>poly8x16_t vreinterpretq_p8_s32 (int32x4_t) 8469</ul> 8470 8471 <ul> 8472<li>poly8x16_t vreinterpretq_p8_s16 (int16x8_t) 8473</ul> 8474 8475 <ul> 8476<li>poly8x16_t vreinterpretq_p8_s8 (int8x16_t) 8477</ul> 8478 8479 <ul> 8480<li>poly8x16_t vreinterpretq_p8_u64 (uint64x2_t) 8481</ul> 8482 8483 <ul> 8484<li>poly8x16_t vreinterpretq_p8_s64 (int64x2_t) 8485</ul> 8486 8487 <ul> 8488<li>poly8x16_t vreinterpretq_p8_f32 (float32x4_t) 8489</ul> 8490 8491 <ul> 8492<li>poly8x16_t vreinterpretq_p8_p16 (poly16x8_t) 8493</ul> 8494 8495 <ul> 8496<li>poly16x4_t vreinterpret_p16_u32 (uint32x2_t) 8497</ul> 8498 8499 <ul> 8500<li>poly16x4_t vreinterpret_p16_u16 (uint16x4_t) 8501</ul> 8502 8503 <ul> 8504<li>poly16x4_t vreinterpret_p16_u8 (uint8x8_t) 8505</ul> 8506 8507 <ul> 8508<li>poly16x4_t vreinterpret_p16_s32 (int32x2_t) 8509</ul> 8510 8511 <ul> 8512<li>poly16x4_t vreinterpret_p16_s16 (int16x4_t) 8513</ul> 8514 8515 <ul> 8516<li>poly16x4_t vreinterpret_p16_s8 (int8x8_t) 8517</ul> 8518 8519 <ul> 8520<li>poly16x4_t vreinterpret_p16_u64 (uint64x1_t) 8521</ul> 8522 8523 <ul> 8524<li>poly16x4_t vreinterpret_p16_s64 (int64x1_t) 8525</ul> 8526 8527 <ul> 8528<li>poly16x4_t vreinterpret_p16_f32 (float32x2_t) 8529</ul> 8530 8531 <ul> 8532<li>poly16x4_t vreinterpret_p16_p8 (poly8x8_t) 8533</ul> 8534 8535 <ul> 8536<li>poly16x8_t vreinterpretq_p16_u32 (uint32x4_t) 8537</ul> 8538 8539 <ul> 8540<li>poly16x8_t vreinterpretq_p16_u16 (uint16x8_t) 8541</ul> 8542 8543 <ul> 8544<li>poly16x8_t vreinterpretq_p16_u8 (uint8x16_t) 8545</ul> 8546 8547 <ul> 8548<li>poly16x8_t vreinterpretq_p16_s32 (int32x4_t) 8549</ul> 8550 8551 <ul> 8552<li>poly16x8_t vreinterpretq_p16_s16 (int16x8_t) 8553</ul> 8554 8555 <ul> 8556<li>poly16x8_t vreinterpretq_p16_s8 (int8x16_t) 8557</ul> 8558 8559 <ul> 8560<li>poly16x8_t vreinterpretq_p16_u64 (uint64x2_t) 8561</ul> 8562 8563 <ul> 8564<li>poly16x8_t vreinterpretq_p16_s64 (int64x2_t) 8565</ul> 8566 8567 <ul> 8568<li>poly16x8_t vreinterpretq_p16_f32 (float32x4_t) 8569</ul> 8570 8571 <ul> 8572<li>poly16x8_t vreinterpretq_p16_p8 (poly8x16_t) 8573</ul> 8574 8575 <ul> 8576<li>float32x2_t vreinterpret_f32_u32 (uint32x2_t) 8577</ul> 8578 8579 <ul> 8580<li>float32x2_t vreinterpret_f32_u16 (uint16x4_t) 8581</ul> 8582 8583 <ul> 8584<li>float32x2_t vreinterpret_f32_u8 (uint8x8_t) 8585</ul> 8586 8587 <ul> 8588<li>float32x2_t vreinterpret_f32_s32 (int32x2_t) 8589</ul> 8590 8591 <ul> 8592<li>float32x2_t vreinterpret_f32_s16 (int16x4_t) 8593</ul> 8594 8595 <ul> 8596<li>float32x2_t vreinterpret_f32_s8 (int8x8_t) 8597</ul> 8598 8599 <ul> 8600<li>float32x2_t vreinterpret_f32_u64 (uint64x1_t) 8601</ul> 8602 8603 <ul> 8604<li>float32x2_t vreinterpret_f32_s64 (int64x1_t) 8605</ul> 8606 8607 <ul> 8608<li>float32x2_t vreinterpret_f32_p16 (poly16x4_t) 8609</ul> 8610 8611 <ul> 8612<li>float32x2_t vreinterpret_f32_p8 (poly8x8_t) 8613</ul> 8614 8615 <ul> 8616<li>float32x4_t vreinterpretq_f32_u32 (uint32x4_t) 8617</ul> 8618 8619 <ul> 8620<li>float32x4_t vreinterpretq_f32_u16 (uint16x8_t) 8621</ul> 8622 8623 <ul> 8624<li>float32x4_t vreinterpretq_f32_u8 (uint8x16_t) 8625</ul> 8626 8627 <ul> 8628<li>float32x4_t vreinterpretq_f32_s32 (int32x4_t) 8629</ul> 8630 8631 <ul> 8632<li>float32x4_t vreinterpretq_f32_s16 (int16x8_t) 8633</ul> 8634 8635 <ul> 8636<li>float32x4_t vreinterpretq_f32_s8 (int8x16_t) 8637</ul> 8638 8639 <ul> 8640<li>float32x4_t vreinterpretq_f32_u64 (uint64x2_t) 8641</ul> 8642 8643 <ul> 8644<li>float32x4_t vreinterpretq_f32_s64 (int64x2_t) 8645</ul> 8646 8647 <ul> 8648<li>float32x4_t vreinterpretq_f32_p16 (poly16x8_t) 8649</ul> 8650 8651 <ul> 8652<li>float32x4_t vreinterpretq_f32_p8 (poly8x16_t) 8653</ul> 8654 8655 <ul> 8656<li>int64x1_t vreinterpret_s64_u32 (uint32x2_t) 8657</ul> 8658 8659 <ul> 8660<li>int64x1_t vreinterpret_s64_u16 (uint16x4_t) 8661</ul> 8662 8663 <ul> 8664<li>int64x1_t vreinterpret_s64_u8 (uint8x8_t) 8665</ul> 8666 8667 <ul> 8668<li>int64x1_t vreinterpret_s64_s32 (int32x2_t) 8669</ul> 8670 8671 <ul> 8672<li>int64x1_t vreinterpret_s64_s16 (int16x4_t) 8673</ul> 8674 8675 <ul> 8676<li>int64x1_t vreinterpret_s64_s8 (int8x8_t) 8677</ul> 8678 8679 <ul> 8680<li>int64x1_t vreinterpret_s64_u64 (uint64x1_t) 8681</ul> 8682 8683 <ul> 8684<li>int64x1_t vreinterpret_s64_f32 (float32x2_t) 8685</ul> 8686 8687 <ul> 8688<li>int64x1_t vreinterpret_s64_p16 (poly16x4_t) 8689</ul> 8690 8691 <ul> 8692<li>int64x1_t vreinterpret_s64_p8 (poly8x8_t) 8693</ul> 8694 8695 <ul> 8696<li>int64x2_t vreinterpretq_s64_u32 (uint32x4_t) 8697</ul> 8698 8699 <ul> 8700<li>int64x2_t vreinterpretq_s64_u16 (uint16x8_t) 8701</ul> 8702 8703 <ul> 8704<li>int64x2_t vreinterpretq_s64_u8 (uint8x16_t) 8705</ul> 8706 8707 <ul> 8708<li>int64x2_t vreinterpretq_s64_s32 (int32x4_t) 8709</ul> 8710 8711 <ul> 8712<li>int64x2_t vreinterpretq_s64_s16 (int16x8_t) 8713</ul> 8714 8715 <ul> 8716<li>int64x2_t vreinterpretq_s64_s8 (int8x16_t) 8717</ul> 8718 8719 <ul> 8720<li>int64x2_t vreinterpretq_s64_u64 (uint64x2_t) 8721</ul> 8722 8723 <ul> 8724<li>int64x2_t vreinterpretq_s64_f32 (float32x4_t) 8725</ul> 8726 8727 <ul> 8728<li>int64x2_t vreinterpretq_s64_p16 (poly16x8_t) 8729</ul> 8730 8731 <ul> 8732<li>int64x2_t vreinterpretq_s64_p8 (poly8x16_t) 8733</ul> 8734 8735 <ul> 8736<li>uint64x1_t vreinterpret_u64_u32 (uint32x2_t) 8737</ul> 8738 8739 <ul> 8740<li>uint64x1_t vreinterpret_u64_u16 (uint16x4_t) 8741</ul> 8742 8743 <ul> 8744<li>uint64x1_t vreinterpret_u64_u8 (uint8x8_t) 8745</ul> 8746 8747 <ul> 8748<li>uint64x1_t vreinterpret_u64_s32 (int32x2_t) 8749</ul> 8750 8751 <ul> 8752<li>uint64x1_t vreinterpret_u64_s16 (int16x4_t) 8753</ul> 8754 8755 <ul> 8756<li>uint64x1_t vreinterpret_u64_s8 (int8x8_t) 8757</ul> 8758 8759 <ul> 8760<li>uint64x1_t vreinterpret_u64_s64 (int64x1_t) 8761</ul> 8762 8763 <ul> 8764<li>uint64x1_t vreinterpret_u64_f32 (float32x2_t) 8765</ul> 8766 8767 <ul> 8768<li>uint64x1_t vreinterpret_u64_p16 (poly16x4_t) 8769</ul> 8770 8771 <ul> 8772<li>uint64x1_t vreinterpret_u64_p8 (poly8x8_t) 8773</ul> 8774 8775 <ul> 8776<li>uint64x2_t vreinterpretq_u64_u32 (uint32x4_t) 8777</ul> 8778 8779 <ul> 8780<li>uint64x2_t vreinterpretq_u64_u16 (uint16x8_t) 8781</ul> 8782 8783 <ul> 8784<li>uint64x2_t vreinterpretq_u64_u8 (uint8x16_t) 8785</ul> 8786 8787 <ul> 8788<li>uint64x2_t vreinterpretq_u64_s32 (int32x4_t) 8789</ul> 8790 8791 <ul> 8792<li>uint64x2_t vreinterpretq_u64_s16 (int16x8_t) 8793</ul> 8794 8795 <ul> 8796<li>uint64x2_t vreinterpretq_u64_s8 (int8x16_t) 8797</ul> 8798 8799 <ul> 8800<li>uint64x2_t vreinterpretq_u64_s64 (int64x2_t) 8801</ul> 8802 8803 <ul> 8804<li>uint64x2_t vreinterpretq_u64_f32 (float32x4_t) 8805</ul> 8806 8807 <ul> 8808<li>uint64x2_t vreinterpretq_u64_p16 (poly16x8_t) 8809</ul> 8810 8811 <ul> 8812<li>uint64x2_t vreinterpretq_u64_p8 (poly8x16_t) 8813</ul> 8814 8815 <ul> 8816<li>int8x8_t vreinterpret_s8_u32 (uint32x2_t) 8817</ul> 8818 8819 <ul> 8820<li>int8x8_t vreinterpret_s8_u16 (uint16x4_t) 8821</ul> 8822 8823 <ul> 8824<li>int8x8_t vreinterpret_s8_u8 (uint8x8_t) 8825</ul> 8826 8827 <ul> 8828<li>int8x8_t vreinterpret_s8_s32 (int32x2_t) 8829</ul> 8830 8831 <ul> 8832<li>int8x8_t vreinterpret_s8_s16 (int16x4_t) 8833</ul> 8834 8835 <ul> 8836<li>int8x8_t vreinterpret_s8_u64 (uint64x1_t) 8837</ul> 8838 8839 <ul> 8840<li>int8x8_t vreinterpret_s8_s64 (int64x1_t) 8841</ul> 8842 8843 <ul> 8844<li>int8x8_t vreinterpret_s8_f32 (float32x2_t) 8845</ul> 8846 8847 <ul> 8848<li>int8x8_t vreinterpret_s8_p16 (poly16x4_t) 8849</ul> 8850 8851 <ul> 8852<li>int8x8_t vreinterpret_s8_p8 (poly8x8_t) 8853</ul> 8854 8855 <ul> 8856<li>int8x16_t vreinterpretq_s8_u32 (uint32x4_t) 8857</ul> 8858 8859 <ul> 8860<li>int8x16_t vreinterpretq_s8_u16 (uint16x8_t) 8861</ul> 8862 8863 <ul> 8864<li>int8x16_t vreinterpretq_s8_u8 (uint8x16_t) 8865</ul> 8866 8867 <ul> 8868<li>int8x16_t vreinterpretq_s8_s32 (int32x4_t) 8869</ul> 8870 8871 <ul> 8872<li>int8x16_t vreinterpretq_s8_s16 (int16x8_t) 8873</ul> 8874 8875 <ul> 8876<li>int8x16_t vreinterpretq_s8_u64 (uint64x2_t) 8877</ul> 8878 8879 <ul> 8880<li>int8x16_t vreinterpretq_s8_s64 (int64x2_t) 8881</ul> 8882 8883 <ul> 8884<li>int8x16_t vreinterpretq_s8_f32 (float32x4_t) 8885</ul> 8886 8887 <ul> 8888<li>int8x16_t vreinterpretq_s8_p16 (poly16x8_t) 8889</ul> 8890 8891 <ul> 8892<li>int8x16_t vreinterpretq_s8_p8 (poly8x16_t) 8893</ul> 8894 8895 <ul> 8896<li>int16x4_t vreinterpret_s16_u32 (uint32x2_t) 8897</ul> 8898 8899 <ul> 8900<li>int16x4_t vreinterpret_s16_u16 (uint16x4_t) 8901</ul> 8902 8903 <ul> 8904<li>int16x4_t vreinterpret_s16_u8 (uint8x8_t) 8905</ul> 8906 8907 <ul> 8908<li>int16x4_t vreinterpret_s16_s32 (int32x2_t) 8909</ul> 8910 8911 <ul> 8912<li>int16x4_t vreinterpret_s16_s8 (int8x8_t) 8913</ul> 8914 8915 <ul> 8916<li>int16x4_t vreinterpret_s16_u64 (uint64x1_t) 8917</ul> 8918 8919 <ul> 8920<li>int16x4_t vreinterpret_s16_s64 (int64x1_t) 8921</ul> 8922 8923 <ul> 8924<li>int16x4_t vreinterpret_s16_f32 (float32x2_t) 8925</ul> 8926 8927 <ul> 8928<li>int16x4_t vreinterpret_s16_p16 (poly16x4_t) 8929</ul> 8930 8931 <ul> 8932<li>int16x4_t vreinterpret_s16_p8 (poly8x8_t) 8933</ul> 8934 8935 <ul> 8936<li>int16x8_t vreinterpretq_s16_u32 (uint32x4_t) 8937</ul> 8938 8939 <ul> 8940<li>int16x8_t vreinterpretq_s16_u16 (uint16x8_t) 8941</ul> 8942 8943 <ul> 8944<li>int16x8_t vreinterpretq_s16_u8 (uint8x16_t) 8945</ul> 8946 8947 <ul> 8948<li>int16x8_t vreinterpretq_s16_s32 (int32x4_t) 8949</ul> 8950 8951 <ul> 8952<li>int16x8_t vreinterpretq_s16_s8 (int8x16_t) 8953</ul> 8954 8955 <ul> 8956<li>int16x8_t vreinterpretq_s16_u64 (uint64x2_t) 8957</ul> 8958 8959 <ul> 8960<li>int16x8_t vreinterpretq_s16_s64 (int64x2_t) 8961</ul> 8962 8963 <ul> 8964<li>int16x8_t vreinterpretq_s16_f32 (float32x4_t) 8965</ul> 8966 8967 <ul> 8968<li>int16x8_t vreinterpretq_s16_p16 (poly16x8_t) 8969</ul> 8970 8971 <ul> 8972<li>int16x8_t vreinterpretq_s16_p8 (poly8x16_t) 8973</ul> 8974 8975 <ul> 8976<li>int32x2_t vreinterpret_s32_u32 (uint32x2_t) 8977</ul> 8978 8979 <ul> 8980<li>int32x2_t vreinterpret_s32_u16 (uint16x4_t) 8981</ul> 8982 8983 <ul> 8984<li>int32x2_t vreinterpret_s32_u8 (uint8x8_t) 8985</ul> 8986 8987 <ul> 8988<li>int32x2_t vreinterpret_s32_s16 (int16x4_t) 8989</ul> 8990 8991 <ul> 8992<li>int32x2_t vreinterpret_s32_s8 (int8x8_t) 8993</ul> 8994 8995 <ul> 8996<li>int32x2_t vreinterpret_s32_u64 (uint64x1_t) 8997</ul> 8998 8999 <ul> 9000<li>int32x2_t vreinterpret_s32_s64 (int64x1_t) 9001</ul> 9002 9003 <ul> 9004<li>int32x2_t vreinterpret_s32_f32 (float32x2_t) 9005</ul> 9006 9007 <ul> 9008<li>int32x2_t vreinterpret_s32_p16 (poly16x4_t) 9009</ul> 9010 9011 <ul> 9012<li>int32x2_t vreinterpret_s32_p8 (poly8x8_t) 9013</ul> 9014 9015 <ul> 9016<li>int32x4_t vreinterpretq_s32_u32 (uint32x4_t) 9017</ul> 9018 9019 <ul> 9020<li>int32x4_t vreinterpretq_s32_u16 (uint16x8_t) 9021</ul> 9022 9023 <ul> 9024<li>int32x4_t vreinterpretq_s32_u8 (uint8x16_t) 9025</ul> 9026 9027 <ul> 9028<li>int32x4_t vreinterpretq_s32_s16 (int16x8_t) 9029</ul> 9030 9031 <ul> 9032<li>int32x4_t vreinterpretq_s32_s8 (int8x16_t) 9033</ul> 9034 9035 <ul> 9036<li>int32x4_t vreinterpretq_s32_u64 (uint64x2_t) 9037</ul> 9038 9039 <ul> 9040<li>int32x4_t vreinterpretq_s32_s64 (int64x2_t) 9041</ul> 9042 9043 <ul> 9044<li>int32x4_t vreinterpretq_s32_f32 (float32x4_t) 9045</ul> 9046 9047 <ul> 9048<li>int32x4_t vreinterpretq_s32_p16 (poly16x8_t) 9049</ul> 9050 9051 <ul> 9052<li>int32x4_t vreinterpretq_s32_p8 (poly8x16_t) 9053</ul> 9054 9055 <ul> 9056<li>uint8x8_t vreinterpret_u8_u32 (uint32x2_t) 9057</ul> 9058 9059 <ul> 9060<li>uint8x8_t vreinterpret_u8_u16 (uint16x4_t) 9061</ul> 9062 9063 <ul> 9064<li>uint8x8_t vreinterpret_u8_s32 (int32x2_t) 9065</ul> 9066 9067 <ul> 9068<li>uint8x8_t vreinterpret_u8_s16 (int16x4_t) 9069</ul> 9070 9071 <ul> 9072<li>uint8x8_t vreinterpret_u8_s8 (int8x8_t) 9073</ul> 9074 9075 <ul> 9076<li>uint8x8_t vreinterpret_u8_u64 (uint64x1_t) 9077</ul> 9078 9079 <ul> 9080<li>uint8x8_t vreinterpret_u8_s64 (int64x1_t) 9081</ul> 9082 9083 <ul> 9084<li>uint8x8_t vreinterpret_u8_f32 (float32x2_t) 9085</ul> 9086 9087 <ul> 9088<li>uint8x8_t vreinterpret_u8_p16 (poly16x4_t) 9089</ul> 9090 9091 <ul> 9092<li>uint8x8_t vreinterpret_u8_p8 (poly8x8_t) 9093</ul> 9094 9095 <ul> 9096<li>uint8x16_t vreinterpretq_u8_u32 (uint32x4_t) 9097</ul> 9098 9099 <ul> 9100<li>uint8x16_t vreinterpretq_u8_u16 (uint16x8_t) 9101</ul> 9102 9103 <ul> 9104<li>uint8x16_t vreinterpretq_u8_s32 (int32x4_t) 9105</ul> 9106 9107 <ul> 9108<li>uint8x16_t vreinterpretq_u8_s16 (int16x8_t) 9109</ul> 9110 9111 <ul> 9112<li>uint8x16_t vreinterpretq_u8_s8 (int8x16_t) 9113</ul> 9114 9115 <ul> 9116<li>uint8x16_t vreinterpretq_u8_u64 (uint64x2_t) 9117</ul> 9118 9119 <ul> 9120<li>uint8x16_t vreinterpretq_u8_s64 (int64x2_t) 9121</ul> 9122 9123 <ul> 9124<li>uint8x16_t vreinterpretq_u8_f32 (float32x4_t) 9125</ul> 9126 9127 <ul> 9128<li>uint8x16_t vreinterpretq_u8_p16 (poly16x8_t) 9129</ul> 9130 9131 <ul> 9132<li>uint8x16_t vreinterpretq_u8_p8 (poly8x16_t) 9133</ul> 9134 9135 <ul> 9136<li>uint16x4_t vreinterpret_u16_u32 (uint32x2_t) 9137</ul> 9138 9139 <ul> 9140<li>uint16x4_t vreinterpret_u16_u8 (uint8x8_t) 9141</ul> 9142 9143 <ul> 9144<li>uint16x4_t vreinterpret_u16_s32 (int32x2_t) 9145</ul> 9146 9147 <ul> 9148<li>uint16x4_t vreinterpret_u16_s16 (int16x4_t) 9149</ul> 9150 9151 <ul> 9152<li>uint16x4_t vreinterpret_u16_s8 (int8x8_t) 9153</ul> 9154 9155 <ul> 9156<li>uint16x4_t vreinterpret_u16_u64 (uint64x1_t) 9157</ul> 9158 9159 <ul> 9160<li>uint16x4_t vreinterpret_u16_s64 (int64x1_t) 9161</ul> 9162 9163 <ul> 9164<li>uint16x4_t vreinterpret_u16_f32 (float32x2_t) 9165</ul> 9166 9167 <ul> 9168<li>uint16x4_t vreinterpret_u16_p16 (poly16x4_t) 9169</ul> 9170 9171 <ul> 9172<li>uint16x4_t vreinterpret_u16_p8 (poly8x8_t) 9173</ul> 9174 9175 <ul> 9176<li>uint16x8_t vreinterpretq_u16_u32 (uint32x4_t) 9177</ul> 9178 9179 <ul> 9180<li>uint16x8_t vreinterpretq_u16_u8 (uint8x16_t) 9181</ul> 9182 9183 <ul> 9184<li>uint16x8_t vreinterpretq_u16_s32 (int32x4_t) 9185</ul> 9186 9187 <ul> 9188<li>uint16x8_t vreinterpretq_u16_s16 (int16x8_t) 9189</ul> 9190 9191 <ul> 9192<li>uint16x8_t vreinterpretq_u16_s8 (int8x16_t) 9193</ul> 9194 9195 <ul> 9196<li>uint16x8_t vreinterpretq_u16_u64 (uint64x2_t) 9197</ul> 9198 9199 <ul> 9200<li>uint16x8_t vreinterpretq_u16_s64 (int64x2_t) 9201</ul> 9202 9203 <ul> 9204<li>uint16x8_t vreinterpretq_u16_f32 (float32x4_t) 9205</ul> 9206 9207 <ul> 9208<li>uint16x8_t vreinterpretq_u16_p16 (poly16x8_t) 9209</ul> 9210 9211 <ul> 9212<li>uint16x8_t vreinterpretq_u16_p8 (poly8x16_t) 9213</ul> 9214 9215 <ul> 9216<li>uint32x2_t vreinterpret_u32_u16 (uint16x4_t) 9217</ul> 9218 9219 <ul> 9220<li>uint32x2_t vreinterpret_u32_u8 (uint8x8_t) 9221</ul> 9222 9223 <ul> 9224<li>uint32x2_t vreinterpret_u32_s32 (int32x2_t) 9225</ul> 9226 9227 <ul> 9228<li>uint32x2_t vreinterpret_u32_s16 (int16x4_t) 9229</ul> 9230 9231 <ul> 9232<li>uint32x2_t vreinterpret_u32_s8 (int8x8_t) 9233</ul> 9234 9235 <ul> 9236<li>uint32x2_t vreinterpret_u32_u64 (uint64x1_t) 9237</ul> 9238 9239 <ul> 9240<li>uint32x2_t vreinterpret_u32_s64 (int64x1_t) 9241</ul> 9242 9243 <ul> 9244<li>uint32x2_t vreinterpret_u32_f32 (float32x2_t) 9245</ul> 9246 9247 <ul> 9248<li>uint32x2_t vreinterpret_u32_p16 (poly16x4_t) 9249</ul> 9250 9251 <ul> 9252<li>uint32x2_t vreinterpret_u32_p8 (poly8x8_t) 9253</ul> 9254 9255 <ul> 9256<li>uint32x4_t vreinterpretq_u32_u16 (uint16x8_t) 9257</ul> 9258 9259 <ul> 9260<li>uint32x4_t vreinterpretq_u32_u8 (uint8x16_t) 9261</ul> 9262 9263 <ul> 9264<li>uint32x4_t vreinterpretq_u32_s32 (int32x4_t) 9265</ul> 9266 9267 <ul> 9268<li>uint32x4_t vreinterpretq_u32_s16 (int16x8_t) 9269</ul> 9270 9271 <ul> 9272<li>uint32x4_t vreinterpretq_u32_s8 (int8x16_t) 9273</ul> 9274 9275 <ul> 9276<li>uint32x4_t vreinterpretq_u32_u64 (uint64x2_t) 9277</ul> 9278 9279 <ul> 9280<li>uint32x4_t vreinterpretq_u32_s64 (int64x2_t) 9281</ul> 9282 9283 <ul> 9284<li>uint32x4_t vreinterpretq_u32_f32 (float32x4_t) 9285</ul> 9286 9287 <ul> 9288<li>uint32x4_t vreinterpretq_u32_p16 (poly16x8_t) 9289</ul> 9290 9291 <ul> 9292<li>uint32x4_t vreinterpretq_u32_p8 (poly8x16_t) 9293</ul> 9294 9295 </body></html> 9296 9297