1/* Definitions of target machine for GNU compiler, for ARM. 2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 4 Free Software Foundation, Inc. 5 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) 6 and Martin Simmons (@harleqn.co.uk). 7 More major hacks by Richard Earnshaw (rearnsha@arm.com) 8 Minor hacks by Nick Clifton (nickc@cygnus.com) 9 10 This file is part of GCC. 11 12 GCC is free software; you can redistribute it and/or modify it 13 under the terms of the GNU General Public License as published 14 by the Free Software Foundation; either version 3, or (at your 15 option) any later version. 16 17 GCC is distributed in the hope that it will be useful, but WITHOUT 18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 19 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 20 License for more details. 21 22 You should have received a copy of the GNU General Public License 23 along with GCC; see the file COPYING3. If not see 24 <http://www.gnu.org/licenses/>. */ 25 26#ifndef GCC_ARM_H 27#define GCC_ARM_H 28 29/* We can't use enum machine_mode inside a generator file because it 30 hasn't been created yet; we shouldn't be using any code that 31 needs the real definition though, so this ought to be safe. */ 32#ifdef GENERATOR_FILE 33#define MACHMODE int 34#else 35#include "insn-modes.h" 36#define MACHMODE enum machine_mode 37#endif 38 39#include "config/vxworks-dummy.h" 40 41/* The architecture define. */ 42extern char arm_arch_name[]; 43 44/* Target CPU builtins. */ 45#define TARGET_CPU_CPP_BUILTINS() \ 46 do \ 47 { \ 48 /* Define __arm__ even when in thumb mode, for \ 49 consistency with armcc. */ \ 50 builtin_define ("__arm__"); \ 51 builtin_define ("__APCS_32__"); \ 52 if (TARGET_THUMB) \ 53 builtin_define ("__thumb__"); \ 54 if (TARGET_THUMB2) \ 55 builtin_define ("__thumb2__"); \ 56 \ 57 if (TARGET_BIG_END) \ 58 { \ 59 builtin_define ("__ARMEB__"); \ 60 if (TARGET_THUMB) \ 61 builtin_define ("__THUMBEB__"); \ 62 if (TARGET_LITTLE_WORDS) \ 63 builtin_define ("__ARMWEL__"); \ 64 } \ 65 else \ 66 { \ 67 builtin_define ("__ARMEL__"); \ 68 if (TARGET_THUMB) \ 69 builtin_define ("__THUMBEL__"); \ 70 } \ 71 \ 72 if (TARGET_SOFT_FLOAT) \ 73 builtin_define ("__SOFTFP__"); \ 74 \ 75 if (TARGET_VFP) \ 76 builtin_define ("__VFP_FP__"); \ 77 \ 78 if (TARGET_NEON) \ 79 builtin_define ("__ARM_NEON__"); \ 80 \ 81 /* Add a define for interworking. \ 82 Needed when building libgcc.a. */ \ 83 if (arm_cpp_interwork) \ 84 builtin_define ("__THUMB_INTERWORK__"); \ 85 \ 86 builtin_assert ("cpu=arm"); \ 87 builtin_assert ("machine=arm"); \ 88 \ 89 builtin_define (arm_arch_name); \ 90 if (arm_arch_cirrus) \ 91 builtin_define ("__MAVERICK__"); \ 92 if (arm_arch_xscale) \ 93 builtin_define ("__XSCALE__"); \ 94 if (arm_arch_iwmmxt) \ 95 builtin_define ("__IWMMXT__"); \ 96 if (TARGET_AAPCS_BASED) \ 97 { \ 98 if (arm_pcs_default == ARM_PCS_AAPCS_VFP) \ 99 builtin_define ("__ARM_PCS_VFP"); \ 100 else if (arm_pcs_default == ARM_PCS_AAPCS) \ 101 builtin_define ("__ARM_PCS"); \ 102 builtin_define ("__ARM_EABI__"); \ 103 } \ 104 if (TARGET_IDIV) \ 105 builtin_define ("__ARM_ARCH_EXT_IDIV__"); \ 106 } while (0) 107 108/* The various ARM cores. */ 109enum processor_type 110{ 111#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \ 112 IDENT, 113#include "arm-cores.def" 114#undef ARM_CORE 115 /* Used to indicate that no processor has been specified. */ 116 arm_none 117}; 118 119enum target_cpus 120{ 121#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \ 122 TARGET_CPU_##IDENT, 123#include "arm-cores.def" 124#undef ARM_CORE 125 TARGET_CPU_generic 126}; 127 128/* The processor for which instructions should be scheduled. */ 129extern enum processor_type arm_tune; 130 131enum arm_sync_generator_tag 132 { 133 arm_sync_generator_omn, 134 arm_sync_generator_omrn 135 }; 136 137/* Wrapper to pass around a polymorphic pointer to a sync instruction 138 generator and. */ 139struct arm_sync_generator 140{ 141 enum arm_sync_generator_tag op; 142 union 143 { 144 rtx (* omn) (rtx, rtx, rtx); 145 rtx (* omrn) (rtx, rtx, rtx, rtx); 146 } u; 147}; 148 149typedef enum arm_cond_code 150{ 151 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, 152 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV 153} 154arm_cc; 155 156extern arm_cc arm_current_cc; 157 158#define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1)) 159 160extern int arm_target_label; 161extern int arm_ccfsm_state; 162extern GTY(()) rtx arm_target_insn; 163/* The label of the current constant pool. */ 164extern rtx pool_vector_label; 165/* Set to 1 when a return insn is output, this means that the epilogue 166 is not needed. */ 167extern int return_used_this_function; 168/* Callback to output language specific object attributes. */ 169extern void (*arm_lang_output_object_attributes_hook)(void); 170 171/* Just in case configure has failed to define anything. */ 172#ifndef TARGET_CPU_DEFAULT 173#define TARGET_CPU_DEFAULT TARGET_CPU_generic 174#endif 175 176 177#undef CPP_SPEC 178#define CPP_SPEC "%(subtarget_cpp_spec) \ 179%{msoft-float:%{mhard-float: \ 180 %e-msoft-float and -mhard_float may not be used together}} \ 181%{mbig-endian:%{mlittle-endian: \ 182 %e-mbig-endian and -mlittle-endian may not be used together}}" 183 184#ifndef CC1_SPEC 185#define CC1_SPEC "" 186#endif 187 188/* This macro defines names of additional specifications to put in the specs 189 that can be used in various specifications like CC1_SPEC. Its definition 190 is an initializer with a subgrouping for each command option. 191 192 Each subgrouping contains a string constant, that defines the 193 specification name, and a string constant that used by the GCC driver 194 program. 195 196 Do not define this macro if it does not need to do anything. */ 197#define EXTRA_SPECS \ 198 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ 199 SUBTARGET_EXTRA_SPECS 200 201#ifndef SUBTARGET_EXTRA_SPECS 202#define SUBTARGET_EXTRA_SPECS 203#endif 204 205#ifndef SUBTARGET_CPP_SPEC 206#define SUBTARGET_CPP_SPEC "" 207#endif 208 209/* Run-time Target Specification. */ 210#ifndef TARGET_VERSION 211#define TARGET_VERSION fputs (" (ARM/generic)", stderr); 212#endif 213 214#define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT) 215/* Use hardware floating point instructions. */ 216#define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT) 217/* Use hardware floating point calling convention. */ 218#define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD) 219#define TARGET_FPA (arm_fpu_desc->model == ARM_FP_MODEL_FPA) 220#define TARGET_MAVERICK (arm_fpu_desc->model == ARM_FP_MODEL_MAVERICK) 221#define TARGET_VFP (arm_fpu_desc->model == ARM_FP_MODEL_VFP) 222#define TARGET_IWMMXT (arm_arch_iwmmxt) 223#define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT) 224#define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT) 225#define TARGET_ARM (! TARGET_THUMB) 226#define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ 227#define TARGET_BACKTRACE (leaf_function_p () \ 228 ? TARGET_TPCS_LEAF_FRAME \ 229 : TARGET_TPCS_FRAME) 230#define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN) 231#define TARGET_AAPCS_BASED \ 232 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS) 233 234#define TARGET_HARD_TP (target_thread_pointer == TP_CP15) 235#define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT) 236#define TARGET_GNU2_TLS (target_tls_dialect == TLS_GNU2) 237 238/* Only 16-bit thumb code. */ 239#define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2) 240/* Arm or Thumb-2 32-bit code. */ 241#define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2) 242/* 32-bit Thumb-2 code. */ 243#define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2) 244/* Thumb-1 only. */ 245#define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) 246/* FPA emulator without LFM. */ 247#define TARGET_FPA_EMU2 (TARGET_FPA && arm_fpu_desc->rev == 2) 248 249/* The following two macros concern the ability to execute coprocessor 250 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently 251 only ever tested when we know we are generating for VFP hardware; we need 252 to be more careful with TARGET_NEON as noted below. */ 253 254/* FPU is has the full VFPv3/NEON register file of 32 D registers. */ 255#define TARGET_VFPD32 (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_D32) 256 257/* FPU supports VFPv3 instructions. */ 258#define TARGET_VFP3 (TARGET_VFP && arm_fpu_desc->rev >= 3) 259 260/* FPU only supports VFP single-precision instructions. */ 261#define TARGET_VFP_SINGLE (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_SINGLE) 262 263/* FPU supports VFP double-precision instructions. */ 264#define TARGET_VFP_DOUBLE (TARGET_VFP && arm_fpu_desc->regs != VFP_REG_SINGLE) 265 266/* FPU supports half-precision floating-point with NEON element load/store. */ 267#define TARGET_NEON_FP16 \ 268 (TARGET_VFP && arm_fpu_desc->neon && arm_fpu_desc->fp16) 269 270/* FPU supports VFP half-precision floating-point. */ 271#define TARGET_FP16 (TARGET_VFP && arm_fpu_desc->fp16) 272 273/* FPU supports Neon instructions. The setting of this macro gets 274 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT 275 and TARGET_HARD_FLOAT to ensure that NEON instructions are 276 available. */ 277#define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \ 278 && TARGET_VFP && arm_fpu_desc->neon) 279 280/* "DSP" multiply instructions, eg. SMULxy. */ 281#define TARGET_DSP_MULTIPLY \ 282 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7em)) 283/* Integer SIMD instructions, and extend-accumulate instructions. */ 284#define TARGET_INT_SIMD \ 285 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em)) 286 287/* Should MOVW/MOVT be used in preference to a constant pool. */ 288#define TARGET_USE_MOVT \ 289 (arm_arch_thumb2 && !optimize_size && !current_tune->prefer_constant_pool) 290 291/* We could use unified syntax for arm mode, but for now we just use it 292 for Thumb-2. */ 293#define TARGET_UNIFIED_ASM TARGET_THUMB2 294 295/* Nonzero if this chip provides the DMB instruction. */ 296#define TARGET_HAVE_DMB (arm_arch7) 297 298/* Nonzero if this chip implements a memory barrier via CP15. */ 299#define TARGET_HAVE_DMB_MCR (arm_arch6k && ! TARGET_HAVE_DMB) 300 301/* Nonzero if this chip implements a memory barrier instruction. */ 302#define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR) 303 304/* Nonzero if this chip supports ldrex and strex */ 305#define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7) 306 307/* Nonzero if this chip supports ldrex{bhd} and strex{bhd}. */ 308#define TARGET_HAVE_LDREXBHD ((arm_arch6k && TARGET_ARM) || arm_arch7) 309 310/* Nonzero if integer division instructions supported. */ 311#define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \ 312 || (TARGET_THUMB2 && arm_arch_thumb_hwdiv)) 313 314/* True iff the full BPABI is being used. If TARGET_BPABI is true, 315 then TARGET_AAPCS_BASED must be true -- but the converse does not 316 hold. TARGET_BPABI implies the use of the BPABI runtime library, 317 etc., in addition to just the AAPCS calling conventions. */ 318#ifndef TARGET_BPABI 319#define TARGET_BPABI false 320#endif 321 322/* Support for a compile-time default CPU, et cetera. The rules are: 323 --with-arch is ignored if -march or -mcpu are specified. 324 --with-cpu is ignored if -march or -mcpu are specified, and is overridden 325 by --with-arch. 326 --with-tune is ignored if -mtune or -mcpu are specified (but not affected 327 by -march). 328 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are 329 specified. 330 --with-fpu is ignored if -mfpu is specified. 331 --with-abi is ignored is -mabi is specified. 332 --with-tls is ignored if -mtls-dialect is specified. */ 333#define OPTION_DEFAULT_SPECS \ 334 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ 335 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ 336 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \ 337 {"float", \ 338 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \ 339 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \ 340 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \ 341 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"}, \ 342 {"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"}, 343 344/* Which floating point model to use. */ 345enum arm_fp_model 346{ 347 ARM_FP_MODEL_UNKNOWN, 348 /* FPA model (Hardware or software). */ 349 ARM_FP_MODEL_FPA, 350 /* Cirrus Maverick floating point model. */ 351 ARM_FP_MODEL_MAVERICK, 352 /* VFP floating point model. */ 353 ARM_FP_MODEL_VFP 354}; 355 356enum vfp_reg_type 357{ 358 VFP_NONE = 0, 359 VFP_REG_D16, 360 VFP_REG_D32, 361 VFP_REG_SINGLE 362}; 363 364extern const struct arm_fpu_desc 365{ 366 const char *name; 367 enum arm_fp_model model; 368 int rev; 369 enum vfp_reg_type regs; 370 int neon; 371 int fp16; 372} *arm_fpu_desc; 373 374/* Which floating point hardware to schedule for. */ 375extern int arm_fpu_attr; 376 377enum float_abi_type 378{ 379 ARM_FLOAT_ABI_SOFT, 380 ARM_FLOAT_ABI_SOFTFP, 381 ARM_FLOAT_ABI_HARD 382}; 383 384extern enum float_abi_type arm_float_abi; 385 386#ifndef TARGET_DEFAULT_FLOAT_ABI 387#define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT 388#endif 389 390/* Which __fp16 format to use. 391 The enumeration values correspond to the numbering for the 392 Tag_ABI_FP_16bit_format attribute. 393 */ 394enum arm_fp16_format_type 395{ 396 ARM_FP16_FORMAT_NONE = 0, 397 ARM_FP16_FORMAT_IEEE = 1, 398 ARM_FP16_FORMAT_ALTERNATIVE = 2 399}; 400 401extern enum arm_fp16_format_type arm_fp16_format; 402#define LARGEST_EXPONENT_IS_NORMAL(bits) \ 403 ((bits) == 16 && arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE) 404 405/* Which ABI to use. */ 406enum arm_abi_type 407{ 408 ARM_ABI_APCS, 409 ARM_ABI_ATPCS, 410 ARM_ABI_AAPCS, 411 ARM_ABI_IWMMXT, 412 ARM_ABI_AAPCS_LINUX 413}; 414 415extern enum arm_abi_type arm_abi; 416 417#ifndef ARM_DEFAULT_ABI 418#define ARM_DEFAULT_ABI ARM_ABI_APCS 419#endif 420 421/* Which thread pointer access sequence to use. */ 422enum arm_tp_type { 423 TP_AUTO, 424 TP_SOFT, 425 TP_CP15 426}; 427 428enum arm_tls_type { 429 TLS_GNU, 430 TLS_GNU2 431}; 432 433extern enum arm_tp_type target_thread_pointer; 434extern enum arm_tls_type target_tls_dialect; 435 436/* Nonzero if this chip supports the ARM Architecture 3M extensions. */ 437extern int arm_arch3m; 438 439/* Nonzero if this chip supports the ARM Architecture 4 extensions. */ 440extern int arm_arch4; 441 442/* Nonzero if this chip supports the ARM Architecture 4T extensions. */ 443extern int arm_arch4t; 444 445/* Nonzero if this chip supports the ARM Architecture 5 extensions. */ 446extern int arm_arch5; 447 448/* Nonzero if this chip supports the ARM Architecture 5E extensions. */ 449extern int arm_arch5e; 450 451/* Nonzero if this chip supports the ARM Architecture 6 extensions. */ 452extern int arm_arch6; 453 454/* Nonzero if this chip supports the ARM Architecture 6k extensions. */ 455extern int arm_arch6k; 456 457/* Nonzero if this chip supports the ARM Architecture 7 extensions. */ 458extern int arm_arch7; 459 460/* Nonzero if instructions not present in the 'M' profile can be used. */ 461extern int arm_arch_notm; 462 463/* Nonzero if instructions present in ARMv7E-M can be used. */ 464extern int arm_arch7em; 465 466/* Nonzero if this chip can benefit from load scheduling. */ 467extern int arm_ld_sched; 468 469/* Nonzero if generating Thumb code, either Thumb-1 or Thumb-2. */ 470extern int thumb_code; 471 472/* Nonzero if generating Thumb-1 code. */ 473extern int thumb1_code; 474 475/* Nonzero if this chip is a StrongARM. */ 476extern int arm_tune_strongarm; 477 478/* Nonzero if this chip is a Cirrus variant. */ 479extern int arm_arch_cirrus; 480 481/* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */ 482extern int arm_arch_iwmmxt; 483 484/* Nonzero if this chip is an XScale. */ 485extern int arm_arch_xscale; 486 487/* Nonzero if tuning for XScale. */ 488extern int arm_tune_xscale; 489 490/* Nonzero if tuning for stores via the write buffer. */ 491extern int arm_tune_wbuf; 492 493/* Nonzero if tuning for Cortex-A9. */ 494extern int arm_tune_cortex_a9; 495 496/* Nonzero if we should define __THUMB_INTERWORK__ in the 497 preprocessor. 498 XXX This is a bit of a hack, it's intended to help work around 499 problems in GLD which doesn't understand that armv5t code is 500 interworking clean. */ 501extern int arm_cpp_interwork; 502 503/* Nonzero if chip supports Thumb 2. */ 504extern int arm_arch_thumb2; 505 506/* Nonzero if chip supports integer division instruction in ARM mode. */ 507extern int arm_arch_arm_hwdiv; 508 509/* Nonzero if chip supports integer division instruction in Thumb mode. */ 510extern int arm_arch_thumb_hwdiv; 511 512#ifndef TARGET_DEFAULT 513#define TARGET_DEFAULT (MASK_APCS_FRAME) 514#endif 515 516/* Nonzero if PIC code requires explicit qualifiers to generate 517 PLT and GOT relocs rather than the assembler doing so implicitly. 518 Subtargets can override these if required. */ 519#ifndef NEED_GOT_RELOC 520#define NEED_GOT_RELOC 0 521#endif 522#ifndef NEED_PLT_RELOC 523#define NEED_PLT_RELOC 0 524#endif 525 526/* Nonzero if we need to refer to the GOT with a PC-relative 527 offset. In other words, generate 528 529 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)] 530 531 rather than 532 533 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8) 534 535 The default is true, which matches NetBSD. Subtargets can 536 override this if required. */ 537#ifndef GOT_PCREL 538#define GOT_PCREL 1 539#endif 540 541/* Target machine storage Layout. */ 542 543 544/* Define this macro if it is advisable to hold scalars in registers 545 in a wider mode than that declared by the program. In such cases, 546 the value is constrained to be within the bounds of the declared 547 type, but kept valid in the wider mode. The signedness of the 548 extension may differ from that of the type. */ 549 550/* It is far faster to zero extend chars than to sign extend them */ 551 552#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 553 if (GET_MODE_CLASS (MODE) == MODE_INT \ 554 && GET_MODE_SIZE (MODE) < 4) \ 555 { \ 556 if (MODE == QImode) \ 557 UNSIGNEDP = 1; \ 558 else if (MODE == HImode) \ 559 UNSIGNEDP = 1; \ 560 (MODE) = SImode; \ 561 } 562 563/* Define this if most significant bit is lowest numbered 564 in instructions that operate on numbered bit-fields. */ 565#define BITS_BIG_ENDIAN 0 566 567/* Define this if most significant byte of a word is the lowest numbered. 568 Most ARM processors are run in little endian mode, so that is the default. 569 If you want to have it run-time selectable, change the definition in a 570 cover file to be TARGET_BIG_ENDIAN. */ 571#define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) 572 573/* Define this if most significant word of a multiword number is the lowest 574 numbered. 575 This is always false, even when in big-endian mode. */ 576#define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS) 577 578/* Define this if most significant word of doubles is the lowest numbered. 579 The rules are different based on whether or not we use FPA-format, 580 VFP-format or some other floating point co-processor's format doubles. */ 581#define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ()) 582 583#define UNITS_PER_WORD 4 584 585/* True if natural alignment is used for doubleword types. */ 586#define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED 587 588#define DOUBLEWORD_ALIGNMENT 64 589 590#define PARM_BOUNDARY 32 591 592#define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 593 594#define PREFERRED_STACK_BOUNDARY \ 595 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY) 596 597#define FUNCTION_BOUNDARY ((TARGET_THUMB && optimize_size) ? 16 : 32) 598 599/* The lowest bit is used to indicate Thumb-mode functions, so the 600 vbit must go into the delta field of pointers to member 601 functions. */ 602#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 603 604#define EMPTY_FIELD_BOUNDARY 32 605 606#define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 607 608/* XXX Blah -- this macro is used directly by libobjc. Since it 609 supports no vector modes, cut out the complexity and fall back 610 on BIGGEST_FIELD_ALIGNMENT. */ 611#ifdef IN_TARGET_LIBS 612#define BIGGEST_FIELD_ALIGNMENT 64 613#endif 614 615/* Make strings word-aligned so strcpy from constants will be faster. */ 616#define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2) 617 618#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 619 ((TREE_CODE (EXP) == STRING_CST \ 620 && !optimize_size \ 621 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \ 622 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN)) 623 624/* Align definitions of arrays, unions and structures so that 625 initializations and copies can be made more efficient. This is not 626 ABI-changing, so it only affects places where we can see the 627 definition. Increasing the alignment tends to introduce padding, 628 so don't do this when optimizing for size/conserving stack space. */ 629#define ARM_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \ 630 (((COND) && ((ALIGN) < BITS_PER_WORD) \ 631 && (TREE_CODE (EXP) == ARRAY_TYPE \ 632 || TREE_CODE (EXP) == UNION_TYPE \ 633 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 634 635/* Align global data. */ 636#define DATA_ALIGNMENT(EXP, ALIGN) \ 637 ARM_EXPAND_ALIGNMENT(!optimize_size, EXP, ALIGN) 638 639/* Similarly, make sure that objects on the stack are sensibly aligned. */ 640#define LOCAL_ALIGNMENT(EXP, ALIGN) \ 641 ARM_EXPAND_ALIGNMENT(!flag_conserve_stack, EXP, ALIGN) 642 643/* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the 644 value set in previous versions of this toolchain was 8, which produces more 645 compact structures. The command line option -mstructure_size_boundary=<n> 646 can be used to change this value. For compatibility with the ARM SDK 647 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI 648 0020D) page 2-20 says "Structures are aligned on word boundaries". 649 The AAPCS specifies a value of 8. */ 650#define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary 651extern int arm_structure_size_boundary; 652 653/* This is the value used to initialize arm_structure_size_boundary. If a 654 particular arm target wants to change the default value it should change 655 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h 656 for an example of this. */ 657#ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY 658#define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32 659#endif 660 661/* Nonzero if move instructions will actually fail to work 662 when given unaligned data. */ 663#define STRICT_ALIGNMENT 1 664 665/* wchar_t is unsigned under the AAPCS. */ 666#ifndef WCHAR_TYPE 667#define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int") 668 669#define WCHAR_TYPE_SIZE BITS_PER_WORD 670#endif 671 672/* Sized for fixed-point types. */ 673 674#define SHORT_FRACT_TYPE_SIZE 8 675#define FRACT_TYPE_SIZE 16 676#define LONG_FRACT_TYPE_SIZE 32 677#define LONG_LONG_FRACT_TYPE_SIZE 64 678 679#define SHORT_ACCUM_TYPE_SIZE 16 680#define ACCUM_TYPE_SIZE 32 681#define LONG_ACCUM_TYPE_SIZE 64 682#define LONG_LONG_ACCUM_TYPE_SIZE 64 683 684#define MAX_FIXED_MODE_SIZE 64 685 686#ifndef SIZE_TYPE 687#define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int") 688#endif 689 690#ifndef PTRDIFF_TYPE 691#define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int") 692#endif 693 694/* AAPCS requires that structure alignment is affected by bitfields. */ 695#ifndef PCC_BITFIELD_TYPE_MATTERS 696#define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED 697#endif 698 699 700/* Standard register usage. */ 701 702/* Register allocation in ARM Procedure Call Standard (as used on RISCiX): 703 (S - saved over call). 704 705 r0 * argument word/integer result 706 r1-r3 argument word 707 708 r4-r8 S register variable 709 r9 S (rfp) register variable (real frame pointer) 710 711 r10 F S (sl) stack limit (used by -mapcs-stack-check) 712 r11 F S (fp) argument pointer 713 r12 (ip) temp workspace 714 r13 F S (sp) lower end of current stack frame 715 r14 (lr) link address/workspace 716 r15 F (pc) program counter 717 718 f0 floating point result 719 f1-f3 floating point scratch 720 721 f4-f7 S floating point variable 722 723 cc This is NOT a real register, but is used internally 724 to represent things that use or set the condition 725 codes. 726 sfp This isn't either. It is used during rtl generation 727 since the offset between the frame pointer and the 728 auto's isn't known until after register allocation. 729 afp Nor this, we only need this because of non-local 730 goto. Without it fp appears to be used and the 731 elimination code won't get rid of sfp. It tracks 732 fp exactly at all times. 733 734 *: See TARGET_CONDITIONAL_REGISTER_USAGE */ 735 736/* 737 mvf0 Cirrus floating point result 738 mvf1-mvf3 Cirrus floating point scratch 739 mvf4-mvf15 S Cirrus floating point variable. */ 740 741/* s0-s15 VFP scratch (aka d0-d7). 742 s16-s31 S VFP variable (aka d8-d15). 743 vfpcc Not a real register. Represents the VFP condition 744 code flags. */ 745 746/* The stack backtrace structure is as follows: 747 fp points to here: | save code pointer | [fp] 748 | return link value | [fp, #-4] 749 | return sp value | [fp, #-8] 750 | return fp value | [fp, #-12] 751 [| saved r10 value |] 752 [| saved r9 value |] 753 [| saved r8 value |] 754 [| saved r7 value |] 755 [| saved r6 value |] 756 [| saved r5 value |] 757 [| saved r4 value |] 758 [| saved r3 value |] 759 [| saved r2 value |] 760 [| saved r1 value |] 761 [| saved r0 value |] 762 [| saved f7 value |] three words 763 [| saved f6 value |] three words 764 [| saved f5 value |] three words 765 [| saved f4 value |] three words 766 r0-r3 are not normally saved in a C function. */ 767 768/* 1 for registers that have pervasive standard uses 769 and are not available for the register allocator. */ 770#define FIXED_REGISTERS \ 771{ \ 772 0,0,0,0,0,0,0,0, \ 773 0,0,0,0,0,1,0,1, \ 774 0,0,0,0,0,0,0,0, \ 775 1,1,1, \ 776 1,1,1,1,1,1,1,1, \ 777 1,1,1,1,1,1,1,1, \ 778 1,1,1,1,1,1,1,1, \ 779 1,1,1,1,1,1,1,1, \ 780 1,1,1,1, \ 781 1,1,1,1,1,1,1,1, \ 782 1,1,1,1,1,1,1,1, \ 783 1,1,1,1,1,1,1,1, \ 784 1,1,1,1,1,1,1,1, \ 785 1,1,1,1,1,1,1,1, \ 786 1,1,1,1,1,1,1,1, \ 787 1,1,1,1,1,1,1,1, \ 788 1,1,1,1,1,1,1,1, \ 789 1 \ 790} 791 792/* 1 for registers not available across function calls. 793 These must include the FIXED_REGISTERS and also any 794 registers that can be used without being saved. 795 The latter must include the registers where values are returned 796 and the register where structure-value addresses are passed. 797 Aside from that, you can include as many other registers as you like. 798 The CC is not preserved over function calls on the ARM 6, so it is 799 easier to assume this for all. SFP is preserved, since FP is. */ 800#define CALL_USED_REGISTERS \ 801{ \ 802 1,1,1,1,0,0,0,0, \ 803 0,0,0,0,1,1,1,1, \ 804 1,1,1,1,0,0,0,0, \ 805 1,1,1, \ 806 1,1,1,1,1,1,1,1, \ 807 1,1,1,1,1,1,1,1, \ 808 1,1,1,1,1,1,1,1, \ 809 1,1,1,1,1,1,1,1, \ 810 1,1,1,1, \ 811 1,1,1,1,1,1,1,1, \ 812 1,1,1,1,1,1,1,1, \ 813 1,1,1,1,1,1,1,1, \ 814 1,1,1,1,1,1,1,1, \ 815 1,1,1,1,1,1,1,1, \ 816 1,1,1,1,1,1,1,1, \ 817 1,1,1,1,1,1,1,1, \ 818 1,1,1,1,1,1,1,1, \ 819 1 \ 820} 821 822#ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE 823#define SUBTARGET_CONDITIONAL_REGISTER_USAGE 824#endif 825 826/* These are a couple of extensions to the formats accepted 827 by asm_fprintf: 828 %@ prints out ASM_COMMENT_START 829 %r prints out REGISTER_PREFIX reg_names[arg] */ 830#define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ 831 case '@': \ 832 fputs (ASM_COMMENT_START, FILE); \ 833 break; \ 834 \ 835 case 'r': \ 836 fputs (REGISTER_PREFIX, FILE); \ 837 fputs (reg_names [va_arg (ARGS, int)], FILE); \ 838 break; 839 840/* Round X up to the nearest word. */ 841#define ROUND_UP_WORD(X) (((X) + 3) & ~3) 842 843/* Convert fron bytes to ints. */ 844#define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 845 846/* The number of (integer) registers required to hold a quantity of type MODE. 847 Also used for VFP registers. */ 848#define ARM_NUM_REGS(MODE) \ 849 ARM_NUM_INTS (GET_MODE_SIZE (MODE)) 850 851/* The number of (integer) registers required to hold a quantity of TYPE MODE. */ 852#define ARM_NUM_REGS2(MODE, TYPE) \ 853 ARM_NUM_INTS ((MODE) == BLKmode ? \ 854 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) 855 856/* The number of (integer) argument register available. */ 857#define NUM_ARG_REGS 4 858 859/* And similarly for the VFP. */ 860#define NUM_VFP_ARG_REGS 16 861 862/* Return the register number of the N'th (integer) argument. */ 863#define ARG_REGISTER(N) (N - 1) 864 865/* Specify the registers used for certain standard purposes. 866 The values of these macros are register numbers. */ 867 868/* The number of the last argument register. */ 869#define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS) 870 871/* The numbers of the Thumb register ranges. */ 872#define FIRST_LO_REGNUM 0 873#define LAST_LO_REGNUM 7 874#define FIRST_HI_REGNUM 8 875#define LAST_HI_REGNUM 11 876 877/* Overridden by config/arm/bpabi.h. */ 878#ifndef ARM_UNWIND_INFO 879#define ARM_UNWIND_INFO 0 880#endif 881 882/* Use r0 and r1 to pass exception handling information. */ 883#define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM) 884 885/* The register that holds the return address in exception handlers. */ 886#define ARM_EH_STACKADJ_REGNUM 2 887#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM) 888 889/* The native (Norcroft) Pascal compiler for the ARM passes the static chain 890 as an invisible last argument (possible since varargs don't exist in 891 Pascal), so the following is not true. */ 892#define STATIC_CHAIN_REGNUM 12 893 894/* Define this to be where the real frame pointer is if it is not possible to 895 work out the offset between the frame pointer and the automatic variables 896 until after register allocation has taken place. FRAME_POINTER_REGNUM 897 should point to a special register that we will make sure is eliminated. 898 899 For the Thumb we have another problem. The TPCS defines the frame pointer 900 as r11, and GCC believes that it is always possible to use the frame pointer 901 as base register for addressing purposes. (See comments in 902 find_reloads_address()). But - the Thumb does not allow high registers, 903 including r11, to be used as base address registers. Hence our problem. 904 905 The solution used here, and in the old thumb port is to use r7 instead of 906 r11 as the hard frame pointer and to have special code to generate 907 backtrace structures on the stack (if required to do so via a command line 908 option) using r11. This is the only 'user visible' use of r11 as a frame 909 pointer. */ 910#define ARM_HARD_FRAME_POINTER_REGNUM 11 911#define THUMB_HARD_FRAME_POINTER_REGNUM 7 912 913#define HARD_FRAME_POINTER_REGNUM \ 914 (TARGET_ARM \ 915 ? ARM_HARD_FRAME_POINTER_REGNUM \ 916 : THUMB_HARD_FRAME_POINTER_REGNUM) 917 918#define HARD_FRAME_POINTER_IS_FRAME_POINTER 0 919#define HARD_FRAME_POINTER_IS_ARG_POINTER 0 920 921#define FP_REGNUM HARD_FRAME_POINTER_REGNUM 922 923/* Register to use for pushing function arguments. */ 924#define STACK_POINTER_REGNUM SP_REGNUM 925 926/* ARM floating pointer registers. */ 927#define FIRST_FPA_REGNUM 16 928#define LAST_FPA_REGNUM 23 929#define IS_FPA_REGNUM(REGNUM) \ 930 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM)) 931 932#define FIRST_IWMMXT_GR_REGNUM 43 933#define LAST_IWMMXT_GR_REGNUM 46 934#define FIRST_IWMMXT_REGNUM 47 935#define LAST_IWMMXT_REGNUM 62 936#define IS_IWMMXT_REGNUM(REGNUM) \ 937 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM)) 938#define IS_IWMMXT_GR_REGNUM(REGNUM) \ 939 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM)) 940 941/* Base register for access to local variables of the function. */ 942#define FRAME_POINTER_REGNUM 25 943 944/* Base register for access to arguments of the function. */ 945#define ARG_POINTER_REGNUM 26 946 947#define FIRST_CIRRUS_FP_REGNUM 27 948#define LAST_CIRRUS_FP_REGNUM 42 949#define IS_CIRRUS_REGNUM(REGNUM) \ 950 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM)) 951 952#define FIRST_VFP_REGNUM 63 953#define D7_VFP_REGNUM 78 /* Registers 77 and 78 == VFP reg D7. */ 954#define LAST_VFP_REGNUM \ 955 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM) 956 957#define IS_VFP_REGNUM(REGNUM) \ 958 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM)) 959 960/* VFP registers are split into two types: those defined by VFP versions < 3 961 have D registers overlaid on consecutive pairs of S registers. VFP version 3 962 defines 16 new D registers (d16-d31) which, for simplicity and correctness 963 in various parts of the backend, we implement as "fake" single-precision 964 registers (which would be S32-S63, but cannot be used in that way). The 965 following macros define these ranges of registers. */ 966#define LAST_LO_VFP_REGNUM 94 967#define FIRST_HI_VFP_REGNUM 95 968#define LAST_HI_VFP_REGNUM 126 969 970#define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \ 971 ((REGNUM) <= LAST_LO_VFP_REGNUM) 972 973/* DFmode values are only valid in even register pairs. */ 974#define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \ 975 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0) 976 977/* Neon Quad values must start at a multiple of four registers. */ 978#define NEON_REGNO_OK_FOR_QUAD(REGNUM) \ 979 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0) 980 981/* Neon structures of vectors must be in even register pairs and there 982 must be enough registers available. Because of various patterns 983 requiring quad registers, we require them to start at a multiple of 984 four. */ 985#define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \ 986 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \ 987 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1)) 988 989/* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */ 990/* + 16 Cirrus registers take us up to 43. */ 991/* Intel Wireless MMX Technology registers add 16 + 4 more. */ 992/* VFP (VFP3) adds 32 (64) + 1 more. */ 993#define FIRST_PSEUDO_REGISTER 128 994 995#define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO) 996 997/* Value should be nonzero if functions must have frame pointers. 998 Zero means the frame pointer need not be set up (and parms may be accessed 999 via the stack pointer) in functions that seem suitable. 1000 If we have to have a frame pointer we might as well make use of it. 1001 APCS says that the frame pointer does not need to be pushed in leaf 1002 functions, or simple tail call functions. */ 1003 1004#ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1005#define SUBTARGET_FRAME_POINTER_REQUIRED 0 1006#endif 1007 1008/* Return number of consecutive hard regs needed starting at reg REGNO 1009 to hold something of mode MODE. 1010 This is ordinarily the length in words of a value of mode MODE 1011 but can be less for certain modes in special long registers. 1012 1013 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP 1014 mode. */ 1015#define HARD_REGNO_NREGS(REGNO, MODE) \ 1016 ((TARGET_32BIT \ 1017 && REGNO >= FIRST_FPA_REGNUM \ 1018 && REGNO != FRAME_POINTER_REGNUM \ 1019 && REGNO != ARG_POINTER_REGNUM) \ 1020 && !IS_VFP_REGNUM (REGNO) \ 1021 ? 1 : ARM_NUM_REGS (MODE)) 1022 1023/* Return true if REGNO is suitable for holding a quantity of type MODE. */ 1024#define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1025 arm_hard_regno_mode_ok ((REGNO), (MODE)) 1026 1027/* Value is 1 if it is a good idea to tie two pseudo registers 1028 when one has mode MODE1 and one has mode MODE2. 1029 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 1030 for any hard reg, then this must be 0 for correct output. */ 1031#define MODES_TIEABLE_P(MODE1, MODE2) \ 1032 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) 1033 1034#define VALID_IWMMXT_REG_MODE(MODE) \ 1035 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode || (MODE) == SImode) 1036 1037/* Modes valid for Neon D registers. */ 1038#define VALID_NEON_DREG_MODE(MODE) \ 1039 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ 1040 || (MODE) == V2SFmode || (MODE) == DImode) 1041 1042/* Modes valid for Neon Q registers. */ 1043#define VALID_NEON_QREG_MODE(MODE) \ 1044 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ 1045 || (MODE) == V4SFmode || (MODE) == V2DImode) 1046 1047/* Structure modes valid for Neon registers. */ 1048#define VALID_NEON_STRUCT_MODE(MODE) \ 1049 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \ 1050 || (MODE) == CImode || (MODE) == XImode) 1051 1052/* The register numbers in sequence, for passing to arm_gen_load_multiple. */ 1053extern int arm_regs_in_sequence[]; 1054 1055/* The order in which register should be allocated. It is good to use ip 1056 since no saving is required (though calls clobber it) and it never contains 1057 function parameters. It is quite good to use lr since other calls may 1058 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is 1059 least likely to contain a function parameter; in addition results are 1060 returned in r0. 1061 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7), 1062 then D8-D15. The reason for doing this is to attempt to reduce register 1063 pressure when both single- and double-precision registers are used in a 1064 function. */ 1065 1066#define REG_ALLOC_ORDER \ 1067{ \ 1068 3, 2, 1, 0, 12, 14, 4, 5, \ 1069 6, 7, 8, 10, 9, 11, 13, 15, \ 1070 16, 17, 18, 19, 20, 21, 22, 23, \ 1071 27, 28, 29, 30, 31, 32, 33, 34, \ 1072 35, 36, 37, 38, 39, 40, 41, 42, \ 1073 43, 44, 45, 46, 47, 48, 49, 50, \ 1074 51, 52, 53, 54, 55, 56, 57, 58, \ 1075 59, 60, 61, 62, \ 1076 24, 25, 26, \ 1077 95, 96, 97, 98, 99, 100, 101, 102, \ 1078 103, 104, 105, 106, 107, 108, 109, 110, \ 1079 111, 112, 113, 114, 115, 116, 117, 118, \ 1080 119, 120, 121, 122, 123, 124, 125, 126, \ 1081 78, 77, 76, 75, 74, 73, 72, 71, \ 1082 70, 69, 68, 67, 66, 65, 64, 63, \ 1083 79, 80, 81, 82, 83, 84, 85, 86, \ 1084 87, 88, 89, 90, 91, 92, 93, 94, \ 1085 127 \ 1086} 1087 1088/* Use different register alloc ordering for Thumb. */ 1089#define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc () 1090 1091/* Tell IRA to use the order we define rather than messing it up with its 1092 own cost calculations. */ 1093#define HONOR_REG_ALLOC_ORDER 1094 1095/* Interrupt functions can only use registers that have already been 1096 saved by the prologue, even if they would normally be 1097 call-clobbered. */ 1098#define HARD_REGNO_RENAME_OK(SRC, DST) \ 1099 (! IS_INTERRUPT (cfun->machine->func_type) || \ 1100 df_regs_ever_live_p (DST)) 1101 1102/* Register and constant classes. */ 1103 1104/* Register classes: used to be simple, just all ARM regs or all FPA regs 1105 Now that the Thumb is involved it has become more complicated. */ 1106enum reg_class 1107{ 1108 NO_REGS, 1109 FPA_REGS, 1110 CIRRUS_REGS, 1111 VFP_D0_D7_REGS, 1112 VFP_LO_REGS, 1113 VFP_HI_REGS, 1114 VFP_REGS, 1115 IWMMXT_GR_REGS, 1116 IWMMXT_REGS, 1117 LO_REGS, 1118 STACK_REG, 1119 BASE_REGS, 1120 HI_REGS, 1121 CC_REG, 1122 VFPCC_REG, 1123 GENERAL_REGS, 1124 CORE_REGS, 1125 ALL_REGS, 1126 LIM_REG_CLASSES 1127}; 1128 1129#define N_REG_CLASSES (int) LIM_REG_CLASSES 1130 1131/* Give names of register classes as strings for dump file. */ 1132#define REG_CLASS_NAMES \ 1133{ \ 1134 "NO_REGS", \ 1135 "FPA_REGS", \ 1136 "CIRRUS_REGS", \ 1137 "VFP_D0_D7_REGS", \ 1138 "VFP_LO_REGS", \ 1139 "VFP_HI_REGS", \ 1140 "VFP_REGS", \ 1141 "IWMMXT_GR_REGS", \ 1142 "IWMMXT_REGS", \ 1143 "LO_REGS", \ 1144 "STACK_REG", \ 1145 "BASE_REGS", \ 1146 "HI_REGS", \ 1147 "CC_REG", \ 1148 "VFPCC_REG", \ 1149 "GENERAL_REGS", \ 1150 "CORE_REGS", \ 1151 "ALL_REGS", \ 1152} 1153 1154/* Define which registers fit in which classes. 1155 This is an initializer for a vector of HARD_REG_SET 1156 of length N_REG_CLASSES. */ 1157#define REG_CLASS_CONTENTS \ 1158{ \ 1159 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 1160 { 0x00FF0000, 0x00000000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \ 1161 { 0xF8000000, 0x000007FF, 0x00000000, 0x00000000 }, /* CIRRUS_REGS */ \ 1162 { 0x00000000, 0x80000000, 0x00007FFF, 0x00000000 }, /* VFP_D0_D7_REGS */ \ 1163 { 0x00000000, 0x80000000, 0x7FFFFFFF, 0x00000000 }, /* VFP_LO_REGS */ \ 1164 { 0x00000000, 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_HI_REGS */ \ 1165 { 0x00000000, 0x80000000, 0xFFFFFFFF, 0x7FFFFFFF }, /* VFP_REGS */ \ 1166 { 0x00000000, 0x00007800, 0x00000000, 0x00000000 }, /* IWMMXT_GR_REGS */ \ 1167 { 0x00000000, 0x7FFF8000, 0x00000000, 0x00000000 }, /* IWMMXT_REGS */ \ 1168 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \ 1169 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ 1170 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \ 1171 { 0x0000DF00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \ 1172 { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* CC_REG */ \ 1173 { 0x00000000, 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \ 1174 { 0x0000DFFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ 1175 { 0x0000FFFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ 1176 { 0xFAFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \ 1177} 1178 1179/* Any of the VFP register classes. */ 1180#define IS_VFP_CLASS(X) \ 1181 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \ 1182 || (X) == VFP_HI_REGS || (X) == VFP_REGS) 1183 1184/* The same information, inverted: 1185 Return the class number of the smallest class containing 1186 reg number REGNO. This could be a conditional expression 1187 or could index an array. */ 1188#define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO) 1189 1190/* The following macro defines cover classes for Integrated Register 1191 Allocator. Cover classes is a set of non-intersected register 1192 classes covering all hard registers used for register allocation 1193 purpose. Any move between two registers of a cover class should be 1194 cheaper than load or store of the registers. The macro value is 1195 array of register classes with LIM_REG_CLASSES used as the end 1196 marker. */ 1197 1198#define IRA_COVER_CLASSES \ 1199{ \ 1200 GENERAL_REGS, FPA_REGS, CIRRUS_REGS, VFP_REGS, IWMMXT_GR_REGS, IWMMXT_REGS,\ 1201 LIM_REG_CLASSES \ 1202} 1203 1204/* FPA registers can't do subreg as all values are reformatted to internal 1205 precision. VFP registers may only be accessed in the mode they 1206 were set. */ 1207#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1208 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ 1209 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \ 1210 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \ 1211 : 0) 1212 1213/* The class value for index registers, and the one for base regs. */ 1214#define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS) 1215#define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS) 1216 1217/* For the Thumb the high registers cannot be used as base registers 1218 when addressing quantities in QI or HI mode; if we don't know the 1219 mode, then we must be conservative. */ 1220#define MODE_BASE_REG_CLASS(MODE) \ 1221 (TARGET_ARM || (TARGET_THUMB2 && !optimize_size) ? CORE_REGS : \ 1222 (((MODE) == SImode) ? BASE_REGS : LO_REGS)) 1223 1224/* For Thumb we can not support SP+reg addressing, so we return LO_REGS 1225 instead of BASE_REGS. */ 1226#define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS 1227 1228/* When this hook returns true for MODE, the compiler allows 1229 registers explicitly used in the rtl to be used as spill registers 1230 but prevents the compiler from extending the lifetime of these 1231 registers. */ 1232#define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \ 1233 arm_small_register_classes_for_mode_p 1234 1235/* Given an rtx X being reloaded into a reg required to be 1236 in class CLASS, return the class of reg to actually use. 1237 In general this is just CLASS, but for the Thumb core registers and 1238 immediate constants we prefer a LO_REGS class or a subset. */ 1239#define PREFERRED_RELOAD_CLASS(X, CLASS) \ 1240 (TARGET_32BIT ? (CLASS) : \ 1241 ((CLASS) == GENERAL_REGS || (CLASS) == HI_REGS \ 1242 || (CLASS) == NO_REGS || (CLASS) == STACK_REG \ 1243 || (CLASS) == CORE_REGS \ 1244 ? LO_REGS : (CLASS))) 1245 1246/* Must leave BASE_REGS reloads alone */ 1247#define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1248 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1249 ? ((true_regnum (X) == -1 ? LO_REGS \ 1250 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ 1251 : NO_REGS)) \ 1252 : NO_REGS) 1253 1254#define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1255 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1256 ? ((true_regnum (X) == -1 ? LO_REGS \ 1257 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ 1258 : NO_REGS)) \ 1259 : NO_REGS) 1260 1261/* Return the register class of a scratch register needed to copy IN into 1262 or out of a register in CLASS in MODE. If it can be done directly, 1263 NO_REGS is returned. */ 1264#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1265 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1266 ((TARGET_VFP && TARGET_HARD_FLOAT \ 1267 && IS_VFP_CLASS (CLASS)) \ 1268 ? coproc_secondary_reload_class (MODE, X, FALSE) \ 1269 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \ 1270 ? coproc_secondary_reload_class (MODE, X, TRUE) \ 1271 : TARGET_32BIT \ 1272 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ 1273 ? GENERAL_REGS : NO_REGS) \ 1274 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)) 1275 1276/* If we need to load shorts byte-at-a-time, then we need a scratch. */ 1277#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1278 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1279 ((TARGET_VFP && TARGET_HARD_FLOAT \ 1280 && IS_VFP_CLASS (CLASS)) \ 1281 ? coproc_secondary_reload_class (MODE, X, FALSE) : \ 1282 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \ 1283 coproc_secondary_reload_class (MODE, X, TRUE) : \ 1284 /* Cannot load constants into Cirrus registers. */ \ 1285 (TARGET_MAVERICK && TARGET_HARD_FLOAT \ 1286 && (CLASS) == CIRRUS_REGS \ 1287 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \ 1288 ? GENERAL_REGS : \ 1289 (TARGET_32BIT ? \ 1290 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \ 1291 && CONSTANT_P (X)) \ 1292 ? GENERAL_REGS : \ 1293 (((MODE) == HImode && ! arm_arch4 \ 1294 && (GET_CODE (X) == MEM \ 1295 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \ 1296 && true_regnum (X) == -1))) \ 1297 ? GENERAL_REGS : NO_REGS) \ 1298 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) 1299 1300/* Try a machine-dependent way of reloading an illegitimate address 1301 operand. If we find one, push the reload and jump to WIN. This 1302 macro is used in only one place: `find_reloads_address' in reload.c. 1303 1304 For the ARM, we wish to handle large displacements off a base 1305 register by splitting the addend across a MOV and the mem insn. 1306 This can cut the number of reloads needed. */ 1307#define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \ 1308 do \ 1309 { \ 1310 if (arm_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND)) \ 1311 goto WIN; \ 1312 } \ 1313 while (0) 1314 1315/* XXX If an HImode FP+large_offset address is converted to an HImode 1316 SP+large_offset address, then reload won't know how to fix it. It sees 1317 only that SP isn't valid for HImode, and so reloads the SP into an index 1318 register, but the resulting address is still invalid because the offset 1319 is too big. We fix it here instead by reloading the entire address. */ 1320/* We could probably achieve better results by defining PROMOTE_MODE to help 1321 cope with the variances between the Thumb's signed and unsigned byte and 1322 halfword load instructions. */ 1323/* ??? This should be safe for thumb2, but we may be able to do better. */ 1324#define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \ 1325do { \ 1326 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \ 1327 if (new_x) \ 1328 { \ 1329 X = new_x; \ 1330 goto WIN; \ 1331 } \ 1332} while (0) 1333 1334#define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \ 1335 if (TARGET_ARM) \ 1336 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \ 1337 else \ 1338 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) 1339 1340/* Return the maximum number of consecutive registers 1341 needed to represent mode MODE in a register of class CLASS. 1342 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */ 1343#define CLASS_MAX_NREGS(CLASS, MODE) \ 1344 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE)) 1345 1346/* If defined, gives a class of registers that cannot be used as the 1347 operand of a SUBREG that changes the mode of the object illegally. */ 1348 1349/* Moves between FPA_REGS and GENERAL_REGS are two memory insns. 1350 Moves between VFP_REGS and GENERAL_REGS are a single insn, but 1351 it is typically more expensive than a single memory access. We set 1352 the cost to less than two memory accesses so that floating 1353 point to integer conversion does not go through memory. */ 1354#define REGISTER_MOVE_COST(MODE, FROM, TO) \ 1355 (TARGET_32BIT ? \ 1356 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \ 1357 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \ 1358 IS_VFP_CLASS (FROM) && !IS_VFP_CLASS (TO) ? 15 : \ 1359 !IS_VFP_CLASS (FROM) && IS_VFP_CLASS (TO) ? 15 : \ 1360 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \ 1361 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \ 1362 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \ 1363 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \ 1364 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \ 1365 2) \ 1366 : \ 1367 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2) 1368 1369/* Stack layout; function entry, exit and calling. */ 1370 1371/* Define this if pushing a word on the stack 1372 makes the stack pointer a smaller address. */ 1373#define STACK_GROWS_DOWNWARD 1 1374 1375/* Define this to nonzero if the nominal address of the stack frame 1376 is at the high-address end of the local variables; 1377 that is, each additional local variable allocated 1378 goes at a more negative offset in the frame. */ 1379#define FRAME_GROWS_DOWNWARD 1 1380 1381/* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN(). 1382 When present, it is one word in size, and sits at the top of the frame, 1383 between the soft frame pointer and either r7 or r11. 1384 1385 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking, 1386 and only then if some outgoing arguments are passed on the stack. It would 1387 be tempting to also check whether the stack arguments are passed by indirect 1388 calls, but there seems to be no reason in principle why a post-reload pass 1389 couldn't convert a direct call into an indirect one. */ 1390#define CALLER_INTERWORKING_SLOT_SIZE \ 1391 (TARGET_CALLER_INTERWORKING \ 1392 && crtl->outgoing_args_size != 0 \ 1393 ? UNITS_PER_WORD : 0) 1394 1395/* Offset within stack frame to start allocating local variables at. 1396 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1397 first local allocated. Otherwise, it is the offset to the BEGINNING 1398 of the first local allocated. */ 1399#define STARTING_FRAME_OFFSET 0 1400 1401/* If we generate an insn to push BYTES bytes, 1402 this says how many the stack pointer really advances by. */ 1403/* The push insns do not do this rounding implicitly. 1404 So don't define this. */ 1405/* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */ 1406 1407/* Define this if the maximum size of all the outgoing args is to be 1408 accumulated and pushed during the prologue. The amount can be 1409 found in the variable crtl->outgoing_args_size. */ 1410#define ACCUMULATE_OUTGOING_ARGS 1 1411 1412/* Offset of first parameter from the argument pointer register value. */ 1413#define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0) 1414 1415/* Define how to find the value returned by a library function 1416 assuming the value has mode MODE. */ 1417#define LIBCALL_VALUE(MODE) \ 1418 (TARGET_AAPCS_BASED ? aapcs_libcall_value (MODE) \ 1419 : (TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_FPA \ 1420 && GET_MODE_CLASS (MODE) == MODE_FLOAT) \ 1421 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \ 1422 : TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \ 1423 && GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1424 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \ 1425 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \ 1426 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \ 1427 : gen_rtx_REG (MODE, ARG_REGISTER (1))) 1428 1429/* 1 if REGNO is a possible register number for a function value. */ 1430#define FUNCTION_VALUE_REGNO_P(REGNO) \ 1431 ((REGNO) == ARG_REGISTER (1) \ 1432 || (TARGET_AAPCS_BASED && TARGET_32BIT \ 1433 && TARGET_VFP && TARGET_HARD_FLOAT \ 1434 && (REGNO) == FIRST_VFP_REGNUM) \ 1435 || (TARGET_32BIT && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \ 1436 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \ 1437 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \ 1438 || (TARGET_32BIT && ((REGNO) == FIRST_FPA_REGNUM) \ 1439 && TARGET_HARD_FLOAT_ABI && TARGET_FPA)) 1440 1441/* Amount of memory needed for an untyped call to save all possible return 1442 registers. */ 1443#define APPLY_RESULT_SIZE arm_apply_result_size() 1444 1445/* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return 1446 values must be in memory. On the ARM, they need only do so if larger 1447 than a word, or if they contain elements offset from zero in the struct. */ 1448#define DEFAULT_PCC_STRUCT_RETURN 0 1449 1450/* These bits describe the different types of function supported 1451 by the ARM backend. They are exclusive. i.e. a function cannot be both a 1452 normal function and an interworked function, for example. Knowing the 1453 type of a function is important for determining its prologue and 1454 epilogue sequences. 1455 Note value 7 is currently unassigned. Also note that the interrupt 1456 function types all have bit 2 set, so that they can be tested for easily. 1457 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the 1458 machine_function structure is initialized (to zero) func_type will 1459 default to unknown. This will force the first use of arm_current_func_type 1460 to call arm_compute_func_type. */ 1461#define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */ 1462#define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */ 1463#define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */ 1464#define ARM_FT_ISR 4 /* An interrupt service routine. */ 1465#define ARM_FT_FIQ 5 /* A fast interrupt service routine. */ 1466#define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */ 1467 1468#define ARM_FT_TYPE_MASK ((1 << 3) - 1) 1469 1470/* In addition functions can have several type modifiers, 1471 outlined by these bit masks: */ 1472#define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */ 1473#define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */ 1474#define ARM_FT_VOLATILE (1 << 4) /* Does not return. */ 1475#define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */ 1476#define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */ 1477 1478/* Some macros to test these flags. */ 1479#define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK) 1480#define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT) 1481#define IS_VOLATILE(t) (t & ARM_FT_VOLATILE) 1482#define IS_NAKED(t) (t & ARM_FT_NAKED) 1483#define IS_NESTED(t) (t & ARM_FT_NESTED) 1484#define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN) 1485 1486 1487/* Structure used to hold the function stack frame layout. Offsets are 1488 relative to the stack pointer on function entry. Positive offsets are 1489 in the direction of stack growth. 1490 Only soft_frame is used in thumb mode. */ 1491 1492typedef struct GTY(()) arm_stack_offsets 1493{ 1494 int saved_args; /* ARG_POINTER_REGNUM. */ 1495 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */ 1496 int saved_regs; 1497 int soft_frame; /* FRAME_POINTER_REGNUM. */ 1498 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */ 1499 int outgoing_args; /* STACK_POINTER_REGNUM. */ 1500 unsigned int saved_regs_mask; 1501} 1502arm_stack_offsets; 1503 1504#ifndef GENERATOR_FILE 1505/* A C structure for machine-specific, per-function data. 1506 This is added to the cfun structure. */ 1507typedef struct GTY(()) machine_function 1508{ 1509 /* Additional stack adjustment in __builtin_eh_throw. */ 1510 rtx eh_epilogue_sp_ofs; 1511 /* Records if LR has to be saved for far jumps. */ 1512 int far_jump_used; 1513 /* Records if ARG_POINTER was ever live. */ 1514 int arg_pointer_live; 1515 /* Records if the save of LR has been eliminated. */ 1516 int lr_save_eliminated; 1517 /* The size of the stack frame. Only valid after reload. */ 1518 arm_stack_offsets stack_offsets; 1519 /* Records the type of the current function. */ 1520 unsigned long func_type; 1521 /* Record if the function has a variable argument list. */ 1522 int uses_anonymous_args; 1523 /* Records if sibcalls are blocked because an argument 1524 register is needed to preserve stack alignment. */ 1525 int sibcall_blocked; 1526 /* The PIC register for this function. This might be a pseudo. */ 1527 rtx pic_reg; 1528 /* Labels for per-function Thumb call-via stubs. One per potential calling 1529 register. We can never call via LR or PC. We can call via SP if a 1530 trampoline happens to be on the top of the stack. */ 1531 rtx call_via[14]; 1532 /* Set to 1 when a return insn is output, this means that the epilogue 1533 is not needed. */ 1534 int return_used_this_function; 1535 /* When outputting Thumb-1 code, record the last insn that provides 1536 information about condition codes, and the comparison operands. */ 1537 rtx thumb1_cc_insn; 1538 rtx thumb1_cc_op0; 1539 rtx thumb1_cc_op1; 1540 /* Also record the CC mode that is supported. */ 1541 enum machine_mode thumb1_cc_mode; 1542} 1543machine_function; 1544#endif 1545 1546/* As in the machine_function, a global set of call-via labels, for code 1547 that is in text_section. */ 1548extern GTY(()) rtx thumb_call_via_label[14]; 1549 1550/* The number of potential ways of assigning to a co-processor. */ 1551#define ARM_NUM_COPROC_SLOTS 1 1552 1553/* Enumeration of procedure calling standard variants. We don't really 1554 support all of these yet. */ 1555enum arm_pcs 1556{ 1557 ARM_PCS_AAPCS, /* Base standard AAPCS. */ 1558 ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */ 1559 ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */ 1560 /* This must be the last AAPCS variant. */ 1561 ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */ 1562 ARM_PCS_ATPCS, /* ATPCS. */ 1563 ARM_PCS_APCS, /* APCS (legacy Linux etc). */ 1564 ARM_PCS_UNKNOWN 1565}; 1566 1567/* Default procedure calling standard of current compilation unit. */ 1568extern enum arm_pcs arm_pcs_default; 1569 1570/* A C type for declaring a variable that is used as the first argument of 1571 `FUNCTION_ARG' and other related values. */ 1572typedef struct 1573{ 1574 /* This is the number of registers of arguments scanned so far. */ 1575 int nregs; 1576 /* This is the number of iWMMXt register arguments scanned so far. */ 1577 int iwmmxt_nregs; 1578 int named_count; 1579 int nargs; 1580 /* Which procedure call variant to use for this call. */ 1581 enum arm_pcs pcs_variant; 1582 1583 /* AAPCS related state tracking. */ 1584 int aapcs_arg_processed; /* No need to lay out this argument again. */ 1585 int aapcs_cprc_slot; /* Index of co-processor rules to handle 1586 this argument, or -1 if using core 1587 registers. */ 1588 int aapcs_ncrn; 1589 int aapcs_next_ncrn; 1590 rtx aapcs_reg; /* Register assigned to this argument. */ 1591 int aapcs_partial; /* How many bytes are passed in regs (if 1592 split between core regs and stack. 1593 Zero otherwise. */ 1594 int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS]; 1595 int can_split; /* Argument can be split between core regs 1596 and the stack. */ 1597 /* Private data for tracking VFP register allocation */ 1598 unsigned aapcs_vfp_regs_free; 1599 unsigned aapcs_vfp_reg_alloc; 1600 int aapcs_vfp_rcount; 1601 MACHMODE aapcs_vfp_rmode; 1602} CUMULATIVE_ARGS; 1603 1604#define FUNCTION_ARG_PADDING(MODE, TYPE) \ 1605 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward) 1606 1607#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ 1608 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward) 1609 1610/* For AAPCS, padding should never be below the argument. For other ABIs, 1611 * mimic the default. */ 1612#define PAD_VARARGS_DOWN \ 1613 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN) 1614 1615/* Initialize a variable CUM of type CUMULATIVE_ARGS 1616 for a call to a function whose data type is FNTYPE. 1617 For a library call, FNTYPE is 0. 1618 On the ARM, the offset starts at 0. */ 1619#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1620 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) 1621 1622/* 1 if N is a possible register number for function argument passing. 1623 On the ARM, r0-r3 are used to pass args. */ 1624#define FUNCTION_ARG_REGNO_P(REGNO) \ 1625 (IN_RANGE ((REGNO), 0, 3) \ 1626 || (TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT \ 1627 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \ 1628 || (TARGET_IWMMXT_ABI \ 1629 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9))) 1630 1631 1632/* If your target environment doesn't prefix user functions with an 1633 underscore, you may wish to re-define this to prevent any conflicts. */ 1634#ifndef ARM_MCOUNT_NAME 1635#define ARM_MCOUNT_NAME "*mcount" 1636#endif 1637 1638/* Call the function profiler with a given profile label. The Acorn 1639 compiler puts this BEFORE the prolog but gcc puts it afterwards. 1640 On the ARM the full profile code will look like: 1641 .data 1642 LP1 1643 .word 0 1644 .text 1645 mov ip, lr 1646 bl mcount 1647 .word LP1 1648 1649 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER 1650 will output the .text section. 1651 1652 The ``mov ip,lr'' seems like a good idea to stick with cc convention. 1653 ``prof'' doesn't seem to mind about this! 1654 1655 Note - this version of the code is designed to work in both ARM and 1656 Thumb modes. */ 1657#ifndef ARM_FUNCTION_PROFILER 1658#define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \ 1659{ \ 1660 char temp[20]; \ 1661 rtx sym; \ 1662 \ 1663 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \ 1664 IP_REGNUM, LR_REGNUM); \ 1665 assemble_name (STREAM, ARM_MCOUNT_NAME); \ 1666 fputc ('\n', STREAM); \ 1667 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \ 1668 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \ 1669 assemble_aligned_integer (UNITS_PER_WORD, sym); \ 1670} 1671#endif 1672 1673#ifdef THUMB_FUNCTION_PROFILER 1674#define FUNCTION_PROFILER(STREAM, LABELNO) \ 1675 if (TARGET_ARM) \ 1676 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \ 1677 else \ 1678 THUMB_FUNCTION_PROFILER (STREAM, LABELNO) 1679#else 1680#define FUNCTION_PROFILER(STREAM, LABELNO) \ 1681 ARM_FUNCTION_PROFILER (STREAM, LABELNO) 1682#endif 1683 1684/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1685 the stack pointer does not matter. The value is tested only in 1686 functions that have frame pointers. 1687 No definition is equivalent to always zero. 1688 1689 On the ARM, the function epilogue recovers the stack pointer from the 1690 frame. */ 1691#define EXIT_IGNORE_STACK 1 1692 1693#define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNUM) 1694 1695/* Determine if the epilogue should be output as RTL. 1696 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ 1697#define USE_RETURN_INSN(ISCOND) \ 1698 (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0) 1699 1700/* Definitions for register eliminations. 1701 1702 This is an array of structures. Each structure initializes one pair 1703 of eliminable registers. The "from" register number is given first, 1704 followed by "to". Eliminations of the same "from" register are listed 1705 in order of preference. 1706 1707 We have two registers that can be eliminated on the ARM. First, the 1708 arg pointer register can often be eliminated in favor of the stack 1709 pointer register. Secondly, the pseudo frame pointer register can always 1710 be eliminated; it is replaced with either the stack or the real frame 1711 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM 1712 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */ 1713 1714#define ELIMINABLE_REGS \ 1715{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1716 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\ 1717 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1718 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\ 1719 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1720 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1721 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }} 1722 1723/* Define the offset between two registers, one to be eliminated, and the 1724 other its replacement, at the start of a routine. */ 1725#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1726 if (TARGET_ARM) \ 1727 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \ 1728 else \ 1729 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO) 1730 1731/* Special case handling of the location of arguments passed on the stack. */ 1732#define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr) 1733 1734/* Initialize data used by insn expanders. This is called from insn_emit, 1735 once for every function before code is generated. */ 1736#define INIT_EXPANDERS arm_init_expanders () 1737 1738/* Length in units of the trampoline for entering a nested function. */ 1739#define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20) 1740 1741/* Alignment required for a trampoline in bits. */ 1742#define TRAMPOLINE_ALIGNMENT 32 1743 1744/* Addressing modes, and classification of registers for them. */ 1745#define HAVE_POST_INCREMENT 1 1746#define HAVE_PRE_INCREMENT TARGET_32BIT 1747#define HAVE_POST_DECREMENT TARGET_32BIT 1748#define HAVE_PRE_DECREMENT TARGET_32BIT 1749#define HAVE_PRE_MODIFY_DISP TARGET_32BIT 1750#define HAVE_POST_MODIFY_DISP TARGET_32BIT 1751#define HAVE_PRE_MODIFY_REG TARGET_32BIT 1752#define HAVE_POST_MODIFY_REG TARGET_32BIT 1753 1754/* Macros to check register numbers against specific register classes. */ 1755 1756/* These assume that REGNO is a hard or pseudo reg number. 1757 They give nonzero only if REGNO is a hard reg of the suitable class 1758 or a pseudo reg currently allocated to a suitable hard reg. 1759 Since they use reg_renumber, they are safe only once reg_renumber 1760 has been allocated, which happens in local-alloc.c. */ 1761#define TEST_REGNO(R, TEST, VALUE) \ 1762 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE)) 1763 1764/* Don't allow the pc to be used. */ 1765#define ARM_REGNO_OK_FOR_BASE_P(REGNO) \ 1766 (TEST_REGNO (REGNO, <, PC_REGNUM) \ 1767 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \ 1768 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM)) 1769 1770#define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1771 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \ 1772 || (GET_MODE_SIZE (MODE) >= 4 \ 1773 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))) 1774 1775#define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1776 (TARGET_THUMB1 \ 1777 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \ 1778 : ARM_REGNO_OK_FOR_BASE_P (REGNO)) 1779 1780/* Nonzero if X can be the base register in a reg+reg addressing mode. 1781 For Thumb, we can not use SP + reg, so reject SP. */ 1782#define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 1783 REGNO_MODE_OK_FOR_BASE_P (X, QImode) 1784 1785/* For ARM code, we don't care about the mode, but for Thumb, the index 1786 must be suitable for use in a QImode load. */ 1787#define REGNO_OK_FOR_INDEX_P(REGNO) \ 1788 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \ 1789 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)) 1790 1791/* Maximum number of registers that can appear in a valid memory address. 1792 Shifts in addresses can't be by a register. */ 1793#define MAX_REGS_PER_ADDRESS 2 1794 1795/* Recognize any constant value that is a valid address. */ 1796/* XXX We can address any constant, eventually... */ 1797/* ??? Should the TARGET_ARM here also apply to thumb2? */ 1798#define CONSTANT_ADDRESS_P(X) \ 1799 (GET_CODE (X) == SYMBOL_REF \ 1800 && (CONSTANT_POOL_ADDRESS_P (X) \ 1801 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X)))) 1802 1803/* True if SYMBOL + OFFSET constants must refer to something within 1804 SYMBOL's section. */ 1805#define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0 1806 1807/* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */ 1808#ifndef TARGET_DEFAULT_WORD_RELOCATIONS 1809#define TARGET_DEFAULT_WORD_RELOCATIONS 0 1810#endif 1811 1812/* Nonzero if the constant value X is a legitimate general operand. 1813 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. 1814 1815 On the ARM, allow any integer (invalid ones are removed later by insn 1816 patterns), nice doubles and symbol_refs which refer to the function's 1817 constant pool XXX. 1818 1819 When generating pic allow anything. */ 1820#define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X)) 1821 1822#define THUMB_LEGITIMATE_CONSTANT_P(X) \ 1823 ( GET_CODE (X) == CONST_INT \ 1824 || GET_CODE (X) == CONST_DOUBLE \ 1825 || CONSTANT_ADDRESS_P (X) \ 1826 || flag_pic) 1827 1828#define LEGITIMATE_CONSTANT_P(X) \ 1829 (!arm_cannot_force_const_mem (X) \ 1830 && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X) \ 1831 : THUMB_LEGITIMATE_CONSTANT_P (X))) 1832 1833#ifndef SUBTARGET_NAME_ENCODING_LENGTHS 1834#define SUBTARGET_NAME_ENCODING_LENGTHS 1835#endif 1836 1837/* This is a C fragment for the inside of a switch statement. 1838 Each case label should return the number of characters to 1839 be stripped from the start of a function's name, if that 1840 name starts with the indicated character. */ 1841#define ARM_NAME_ENCODING_LENGTHS \ 1842 case '*': return 1; \ 1843 SUBTARGET_NAME_ENCODING_LENGTHS 1844 1845/* This is how to output a reference to a user-level label named NAME. 1846 `assemble_name' uses this. */ 1847#undef ASM_OUTPUT_LABELREF 1848#define ASM_OUTPUT_LABELREF(FILE, NAME) \ 1849 arm_asm_output_labelref (FILE, NAME) 1850 1851/* Output IT instructions for conditionally executed Thumb-2 instructions. */ 1852#define ASM_OUTPUT_OPCODE(STREAM, PTR) \ 1853 if (TARGET_THUMB2) \ 1854 thumb2_asm_output_opcode (STREAM); 1855 1856/* The EABI specifies that constructors should go in .init_array. 1857 Other targets use .ctors for compatibility. */ 1858#ifndef ARM_EABI_CTORS_SECTION_OP 1859#define ARM_EABI_CTORS_SECTION_OP \ 1860 "\t.section\t.init_array,\"aw\",%init_array" 1861#endif 1862#ifndef ARM_EABI_DTORS_SECTION_OP 1863#define ARM_EABI_DTORS_SECTION_OP \ 1864 "\t.section\t.fini_array,\"aw\",%fini_array" 1865#endif 1866#define ARM_CTORS_SECTION_OP \ 1867 "\t.section\t.ctors,\"aw\",%progbits" 1868#define ARM_DTORS_SECTION_OP \ 1869 "\t.section\t.dtors,\"aw\",%progbits" 1870 1871/* Define CTORS_SECTION_ASM_OP. */ 1872#undef CTORS_SECTION_ASM_OP 1873#undef DTORS_SECTION_ASM_OP 1874#ifndef IN_LIBGCC2 1875# define CTORS_SECTION_ASM_OP \ 1876 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP) 1877# define DTORS_SECTION_ASM_OP \ 1878 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP) 1879#else /* !defined (IN_LIBGCC2) */ 1880/* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant, 1881 so we cannot use the definition above. */ 1882# ifdef __ARM_EABI__ 1883/* The .ctors section is not part of the EABI, so we do not define 1884 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff 1885 from trying to use it. We do define it when doing normal 1886 compilation, as .init_array can be used instead of .ctors. */ 1887/* There is no need to emit begin or end markers when using 1888 init_array; the dynamic linker will compute the size of the 1889 array itself based on special symbols created by the static 1890 linker. However, we do need to arrange to set up 1891 exception-handling here. */ 1892# define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP) 1893# define CTOR_LIST_END /* empty */ 1894# define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP) 1895# define DTOR_LIST_END /* empty */ 1896# else /* !defined (__ARM_EABI__) */ 1897# define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP 1898# define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP 1899# endif /* !defined (__ARM_EABI__) */ 1900#endif /* !defined (IN_LIBCC2) */ 1901 1902/* True if the operating system can merge entities with vague linkage 1903 (e.g., symbols in COMDAT group) during dynamic linking. */ 1904#ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P 1905#define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true 1906#endif 1907 1908#define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE) 1909 1910/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1911 and check its validity for a certain class. 1912 We have two alternate definitions for each of them. 1913 The usual definition accepts all pseudo regs; the other rejects 1914 them unless they have been allocated suitable hard regs. 1915 The symbol REG_OK_STRICT causes the latter definition to be used. 1916 Thumb-2 has the same restrictions as arm. */ 1917#ifndef REG_OK_STRICT 1918 1919#define ARM_REG_OK_FOR_BASE_P(X) \ 1920 (REGNO (X) <= LAST_ARM_REGNUM \ 1921 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1922 || REGNO (X) == FRAME_POINTER_REGNUM \ 1923 || REGNO (X) == ARG_POINTER_REGNUM) 1924 1925#define ARM_REG_OK_FOR_INDEX_P(X) \ 1926 ((REGNO (X) <= LAST_ARM_REGNUM \ 1927 && REGNO (X) != STACK_POINTER_REGNUM) \ 1928 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1929 || REGNO (X) == FRAME_POINTER_REGNUM \ 1930 || REGNO (X) == ARG_POINTER_REGNUM) 1931 1932#define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1933 (REGNO (X) <= LAST_LO_REGNUM \ 1934 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1935 || (GET_MODE_SIZE (MODE) >= 4 \ 1936 && (REGNO (X) == STACK_POINTER_REGNUM \ 1937 || (X) == hard_frame_pointer_rtx \ 1938 || (X) == arg_pointer_rtx))) 1939 1940#define REG_STRICT_P 0 1941 1942#else /* REG_OK_STRICT */ 1943 1944#define ARM_REG_OK_FOR_BASE_P(X) \ 1945 ARM_REGNO_OK_FOR_BASE_P (REGNO (X)) 1946 1947#define ARM_REG_OK_FOR_INDEX_P(X) \ 1948 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X)) 1949 1950#define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1951 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE) 1952 1953#define REG_STRICT_P 1 1954 1955#endif /* REG_OK_STRICT */ 1956 1957/* Now define some helpers in terms of the above. */ 1958 1959#define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1960 (TARGET_THUMB1 \ 1961 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \ 1962 : ARM_REG_OK_FOR_BASE_P (X)) 1963 1964/* For 16-bit Thumb, a valid index register is anything that can be used in 1965 a byte load instruction. */ 1966#define THUMB1_REG_OK_FOR_INDEX_P(X) \ 1967 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode) 1968 1969/* Nonzero if X is a hard reg that can be used as an index 1970 or if it is a pseudo reg. On the Thumb, the stack pointer 1971 is not suitable. */ 1972#define REG_OK_FOR_INDEX_P(X) \ 1973 (TARGET_THUMB1 \ 1974 ? THUMB1_REG_OK_FOR_INDEX_P (X) \ 1975 : ARM_REG_OK_FOR_INDEX_P (X)) 1976 1977/* Nonzero if X can be the base register in a reg+reg addressing mode. 1978 For Thumb, we can not use SP + reg, so reject SP. */ 1979#define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 1980 REG_OK_FOR_INDEX_P (X) 1981 1982#define ARM_BASE_REGISTER_RTX_P(X) \ 1983 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X)) 1984 1985#define ARM_INDEX_REGISTER_RTX_P(X) \ 1986 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X)) 1987 1988/* Specify the machine mode that this machine uses 1989 for the index in the tablejump instruction. */ 1990#define CASE_VECTOR_MODE Pmode 1991 1992#define CASE_VECTOR_PC_RELATIVE (TARGET_THUMB2 \ 1993 || (TARGET_THUMB1 \ 1994 && (optimize_size || flag_pic))) 1995 1996#define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ 1997 (TARGET_THUMB1 \ 1998 ? (min >= 0 && max < 512 \ 1999 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \ 2000 : min >= -256 && max < 256 \ 2001 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \ 2002 : min >= 0 && max < 8192 \ 2003 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \ 2004 : min >= -4096 && max < 4096 \ 2005 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \ 2006 : SImode) \ 2007 : ((min < 0 || max >= 0x2000 || !TARGET_THUMB2) ? SImode \ 2008 : (max >= 0x200) ? HImode \ 2009 : QImode)) 2010 2011/* signed 'char' is most compatible, but RISC OS wants it unsigned. 2012 unsigned is probably best, but may break some code. */ 2013#ifndef DEFAULT_SIGNED_CHAR 2014#define DEFAULT_SIGNED_CHAR 0 2015#endif 2016 2017/* Max number of bytes we can move from memory to memory 2018 in one reasonably fast instruction. */ 2019#define MOVE_MAX 4 2020 2021#undef MOVE_RATIO 2022#define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2) 2023 2024/* Define if operations between registers always perform the operation 2025 on the full register even if a narrower mode is specified. */ 2026#define WORD_REGISTER_OPERATIONS 2027 2028/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 2029 will either zero-extend or sign-extend. The value of this macro should 2030 be the code that says which one of the two operations is implicitly 2031 done, UNKNOWN if none. */ 2032#define LOAD_EXTEND_OP(MODE) \ 2033 (TARGET_THUMB ? ZERO_EXTEND : \ 2034 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ 2035 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN))) 2036 2037/* Nonzero if access to memory by bytes is slow and undesirable. */ 2038#define SLOW_BYTE_ACCESS 0 2039 2040#define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1 2041 2042/* Immediate shift counts are truncated by the output routines (or was it 2043 the assembler?). Shift counts in a register are truncated by ARM. Note 2044 that the native compiler puts too large (> 32) immediate shift counts 2045 into a register and shifts by the register, letting the ARM decide what 2046 to do instead of doing that itself. */ 2047/* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that 2048 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). 2049 On the arm, Y in a register is used modulo 256 for the shift. Only for 2050 rotates is modulo 32 used. */ 2051/* #define SHIFT_COUNT_TRUNCATED 1 */ 2052 2053/* All integers have the same format so truncation is easy. */ 2054#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 2055 2056/* Calling from registers is a massive pain. */ 2057#define NO_FUNCTION_CSE 1 2058 2059/* The machine modes of pointers and functions */ 2060#define Pmode SImode 2061#define FUNCTION_MODE Pmode 2062 2063#define ARM_FRAME_RTX(X) \ 2064 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ 2065 || (X) == arg_pointer_rtx) 2066 2067/* Moves to and from memory are quite expensive */ 2068#define MEMORY_MOVE_COST(M, CLASS, IN) \ 2069 (TARGET_32BIT ? 10 : \ 2070 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \ 2071 * (CLASS == LO_REGS ? 1 : 2))) 2072 2073/* Try to generate sequences that don't involve branches, we can then use 2074 conditional instructions */ 2075#define BRANCH_COST(speed_p, predictable_p) \ 2076 (current_tune->branch_cost (speed_p, predictable_p)) 2077 2078 2079/* Position Independent Code. */ 2080/* We decide which register to use based on the compilation options and 2081 the assembler in use; this is more general than the APCS restriction of 2082 using sb (r9) all the time. */ 2083extern unsigned arm_pic_register; 2084 2085/* The register number of the register used to address a table of static 2086 data addresses in memory. */ 2087#define PIC_OFFSET_TABLE_REGNUM arm_pic_register 2088 2089/* We can't directly access anything that contains a symbol, 2090 nor can we indirect via the constant pool. One exception is 2091 UNSPEC_TLS, which is always PIC. */ 2092#define LEGITIMATE_PIC_OPERAND_P(X) \ 2093 (!(symbol_mentioned_p (X) \ 2094 || label_mentioned_p (X) \ 2095 || (GET_CODE (X) == SYMBOL_REF \ 2096 && CONSTANT_POOL_ADDRESS_P (X) \ 2097 && (symbol_mentioned_p (get_pool_constant (X)) \ 2098 || label_mentioned_p (get_pool_constant (X))))) \ 2099 || tls_mentioned_p (X)) 2100 2101/* We need to know when we are making a constant pool; this determines 2102 whether data needs to be in the GOT or can be referenced via a GOT 2103 offset. */ 2104extern int making_const_table; 2105 2106/* Handle pragmas for compatibility with Intel's compilers. */ 2107/* Also abuse this to register additional C specific EABI attributes. */ 2108#define REGISTER_TARGET_PRAGMAS() do { \ 2109 c_register_pragma (0, "long_calls", arm_pr_long_calls); \ 2110 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \ 2111 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \ 2112 arm_lang_object_attributes_init(); \ 2113} while (0) 2114 2115/* Condition code information. */ 2116/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2117 return the mode to be used for the comparison. */ 2118 2119#define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y) 2120 2121#define REVERSIBLE_CC_MODE(MODE) 1 2122 2123#define REVERSE_CONDITION(CODE,MODE) \ 2124 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ 2125 ? reverse_condition_maybe_unordered (code) \ 2126 : reverse_condition (code)) 2127 2128#define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \ 2129 (CODE) = arm_canonicalize_comparison (CODE, &(OP0), &(OP1)) 2130 2131/* The arm5 clz instruction returns 32. */ 2132#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) 2133#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) 2134 2135#define CC_STATUS_INIT \ 2136 do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0) 2137 2138#undef ASM_APP_OFF 2139#define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \ 2140 TARGET_THUMB2 ? "\t.thumb\n" : "") 2141 2142/* Output a push or a pop instruction (only used when profiling). 2143 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know 2144 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and 2145 that r7 isn't used by the function profiler, so we can use it as a 2146 scratch reg. WARNING: This isn't safe in the general case! It may be 2147 sensitive to future changes in final.c:profile_function. */ 2148#define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ 2149 do \ 2150 { \ 2151 if (TARGET_ARM) \ 2152 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \ 2153 STACK_POINTER_REGNUM, REGNO); \ 2154 else if (TARGET_THUMB1 \ 2155 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2156 { \ 2157 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2158 asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\ 2159 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2160 } \ 2161 else \ 2162 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \ 2163 } while (0) 2164 2165 2166/* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */ 2167#define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ 2168 do \ 2169 { \ 2170 if (TARGET_ARM) \ 2171 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \ 2172 STACK_POINTER_REGNUM, REGNO); \ 2173 else if (TARGET_THUMB1 \ 2174 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2175 { \ 2176 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2177 asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\ 2178 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2179 } \ 2180 else \ 2181 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \ 2182 } while (0) 2183 2184/* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */ 2185#define ADDR_VEC_ALIGN(JUMPTABLE) 0 2186 2187/* This is how to output a label which precedes a jumptable. Since 2188 Thumb instructions are 2 bytes, we may need explicit alignment here. */ 2189#undef ASM_OUTPUT_CASE_LABEL 2190#define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \ 2191 do \ 2192 { \ 2193 if (TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) \ 2194 ASM_OUTPUT_ALIGN (FILE, 2); \ 2195 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \ 2196 } \ 2197 while (0) 2198 2199/* Make sure subsequent insns are aligned after a TBB. */ 2200#define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \ 2201 do \ 2202 { \ 2203 if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \ 2204 ASM_OUTPUT_ALIGN (FILE, 1); \ 2205 } \ 2206 while (0) 2207 2208#define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ 2209 do \ 2210 { \ 2211 if (TARGET_THUMB) \ 2212 { \ 2213 if (is_called_in_ARM_mode (DECL) \ 2214 || (TARGET_THUMB1 && !TARGET_THUMB1_ONLY \ 2215 && cfun->is_thunk)) \ 2216 fprintf (STREAM, "\t.code 32\n") ; \ 2217 else if (TARGET_THUMB1) \ 2218 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \ 2219 else \ 2220 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \ 2221 } \ 2222 if (TARGET_POKE_FUNCTION_NAME) \ 2223 arm_poke_function_name (STREAM, (const char *) NAME); \ 2224 } \ 2225 while (0) 2226 2227/* For aliases of functions we use .thumb_set instead. */ 2228#define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \ 2229 do \ 2230 { \ 2231 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \ 2232 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \ 2233 \ 2234 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \ 2235 { \ 2236 fprintf (FILE, "\t.thumb_set "); \ 2237 assemble_name (FILE, LABEL1); \ 2238 fprintf (FILE, ","); \ 2239 assemble_name (FILE, LABEL2); \ 2240 fprintf (FILE, "\n"); \ 2241 } \ 2242 else \ 2243 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \ 2244 } \ 2245 while (0) 2246 2247#ifdef HAVE_GAS_MAX_SKIP_P2ALIGN 2248/* To support -falign-* switches we need to use .p2align so 2249 that alignment directives in code sections will be padded 2250 with no-op instructions, rather than zeroes. */ 2251#define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \ 2252 if ((LOG) != 0) \ 2253 { \ 2254 if ((MAX_SKIP) == 0) \ 2255 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \ 2256 else \ 2257 fprintf ((FILE), "\t.p2align %d,,%d\n", \ 2258 (int) (LOG), (int) (MAX_SKIP)); \ 2259 } 2260#endif 2261 2262/* Add two bytes to the length of conditionally executed Thumb-2 2263 instructions for the IT instruction. */ 2264#define ADJUST_INSN_LENGTH(insn, length) \ 2265 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \ 2266 length += 2; 2267 2268/* Only perform branch elimination (by making instructions conditional) if 2269 we're optimizing. For Thumb-2 check if any IT instructions need 2270 outputting. */ 2271#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 2272 if (TARGET_ARM && optimize) \ 2273 arm_final_prescan_insn (INSN); \ 2274 else if (TARGET_THUMB2) \ 2275 thumb2_final_prescan_insn (INSN); \ 2276 else if (TARGET_THUMB1) \ 2277 thumb1_final_prescan_insn (INSN) 2278 2279#define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ 2280 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \ 2281 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\ 2282 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \ 2283 ? ((~ (unsigned HOST_WIDE_INT) 0) \ 2284 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \ 2285 : 0)))) 2286 2287/* A C expression whose value is RTL representing the value of the return 2288 address for the frame COUNT steps up from the current frame. */ 2289 2290#define RETURN_ADDR_RTX(COUNT, FRAME) \ 2291 arm_return_addr (COUNT, FRAME) 2292 2293#define RETURN_ADDR_REGNUM LR_REGNUM 2294 2295/* Mask of the bits in the PC that contain the real return address 2296 when running in 26-bit mode. */ 2297#define RETURN_ADDR_MASK26 (0x03fffffc) 2298 2299/* Pick up the return address upon entry to a procedure. Used for 2300 dwarf2 unwind information. This also enables the table driven 2301 mechanism. */ 2302#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) 2303#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) 2304 2305/* Used to mask out junk bits from the return address, such as 2306 processor state, interrupt status, condition codes and the like. */ 2307#define MASK_RETURN_ADDR \ 2308 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ 2309 in 26 bit mode, the condition codes must be masked out of the \ 2310 return address. This does not apply to ARM6 and later processors \ 2311 when running in 32 bit mode. */ \ 2312 ((arm_arch4 || TARGET_THUMB) \ 2313 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \ 2314 : arm_gen_return_addr_mask ()) 2315 2316 2317/* Neon defines builtins from ARM_BUILTIN_MAX upwards, though they don't have 2318 symbolic names defined here (which would require too much duplication). 2319 FIXME? */ 2320enum arm_builtins 2321{ 2322 ARM_BUILTIN_GETWCX, 2323 ARM_BUILTIN_SETWCX, 2324 2325 ARM_BUILTIN_WZERO, 2326 2327 ARM_BUILTIN_WAVG2BR, 2328 ARM_BUILTIN_WAVG2HR, 2329 ARM_BUILTIN_WAVG2B, 2330 ARM_BUILTIN_WAVG2H, 2331 2332 ARM_BUILTIN_WACCB, 2333 ARM_BUILTIN_WACCH, 2334 ARM_BUILTIN_WACCW, 2335 2336 ARM_BUILTIN_WMACS, 2337 ARM_BUILTIN_WMACSZ, 2338 ARM_BUILTIN_WMACU, 2339 ARM_BUILTIN_WMACUZ, 2340 2341 ARM_BUILTIN_WSADB, 2342 ARM_BUILTIN_WSADBZ, 2343 ARM_BUILTIN_WSADH, 2344 ARM_BUILTIN_WSADHZ, 2345 2346 ARM_BUILTIN_WALIGN, 2347 2348 ARM_BUILTIN_TMIA, 2349 ARM_BUILTIN_TMIAPH, 2350 ARM_BUILTIN_TMIABB, 2351 ARM_BUILTIN_TMIABT, 2352 ARM_BUILTIN_TMIATB, 2353 ARM_BUILTIN_TMIATT, 2354 2355 ARM_BUILTIN_TMOVMSKB, 2356 ARM_BUILTIN_TMOVMSKH, 2357 ARM_BUILTIN_TMOVMSKW, 2358 2359 ARM_BUILTIN_TBCSTB, 2360 ARM_BUILTIN_TBCSTH, 2361 ARM_BUILTIN_TBCSTW, 2362 2363 ARM_BUILTIN_WMADDS, 2364 ARM_BUILTIN_WMADDU, 2365 2366 ARM_BUILTIN_WPACKHSS, 2367 ARM_BUILTIN_WPACKWSS, 2368 ARM_BUILTIN_WPACKDSS, 2369 ARM_BUILTIN_WPACKHUS, 2370 ARM_BUILTIN_WPACKWUS, 2371 ARM_BUILTIN_WPACKDUS, 2372 2373 ARM_BUILTIN_WADDB, 2374 ARM_BUILTIN_WADDH, 2375 ARM_BUILTIN_WADDW, 2376 ARM_BUILTIN_WADDSSB, 2377 ARM_BUILTIN_WADDSSH, 2378 ARM_BUILTIN_WADDSSW, 2379 ARM_BUILTIN_WADDUSB, 2380 ARM_BUILTIN_WADDUSH, 2381 ARM_BUILTIN_WADDUSW, 2382 ARM_BUILTIN_WSUBB, 2383 ARM_BUILTIN_WSUBH, 2384 ARM_BUILTIN_WSUBW, 2385 ARM_BUILTIN_WSUBSSB, 2386 ARM_BUILTIN_WSUBSSH, 2387 ARM_BUILTIN_WSUBSSW, 2388 ARM_BUILTIN_WSUBUSB, 2389 ARM_BUILTIN_WSUBUSH, 2390 ARM_BUILTIN_WSUBUSW, 2391 2392 ARM_BUILTIN_WAND, 2393 ARM_BUILTIN_WANDN, 2394 ARM_BUILTIN_WOR, 2395 ARM_BUILTIN_WXOR, 2396 2397 ARM_BUILTIN_WCMPEQB, 2398 ARM_BUILTIN_WCMPEQH, 2399 ARM_BUILTIN_WCMPEQW, 2400 ARM_BUILTIN_WCMPGTUB, 2401 ARM_BUILTIN_WCMPGTUH, 2402 ARM_BUILTIN_WCMPGTUW, 2403 ARM_BUILTIN_WCMPGTSB, 2404 ARM_BUILTIN_WCMPGTSH, 2405 ARM_BUILTIN_WCMPGTSW, 2406 2407 ARM_BUILTIN_TEXTRMSB, 2408 ARM_BUILTIN_TEXTRMSH, 2409 ARM_BUILTIN_TEXTRMSW, 2410 ARM_BUILTIN_TEXTRMUB, 2411 ARM_BUILTIN_TEXTRMUH, 2412 ARM_BUILTIN_TEXTRMUW, 2413 ARM_BUILTIN_TINSRB, 2414 ARM_BUILTIN_TINSRH, 2415 ARM_BUILTIN_TINSRW, 2416 2417 ARM_BUILTIN_WMAXSW, 2418 ARM_BUILTIN_WMAXSH, 2419 ARM_BUILTIN_WMAXSB, 2420 ARM_BUILTIN_WMAXUW, 2421 ARM_BUILTIN_WMAXUH, 2422 ARM_BUILTIN_WMAXUB, 2423 ARM_BUILTIN_WMINSW, 2424 ARM_BUILTIN_WMINSH, 2425 ARM_BUILTIN_WMINSB, 2426 ARM_BUILTIN_WMINUW, 2427 ARM_BUILTIN_WMINUH, 2428 ARM_BUILTIN_WMINUB, 2429 2430 ARM_BUILTIN_WMULUM, 2431 ARM_BUILTIN_WMULSM, 2432 ARM_BUILTIN_WMULUL, 2433 2434 ARM_BUILTIN_PSADBH, 2435 ARM_BUILTIN_WSHUFH, 2436 2437 ARM_BUILTIN_WSLLH, 2438 ARM_BUILTIN_WSLLW, 2439 ARM_BUILTIN_WSLLD, 2440 ARM_BUILTIN_WSRAH, 2441 ARM_BUILTIN_WSRAW, 2442 ARM_BUILTIN_WSRAD, 2443 ARM_BUILTIN_WSRLH, 2444 ARM_BUILTIN_WSRLW, 2445 ARM_BUILTIN_WSRLD, 2446 ARM_BUILTIN_WRORH, 2447 ARM_BUILTIN_WRORW, 2448 ARM_BUILTIN_WRORD, 2449 ARM_BUILTIN_WSLLHI, 2450 ARM_BUILTIN_WSLLWI, 2451 ARM_BUILTIN_WSLLDI, 2452 ARM_BUILTIN_WSRAHI, 2453 ARM_BUILTIN_WSRAWI, 2454 ARM_BUILTIN_WSRADI, 2455 ARM_BUILTIN_WSRLHI, 2456 ARM_BUILTIN_WSRLWI, 2457 ARM_BUILTIN_WSRLDI, 2458 ARM_BUILTIN_WRORHI, 2459 ARM_BUILTIN_WRORWI, 2460 ARM_BUILTIN_WRORDI, 2461 2462 ARM_BUILTIN_WUNPCKIHB, 2463 ARM_BUILTIN_WUNPCKIHH, 2464 ARM_BUILTIN_WUNPCKIHW, 2465 ARM_BUILTIN_WUNPCKILB, 2466 ARM_BUILTIN_WUNPCKILH, 2467 ARM_BUILTIN_WUNPCKILW, 2468 2469 ARM_BUILTIN_WUNPCKEHSB, 2470 ARM_BUILTIN_WUNPCKEHSH, 2471 ARM_BUILTIN_WUNPCKEHSW, 2472 ARM_BUILTIN_WUNPCKEHUB, 2473 ARM_BUILTIN_WUNPCKEHUH, 2474 ARM_BUILTIN_WUNPCKEHUW, 2475 ARM_BUILTIN_WUNPCKELSB, 2476 ARM_BUILTIN_WUNPCKELSH, 2477 ARM_BUILTIN_WUNPCKELSW, 2478 ARM_BUILTIN_WUNPCKELUB, 2479 ARM_BUILTIN_WUNPCKELUH, 2480 ARM_BUILTIN_WUNPCKELUW, 2481 2482 ARM_BUILTIN_THREAD_POINTER, 2483 2484 ARM_BUILTIN_NEON_BASE, 2485 2486 ARM_BUILTIN_MAX = ARM_BUILTIN_NEON_BASE /* FIXME: Wrong! */ 2487}; 2488 2489/* Do not emit .note.GNU-stack by default. */ 2490#ifndef NEED_INDICATE_EXEC_STACK 2491#define NEED_INDICATE_EXEC_STACK 0 2492#endif 2493 2494/* The maximum number of parallel loads or stores we support in an ldm/stm 2495 instruction. */ 2496#define MAX_LDM_STM_OPS 4 2497 2498#endif /* ! GCC_ARM_H */ 2499