1/* 2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 27#ifndef _I915_DRM_H_ 28#define _I915_DRM_H_ 29 30#include "drm.h" 31 32/* Please note that modifications to all structs defined here are 33 * subject to backwards-compatibility constraints. 34 */ 35 36 37/* Each region is a minimum of 16k, and there are at most 255 of them. 38 */ 39#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 40 * of chars for next/prev indices */ 41#define I915_LOG_MIN_TEX_REGION_SIZE 14 42 43typedef struct _drm_i915_init { 44 enum { 45 I915_INIT_DMA = 0x01, 46 I915_CLEANUP_DMA = 0x02, 47 I915_RESUME_DMA = 0x03 48 } func; 49 unsigned int mmio_offset; 50 int sarea_priv_offset; 51 unsigned int ring_start; 52 unsigned int ring_end; 53 unsigned int ring_size; 54 unsigned int front_offset; 55 unsigned int back_offset; 56 unsigned int depth_offset; 57 unsigned int w; 58 unsigned int h; 59 unsigned int pitch; 60 unsigned int pitch_bits; 61 unsigned int back_pitch; 62 unsigned int depth_pitch; 63 unsigned int cpp; 64 unsigned int chipset; 65} drm_i915_init_t; 66 67typedef struct _drm_i915_sarea { 68 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 69 int last_upload; /* last time texture was uploaded */ 70 int last_enqueue; /* last time a buffer was enqueued */ 71 int last_dispatch; /* age of the most recently dispatched buffer */ 72 int ctxOwner; /* last context to upload state */ 73 int texAge; 74 int pf_enabled; /* is pageflipping allowed? */ 75 int pf_active; 76 int pf_current_page; /* which buffer is being displayed? */ 77 int perf_boxes; /* performance boxes to be displayed */ 78 int width, height; /* screen size in pixels */ 79 80 drm_handle_t front_handle; 81 int front_offset; 82 int front_size; 83 84 drm_handle_t back_handle; 85 int back_offset; 86 int back_size; 87 88 drm_handle_t depth_handle; 89 int depth_offset; 90 int depth_size; 91 92 drm_handle_t tex_handle; 93 int tex_offset; 94 int tex_size; 95 int log_tex_granularity; 96 int pitch; 97 int rotation; /* 0, 90, 180 or 270 */ 98 int rotated_offset; 99 int rotated_size; 100 int rotated_pitch; 101 int virtualX, virtualY; 102 103 unsigned int front_tiled; 104 unsigned int back_tiled; 105 unsigned int depth_tiled; 106 unsigned int rotated_tiled; 107 unsigned int rotated2_tiled; 108 109 int pipeA_x; 110 int pipeA_y; 111 int pipeA_w; 112 int pipeA_h; 113 int pipeB_x; 114 int pipeB_y; 115 int pipeB_w; 116 int pipeB_h; 117 118 /* fill out some space for old userspace triple buffer */ 119 drm_handle_t unused_handle; 120 __u32 unused1, unused2, unused3; 121 122 /* buffer object handles for static buffers. May change 123 * over the lifetime of the client. 124 */ 125 __u32 front_bo_handle; 126 __u32 back_bo_handle; 127 __u32 unused_bo_handle; 128 __u32 depth_bo_handle; 129 130} drm_i915_sarea_t; 131 132/* due to userspace building against these headers we need some compat here */ 133#define planeA_x pipeA_x 134#define planeA_y pipeA_y 135#define planeA_w pipeA_w 136#define planeA_h pipeA_h 137#define planeB_x pipeB_x 138#define planeB_y pipeB_y 139#define planeB_w pipeB_w 140#define planeB_h pipeB_h 141 142/* Flags for perf_boxes 143 */ 144#define I915_BOX_RING_EMPTY 0x1 145#define I915_BOX_FLIP 0x2 146#define I915_BOX_WAIT 0x4 147#define I915_BOX_TEXTURE_LOAD 0x8 148#define I915_BOX_LOST_CONTEXT 0x10 149 150/* I915 specific ioctls 151 * The device specific ioctl range is 0x40 to 0x79. 152 */ 153#define DRM_I915_INIT 0x00 154#define DRM_I915_FLUSH 0x01 155#define DRM_I915_FLIP 0x02 156#define DRM_I915_BATCHBUFFER 0x03 157#define DRM_I915_IRQ_EMIT 0x04 158#define DRM_I915_IRQ_WAIT 0x05 159#define DRM_I915_GETPARAM 0x06 160#define DRM_I915_SETPARAM 0x07 161#define DRM_I915_ALLOC 0x08 162#define DRM_I915_FREE 0x09 163#define DRM_I915_INIT_HEAP 0x0a 164#define DRM_I915_CMDBUFFER 0x0b 165#define DRM_I915_DESTROY_HEAP 0x0c 166#define DRM_I915_SET_VBLANK_PIPE 0x0d 167#define DRM_I915_GET_VBLANK_PIPE 0x0e 168#define DRM_I915_VBLANK_SWAP 0x0f 169#define DRM_I915_HWS_ADDR 0x11 170#define DRM_I915_GEM_INIT 0x13 171#define DRM_I915_GEM_EXECBUFFER 0x14 172#define DRM_I915_GEM_PIN 0x15 173#define DRM_I915_GEM_UNPIN 0x16 174#define DRM_I915_GEM_BUSY 0x17 175#define DRM_I915_GEM_THROTTLE 0x18 176#define DRM_I915_GEM_ENTERVT 0x19 177#define DRM_I915_GEM_LEAVEVT 0x1a 178#define DRM_I915_GEM_CREATE 0x1b 179#define DRM_I915_GEM_PREAD 0x1c 180#define DRM_I915_GEM_PWRITE 0x1d 181#define DRM_I915_GEM_MMAP 0x1e 182#define DRM_I915_GEM_SET_DOMAIN 0x1f 183#define DRM_I915_GEM_SW_FINISH 0x20 184#define DRM_I915_GEM_SET_TILING 0x21 185#define DRM_I915_GEM_GET_TILING 0x22 186#define DRM_I915_GEM_GET_APERTURE 0x23 187#define DRM_I915_GEM_MMAP_GTT 0x24 188#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 189#define DRM_I915_GEM_MADVISE 0x26 190#define DRM_I915_OVERLAY_PUT_IMAGE 0x27 191#define DRM_I915_OVERLAY_ATTRS 0x28 192#define DRM_I915_GEM_EXECBUFFER2 0x29 193 194#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 195#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 196#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 197#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 198#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 199#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 200#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 201#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 202#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 203#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 204#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 205#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 206#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 207#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 208#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 209#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 210#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 211#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 212#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 213#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 214#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 215#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 216#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 217#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 218#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 219#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 220#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 221#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 222#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 223#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 224#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 225#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 226#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 227#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 228#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 229#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 230#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 231#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 232#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_IOCTL_I915_OVERLAY_ATTRS, struct drm_intel_overlay_put_image) 233#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 234 235/* Allow drivers to submit batchbuffers directly to hardware, relying 236 * on the security mechanisms provided by hardware. 237 */ 238typedef struct drm_i915_batchbuffer { 239 int start; /* agp offset */ 240 int used; /* nr bytes in use */ 241 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 242 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 243 int num_cliprects; /* mulitpass with multiple cliprects? */ 244 struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */ 245} drm_i915_batchbuffer_t; 246 247/* As above, but pass a pointer to userspace buffer which can be 248 * validated by the kernel prior to sending to hardware. 249 */ 250typedef struct _drm_i915_cmdbuffer { 251 char *buf; /* pointer to userspace command buffer */ 252 int sz; /* nr bytes in buf */ 253 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 254 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 255 int num_cliprects; /* mulitpass with multiple cliprects? */ 256 struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */ 257} drm_i915_cmdbuffer_t; 258 259/* Userspace can request & wait on irq's: 260 */ 261typedef struct drm_i915_irq_emit { 262 int *irq_seq; 263} drm_i915_irq_emit_t; 264 265typedef struct drm_i915_irq_wait { 266 int irq_seq; 267} drm_i915_irq_wait_t; 268 269/* Ioctl to query kernel params: 270 */ 271#define I915_PARAM_IRQ_ACTIVE 1 272#define I915_PARAM_ALLOW_BATCHBUFFER 2 273#define I915_PARAM_LAST_DISPATCH 3 274#define I915_PARAM_CHIPSET_ID 4 275#define I915_PARAM_HAS_GEM 5 276#define I915_PARAM_NUM_FENCES_AVAIL 6 277#define I915_PARAM_HAS_OVERLAY 7 278#define I915_PARAM_HAS_PAGEFLIPPING 8 279#define I915_PARAM_HAS_EXECBUF2 9 280#define I915_PARAM_HAS_BSD 10 281 282typedef struct drm_i915_getparam { 283 int param; 284 int *value; 285} drm_i915_getparam_t; 286 287/* Ioctl to set kernel params: 288 */ 289#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 290#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 291#define I915_SETPARAM_ALLOW_BATCHBUFFER 3 292#define I915_SETPARAM_NUM_USED_FENCES 4 293 294typedef struct drm_i915_setparam { 295 int param; 296 int value; 297} drm_i915_setparam_t; 298 299/* A memory manager for regions of shared memory: 300 */ 301#define I915_MEM_REGION_AGP 1 302 303typedef struct drm_i915_mem_alloc { 304 int region; 305 int alignment; 306 int size; 307 int *region_offset; /* offset from start of fb or agp */ 308} drm_i915_mem_alloc_t; 309 310typedef struct drm_i915_mem_free { 311 int region; 312 int region_offset; 313} drm_i915_mem_free_t; 314 315typedef struct drm_i915_mem_init_heap { 316 int region; 317 int size; 318 int start; 319} drm_i915_mem_init_heap_t; 320 321/* Allow memory manager to be torn down and re-initialized (eg on 322 * rotate): 323 */ 324typedef struct drm_i915_mem_destroy_heap { 325 int region; 326} drm_i915_mem_destroy_heap_t; 327 328/* Allow X server to configure which pipes to monitor for vblank signals 329 */ 330#define DRM_I915_VBLANK_PIPE_A 1 331#define DRM_I915_VBLANK_PIPE_B 2 332 333typedef struct drm_i915_vblank_pipe { 334 int pipe; 335} drm_i915_vblank_pipe_t; 336 337/* Schedule buffer swap at given vertical blank: 338 */ 339typedef struct drm_i915_vblank_swap { 340 drm_drawable_t drawable; 341 enum drm_vblank_seq_type seqtype; 342 unsigned int sequence; 343} drm_i915_vblank_swap_t; 344 345typedef struct drm_i915_hws_addr { 346 __u64 addr; 347} drm_i915_hws_addr_t; 348 349struct drm_i915_gem_init { 350 /** 351 * Beginning offset in the GTT to be managed by the DRM memory 352 * manager. 353 */ 354 __u64 gtt_start; 355 /** 356 * Ending offset in the GTT to be managed by the DRM memory 357 * manager. 358 */ 359 __u64 gtt_end; 360}; 361 362struct drm_i915_gem_create { 363 /** 364 * Requested size for the object. 365 * 366 * The (page-aligned) allocated size for the object will be returned. 367 */ 368 __u64 size; 369 /** 370 * Returned handle for the object. 371 * 372 * Object handles are nonzero. 373 */ 374 __u32 handle; 375 __u32 pad; 376}; 377 378struct drm_i915_gem_pread { 379 /** Handle for the object being read. */ 380 __u32 handle; 381 __u32 pad; 382 /** Offset into the object to read from */ 383 __u64 offset; 384 /** Length of data to read */ 385 __u64 size; 386 /** 387 * Pointer to write the data into. 388 * 389 * This is a fixed-size type for 32/64 compatibility. 390 */ 391 __u64 data_ptr; 392}; 393 394struct drm_i915_gem_pwrite { 395 /** Handle for the object being written to. */ 396 __u32 handle; 397 __u32 pad; 398 /** Offset into the object to write to */ 399 __u64 offset; 400 /** Length of data to write */ 401 __u64 size; 402 /** 403 * Pointer to read the data from. 404 * 405 * This is a fixed-size type for 32/64 compatibility. 406 */ 407 __u64 data_ptr; 408}; 409 410struct drm_i915_gem_mmap { 411 /** Handle for the object being mapped. */ 412 __u32 handle; 413 __u32 pad; 414 /** Offset in the object to map. */ 415 __u64 offset; 416 /** 417 * Length of data to map. 418 * 419 * The value will be page-aligned. 420 */ 421 __u64 size; 422 /** 423 * Returned pointer the data was mapped at. 424 * 425 * This is a fixed-size type for 32/64 compatibility. 426 */ 427 __u64 addr_ptr; 428}; 429 430struct drm_i915_gem_mmap_gtt { 431 /** Handle for the object being mapped. */ 432 __u32 handle; 433 __u32 pad; 434 /** 435 * Fake offset to use for subsequent mmap call 436 * 437 * This is a fixed-size type for 32/64 compatibility. 438 */ 439 __u64 offset; 440}; 441 442struct drm_i915_gem_set_domain { 443 /** Handle for the object */ 444 __u32 handle; 445 446 /** New read domains */ 447 __u32 read_domains; 448 449 /** New write domain */ 450 __u32 write_domain; 451}; 452 453struct drm_i915_gem_sw_finish { 454 /** Handle for the object */ 455 __u32 handle; 456}; 457 458struct drm_i915_gem_relocation_entry { 459 /** 460 * Handle of the buffer being pointed to by this relocation entry. 461 * 462 * It's appealing to make this be an index into the mm_validate_entry 463 * list to refer to the buffer, but this allows the driver to create 464 * a relocation list for state buffers and not re-write it per 465 * exec using the buffer. 466 */ 467 __u32 target_handle; 468 469 /** 470 * Value to be added to the offset of the target buffer to make up 471 * the relocation entry. 472 */ 473 __u32 delta; 474 475 /** Offset in the buffer the relocation entry will be written into */ 476 __u64 offset; 477 478 /** 479 * Offset value of the target buffer that the relocation entry was last 480 * written as. 481 * 482 * If the buffer has the same offset as last time, we can skip syncing 483 * and writing the relocation. This value is written back out by 484 * the execbuffer ioctl when the relocation is written. 485 */ 486 __u64 presumed_offset; 487 488 /** 489 * Target memory domains read by this operation. 490 */ 491 __u32 read_domains; 492 493 /** 494 * Target memory domains written by this operation. 495 * 496 * Note that only one domain may be written by the whole 497 * execbuffer operation, so that where there are conflicts, 498 * the application will get -EINVAL back. 499 */ 500 __u32 write_domain; 501}; 502 503/** @{ 504 * Intel memory domains 505 * 506 * Most of these just align with the various caches in 507 * the system and are used to flush and invalidate as 508 * objects end up cached in different domains. 509 */ 510/** CPU cache */ 511#define I915_GEM_DOMAIN_CPU 0x00000001 512/** Render cache, used by 2D and 3D drawing */ 513#define I915_GEM_DOMAIN_RENDER 0x00000002 514/** Sampler cache, used by texture engine */ 515#define I915_GEM_DOMAIN_SAMPLER 0x00000004 516/** Command queue, used to load batch buffers */ 517#define I915_GEM_DOMAIN_COMMAND 0x00000008 518/** Instruction cache, used by shader programs */ 519#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 520/** Vertex address cache */ 521#define I915_GEM_DOMAIN_VERTEX 0x00000020 522/** GTT domain - aperture and scanout */ 523#define I915_GEM_DOMAIN_GTT 0x00000040 524/** @} */ 525 526struct drm_i915_gem_exec_object { 527 /** 528 * User's handle for a buffer to be bound into the GTT for this 529 * operation. 530 */ 531 __u32 handle; 532 533 /** Number of relocations to be performed on this buffer */ 534 __u32 relocation_count; 535 /** 536 * Pointer to array of struct drm_i915_gem_relocation_entry containing 537 * the relocations to be performed in this buffer. 538 */ 539 __u64 relocs_ptr; 540 541 /** Required alignment in graphics aperture */ 542 __u64 alignment; 543 544 /** 545 * Returned value of the updated offset of the object, for future 546 * presumed_offset writes. 547 */ 548 __u64 offset; 549}; 550 551struct drm_i915_gem_execbuffer { 552 /** 553 * List of buffers to be validated with their relocations to be 554 * performend on them. 555 * 556 * This is a pointer to an array of struct drm_i915_gem_validate_entry. 557 * 558 * These buffers must be listed in an order such that all relocations 559 * a buffer is performing refer to buffers that have already appeared 560 * in the validate list. 561 */ 562 __u64 buffers_ptr; 563 __u32 buffer_count; 564 565 /** Offset in the batchbuffer to start execution from. */ 566 __u32 batch_start_offset; 567 /** Bytes used in batchbuffer from batch_start_offset */ 568 __u32 batch_len; 569 __u32 DR1; 570 __u32 DR4; 571 __u32 num_cliprects; 572 /** This is a struct drm_clip_rect *cliprects */ 573 __u64 cliprects_ptr; 574}; 575 576struct drm_i915_gem_exec_object2 { 577 /** 578 * User's handle for a buffer to be bound into the GTT for this 579 * operation. 580 */ 581 __u32 handle; 582 583 /** Number of relocations to be performed on this buffer */ 584 __u32 relocation_count; 585 /** 586 * Pointer to array of struct drm_i915_gem_relocation_entry containing 587 * the relocations to be performed in this buffer. 588 */ 589 __u64 relocs_ptr; 590 591 /** Required alignment in graphics aperture */ 592 __u64 alignment; 593 594 /** 595 * Returned value of the updated offset of the object, for future 596 * presumed_offset writes. 597 */ 598 __u64 offset; 599 600#define EXEC_OBJECT_NEEDS_FENCE (1<<0) 601 __u64 flags; 602 __u64 rsvd1; 603 __u64 rsvd2; 604}; 605 606struct drm_i915_gem_execbuffer2 { 607 /** 608 * List of gem_exec_object2 structs 609 */ 610 __u64 buffers_ptr; 611 __u32 buffer_count; 612 613 /** Offset in the batchbuffer to start execution from. */ 614 __u32 batch_start_offset; 615 /** Bytes used in batchbuffer from batch_start_offset */ 616 __u32 batch_len; 617 __u32 DR1; 618 __u32 DR4; 619 __u32 num_cliprects; 620 /** This is a struct drm_clip_rect *cliprects */ 621 __u64 cliprects_ptr; 622#define I915_EXEC_RENDER (1<<0) 623#define I915_EXEC_BSD (1<<1) 624 __u64 flags; 625 __u64 rsvd1; 626 __u64 rsvd2; 627}; 628 629struct drm_i915_gem_pin { 630 /** Handle of the buffer to be pinned. */ 631 __u32 handle; 632 __u32 pad; 633 634 /** alignment required within the aperture */ 635 __u64 alignment; 636 637 /** Returned GTT offset of the buffer. */ 638 __u64 offset; 639}; 640 641struct drm_i915_gem_unpin { 642 /** Handle of the buffer to be unpinned. */ 643 __u32 handle; 644 __u32 pad; 645}; 646 647struct drm_i915_gem_busy { 648 /** Handle of the buffer to check for busy */ 649 __u32 handle; 650 651 /** Return busy status (1 if busy, 0 if idle) */ 652 __u32 busy; 653}; 654 655#define I915_TILING_NONE 0 656#define I915_TILING_X 1 657#define I915_TILING_Y 2 658 659#define I915_BIT_6_SWIZZLE_NONE 0 660#define I915_BIT_6_SWIZZLE_9 1 661#define I915_BIT_6_SWIZZLE_9_10 2 662#define I915_BIT_6_SWIZZLE_9_11 3 663#define I915_BIT_6_SWIZZLE_9_10_11 4 664/* Not seen by userland */ 665#define I915_BIT_6_SWIZZLE_UNKNOWN 5 666/* Seen by userland. */ 667#define I915_BIT_6_SWIZZLE_9_17 6 668#define I915_BIT_6_SWIZZLE_9_10_17 7 669 670struct drm_i915_gem_set_tiling { 671 /** Handle of the buffer to have its tiling state updated */ 672 __u32 handle; 673 674 /** 675 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 676 * I915_TILING_Y). 677 * 678 * This value is to be set on request, and will be updated by the 679 * kernel on successful return with the actual chosen tiling layout. 680 * 681 * The tiling mode may be demoted to I915_TILING_NONE when the system 682 * has bit 6 swizzling that can't be managed correctly by GEM. 683 * 684 * Buffer contents become undefined when changing tiling_mode. 685 */ 686 __u32 tiling_mode; 687 688 /** 689 * Stride in bytes for the object when in I915_TILING_X or 690 * I915_TILING_Y. 691 */ 692 __u32 stride; 693 694 /** 695 * Returned address bit 6 swizzling required for CPU access through 696 * mmap mapping. 697 */ 698 __u32 swizzle_mode; 699}; 700 701struct drm_i915_gem_get_tiling { 702 /** Handle of the buffer to get tiling state for. */ 703 __u32 handle; 704 705 /** 706 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 707 * I915_TILING_Y). 708 */ 709 __u32 tiling_mode; 710 711 /** 712 * Returned address bit 6 swizzling required for CPU access through 713 * mmap mapping. 714 */ 715 __u32 swizzle_mode; 716}; 717 718struct drm_i915_gem_get_aperture { 719 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 720 __u64 aper_size; 721 722 /** 723 * Available space in the aperture used by i915_gem_execbuffer, in 724 * bytes 725 */ 726 __u64 aper_available_size; 727}; 728 729struct drm_i915_get_pipe_from_crtc_id { 730 /** ID of CRTC being requested **/ 731 __u32 crtc_id; 732 733 /** pipe of requested CRTC **/ 734 __u32 pipe; 735}; 736 737#define I915_MADV_WILLNEED 0 738#define I915_MADV_DONTNEED 1 739#define __I915_MADV_PURGED 2 /* internal state */ 740 741struct drm_i915_gem_madvise { 742 /** Handle of the buffer to change the backing store advice */ 743 __u32 handle; 744 745 /* Advice: either the buffer will be needed again in the near future, 746 * or wont be and could be discarded under memory pressure. 747 */ 748 __u32 madv; 749 750 /** Whether the backing store still exists. */ 751 __u32 retained; 752}; 753 754/* flags */ 755#define I915_OVERLAY_TYPE_MASK 0xff 756#define I915_OVERLAY_YUV_PLANAR 0x01 757#define I915_OVERLAY_YUV_PACKED 0x02 758#define I915_OVERLAY_RGB 0x03 759 760#define I915_OVERLAY_DEPTH_MASK 0xff00 761#define I915_OVERLAY_RGB24 0x1000 762#define I915_OVERLAY_RGB16 0x2000 763#define I915_OVERLAY_RGB15 0x3000 764#define I915_OVERLAY_YUV422 0x0100 765#define I915_OVERLAY_YUV411 0x0200 766#define I915_OVERLAY_YUV420 0x0300 767#define I915_OVERLAY_YUV410 0x0400 768 769#define I915_OVERLAY_SWAP_MASK 0xff0000 770#define I915_OVERLAY_NO_SWAP 0x000000 771#define I915_OVERLAY_UV_SWAP 0x010000 772#define I915_OVERLAY_Y_SWAP 0x020000 773#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 774 775#define I915_OVERLAY_FLAGS_MASK 0xff000000 776#define I915_OVERLAY_ENABLE 0x01000000 777 778struct drm_intel_overlay_put_image { 779 /* various flags and src format description */ 780 __u32 flags; 781 /* source picture description */ 782 __u32 bo_handle; 783 /* stride values and offsets are in bytes, buffer relative */ 784 __u16 stride_Y; /* stride for packed formats */ 785 __u16 stride_UV; 786 __u32 offset_Y; /* offset for packet formats */ 787 __u32 offset_U; 788 __u32 offset_V; 789 /* in pixels */ 790 __u16 src_width; 791 __u16 src_height; 792 /* to compensate the scaling factors for partially covered surfaces */ 793 __u16 src_scan_width; 794 __u16 src_scan_height; 795 /* output crtc description */ 796 __u32 crtc_id; 797 __u16 dst_x; 798 __u16 dst_y; 799 __u16 dst_width; 800 __u16 dst_height; 801}; 802 803/* flags */ 804#define I915_OVERLAY_UPDATE_ATTRS (1<<0) 805#define I915_OVERLAY_UPDATE_GAMMA (1<<1) 806struct drm_intel_overlay_attrs { 807 __u32 flags; 808 __u32 color_key; 809 __s32 brightness; 810 __u32 contrast; 811 __u32 saturation; 812 __u32 gamma0; 813 __u32 gamma1; 814 __u32 gamma2; 815 __u32 gamma3; 816 __u32 gamma4; 817 __u32 gamma5; 818}; 819 820#endif /* _I915_DRM_H_ */ 821