1/*
2 * BCM947XX DRAM init & sizing
3 *
4 * Used by both cfe and shared/boot.
5 *
6 * Copyright (C) 2015, Broadcom Corporation. All Rights Reserved.
7 *
8 * Permission to use, copy, modify, and/or distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
15 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
17 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
18 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 *
20 * $Id: sisdram.S,v 1.9 2010-08-06 00:03:55 $
21 */
22
23#include "mipsinc.h"
24#include "hndsoc.h"
25#include "sbchipc.h"
26#include "bcmdevs.h"
27
28
29/* Debug macro - write a number to a pair of chipc regs - use it with caution,
30 *  the registers being used only exist in chip rev >= 22, meaning NOT in 5354
31 *  and previous chips. Also,  it changes k0 and k1 registers.
32 *  Value can be read from epidiag -j using "pci r 0x180000d0 4"
33 */
34#ifdef	BCMDBG
35#if	defined(IL_BIGENDIAN) && defined(BCMHND74K)
36#define	BPADDR_OFF	4
37#define	BPDATA_OFF	12
38#else
39#define	BPADDR_OFF	0
40#define	BPDATA_OFF	8
41#endif
42
43#define TRACEINIT(x) \
44	li	k0,KSEG1ADDR(0x180000d0); \
45	li	k1,x; \
46	sw	k1,BPADDR_OFF(k0)
47
48#define TRACE(x) \
49	li	k1,x; \
50	sw	k1,BPADDR_OFF(k0)
51
52#define TRACE2(x) \
53	li	k1,x; \
54	sw	k1,BPDATA_OFF(k0)
55
56#else
57#define TRACEINIT(x)
58#define TRACE(x)
59#define TRACE2(x)
60#endif	/* BCMDBG */
61
62	/*
63	 * This file exists because board_draminit is an entry point for cfe as well
64	 * as for hndrte & min_osl. Because of the former case, we cannot assume
65	 * any of the register settings from boot.S,
66	 */
67
68	.text
69	LEAF(board_draminit)
70	.set	noreorder
71
72	TRACEINIT(0x535301)
73	move	gp,ra
74
75	/* Figure out if we have an SB or AI chip */
76	li	s2,KSEG1ADDR(SI_ENUM_BASE)	# s2 = SI_ENUM_BASE
77	li	t0,CID_TYPE_MASK
78	lw	s6,CC_CHIPID(s2)		# s6 = ChipId reg
79	and	t1,t0,s6
80	srl	s7,t1,CID_TYPE_SHIFT		# s7 = ChipType (0 for SB, = 1 for AI)
81
82	/* Check if we booted from flash, compute reloc for text addresses */
83	bal	1f
84	nop
85
861:	li	t0,PHYSADDR_MASK
87	and	t0,t0,ra
88	li	t1,SI_FLASH1
89	blt	t0,t1,2f
90	move	s5,zero
91	la	t0,1b
92	sub	s5,ra,t0			# s5: Relocation factor
93
94	/* Call appropriate draminit for chip type */
952:	TRACE(0x535302)
96#if	!defined(BCMCHIPTYPE) || (BCMCHIPTYPE == 0)
97	la	t2,sb_draminit
98	beqz	s7,3f
99	nop
100#endif
101	TRACE(0x535303)
102#if	!defined(BCMCHIPTYPE) || (BCMCHIPTYPE == 1)
103	la	t2,ai_draminit
104	bnez	s7,3f
105	nop
106#endif
107
108#ifdef	BCMCHIPTYPE
109	/* BCMCHIPTYPE defined but does not match this chip */
110	TRACE2(0x5353fe)
111	b	sisdead
112	nop
113#endif
114
1153:	add	t2,t2,s5
116	jalr	t2
117	nop
118
119	/* Size memory if needed (Need to reinit TRACE after sb_draminit) */
120	TRACEINIT(0x535304)
121	beqz	v0,szmem
122	nop
123
124	li	a0,-1				# -1 means no controller
125	bne	v0,a0,4f
126	nop
127
128sisdead:
129	TRACE2(0x5353ff)
130	b	sisdead
131	nop
132
1334:	jr	gp
134	nop
135
136szmem:
137	TRACE(0x535305)
138	li	s3,KSEG1			# s3 = KSEG1
139	li	t2,0xaa55beef
140	sw	zero,0x3c(s3)
141	li	v0,(1 << 20)
142	li	v1,(128 << 20)
143
1445:	or	t0,v0,s3
145	sw	t2,0x3c(t0)
146	lw	t1,0x3c(t0)			# Read back to ensure completion
147	lw	t1,0x3c(s3)
148	beq	t1,t2,6f
149	nop
150
151	sll	v0,v0,1
152	bne	v0,v1,5b
153	nop
154	/* Didn't find an alias, must be 128MB */
155
1566:	jr	gp
157	nop
158
159	END(board_draminit)
160