1/* frv simulator support code 2 Copyright (C) 1999, 2000, 2001, 2003, 2007 Free Software Foundation, Inc. 3 Contributed by Red Hat. 4 5This file is part of the GNU simulators. 6 7This program is free software; you can redistribute it and/or modify 8it under the terms of the GNU General Public License as published by 9the Free Software Foundation; either version 3 of the License, or 10(at your option) any later version. 11 12This program is distributed in the hope that it will be useful, 13but WITHOUT ANY WARRANTY; without even the implied warranty of 14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15GNU General Public License for more details. 16 17You should have received a copy of the GNU General Public License 18along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20#define WANT_CPU 21#define WANT_CPU_FRVBF 22 23#include "sim-main.h" 24#include "bfd.h" 25 26/* Initialize the frv simulator. */ 27void 28frv_initialize (SIM_CPU *current_cpu, SIM_DESC sd) 29{ 30 FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (current_cpu); 31 PROFILE_DATA *p = CPU_PROFILE_DATA (current_cpu); 32 FRV_CACHE *insn_cache = CPU_INSN_CACHE (current_cpu); 33 FRV_CACHE *data_cache = CPU_DATA_CACHE (current_cpu); 34 int insn_cache_enabled = CACHE_INITIALIZED (insn_cache); 35 int data_cache_enabled = CACHE_INITIALIZED (data_cache); 36 USI hsr0; 37 38 /* Initialize the register control information first since some of the 39 register values are used in further configuration. */ 40 frv_register_control_init (current_cpu); 41 42 /* We need to ensure that the caches are initialized even if they are not 43 initially enabled (via commandline) because they can be enabled by 44 software. */ 45 if (! insn_cache_enabled) 46 frv_cache_init (current_cpu, CPU_INSN_CACHE (current_cpu)); 47 if (! data_cache_enabled) 48 frv_cache_init (current_cpu, CPU_DATA_CACHE (current_cpu)); 49 50 /* Set the default cpu frequency if it has not been set on the command 51 line. */ 52 if (PROFILE_CPU_FREQ (p) == 0) 53 PROFILE_CPU_FREQ (p) = 266000000; /* 266MHz */ 54 55 /* Allocate one cache line of memory containing the address of the reset 56 register Use the largest of the insn cache line size and the data cache 57 line size. */ 58 { 59 int addr = RSTR_ADDRESS; 60 void *aligned_buffer; 61 int bytes; 62 63 if (CPU_INSN_CACHE (current_cpu)->line_size 64 > CPU_DATA_CACHE (current_cpu)->line_size) 65 bytes = CPU_INSN_CACHE (current_cpu)->line_size; 66 else 67 bytes = CPU_DATA_CACHE (current_cpu)->line_size; 68 69 /* 'bytes' is a power of 2. Calculate the starting address of the 70 cache line. */ 71 addr &= ~(bytes - 1); 72 aligned_buffer = zalloc (bytes); /* clear */ 73 sim_core_attach (sd, NULL, 0, access_read_write, 0, addr, bytes, 74 0, NULL, aligned_buffer); 75 } 76 77 PROFILE_INFO_CPU_CALLBACK(p) = frv_profile_info; 78 ps->insn_fetch_address = -1; 79 ps->branch_address = -1; 80 81 cgen_init_accurate_fpu (current_cpu, CGEN_CPU_FPU (current_cpu), 82 frvbf_fpu_error); 83 84 /* Now perform power-on reset. */ 85 frv_power_on_reset (current_cpu); 86 87 /* Make sure that HSR0.ICE and HSR0.DCE are set properly. */ 88 hsr0 = GET_HSR0 (); 89 if (insn_cache_enabled) 90 SET_HSR0_ICE (hsr0); 91 else 92 CLEAR_HSR0_ICE (hsr0); 93 if (data_cache_enabled) 94 SET_HSR0_DCE (hsr0); 95 else 96 CLEAR_HSR0_DCE (hsr0); 97 SET_HSR0 (hsr0); 98} 99 100/* Initialize the frv simulator. */ 101void 102frv_term (SIM_DESC sd) 103{ 104 /* If the timer is enabled, and model profiling was not originally enabled, 105 then turn it off again. This is the only place we can currently gain 106 control to do this. */ 107 if (frv_interrupt_state.timer.enabled && ! frv_save_profile_model_p) 108 sim_profile_set_option (current_state, "-model", PROFILE_MODEL_IDX, "0"); 109} 110 111/* Perform a power on reset. */ 112void 113frv_power_on_reset (SIM_CPU *cpu) 114{ 115 /* GR, FR and CPR registers are undefined at initialization time. */ 116 frv_initialize_spr (cpu); 117 /* Initialize the RSTR register (in memory). */ 118 if (frv_cache_enabled (CPU_DATA_CACHE (cpu))) 119 frvbf_mem_set_SI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_INITIAL_VALUE); 120 else 121 SETMEMSI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_INITIAL_VALUE); 122} 123 124/* Perform a hardware reset. */ 125void 126frv_hardware_reset (SIM_CPU *cpu) 127{ 128 /* GR, FR and CPR registers are undefined at hardware reset. */ 129 frv_initialize_spr (cpu); 130 /* Reset the RSTR register (in memory). */ 131 if (frv_cache_enabled (CPU_DATA_CACHE (cpu))) 132 frvbf_mem_set_SI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_HARDWARE_RESET); 133 else 134 SETMEMSI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_HARDWARE_RESET); 135 /* Reset the insn and data caches. */ 136 frv_cache_invalidate_all (CPU_INSN_CACHE (cpu), 0/* no flush */); 137 frv_cache_invalidate_all (CPU_DATA_CACHE (cpu), 0/* no flush */); 138} 139 140/* Perform a software reset. */ 141void 142frv_software_reset (SIM_CPU *cpu) 143{ 144 /* GR, FR and CPR registers are undefined at software reset. */ 145 frv_reset_spr (cpu); 146 /* Reset the RSTR register (in memory). */ 147 if (frv_cache_enabled (CPU_DATA_CACHE (cpu))) 148 frvbf_mem_set_SI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_SOFTWARE_RESET); 149 else 150 SETMEMSI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_SOFTWARE_RESET); 151} 152