1/* Target-dependent code for GNU/Linux on MIPS processors. 2 3 Copyright (C) 2001, 2002, 2004, 2005, 2006, 2007 4 Free Software Foundation, Inc. 5 6 This file is part of GDB. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 20 21#include "defs.h" 22#include "gdbcore.h" 23#include "target.h" 24#include "solib-svr4.h" 25#include "osabi.h" 26#include "mips-tdep.h" 27#include "gdb_string.h" 28#include "gdb_assert.h" 29#include "frame.h" 30#include "regcache.h" 31#include "trad-frame.h" 32#include "tramp-frame.h" 33#include "gdbtypes.h" 34#include "solib.h" 35#include "solib-svr4.h" 36#include "solist.h" 37#include "symtab.h" 38#include "target-descriptions.h" 39#include "mips-linux-tdep.h" 40 41static struct target_so_ops mips_svr4_so_ops; 42 43/* Figure out where the longjmp will land. 44 We expect the first arg to be a pointer to the jmp_buf structure 45 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land 46 at. The pc is copied into PC. This routine returns 1 on 47 success. */ 48 49#define MIPS_LINUX_JB_ELEMENT_SIZE 4 50#define MIPS_LINUX_JB_PC 0 51 52static int 53mips_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) 54{ 55 CORE_ADDR jb_addr; 56 char buf[gdbarch_ptr_bit (current_gdbarch) / TARGET_CHAR_BIT]; 57 58 jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM); 59 60 if (target_read_memory (jb_addr 61 + MIPS_LINUX_JB_PC * MIPS_LINUX_JB_ELEMENT_SIZE, 62 buf, 63 gdbarch_ptr_bit (current_gdbarch) / TARGET_CHAR_BIT)) 64 return 0; 65 66 *pc = extract_unsigned_integer (buf, 67 gdbarch_ptr_bit (current_gdbarch) 68 / TARGET_CHAR_BIT); 69 70 return 1; 71} 72 73/* Transform the bits comprising a 32-bit register to the right size 74 for regcache_raw_supply(). This is needed when mips_isa_regsize() 75 is 8. */ 76 77static void 78supply_32bit_reg (struct regcache *regcache, int regnum, const void *addr) 79{ 80 gdb_byte buf[MAX_REGISTER_SIZE]; 81 store_signed_integer (buf, register_size (current_gdbarch, regnum), 82 extract_signed_integer (addr, 4)); 83 regcache_raw_supply (regcache, regnum, buf); 84} 85 86/* Unpack an elf_gregset_t into GDB's register cache. */ 87 88void 89mips_supply_gregset (struct regcache *regcache, 90 const mips_elf_gregset_t *gregsetp) 91{ 92 int regi; 93 const mips_elf_greg_t *regp = *gregsetp; 94 char zerobuf[MAX_REGISTER_SIZE]; 95 96 memset (zerobuf, 0, MAX_REGISTER_SIZE); 97 98 for (regi = EF_REG0 + 1; regi <= EF_REG31; regi++) 99 supply_32bit_reg (regcache, regi - EF_REG0, regp + regi); 100 101 if (mips_linux_restart_reg_p (current_gdbarch)) 102 supply_32bit_reg (regcache, MIPS_RESTART_REGNUM, regp + EF_REG0); 103 104 supply_32bit_reg (regcache, mips_regnum (current_gdbarch)->lo, 105 regp + EF_LO); 106 supply_32bit_reg (regcache, mips_regnum (current_gdbarch)->hi, 107 regp + EF_HI); 108 109 supply_32bit_reg (regcache, mips_regnum (current_gdbarch)->pc, 110 regp + EF_CP0_EPC); 111 supply_32bit_reg (regcache, mips_regnum (current_gdbarch)->badvaddr, 112 regp + EF_CP0_BADVADDR); 113 supply_32bit_reg (regcache, MIPS_PS_REGNUM, regp + EF_CP0_STATUS); 114 supply_32bit_reg (regcache, mips_regnum (current_gdbarch)->cause, 115 regp + EF_CP0_CAUSE); 116 117 /* Fill inaccessible registers with zero. */ 118 regcache_raw_supply (regcache, MIPS_ZERO_REGNUM, zerobuf); 119 regcache_raw_supply (regcache, MIPS_UNUSED_REGNUM, zerobuf); 120 for (regi = MIPS_FIRST_EMBED_REGNUM; 121 regi <= MIPS_LAST_EMBED_REGNUM; 122 regi++) 123 regcache_raw_supply (regcache, regi, zerobuf); 124} 125 126/* Pack our registers (or one register) into an elf_gregset_t. */ 127 128void 129mips_fill_gregset (const struct regcache *regcache, 130 mips_elf_gregset_t *gregsetp, int regno) 131{ 132 int regaddr, regi; 133 mips_elf_greg_t *regp = *gregsetp; 134 void *dst; 135 136 if (regno == -1) 137 { 138 memset (regp, 0, sizeof (mips_elf_gregset_t)); 139 for (regi = 1; regi < 32; regi++) 140 mips_fill_gregset (regcache, gregsetp, regi); 141 mips_fill_gregset (regcache, gregsetp, 142 mips_regnum (current_gdbarch)->lo); 143 mips_fill_gregset (regcache, gregsetp, 144 mips_regnum (current_gdbarch)->hi); 145 mips_fill_gregset (regcache, gregsetp, 146 mips_regnum (current_gdbarch)->pc); 147 mips_fill_gregset (regcache, gregsetp, 148 mips_regnum (current_gdbarch)->badvaddr); 149 mips_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM); 150 mips_fill_gregset (regcache, gregsetp, 151 mips_regnum (current_gdbarch)->cause); 152 mips_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM); 153 return; 154 } 155 156 if (regno > 0 && regno < 32) 157 { 158 dst = regp + regno + EF_REG0; 159 regcache_raw_collect (regcache, regno, dst); 160 return; 161 } 162 163 if (regno == mips_regnum (current_gdbarch)->lo) 164 regaddr = EF_LO; 165 else if (regno == mips_regnum (current_gdbarch)->hi) 166 regaddr = EF_HI; 167 else if (regno == mips_regnum (current_gdbarch)->pc) 168 regaddr = EF_CP0_EPC; 169 else if (regno == mips_regnum (current_gdbarch)->badvaddr) 170 regaddr = EF_CP0_BADVADDR; 171 else if (regno == MIPS_PS_REGNUM) 172 regaddr = EF_CP0_STATUS; 173 else if (regno == mips_regnum (current_gdbarch)->cause) 174 regaddr = EF_CP0_CAUSE; 175 else if (mips_linux_restart_reg_p (current_gdbarch) 176 && regno == MIPS_RESTART_REGNUM) 177 regaddr = EF_REG0; 178 else 179 regaddr = -1; 180 181 if (regaddr != -1) 182 { 183 dst = regp + regaddr; 184 regcache_raw_collect (regcache, regno, dst); 185 } 186} 187 188/* Likewise, unpack an elf_fpregset_t. */ 189 190void 191mips_supply_fpregset (struct regcache *regcache, 192 const mips_elf_fpregset_t *fpregsetp) 193{ 194 int regi; 195 char zerobuf[MAX_REGISTER_SIZE]; 196 197 memset (zerobuf, 0, MAX_REGISTER_SIZE); 198 199 for (regi = 0; regi < 32; regi++) 200 regcache_raw_supply (regcache, 201 gdbarch_fp0_regnum (current_gdbarch) + regi, 202 *fpregsetp + regi); 203 204 regcache_raw_supply (regcache, 205 mips_regnum (current_gdbarch)->fp_control_status, 206 *fpregsetp + 32); 207 208 /* FIXME: how can we supply FCRIR? The ABI doesn't tell us. */ 209 regcache_raw_supply (regcache, 210 mips_regnum (current_gdbarch)->fp_implementation_revision, 211 zerobuf); 212} 213 214/* Likewise, pack one or all floating point registers into an 215 elf_fpregset_t. */ 216 217void 218mips_fill_fpregset (const struct regcache *regcache, 219 mips_elf_fpregset_t *fpregsetp, int regno) 220{ 221 char *from, *to; 222 223 if ((regno >= gdbarch_fp0_regnum (current_gdbarch)) 224 && (regno < gdbarch_fp0_regnum (current_gdbarch) + 32)) 225 { 226 to = (char *) (*fpregsetp + regno - gdbarch_fp0_regnum (current_gdbarch)); 227 regcache_raw_collect (regcache, regno, to); 228 } 229 else if (regno == mips_regnum (current_gdbarch)->fp_control_status) 230 { 231 to = (char *) (*fpregsetp + 32); 232 regcache_raw_collect (regcache, regno, to); 233 } 234 else if (regno == -1) 235 { 236 int regi; 237 238 for (regi = 0; regi < 32; regi++) 239 mips_fill_fpregset (regcache, fpregsetp, 240 gdbarch_fp0_regnum (current_gdbarch) + regi); 241 mips_fill_fpregset (regcache, fpregsetp, 242 mips_regnum (current_gdbarch)->fp_control_status); 243 } 244} 245 246/* Support for 64-bit ABIs. */ 247 248/* Figure out where the longjmp will land. 249 We expect the first arg to be a pointer to the jmp_buf structure 250 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land 251 at. The pc is copied into PC. This routine returns 1 on 252 success. */ 253 254/* Details about jmp_buf. */ 255 256#define MIPS64_LINUX_JB_PC 0 257 258static int 259mips64_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) 260{ 261 CORE_ADDR jb_addr; 262 void *buf = alloca (gdbarch_ptr_bit (current_gdbarch) / TARGET_CHAR_BIT); 263 int element_size = gdbarch_ptr_bit (current_gdbarch) == 32 ? 4 : 8; 264 265 jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM); 266 267 if (target_read_memory (jb_addr + MIPS64_LINUX_JB_PC * element_size, 268 buf, 269 gdbarch_ptr_bit (current_gdbarch) / TARGET_CHAR_BIT)) 270 return 0; 271 272 *pc = extract_unsigned_integer (buf, 273 gdbarch_ptr_bit (current_gdbarch) 274 / TARGET_CHAR_BIT); 275 276 return 1; 277} 278 279/* Register set support functions. These operate on standard 64-bit 280 regsets, but work whether the target is 32-bit or 64-bit. A 32-bit 281 target will still use the 64-bit format for PTRACE_GETREGS. */ 282 283/* Supply a 64-bit register. */ 284 285void 286supply_64bit_reg (struct regcache *regcache, int regnum, 287 const gdb_byte *buf) 288{ 289 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG 290 && register_size (current_gdbarch, regnum) == 4) 291 regcache_raw_supply (regcache, regnum, buf + 4); 292 else 293 regcache_raw_supply (regcache, regnum, buf); 294} 295 296/* Unpack a 64-bit elf_gregset_t into GDB's register cache. */ 297 298void 299mips64_supply_gregset (struct regcache *regcache, 300 const mips64_elf_gregset_t *gregsetp) 301{ 302 int regi; 303 const mips64_elf_greg_t *regp = *gregsetp; 304 gdb_byte zerobuf[MAX_REGISTER_SIZE]; 305 306 memset (zerobuf, 0, MAX_REGISTER_SIZE); 307 308 for (regi = MIPS64_EF_REG0 + 1; regi <= MIPS64_EF_REG31; regi++) 309 supply_64bit_reg (regcache, regi - MIPS64_EF_REG0, 310 (const gdb_byte *)(regp + regi)); 311 312 if (mips_linux_restart_reg_p (current_gdbarch)) 313 supply_64bit_reg (regcache, MIPS_RESTART_REGNUM, 314 (const gdb_byte *)(regp + MIPS64_EF_REG0)); 315 316 supply_64bit_reg (regcache, mips_regnum (current_gdbarch)->lo, 317 (const gdb_byte *) (regp + MIPS64_EF_LO)); 318 supply_64bit_reg (regcache, mips_regnum (current_gdbarch)->hi, 319 (const gdb_byte *) (regp + MIPS64_EF_HI)); 320 321 supply_64bit_reg (regcache, mips_regnum (current_gdbarch)->pc, 322 (const gdb_byte *) (regp + MIPS64_EF_CP0_EPC)); 323 supply_64bit_reg (regcache, mips_regnum (current_gdbarch)->badvaddr, 324 (const gdb_byte *) (regp + MIPS64_EF_CP0_BADVADDR)); 325 supply_64bit_reg (regcache, MIPS_PS_REGNUM, 326 (const gdb_byte *) (regp + MIPS64_EF_CP0_STATUS)); 327 supply_64bit_reg (regcache, mips_regnum (current_gdbarch)->cause, 328 (const gdb_byte *) (regp + MIPS64_EF_CP0_CAUSE)); 329 330 /* Fill inaccessible registers with zero. */ 331 regcache_raw_supply (regcache, MIPS_ZERO_REGNUM, zerobuf); 332 regcache_raw_supply (regcache, MIPS_UNUSED_REGNUM, zerobuf); 333 for (regi = MIPS_FIRST_EMBED_REGNUM; 334 regi <= MIPS_LAST_EMBED_REGNUM; 335 regi++) 336 regcache_raw_supply (regcache, regi, zerobuf); 337} 338 339/* Pack our registers (or one register) into a 64-bit elf_gregset_t. */ 340 341void 342mips64_fill_gregset (const struct regcache *regcache, 343 mips64_elf_gregset_t *gregsetp, int regno) 344{ 345 int regaddr, regi; 346 mips64_elf_greg_t *regp = *gregsetp; 347 void *src, *dst; 348 349 if (regno == -1) 350 { 351 memset (regp, 0, sizeof (mips64_elf_gregset_t)); 352 for (regi = 1; regi < 32; regi++) 353 mips64_fill_gregset (regcache, gregsetp, regi); 354 mips64_fill_gregset (regcache, gregsetp, 355 mips_regnum (current_gdbarch)->lo); 356 mips64_fill_gregset (regcache, gregsetp, 357 mips_regnum (current_gdbarch)->hi); 358 mips64_fill_gregset (regcache, gregsetp, 359 mips_regnum (current_gdbarch)->pc); 360 mips64_fill_gregset (regcache, gregsetp, 361 mips_regnum (current_gdbarch)->badvaddr); 362 mips64_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM); 363 mips64_fill_gregset (regcache, gregsetp, 364 mips_regnum (current_gdbarch)->cause); 365 mips64_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM); 366 return; 367 } 368 369 if (regno > 0 && regno < 32) 370 regaddr = regno + MIPS64_EF_REG0; 371 else if (regno == mips_regnum (current_gdbarch)->lo) 372 regaddr = MIPS64_EF_LO; 373 else if (regno == mips_regnum (current_gdbarch)->hi) 374 regaddr = MIPS64_EF_HI; 375 else if (regno == mips_regnum (current_gdbarch)->pc) 376 regaddr = MIPS64_EF_CP0_EPC; 377 else if (regno == mips_regnum (current_gdbarch)->badvaddr) 378 regaddr = MIPS64_EF_CP0_BADVADDR; 379 else if (regno == MIPS_PS_REGNUM) 380 regaddr = MIPS64_EF_CP0_STATUS; 381 else if (regno == mips_regnum (current_gdbarch)->cause) 382 regaddr = MIPS64_EF_CP0_CAUSE; 383 else if (mips_linux_restart_reg_p (current_gdbarch) 384 && regno == MIPS_RESTART_REGNUM) 385 regaddr = MIPS64_EF_REG0; 386 else 387 regaddr = -1; 388 389 if (regaddr != -1) 390 { 391 gdb_byte buf[MAX_REGISTER_SIZE]; 392 LONGEST val; 393 394 regcache_raw_collect (regcache, regno, buf); 395 val = extract_signed_integer (buf, 396 register_size (current_gdbarch, regno)); 397 dst = regp + regaddr; 398 store_signed_integer (dst, 8, val); 399 } 400} 401 402/* Likewise, unpack an elf_fpregset_t. */ 403 404void 405mips64_supply_fpregset (struct regcache *regcache, 406 const mips64_elf_fpregset_t *fpregsetp) 407{ 408 int regi; 409 410 /* See mips_linux_o32_sigframe_init for a description of the 411 peculiar FP register layout. */ 412 if (register_size (current_gdbarch, 413 gdbarch_fp0_regnum (current_gdbarch)) == 4) 414 for (regi = 0; regi < 32; regi++) 415 { 416 const gdb_byte *reg_ptr = (const gdb_byte *)(*fpregsetp + (regi & ~1)); 417 if ((gdbarch_byte_order (current_gdbarch) 418 == BFD_ENDIAN_BIG) != (regi & 1)) 419 reg_ptr += 4; 420 regcache_raw_supply (regcache, 421 gdbarch_fp0_regnum (current_gdbarch) + regi, 422 reg_ptr); 423 } 424 else 425 for (regi = 0; regi < 32; regi++) 426 regcache_raw_supply (regcache, 427 gdbarch_fp0_regnum (current_gdbarch) + regi, 428 (const char *)(*fpregsetp + regi)); 429 430 supply_32bit_reg (regcache, mips_regnum (current_gdbarch)->fp_control_status, 431 (const gdb_byte *)(*fpregsetp + 32)); 432 433 /* The ABI doesn't tell us how to supply FCRIR, and core dumps don't 434 include it - but the result of PTRACE_GETFPREGS does. The best we 435 can do is to assume that its value is present. */ 436 supply_32bit_reg (regcache, 437 mips_regnum (current_gdbarch)->fp_implementation_revision, 438 (const gdb_byte *)(*fpregsetp + 32) + 4); 439} 440 441/* Likewise, pack one or all floating point registers into an 442 elf_fpregset_t. */ 443 444void 445mips64_fill_fpregset (const struct regcache *regcache, 446 mips64_elf_fpregset_t *fpregsetp, int regno) 447{ 448 gdb_byte *to; 449 450 if ((regno >= gdbarch_fp0_regnum (current_gdbarch)) 451 && (regno < gdbarch_fp0_regnum (current_gdbarch) + 32)) 452 { 453 /* See mips_linux_o32_sigframe_init for a description of the 454 peculiar FP register layout. */ 455 if (register_size (current_gdbarch, regno) == 4) 456 { 457 int regi = regno - gdbarch_fp0_regnum (current_gdbarch); 458 459 to = (gdb_byte *) (*fpregsetp + (regi & ~1)); 460 if ((gdbarch_byte_order (current_gdbarch) 461 == BFD_ENDIAN_BIG) != (regi & 1)) 462 to += 4; 463 regcache_raw_collect (regcache, regno, to); 464 } 465 else 466 { 467 to = (gdb_byte *) (*fpregsetp + regno 468 - gdbarch_fp0_regnum (current_gdbarch)); 469 regcache_raw_collect (regcache, regno, to); 470 } 471 } 472 else if (regno == mips_regnum (current_gdbarch)->fp_control_status) 473 { 474 gdb_byte buf[MAX_REGISTER_SIZE]; 475 LONGEST val; 476 477 regcache_raw_collect (regcache, regno, buf); 478 val = extract_signed_integer (buf, 479 register_size (current_gdbarch, regno)); 480 to = (gdb_byte *) (*fpregsetp + 32); 481 store_signed_integer (to, 4, val); 482 } 483 else if (regno == mips_regnum (current_gdbarch)->fp_implementation_revision) 484 { 485 gdb_byte buf[MAX_REGISTER_SIZE]; 486 LONGEST val; 487 488 regcache_raw_collect (regcache, regno, buf); 489 val = extract_signed_integer (buf, 490 register_size (current_gdbarch, regno)); 491 to = (gdb_byte *) (*fpregsetp + 32) + 4; 492 store_signed_integer (to, 4, val); 493 } 494 else if (regno == -1) 495 { 496 int regi; 497 498 for (regi = 0; regi < 32; regi++) 499 mips64_fill_fpregset (regcache, fpregsetp, 500 gdbarch_fp0_regnum (current_gdbarch) + regi); 501 mips64_fill_fpregset (regcache, fpregsetp, 502 mips_regnum (current_gdbarch)->fp_control_status); 503 mips64_fill_fpregset (regcache, fpregsetp, 504 (mips_regnum (current_gdbarch) 505 ->fp_implementation_revision)); 506 } 507} 508 509 510/* Use a local version of this function to get the correct types for 511 regsets, until multi-arch core support is ready. */ 512 513static void 514fetch_core_registers (struct regcache *regcache, 515 char *core_reg_sect, unsigned core_reg_size, 516 int which, CORE_ADDR reg_addr) 517{ 518 mips_elf_gregset_t gregset; 519 mips_elf_fpregset_t fpregset; 520 mips64_elf_gregset_t gregset64; 521 mips64_elf_fpregset_t fpregset64; 522 523 if (which == 0) 524 { 525 if (core_reg_size == sizeof (gregset)) 526 { 527 memcpy ((char *) &gregset, core_reg_sect, sizeof (gregset)); 528 mips_supply_gregset (regcache, 529 (const mips_elf_gregset_t *) &gregset); 530 } 531 else if (core_reg_size == sizeof (gregset64)) 532 { 533 memcpy ((char *) &gregset64, core_reg_sect, sizeof (gregset64)); 534 mips64_supply_gregset (regcache, 535 (const mips64_elf_gregset_t *) &gregset64); 536 } 537 else 538 { 539 warning (_("wrong size gregset struct in core file")); 540 } 541 } 542 else if (which == 2) 543 { 544 if (core_reg_size == sizeof (fpregset)) 545 { 546 memcpy ((char *) &fpregset, core_reg_sect, sizeof (fpregset)); 547 mips_supply_fpregset (regcache, 548 (const mips_elf_fpregset_t *) &fpregset); 549 } 550 else if (core_reg_size == sizeof (fpregset64)) 551 { 552 memcpy ((char *) &fpregset64, core_reg_sect, 553 sizeof (fpregset64)); 554 mips64_supply_fpregset (regcache, 555 (const mips64_elf_fpregset_t *) &fpregset64); 556 } 557 else 558 { 559 warning (_("wrong size fpregset struct in core file")); 560 } 561 } 562} 563 564/* Register that we are able to handle ELF file formats using standard 565 procfs "regset" structures. */ 566 567static struct core_fns regset_core_fns = 568{ 569 bfd_target_elf_flavour, /* core_flavour */ 570 default_check_format, /* check_format */ 571 default_core_sniffer, /* core_sniffer */ 572 fetch_core_registers, /* core_read_registers */ 573 NULL /* next */ 574}; 575 576 577/* Check the code at PC for a dynamic linker lazy resolution stub. 578 Because they aren't in the .plt section, we pattern-match on the 579 code generated by GNU ld. They look like this: 580 581 lw t9,0x8010(gp) 582 addu t7,ra 583 jalr t9,ra 584 addiu t8,zero,INDEX 585 586 (with the appropriate doubleword instructions for N64). Also 587 return the dynamic symbol index used in the last instruction. */ 588 589static int 590mips_linux_in_dynsym_stub (CORE_ADDR pc, char *name) 591{ 592 unsigned char buf[28], *p; 593 ULONGEST insn, insn1; 594 int n64 = (mips_abi (current_gdbarch) == MIPS_ABI_N64); 595 596 read_memory (pc - 12, buf, 28); 597 598 if (n64) 599 { 600 /* ld t9,0x8010(gp) */ 601 insn1 = 0xdf998010; 602 } 603 else 604 { 605 /* lw t9,0x8010(gp) */ 606 insn1 = 0x8f998010; 607 } 608 609 p = buf + 12; 610 while (p >= buf) 611 { 612 insn = extract_unsigned_integer (p, 4); 613 if (insn == insn1) 614 break; 615 p -= 4; 616 } 617 if (p < buf) 618 return 0; 619 620 insn = extract_unsigned_integer (p + 4, 4); 621 if (n64) 622 { 623 /* daddu t7,ra */ 624 if (insn != 0x03e0782d) 625 return 0; 626 } 627 else 628 { 629 /* addu t7,ra */ 630 if (insn != 0x03e07821) 631 return 0; 632 } 633 634 insn = extract_unsigned_integer (p + 8, 4); 635 /* jalr t9,ra */ 636 if (insn != 0x0320f809) 637 return 0; 638 639 insn = extract_unsigned_integer (p + 12, 4); 640 if (n64) 641 { 642 /* daddiu t8,zero,0 */ 643 if ((insn & 0xffff0000) != 0x64180000) 644 return 0; 645 } 646 else 647 { 648 /* addiu t8,zero,0 */ 649 if ((insn & 0xffff0000) != 0x24180000) 650 return 0; 651 } 652 653 return (insn & 0xffff); 654} 655 656/* Return non-zero iff PC belongs to the dynamic linker resolution 657 code or to a stub. */ 658 659static int 660mips_linux_in_dynsym_resolve_code (CORE_ADDR pc) 661{ 662 /* Check whether PC is in the dynamic linker. This also checks 663 whether it is in the .plt section, which MIPS does not use. */ 664 if (svr4_in_dynsym_resolve_code (pc)) 665 return 1; 666 667 /* Pattern match for the stub. It would be nice if there were a 668 more efficient way to avoid this check. */ 669 if (mips_linux_in_dynsym_stub (pc, NULL)) 670 return 1; 671 672 return 0; 673} 674 675/* See the comments for SKIP_SOLIB_RESOLVER at the top of infrun.c, 676 and glibc_skip_solib_resolver in glibc-tdep.c. The normal glibc 677 implementation of this triggers at "fixup" from the same objfile as 678 "_dl_runtime_resolve"; MIPS GNU/Linux can trigger at 679 "__dl_runtime_resolve" directly. An unresolved PLT entry will 680 point to _dl_runtime_resolve, which will first call 681 __dl_runtime_resolve, and then pass control to the resolved 682 function. */ 683 684static CORE_ADDR 685mips_linux_skip_resolver (struct gdbarch *gdbarch, CORE_ADDR pc) 686{ 687 struct minimal_symbol *resolver; 688 689 resolver = lookup_minimal_symbol ("__dl_runtime_resolve", NULL, NULL); 690 691 if (resolver && SYMBOL_VALUE_ADDRESS (resolver) == pc) 692 return frame_pc_unwind (get_current_frame ()); 693 694 return 0; 695} 696 697/* Signal trampoline support. There are four supported layouts for a 698 signal frame: o32 sigframe, o32 rt_sigframe, n32 rt_sigframe, and 699 n64 rt_sigframe. We handle them all independently; not the most 700 efficient way, but simplest. First, declare all the unwinders. */ 701 702static void mips_linux_o32_sigframe_init (const struct tramp_frame *self, 703 struct frame_info *next_frame, 704 struct trad_frame_cache *this_cache, 705 CORE_ADDR func); 706 707static void mips_linux_n32n64_sigframe_init (const struct tramp_frame *self, 708 struct frame_info *next_frame, 709 struct trad_frame_cache *this_cache, 710 CORE_ADDR func); 711 712#define MIPS_NR_LINUX 4000 713#define MIPS_NR_N64_LINUX 5000 714#define MIPS_NR_N32_LINUX 6000 715 716#define MIPS_NR_sigreturn MIPS_NR_LINUX + 119 717#define MIPS_NR_rt_sigreturn MIPS_NR_LINUX + 193 718#define MIPS_NR_N64_rt_sigreturn MIPS_NR_N64_LINUX + 211 719#define MIPS_NR_N32_rt_sigreturn MIPS_NR_N32_LINUX + 211 720 721#define MIPS_INST_LI_V0_SIGRETURN 0x24020000 + MIPS_NR_sigreturn 722#define MIPS_INST_LI_V0_RT_SIGRETURN 0x24020000 + MIPS_NR_rt_sigreturn 723#define MIPS_INST_LI_V0_N64_RT_SIGRETURN 0x24020000 + MIPS_NR_N64_rt_sigreturn 724#define MIPS_INST_LI_V0_N32_RT_SIGRETURN 0x24020000 + MIPS_NR_N32_rt_sigreturn 725#define MIPS_INST_SYSCALL 0x0000000c 726 727static const struct tramp_frame mips_linux_o32_sigframe = { 728 SIGTRAMP_FRAME, 729 4, 730 { 731 { MIPS_INST_LI_V0_SIGRETURN, -1 }, 732 { MIPS_INST_SYSCALL, -1 }, 733 { TRAMP_SENTINEL_INSN, -1 } 734 }, 735 mips_linux_o32_sigframe_init 736}; 737 738static const struct tramp_frame mips_linux_o32_rt_sigframe = { 739 SIGTRAMP_FRAME, 740 4, 741 { 742 { MIPS_INST_LI_V0_RT_SIGRETURN, -1 }, 743 { MIPS_INST_SYSCALL, -1 }, 744 { TRAMP_SENTINEL_INSN, -1 } }, 745 mips_linux_o32_sigframe_init 746}; 747 748static const struct tramp_frame mips_linux_n32_rt_sigframe = { 749 SIGTRAMP_FRAME, 750 4, 751 { 752 { MIPS_INST_LI_V0_N32_RT_SIGRETURN, -1 }, 753 { MIPS_INST_SYSCALL, -1 }, 754 { TRAMP_SENTINEL_INSN, -1 } 755 }, 756 mips_linux_n32n64_sigframe_init 757}; 758 759static const struct tramp_frame mips_linux_n64_rt_sigframe = { 760 SIGTRAMP_FRAME, 761 4, 762 { 763 { MIPS_INST_LI_V0_N64_RT_SIGRETURN, -1 }, 764 { MIPS_INST_SYSCALL, -1 }, 765 { TRAMP_SENTINEL_INSN, -1 } 766 }, 767 mips_linux_n32n64_sigframe_init 768}; 769 770/* *INDENT-OFF* */ 771/* The unwinder for o32 signal frames. The legacy structures look 772 like this: 773 774 struct sigframe { 775 u32 sf_ass[4]; [argument save space for o32] 776 u32 sf_code[2]; [signal trampoline] 777 struct sigcontext sf_sc; 778 sigset_t sf_mask; 779 }; 780 781 struct sigcontext { 782 unsigned int sc_regmask; [Unused] 783 unsigned int sc_status; 784 unsigned long long sc_pc; 785 unsigned long long sc_regs[32]; 786 unsigned long long sc_fpregs[32]; 787 unsigned int sc_ownedfp; 788 unsigned int sc_fpc_csr; 789 unsigned int sc_fpc_eir; [Unused] 790 unsigned int sc_used_math; 791 unsigned int sc_ssflags; [Unused] 792 [Alignment hole of four bytes] 793 unsigned long long sc_mdhi; 794 unsigned long long sc_mdlo; 795 796 unsigned int sc_cause; [Unused] 797 unsigned int sc_badvaddr; [Unused] 798 799 unsigned long sc_sigset[4]; [kernel's sigset_t] 800 }; 801 802 The RT signal frames look like this: 803 804 struct rt_sigframe { 805 u32 rs_ass[4]; [argument save space for o32] 806 u32 rs_code[2] [signal trampoline] 807 struct siginfo rs_info; 808 struct ucontext rs_uc; 809 }; 810 811 struct ucontext { 812 unsigned long uc_flags; 813 struct ucontext *uc_link; 814 stack_t uc_stack; 815 [Alignment hole of four bytes] 816 struct sigcontext uc_mcontext; 817 sigset_t uc_sigmask; 818 }; */ 819/* *INDENT-ON* */ 820 821#define SIGFRAME_CODE_OFFSET (4 * 4) 822#define SIGFRAME_SIGCONTEXT_OFFSET (6 * 4) 823 824#define RTSIGFRAME_SIGINFO_SIZE 128 825#define STACK_T_SIZE (3 * 4) 826#define UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + STACK_T_SIZE + 4) 827#define RTSIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ 828 + RTSIGFRAME_SIGINFO_SIZE \ 829 + UCONTEXT_SIGCONTEXT_OFFSET) 830 831#define SIGCONTEXT_PC (1 * 8) 832#define SIGCONTEXT_REGS (2 * 8) 833#define SIGCONTEXT_FPREGS (34 * 8) 834#define SIGCONTEXT_FPCSR (66 * 8 + 4) 835#define SIGCONTEXT_HI (69 * 8) 836#define SIGCONTEXT_LO (70 * 8) 837#define SIGCONTEXT_CAUSE (71 * 8 + 0) 838#define SIGCONTEXT_BADVADDR (71 * 8 + 4) 839 840#define SIGCONTEXT_REG_SIZE 8 841 842static void 843mips_linux_o32_sigframe_init (const struct tramp_frame *self, 844 struct frame_info *next_frame, 845 struct trad_frame_cache *this_cache, 846 CORE_ADDR func) 847{ 848 int ireg, reg_position; 849 CORE_ADDR sigcontext_base = func - SIGFRAME_CODE_OFFSET; 850 const struct mips_regnum *regs = mips_regnum (current_gdbarch); 851 CORE_ADDR regs_base; 852 853 if (self == &mips_linux_o32_sigframe) 854 sigcontext_base += SIGFRAME_SIGCONTEXT_OFFSET; 855 else 856 sigcontext_base += RTSIGFRAME_SIGCONTEXT_OFFSET; 857 858 /* I'm not proud of this hack. Eventually we will have the 859 infrastructure to indicate the size of saved registers on a 860 per-frame basis, but right now we don't; the kernel saves eight 861 bytes but we only want four. Use regs_base to access any 862 64-bit fields. */ 863 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) 864 regs_base = sigcontext_base + 4; 865 else 866 regs_base = sigcontext_base; 867 868 if (mips_linux_restart_reg_p (current_gdbarch)) 869 trad_frame_set_reg_addr (this_cache, 870 (MIPS_RESTART_REGNUM 871 + gdbarch_num_regs (current_gdbarch)), 872 regs_base + SIGCONTEXT_REGS); 873 874 for (ireg = 1; ireg < 32; ireg++) 875 trad_frame_set_reg_addr (this_cache, 876 ireg + MIPS_ZERO_REGNUM 877 + gdbarch_num_regs (current_gdbarch), 878 regs_base + SIGCONTEXT_REGS 879 + ireg * SIGCONTEXT_REG_SIZE); 880 881 /* The way that floating point registers are saved, unfortunately, 882 depends on the architecture the kernel is built for. For the r3000 and 883 tx39, four bytes of each register are at the beginning of each of the 884 32 eight byte slots. For everything else, the registers are saved 885 using double precision; only the even-numbered slots are initialized, 886 and the high bits are the odd-numbered register. Assume the latter 887 layout, since we can't tell, and it's much more common. Which bits are 888 the "high" bits depends on endianness. */ 889 for (ireg = 0; ireg < 32; ireg++) 890 if ((gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) != (ireg & 1)) 891 trad_frame_set_reg_addr (this_cache, 892 ireg + regs->fp0 + 893 gdbarch_num_regs (current_gdbarch), 894 sigcontext_base + SIGCONTEXT_FPREGS + 4 895 + (ireg & ~1) * SIGCONTEXT_REG_SIZE); 896 else 897 trad_frame_set_reg_addr (this_cache, 898 ireg + regs->fp0 899 + gdbarch_num_regs (current_gdbarch), 900 sigcontext_base + SIGCONTEXT_FPREGS 901 + (ireg & ~1) * SIGCONTEXT_REG_SIZE); 902 903 trad_frame_set_reg_addr (this_cache, 904 regs->pc + gdbarch_num_regs (current_gdbarch), 905 regs_base + SIGCONTEXT_PC); 906 907 trad_frame_set_reg_addr (this_cache, 908 regs->fp_control_status 909 + gdbarch_num_regs (current_gdbarch), 910 sigcontext_base + SIGCONTEXT_FPCSR); 911 trad_frame_set_reg_addr (this_cache, 912 regs->hi + gdbarch_num_regs (current_gdbarch), 913 regs_base + SIGCONTEXT_HI); 914 trad_frame_set_reg_addr (this_cache, 915 regs->lo + gdbarch_num_regs (current_gdbarch), 916 regs_base + SIGCONTEXT_LO); 917 trad_frame_set_reg_addr (this_cache, 918 regs->cause + gdbarch_num_regs (current_gdbarch), 919 sigcontext_base + SIGCONTEXT_CAUSE); 920 trad_frame_set_reg_addr (this_cache, 921 regs->badvaddr + gdbarch_num_regs (current_gdbarch), 922 sigcontext_base + SIGCONTEXT_BADVADDR); 923 924 /* Choice of the bottom of the sigframe is somewhat arbitrary. */ 925 trad_frame_set_id (this_cache, 926 frame_id_build (func - SIGFRAME_CODE_OFFSET, 927 func)); 928} 929 930/* *INDENT-OFF* */ 931/* For N32/N64 things look different. There is no non-rt signal frame. 932 933 struct rt_sigframe_n32 { 934 u32 rs_ass[4]; [ argument save space for o32 ] 935 u32 rs_code[2]; [ signal trampoline ] 936 struct siginfo rs_info; 937 struct ucontextn32 rs_uc; 938 }; 939 940 struct ucontextn32 { 941 u32 uc_flags; 942 s32 uc_link; 943 stack32_t uc_stack; 944 struct sigcontext uc_mcontext; 945 sigset_t uc_sigmask; [ mask last for extensibility ] 946 }; 947 948 struct rt_sigframe_n32 { 949 u32 rs_ass[4]; [ argument save space for o32 ] 950 u32 rs_code[2]; [ signal trampoline ] 951 struct siginfo rs_info; 952 struct ucontext rs_uc; 953 }; 954 955 struct ucontext { 956 unsigned long uc_flags; 957 struct ucontext *uc_link; 958 stack_t uc_stack; 959 struct sigcontext uc_mcontext; 960 sigset_t uc_sigmask; [ mask last for extensibility ] 961 }; 962 963 And the sigcontext is different (this is for both n32 and n64): 964 965 struct sigcontext { 966 unsigned long long sc_regs[32]; 967 unsigned long long sc_fpregs[32]; 968 unsigned long long sc_mdhi; 969 unsigned long long sc_mdlo; 970 unsigned long long sc_pc; 971 unsigned int sc_status; 972 unsigned int sc_fpc_csr; 973 unsigned int sc_fpc_eir; 974 unsigned int sc_used_math; 975 unsigned int sc_cause; 976 unsigned int sc_badvaddr; 977 }; */ 978/* *INDENT-ON* */ 979 980#define N32_STACK_T_SIZE STACK_T_SIZE 981#define N64_STACK_T_SIZE (2 * 8 + 4) 982#define N32_UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + N32_STACK_T_SIZE + 4) 983#define N64_UCONTEXT_SIGCONTEXT_OFFSET (2 * 8 + N64_STACK_T_SIZE + 4) 984#define N32_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ 985 + RTSIGFRAME_SIGINFO_SIZE \ 986 + N32_UCONTEXT_SIGCONTEXT_OFFSET) 987#define N64_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ 988 + RTSIGFRAME_SIGINFO_SIZE \ 989 + N64_UCONTEXT_SIGCONTEXT_OFFSET) 990 991#define N64_SIGCONTEXT_REGS (0 * 8) 992#define N64_SIGCONTEXT_FPREGS (32 * 8) 993#define N64_SIGCONTEXT_HI (64 * 8) 994#define N64_SIGCONTEXT_LO (65 * 8) 995#define N64_SIGCONTEXT_PC (66 * 8) 996#define N64_SIGCONTEXT_FPCSR (67 * 8 + 1 * 4) 997#define N64_SIGCONTEXT_FIR (67 * 8 + 2 * 4) 998#define N64_SIGCONTEXT_CAUSE (67 * 8 + 4 * 4) 999#define N64_SIGCONTEXT_BADVADDR (67 * 8 + 5 * 4) 1000 1001#define N64_SIGCONTEXT_REG_SIZE 8 1002 1003static void 1004mips_linux_n32n64_sigframe_init (const struct tramp_frame *self, 1005 struct frame_info *next_frame, 1006 struct trad_frame_cache *this_cache, 1007 CORE_ADDR func) 1008{ 1009 int ireg, reg_position; 1010 CORE_ADDR sigcontext_base = func - SIGFRAME_CODE_OFFSET; 1011 const struct mips_regnum *regs = mips_regnum (current_gdbarch); 1012 1013 if (self == &mips_linux_n32_rt_sigframe) 1014 sigcontext_base += N32_SIGFRAME_SIGCONTEXT_OFFSET; 1015 else 1016 sigcontext_base += N64_SIGFRAME_SIGCONTEXT_OFFSET; 1017 1018 if (mips_linux_restart_reg_p (current_gdbarch)) 1019 trad_frame_set_reg_addr (this_cache, 1020 (MIPS_RESTART_REGNUM 1021 + gdbarch_num_regs (current_gdbarch)), 1022 sigcontext_base + N64_SIGCONTEXT_REGS); 1023 1024 for (ireg = 1; ireg < 32; ireg++) 1025 trad_frame_set_reg_addr (this_cache, 1026 ireg + MIPS_ZERO_REGNUM 1027 + gdbarch_num_regs (current_gdbarch), 1028 sigcontext_base + N64_SIGCONTEXT_REGS 1029 + ireg * N64_SIGCONTEXT_REG_SIZE); 1030 1031 for (ireg = 0; ireg < 32; ireg++) 1032 trad_frame_set_reg_addr (this_cache, 1033 ireg + regs->fp0 1034 + gdbarch_num_regs (current_gdbarch), 1035 sigcontext_base + N64_SIGCONTEXT_FPREGS 1036 + ireg * N64_SIGCONTEXT_REG_SIZE); 1037 1038 trad_frame_set_reg_addr (this_cache, 1039 regs->pc + gdbarch_num_regs (current_gdbarch), 1040 sigcontext_base + N64_SIGCONTEXT_PC); 1041 1042 trad_frame_set_reg_addr (this_cache, 1043 regs->fp_control_status 1044 + gdbarch_num_regs (current_gdbarch), 1045 sigcontext_base + N64_SIGCONTEXT_FPCSR); 1046 trad_frame_set_reg_addr (this_cache, 1047 regs->hi + gdbarch_num_regs (current_gdbarch), 1048 sigcontext_base + N64_SIGCONTEXT_HI); 1049 trad_frame_set_reg_addr (this_cache, 1050 regs->lo + gdbarch_num_regs (current_gdbarch), 1051 sigcontext_base + N64_SIGCONTEXT_LO); 1052 trad_frame_set_reg_addr (this_cache, 1053 regs->cause + gdbarch_num_regs (current_gdbarch), 1054 sigcontext_base + N64_SIGCONTEXT_CAUSE); 1055 trad_frame_set_reg_addr (this_cache, 1056 regs->badvaddr + gdbarch_num_regs (current_gdbarch), 1057 sigcontext_base + N64_SIGCONTEXT_BADVADDR); 1058 1059 /* Choice of the bottom of the sigframe is somewhat arbitrary. */ 1060 trad_frame_set_id (this_cache, 1061 frame_id_build (func - SIGFRAME_CODE_OFFSET, 1062 func)); 1063} 1064 1065static void 1066mips_linux_write_pc (struct regcache *regcache, CORE_ADDR pc) 1067{ 1068 regcache_cooked_write_unsigned (regcache, 1069 gdbarch_pc_regnum (current_gdbarch), pc); 1070 1071 /* Clear the syscall restart flag. */ 1072 if (mips_linux_restart_reg_p (current_gdbarch)) 1073 regcache_cooked_write_unsigned (regcache, MIPS_RESTART_REGNUM, 0); 1074} 1075 1076/* Return 1 if MIPS_RESTART_REGNUM is usable. */ 1077 1078int 1079mips_linux_restart_reg_p (struct gdbarch *gdbarch) 1080{ 1081 /* If we do not have a target description with registers, then 1082 MIPS_RESTART_REGNUM will not be included in the register set. */ 1083 if (!tdesc_has_registers (gdbarch_target_desc (gdbarch))) 1084 return 0; 1085 1086 /* If we do, then MIPS_RESTART_REGNUM is safe to check; it will 1087 either be GPR-sized or missing. */ 1088 return register_size (gdbarch, MIPS_RESTART_REGNUM) > 0; 1089} 1090 1091/* Initialize one of the GNU/Linux OS ABIs. */ 1092 1093static void 1094mips_linux_init_abi (struct gdbarch_info info, 1095 struct gdbarch *gdbarch) 1096{ 1097 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 1098 enum mips_abi abi = mips_abi (gdbarch); 1099 struct tdesc_arch_data *tdesc_data = (void *) info.tdep_info; 1100 1101 switch (abi) 1102 { 1103 case MIPS_ABI_O32: 1104 set_gdbarch_get_longjmp_target (gdbarch, 1105 mips_linux_get_longjmp_target); 1106 set_solib_svr4_fetch_link_map_offsets 1107 (gdbarch, svr4_ilp32_fetch_link_map_offsets); 1108 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_sigframe); 1109 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_rt_sigframe); 1110 break; 1111 case MIPS_ABI_N32: 1112 set_gdbarch_get_longjmp_target (gdbarch, 1113 mips_linux_get_longjmp_target); 1114 set_solib_svr4_fetch_link_map_offsets 1115 (gdbarch, svr4_ilp32_fetch_link_map_offsets); 1116 set_gdbarch_long_double_bit (gdbarch, 128); 1117 /* These floatformats should probably be renamed. MIPS uses 1118 the same 128-bit IEEE floating point format that IA-64 uses, 1119 except that the quiet/signalling NaN bit is reversed (GDB 1120 does not distinguish between quiet and signalling NaNs). */ 1121 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); 1122 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n32_rt_sigframe); 1123 break; 1124 case MIPS_ABI_N64: 1125 set_gdbarch_get_longjmp_target (gdbarch, 1126 mips64_linux_get_longjmp_target); 1127 set_solib_svr4_fetch_link_map_offsets 1128 (gdbarch, svr4_lp64_fetch_link_map_offsets); 1129 set_gdbarch_long_double_bit (gdbarch, 128); 1130 /* These floatformats should probably be renamed. MIPS uses 1131 the same 128-bit IEEE floating point format that IA-64 uses, 1132 except that the quiet/signalling NaN bit is reversed (GDB 1133 does not distinguish between quiet and signalling NaNs). */ 1134 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); 1135 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n64_rt_sigframe); 1136 break; 1137 default: 1138 internal_error (__FILE__, __LINE__, _("can't handle ABI")); 1139 break; 1140 } 1141 1142 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); 1143 set_gdbarch_skip_solib_resolver (gdbarch, mips_linux_skip_resolver); 1144 1145 set_gdbarch_software_single_step (gdbarch, mips_software_single_step); 1146 1147 /* Enable TLS support. */ 1148 set_gdbarch_fetch_tls_load_module_address (gdbarch, 1149 svr4_fetch_objfile_link_map); 1150 1151 /* Initialize this lazily, to avoid an initialization order 1152 dependency on solib-svr4.c's _initialize routine. */ 1153 if (mips_svr4_so_ops.in_dynsym_resolve_code == NULL) 1154 { 1155 mips_svr4_so_ops = svr4_so_ops; 1156 mips_svr4_so_ops.in_dynsym_resolve_code 1157 = mips_linux_in_dynsym_resolve_code; 1158 } 1159 set_solib_ops (gdbarch, &mips_svr4_so_ops); 1160 1161 set_gdbarch_write_pc (gdbarch, mips_linux_write_pc); 1162 1163 if (tdesc_data) 1164 { 1165 const struct tdesc_feature *feature; 1166 1167 /* If we have target-described registers, then we can safely 1168 reserve a number for MIPS_RESTART_REGNUM (whether it is 1169 described or not). */ 1170 gdb_assert (gdbarch_num_regs (gdbarch) <= MIPS_RESTART_REGNUM); 1171 set_gdbarch_num_regs (gdbarch, MIPS_RESTART_REGNUM + 1); 1172 1173 /* If it's present, then assign it to the reserved number. */ 1174 feature = tdesc_find_feature (info.target_desc, 1175 "org.gnu.gdb.mips.linux"); 1176 if (feature != NULL) 1177 tdesc_numbered_register (feature, tdesc_data, MIPS_RESTART_REGNUM, 1178 "restart"); 1179 } 1180} 1181 1182void 1183_initialize_mips_linux_tdep (void) 1184{ 1185 const struct bfd_arch_info *arch_info; 1186 1187 for (arch_info = bfd_lookup_arch (bfd_arch_mips, 0); 1188 arch_info != NULL; 1189 arch_info = arch_info->next) 1190 { 1191 gdbarch_register_osabi (bfd_arch_mips, arch_info->mach, 1192 GDB_OSABI_LINUX, 1193 mips_linux_init_abi); 1194 } 1195 1196 deprecated_add_core_fns (®set_core_fns); 1197} 1198