1/* Functions specific to running gdb native on IA-64 running 2 GNU/Linux. 3 4 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 5 Free Software Foundation, Inc. 6 7 This file is part of GDB. 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 21 22#include "defs.h" 23#include "gdb_string.h" 24#include "inferior.h" 25#include "target.h" 26#include "gdbcore.h" 27#include "regcache.h" 28#include "ia64-tdep.h" 29#include "linux-nat.h" 30 31#include <signal.h> 32#include <sys/ptrace.h> 33#include "gdb_wait.h" 34#ifdef HAVE_SYS_REG_H 35#include <sys/reg.h> 36#endif 37#include <sys/syscall.h> 38#include <sys/user.h> 39 40#include <asm/ptrace_offsets.h> 41#include <sys/procfs.h> 42 43/* Prototypes for supply_gregset etc. */ 44#include "gregset.h" 45 46/* These must match the order of the register names. 47 48 Some sort of lookup table is needed because the offsets associated 49 with the registers are all over the board. */ 50 51static int u_offsets[] = 52 { 53 /* general registers */ 54 -1, /* gr0 not available; i.e, it's always zero */ 55 PT_R1, 56 PT_R2, 57 PT_R3, 58 PT_R4, 59 PT_R5, 60 PT_R6, 61 PT_R7, 62 PT_R8, 63 PT_R9, 64 PT_R10, 65 PT_R11, 66 PT_R12, 67 PT_R13, 68 PT_R14, 69 PT_R15, 70 PT_R16, 71 PT_R17, 72 PT_R18, 73 PT_R19, 74 PT_R20, 75 PT_R21, 76 PT_R22, 77 PT_R23, 78 PT_R24, 79 PT_R25, 80 PT_R26, 81 PT_R27, 82 PT_R28, 83 PT_R29, 84 PT_R30, 85 PT_R31, 86 /* gr32 through gr127 not directly available via the ptrace interface */ 87 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 88 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 89 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 90 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 91 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 92 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 93 /* Floating point registers */ 94 -1, -1, /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0) */ 95 PT_F2, 96 PT_F3, 97 PT_F4, 98 PT_F5, 99 PT_F6, 100 PT_F7, 101 PT_F8, 102 PT_F9, 103 PT_F10, 104 PT_F11, 105 PT_F12, 106 PT_F13, 107 PT_F14, 108 PT_F15, 109 PT_F16, 110 PT_F17, 111 PT_F18, 112 PT_F19, 113 PT_F20, 114 PT_F21, 115 PT_F22, 116 PT_F23, 117 PT_F24, 118 PT_F25, 119 PT_F26, 120 PT_F27, 121 PT_F28, 122 PT_F29, 123 PT_F30, 124 PT_F31, 125 PT_F32, 126 PT_F33, 127 PT_F34, 128 PT_F35, 129 PT_F36, 130 PT_F37, 131 PT_F38, 132 PT_F39, 133 PT_F40, 134 PT_F41, 135 PT_F42, 136 PT_F43, 137 PT_F44, 138 PT_F45, 139 PT_F46, 140 PT_F47, 141 PT_F48, 142 PT_F49, 143 PT_F50, 144 PT_F51, 145 PT_F52, 146 PT_F53, 147 PT_F54, 148 PT_F55, 149 PT_F56, 150 PT_F57, 151 PT_F58, 152 PT_F59, 153 PT_F60, 154 PT_F61, 155 PT_F62, 156 PT_F63, 157 PT_F64, 158 PT_F65, 159 PT_F66, 160 PT_F67, 161 PT_F68, 162 PT_F69, 163 PT_F70, 164 PT_F71, 165 PT_F72, 166 PT_F73, 167 PT_F74, 168 PT_F75, 169 PT_F76, 170 PT_F77, 171 PT_F78, 172 PT_F79, 173 PT_F80, 174 PT_F81, 175 PT_F82, 176 PT_F83, 177 PT_F84, 178 PT_F85, 179 PT_F86, 180 PT_F87, 181 PT_F88, 182 PT_F89, 183 PT_F90, 184 PT_F91, 185 PT_F92, 186 PT_F93, 187 PT_F94, 188 PT_F95, 189 PT_F96, 190 PT_F97, 191 PT_F98, 192 PT_F99, 193 PT_F100, 194 PT_F101, 195 PT_F102, 196 PT_F103, 197 PT_F104, 198 PT_F105, 199 PT_F106, 200 PT_F107, 201 PT_F108, 202 PT_F109, 203 PT_F110, 204 PT_F111, 205 PT_F112, 206 PT_F113, 207 PT_F114, 208 PT_F115, 209 PT_F116, 210 PT_F117, 211 PT_F118, 212 PT_F119, 213 PT_F120, 214 PT_F121, 215 PT_F122, 216 PT_F123, 217 PT_F124, 218 PT_F125, 219 PT_F126, 220 PT_F127, 221 /* predicate registers - we don't fetch these individually */ 222 -1, -1, -1, -1, -1, -1, -1, -1, 223 -1, -1, -1, -1, -1, -1, -1, -1, 224 -1, -1, -1, -1, -1, -1, -1, -1, 225 -1, -1, -1, -1, -1, -1, -1, -1, 226 -1, -1, -1, -1, -1, -1, -1, -1, 227 -1, -1, -1, -1, -1, -1, -1, -1, 228 -1, -1, -1, -1, -1, -1, -1, -1, 229 -1, -1, -1, -1, -1, -1, -1, -1, 230 /* branch registers */ 231 PT_B0, 232 PT_B1, 233 PT_B2, 234 PT_B3, 235 PT_B4, 236 PT_B5, 237 PT_B6, 238 PT_B7, 239 /* virtual frame pointer and virtual return address pointer */ 240 -1, -1, 241 /* other registers */ 242 PT_PR, 243 PT_CR_IIP, /* ip */ 244 PT_CR_IPSR, /* psr */ 245 PT_CFM, /* cfm */ 246 /* kernel registers not visible via ptrace interface (?) */ 247 -1, -1, -1, -1, -1, -1, -1, -1, 248 /* hole */ 249 -1, -1, -1, -1, -1, -1, -1, -1, 250 PT_AR_RSC, 251 PT_AR_BSP, 252 PT_AR_BSPSTORE, 253 PT_AR_RNAT, 254 -1, 255 -1, /* Not available: FCR, IA32 floating control register */ 256 -1, -1, 257 -1, /* Not available: EFLAG */ 258 -1, /* Not available: CSD */ 259 -1, /* Not available: SSD */ 260 -1, /* Not available: CFLG */ 261 -1, /* Not available: FSR */ 262 -1, /* Not available: FIR */ 263 -1, /* Not available: FDR */ 264 -1, 265 PT_AR_CCV, 266 -1, -1, -1, 267 PT_AR_UNAT, 268 -1, -1, -1, 269 PT_AR_FPSR, 270 -1, -1, -1, 271 -1, /* Not available: ITC */ 272 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 273 -1, -1, -1, -1, -1, -1, -1, -1, -1, 274 PT_AR_PFS, 275 PT_AR_LC, 276 -1, /* Not available: EC, the Epilog Count register */ 277 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 278 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 279 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 280 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 281 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 282 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 283 -1, 284 /* nat bits - not fetched directly; instead we obtain these bits from 285 either rnat or unat or from memory. */ 286 -1, -1, -1, -1, -1, -1, -1, -1, 287 -1, -1, -1, -1, -1, -1, -1, -1, 288 -1, -1, -1, -1, -1, -1, -1, -1, 289 -1, -1, -1, -1, -1, -1, -1, -1, 290 -1, -1, -1, -1, -1, -1, -1, -1, 291 -1, -1, -1, -1, -1, -1, -1, -1, 292 -1, -1, -1, -1, -1, -1, -1, -1, 293 -1, -1, -1, -1, -1, -1, -1, -1, 294 -1, -1, -1, -1, -1, -1, -1, -1, 295 -1, -1, -1, -1, -1, -1, -1, -1, 296 -1, -1, -1, -1, -1, -1, -1, -1, 297 -1, -1, -1, -1, -1, -1, -1, -1, 298 -1, -1, -1, -1, -1, -1, -1, -1, 299 -1, -1, -1, -1, -1, -1, -1, -1, 300 -1, -1, -1, -1, -1, -1, -1, -1, 301 -1, -1, -1, -1, -1, -1, -1, -1, 302 }; 303 304static CORE_ADDR 305ia64_register_addr (int regno) 306{ 307 CORE_ADDR addr; 308 309 if (regno < 0 || regno >= gdbarch_num_regs (current_gdbarch)) 310 error (_("Invalid register number %d."), regno); 311 312 if (u_offsets[regno] == -1) 313 addr = 0; 314 else 315 addr = (CORE_ADDR) u_offsets[regno]; 316 317 return addr; 318} 319 320static int 321ia64_cannot_fetch_register (int regno) 322{ 323 return regno < 0 324 || regno >= gdbarch_num_regs (current_gdbarch) 325 || u_offsets[regno] == -1; 326} 327 328static int 329ia64_cannot_store_register (int regno) 330{ 331 /* Rationale behind not permitting stores to bspstore... 332 333 The IA-64 architecture provides bspstore and bsp which refer 334 memory locations in the RSE's backing store. bspstore is the 335 next location which will be written when the RSE needs to write 336 to memory. bsp is the address at which r32 in the current frame 337 would be found if it were written to the backing store. 338 339 The IA-64 architecture provides read-only access to bsp and 340 read/write access to bspstore (but only when the RSE is in 341 the enforced lazy mode). It should be noted that stores 342 to bspstore also affect the value of bsp. Changing bspstore 343 does not affect the number of dirty entries between bspstore 344 and bsp, so changing bspstore by N words will also cause bsp 345 to be changed by (roughly) N as well. (It could be N-1 or N+1 346 depending upon where the NaT collection bits fall.) 347 348 OTOH, the Linux kernel provides read/write access to bsp (and 349 currently read/write access to bspstore as well). But it 350 is definitely the case that if you change one, the other 351 will change at the same time. It is more useful to gdb to 352 be able to change bsp. So in order to prevent strange and 353 undesirable things from happening when a dummy stack frame 354 is popped (after calling an inferior function), we allow 355 bspstore to be read, but not written. (Note that popping 356 a (generic) dummy stack frame causes all registers that 357 were previously read from the inferior process to be written 358 back.) */ 359 360 return regno < 0 361 || regno >= gdbarch_num_regs (current_gdbarch) 362 || u_offsets[regno] == -1 363 || regno == IA64_BSPSTORE_REGNUM; 364} 365 366void 367supply_gregset (struct regcache *regcache, const gregset_t *gregsetp) 368{ 369 int regi; 370 const greg_t *regp = (const greg_t *) gregsetp; 371 372 for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++) 373 { 374 regcache_raw_supply (regcache, regi, regp + (regi - IA64_GR0_REGNUM)); 375 } 376 377 /* FIXME: NAT collection bits are at index 32; gotta deal with these 378 somehow... */ 379 380 regcache_raw_supply (regcache, IA64_PR_REGNUM, regp + 33); 381 382 for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++) 383 { 384 regcache_raw_supply (regcache, regi, 385 regp + 34 + (regi - IA64_BR0_REGNUM)); 386 } 387 388 regcache_raw_supply (regcache, IA64_IP_REGNUM, regp + 42); 389 regcache_raw_supply (regcache, IA64_CFM_REGNUM, regp + 43); 390 regcache_raw_supply (regcache, IA64_PSR_REGNUM, regp + 44); 391 regcache_raw_supply (regcache, IA64_RSC_REGNUM, regp + 45); 392 regcache_raw_supply (regcache, IA64_BSP_REGNUM, regp + 46); 393 regcache_raw_supply (regcache, IA64_BSPSTORE_REGNUM, regp + 47); 394 regcache_raw_supply (regcache, IA64_RNAT_REGNUM, regp + 48); 395 regcache_raw_supply (regcache, IA64_CCV_REGNUM, regp + 49); 396 regcache_raw_supply (regcache, IA64_UNAT_REGNUM, regp + 50); 397 regcache_raw_supply (regcache, IA64_FPSR_REGNUM, regp + 51); 398 regcache_raw_supply (regcache, IA64_PFS_REGNUM, regp + 52); 399 regcache_raw_supply (regcache, IA64_LC_REGNUM, regp + 53); 400 regcache_raw_supply (regcache, IA64_EC_REGNUM, regp + 54); 401} 402 403void 404fill_gregset (const struct regcache *regcache, gregset_t *gregsetp, int regno) 405{ 406 int regi; 407 greg_t *regp = (greg_t *) gregsetp; 408 409#define COPY_REG(_idx_,_regi_) \ 410 if ((regno == -1) || regno == _regi_) \ 411 regcache_raw_collect (regcache, _regi_, regp + _idx_) 412 413 for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++) 414 { 415 COPY_REG (regi - IA64_GR0_REGNUM, regi); 416 } 417 418 /* FIXME: NAT collection bits at index 32? */ 419 420 COPY_REG (33, IA64_PR_REGNUM); 421 422 for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++) 423 { 424 COPY_REG (34 + (regi - IA64_BR0_REGNUM), regi); 425 } 426 427 COPY_REG (42, IA64_IP_REGNUM); 428 COPY_REG (43, IA64_CFM_REGNUM); 429 COPY_REG (44, IA64_PSR_REGNUM); 430 COPY_REG (45, IA64_RSC_REGNUM); 431 COPY_REG (46, IA64_BSP_REGNUM); 432 COPY_REG (47, IA64_BSPSTORE_REGNUM); 433 COPY_REG (48, IA64_RNAT_REGNUM); 434 COPY_REG (49, IA64_CCV_REGNUM); 435 COPY_REG (50, IA64_UNAT_REGNUM); 436 COPY_REG (51, IA64_FPSR_REGNUM); 437 COPY_REG (52, IA64_PFS_REGNUM); 438 COPY_REG (53, IA64_LC_REGNUM); 439 COPY_REG (54, IA64_EC_REGNUM); 440} 441 442/* Given a pointer to a floating point register set in /proc format 443 (fpregset_t *), unpack the register contents and supply them as gdb's 444 idea of the current floating point register values. */ 445 446void 447supply_fpregset (struct regcache *regcache, const fpregset_t *fpregsetp) 448{ 449 int regi; 450 const char *from; 451 452 for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++) 453 { 454 from = (const char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]); 455 regcache_raw_supply (regcache, regi, from); 456 } 457} 458 459/* Given a pointer to a floating point register set in /proc format 460 (fpregset_t *), update the register specified by REGNO from gdb's idea 461 of the current floating point register set. If REGNO is -1, update 462 them all. */ 463 464void 465fill_fpregset (const struct regcache *regcache, 466 fpregset_t *fpregsetp, int regno) 467{ 468 int regi; 469 470 for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++) 471 { 472 if ((regno == -1) || (regno == regi)) 473 regcache_raw_collect (regcache, regi, 474 &((*fpregsetp)[regi - IA64_FR0_REGNUM])); 475 } 476} 477 478#define IA64_PSR_DB (1UL << 24) 479#define IA64_PSR_DD (1UL << 39) 480 481static void 482enable_watchpoints_in_psr (struct regcache *regcache) 483{ 484 ULONGEST psr; 485 486 regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr); 487 if (!(psr & IA64_PSR_DB)) 488 { 489 psr |= IA64_PSR_DB; /* Set the db bit - this enables hardware 490 watchpoints and breakpoints. */ 491 regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr); 492 } 493} 494 495static long 496fetch_debug_register (ptid_t ptid, int idx) 497{ 498 long val; 499 int tid; 500 501 tid = TIDGET (ptid); 502 if (tid == 0) 503 tid = PIDGET (ptid); 504 505 val = ptrace (PT_READ_U, tid, (PTRACE_TYPE_ARG3) (PT_DBR + 8 * idx), 0); 506 507 return val; 508} 509 510static void 511store_debug_register (ptid_t ptid, int idx, long val) 512{ 513 int tid; 514 515 tid = TIDGET (ptid); 516 if (tid == 0) 517 tid = PIDGET (ptid); 518 519 (void) ptrace (PT_WRITE_U, tid, (PTRACE_TYPE_ARG3) (PT_DBR + 8 * idx), val); 520} 521 522static void 523fetch_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr, long *dbr_mask) 524{ 525 if (dbr_addr) 526 *dbr_addr = fetch_debug_register (ptid, 2 * idx); 527 if (dbr_mask) 528 *dbr_mask = fetch_debug_register (ptid, 2 * idx + 1); 529} 530 531static void 532store_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr, long *dbr_mask) 533{ 534 if (dbr_addr) 535 store_debug_register (ptid, 2 * idx, *dbr_addr); 536 if (dbr_mask) 537 store_debug_register (ptid, 2 * idx + 1, *dbr_mask); 538} 539 540static int 541is_power_of_2 (int val) 542{ 543 int i, onecount; 544 545 onecount = 0; 546 for (i = 0; i < 8 * sizeof (val); i++) 547 if (val & (1 << i)) 548 onecount++; 549 550 return onecount <= 1; 551} 552 553static int 554ia64_linux_insert_watchpoint (CORE_ADDR addr, int len, int rw) 555{ 556 ptid_t ptid = inferior_ptid; 557 int idx; 558 long dbr_addr, dbr_mask; 559 int max_watchpoints = 4; 560 561 if (len <= 0 || !is_power_of_2 (len)) 562 return -1; 563 564 for (idx = 0; idx < max_watchpoints; idx++) 565 { 566 fetch_debug_register_pair (ptid, idx, NULL, &dbr_mask); 567 if ((dbr_mask & (0x3UL << 62)) == 0) 568 { 569 /* Exit loop if both r and w bits clear */ 570 break; 571 } 572 } 573 574 if (idx == max_watchpoints) 575 return -1; 576 577 dbr_addr = (long) addr; 578 dbr_mask = (~(len - 1) & 0x00ffffffffffffffL); /* construct mask to match */ 579 dbr_mask |= 0x0800000000000000L; /* Only match privilege level 3 */ 580 switch (rw) 581 { 582 case hw_write: 583 dbr_mask |= (1L << 62); /* Set w bit */ 584 break; 585 case hw_read: 586 dbr_mask |= (1L << 63); /* Set r bit */ 587 break; 588 case hw_access: 589 dbr_mask |= (3L << 62); /* Set both r and w bits */ 590 break; 591 default: 592 return -1; 593 } 594 595 store_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask); 596 enable_watchpoints_in_psr (get_current_regcache ()); 597 598 return 0; 599} 600 601static int 602ia64_linux_remove_watchpoint (CORE_ADDR addr, int len, int type) 603{ 604 ptid_t ptid = inferior_ptid; 605 int idx; 606 long dbr_addr, dbr_mask; 607 int max_watchpoints = 4; 608 609 if (len <= 0 || !is_power_of_2 (len)) 610 return -1; 611 612 for (idx = 0; idx < max_watchpoints; idx++) 613 { 614 fetch_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask); 615 if ((dbr_mask & (0x3UL << 62)) && addr == (CORE_ADDR) dbr_addr) 616 { 617 dbr_addr = 0; 618 dbr_mask = 0; 619 store_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask); 620 return 0; 621 } 622 } 623 return -1; 624} 625 626static int 627ia64_linux_stopped_data_address (struct target_ops *ops, CORE_ADDR *addr_p) 628{ 629 CORE_ADDR psr; 630 int tid; 631 struct siginfo siginfo; 632 ptid_t ptid = inferior_ptid; 633 struct regcache *regcache = get_current_regcache (); 634 635 tid = TIDGET(ptid); 636 if (tid == 0) 637 tid = PIDGET (ptid); 638 639 errno = 0; 640 ptrace (PTRACE_GETSIGINFO, tid, (PTRACE_TYPE_ARG3) 0, &siginfo); 641 642 if (errno != 0 || siginfo.si_signo != SIGTRAP || 643 (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) 644 return 0; 645 646 regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr); 647 psr |= IA64_PSR_DD; /* Set the dd bit - this will disable the watchpoint 648 for the next instruction */ 649 regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr); 650 651 *addr_p = (CORE_ADDR)siginfo.si_addr; 652 return 1; 653} 654 655static int 656ia64_linux_stopped_by_watchpoint (void) 657{ 658 CORE_ADDR addr; 659 return ia64_linux_stopped_data_address (¤t_target, &addr); 660} 661 662static int 663ia64_linux_can_use_hw_breakpoint (int type, int cnt, int othertype) 664{ 665 return 1; 666} 667 668 669/* Fetch register REGNUM from the inferior. */ 670 671static void 672ia64_linux_fetch_register (struct regcache *regcache, int regnum) 673{ 674 CORE_ADDR addr; 675 size_t size; 676 PTRACE_TYPE_RET *buf; 677 int pid, i; 678 679 if (ia64_cannot_fetch_register (regnum)) 680 { 681 regcache_raw_supply (regcache, regnum, NULL); 682 return; 683 } 684 685 /* Cater for systems like GNU/Linux, that implement threads as 686 separate processes. */ 687 pid = ptid_get_lwp (inferior_ptid); 688 if (pid == 0) 689 pid = ptid_get_pid (inferior_ptid); 690 691 /* This isn't really an address, but ptrace thinks of it as one. */ 692 addr = ia64_register_addr (regnum); 693 size = register_size (current_gdbarch, regnum); 694 695 gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0); 696 buf = alloca (size); 697 698 /* Read the register contents from the inferior a chunk at a time. */ 699 for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++) 700 { 701 errno = 0; 702 buf[i] = ptrace (PT_READ_U, pid, (PTRACE_TYPE_ARG3)addr, 0); 703 if (errno != 0) 704 error (_("Couldn't read register %s (#%d): %s."), 705 gdbarch_register_name (current_gdbarch, regnum), 706 regnum, safe_strerror (errno)); 707 708 addr += sizeof (PTRACE_TYPE_RET); 709 } 710 regcache_raw_supply (regcache, regnum, buf); 711} 712 713/* Fetch register REGNUM from the inferior. If REGNUM is -1, do this 714 for all registers. */ 715 716static void 717ia64_linux_fetch_registers (struct regcache *regcache, int regnum) 718{ 719 if (regnum == -1) 720 for (regnum = 0; regnum < gdbarch_num_regs (current_gdbarch); regnum++) 721 ia64_linux_fetch_register (regcache, regnum); 722 else 723 ia64_linux_fetch_register (regcache, regnum); 724} 725 726/* Store register REGNUM into the inferior. */ 727 728static void 729ia64_linux_store_register (const struct regcache *regcache, int regnum) 730{ 731 CORE_ADDR addr; 732 size_t size; 733 PTRACE_TYPE_RET *buf; 734 int pid, i; 735 736 if (ia64_cannot_store_register (regnum)) 737 return; 738 739 /* Cater for systems like GNU/Linux, that implement threads as 740 separate processes. */ 741 pid = ptid_get_lwp (inferior_ptid); 742 if (pid == 0) 743 pid = ptid_get_pid (inferior_ptid); 744 745 /* This isn't really an address, but ptrace thinks of it as one. */ 746 addr = ia64_register_addr (regnum); 747 size = register_size (current_gdbarch, regnum); 748 749 gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0); 750 buf = alloca (size); 751 752 /* Write the register contents into the inferior a chunk at a time. */ 753 regcache_raw_collect (regcache, regnum, buf); 754 for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++) 755 { 756 errno = 0; 757 ptrace (PT_WRITE_U, pid, (PTRACE_TYPE_ARG3)addr, buf[i]); 758 if (errno != 0) 759 error (_("Couldn't write register %s (#%d): %s."), 760 gdbarch_register_name (current_gdbarch, regnum), 761 regnum, safe_strerror (errno)); 762 763 addr += sizeof (PTRACE_TYPE_RET); 764 } 765} 766 767/* Store register REGNUM back into the inferior. If REGNUM is -1, do 768 this for all registers. */ 769 770static void 771ia64_linux_store_registers (struct regcache *regcache, int regnum) 772{ 773 if (regnum == -1) 774 for (regnum = 0; regnum < gdbarch_num_regs (current_gdbarch); regnum++) 775 ia64_linux_store_register (regcache, regnum); 776 else 777 ia64_linux_store_register (regcache, regnum); 778} 779 780 781static LONGEST (*super_xfer_partial) (struct target_ops *, enum target_object, 782 const char *, gdb_byte *, const gdb_byte *, 783 ULONGEST, LONGEST); 784 785static LONGEST 786ia64_linux_xfer_partial (struct target_ops *ops, 787 enum target_object object, 788 const char *annex, 789 gdb_byte *readbuf, const gdb_byte *writebuf, 790 ULONGEST offset, LONGEST len) 791{ 792 if (object == TARGET_OBJECT_UNWIND_TABLE && writebuf == NULL && offset == 0) 793 return syscall (__NR_getunwind, readbuf, len); 794 795 return super_xfer_partial (ops, object, annex, readbuf, writebuf, 796 offset, len); 797} 798 799void _initialize_ia64_linux_nat (void); 800 801void 802_initialize_ia64_linux_nat (void) 803{ 804 struct target_ops *t = linux_target (); 805 806 /* Fill in the generic GNU/Linux methods. */ 807 t = linux_target (); 808 809 /* Override the default fetch/store register routines. */ 810 t->to_fetch_registers = ia64_linux_fetch_registers; 811 t->to_store_registers = ia64_linux_store_registers; 812 813 /* Override the default to_xfer_partial. */ 814 super_xfer_partial = t->to_xfer_partial; 815 t->to_xfer_partial = ia64_linux_xfer_partial; 816 817 /* Override watchpoint routines. */ 818 819 /* The IA-64 architecture can step over a watch point (without triggering 820 it again) if the "dd" (data debug fault disable) bit in the processor 821 status word is set. 822 823 This PSR bit is set in ia64_linux_stopped_by_watchpoint when the 824 code there has determined that a hardware watchpoint has indeed 825 been hit. The CPU will then be able to execute one instruction 826 without triggering a watchpoint. */ 827 828 t->to_have_steppable_watchpoint = 1; 829 t->to_can_use_hw_breakpoint = ia64_linux_can_use_hw_breakpoint; 830 t->to_stopped_by_watchpoint = ia64_linux_stopped_by_watchpoint; 831 t->to_stopped_data_address = ia64_linux_stopped_data_address; 832 t->to_insert_watchpoint = ia64_linux_insert_watchpoint; 833 t->to_remove_watchpoint = ia64_linux_remove_watchpoint; 834 835 /* Register the target. */ 836 linux_nat_add_target (t); 837} 838