1/* 2 * Copyright (c) by Jaroslav Kysela <perex@perex.cz> 3 * Abramo Bagnara <abramo@alsa-project.org> 4 * Cirrus Logic, Inc. 5 * Routines for control of Cirrus Logic CS461x chips 6 * 7 * KNOWN BUGS: 8 * - Sometimes the SPDIF input DSP tasks get's unsynchronized 9 * and the SPDIF get somewhat "distorcionated", or/and left right channel 10 * are swapped. To get around this problem when it happens, mute and unmute 11 * the SPDIF input mixer control. 12 * - On the Hercules Game Theater XP the amplifier are sometimes turned 13 * off on inadecuate moments which causes distorcions on sound. 14 * 15 * TODO: 16 * - Secondary CODEC on some soundcards 17 * - SPDIF input support for other sample rates then 48khz 18 * - Posibility to mix the SPDIF output with analog sources. 19 * - PCM channels for Center and LFE on secondary codec 20 * 21 * NOTE: with CONFIG_SND_CS46XX_NEW_DSP unset uses old DSP image (which 22 * is default configuration), no SPDIF, no secondary codec, no 23 * multi channel PCM. But known to work. 24 * 25 * FINALLY: A credit to the developers Tom and Jordan 26 * at Cirrus for have helping me out with the DSP, however we 27 * still don't have sufficient documentation and technical 28 * references to be able to implement all fancy feutures 29 * supported by the cs46xx DSP's. 30 * Benny <benny@hostmobility.com> 31 * 32 * This program is free software; you can redistribute it and/or modify 33 * it under the terms of the GNU General Public License as published by 34 * the Free Software Foundation; either version 2 of the License, or 35 * (at your option) any later version. 36 * 37 * This program is distributed in the hope that it will be useful, 38 * but WITHOUT ANY WARRANTY; without even the implied warranty of 39 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 40 * GNU General Public License for more details. 41 * 42 * You should have received a copy of the GNU General Public License 43 * along with this program; if not, write to the Free Software 44 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 45 * 46 */ 47 48#include <linux/delay.h> 49#include <linux/pci.h> 50#include <linux/pm.h> 51#include <linux/init.h> 52#include <linux/interrupt.h> 53#include <linux/slab.h> 54#include <linux/gameport.h> 55#include <linux/mutex.h> 56 57 58#include <sound/core.h> 59#include <sound/control.h> 60#include <sound/info.h> 61#include <sound/pcm.h> 62#include <sound/pcm_params.h> 63#include <sound/cs46xx.h> 64 65#include <asm/io.h> 66 67#include "cs46xx_lib.h" 68#include "dsp_spos.h" 69 70static void amp_voyetra(struct snd_cs46xx *chip, int change); 71 72#ifdef CONFIG_SND_CS46XX_NEW_DSP 73static struct snd_pcm_ops snd_cs46xx_playback_rear_ops; 74static struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops; 75static struct snd_pcm_ops snd_cs46xx_playback_clfe_ops; 76static struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops; 77static struct snd_pcm_ops snd_cs46xx_playback_iec958_ops; 78static struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops; 79#endif 80 81static struct snd_pcm_ops snd_cs46xx_playback_ops; 82static struct snd_pcm_ops snd_cs46xx_playback_indirect_ops; 83static struct snd_pcm_ops snd_cs46xx_capture_ops; 84static struct snd_pcm_ops snd_cs46xx_capture_indirect_ops; 85 86static unsigned short snd_cs46xx_codec_read(struct snd_cs46xx *chip, 87 unsigned short reg, 88 int codec_index) 89{ 90 int count; 91 unsigned short result,tmp; 92 u32 offset = 0; 93 94 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX && 95 codec_index != CS46XX_SECONDARY_CODEC_INDEX)) 96 return -EINVAL; 97 98 chip->active_ctrl(chip, 1); 99 100 if (codec_index == CS46XX_SECONDARY_CODEC_INDEX) 101 offset = CS46XX_SECONDARY_CODEC_OFFSET; 102 103 /* 104 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address 105 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 106 * 3. Write ACCTL = Control Register = 460h for initiating the write7---55 107 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h 108 * 5. if DCV not cleared, break and return error 109 * 6. Read ACSTS = Status Register = 464h, check VSTS bit 110 */ 111 112 snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset); 113 114 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL); 115 if ((tmp & ACCTL_VFRM) == 0) { 116 snd_printk(KERN_WARNING "cs46xx: ACCTL_VFRM not set 0x%x\n",tmp); 117 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, (tmp & (~ACCTL_ESYN)) | ACCTL_VFRM ); 118 msleep(50); 119 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL + offset); 120 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, tmp | ACCTL_ESYN | ACCTL_VFRM ); 121 122 } 123 124 /* 125 * Setup the AC97 control registers on the CS461x to send the 126 * appropriate command to the AC97 to perform the read. 127 * ACCAD = Command Address Register = 46Ch 128 * ACCDA = Command Data Register = 470h 129 * ACCTL = Control Register = 460h 130 * set DCV - will clear when process completed 131 * set CRW - Read command 132 * set VFRM - valid frame enabled 133 * set ESYN - ASYNC generation enabled 134 * set RSTN - ARST# inactive, AC97 codec not reset 135 */ 136 137 snd_cs46xx_pokeBA0(chip, BA0_ACCAD, reg); 138 snd_cs46xx_pokeBA0(chip, BA0_ACCDA, 0); 139 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) { 140 snd_cs46xx_pokeBA0(chip, BA0_ACCTL,/* clear ACCTL_DCV */ ACCTL_CRW | 141 ACCTL_VFRM | ACCTL_ESYN | 142 ACCTL_RSTN); 143 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | 144 ACCTL_VFRM | ACCTL_ESYN | 145 ACCTL_RSTN); 146 } else { 147 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC | 148 ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | 149 ACCTL_RSTN); 150 } 151 152 /* 153 * Wait for the read to occur. 154 */ 155 for (count = 0; count < 1000; count++) { 156 /* 157 * First, we want to wait for a short time. 158 */ 159 udelay(10); 160 /* 161 * Now, check to see if the read has completed. 162 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 163 */ 164 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) 165 goto ok1; 166 } 167 168 snd_printk(KERN_ERR "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg); 169 result = 0xffff; 170 goto end; 171 172 ok1: 173 /* 174 * Wait for the valid status bit to go active. 175 */ 176 for (count = 0; count < 100; count++) { 177 /* 178 * Read the AC97 status register. 179 * ACSTS = Status Register = 464h 180 * VSTS - Valid Status 181 */ 182 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS + offset) & ACSTS_VSTS) 183 goto ok2; 184 udelay(10); 185 } 186 187 snd_printk(KERN_ERR "AC'97 read problem (ACSTS_VSTS), codec_index %d, reg = 0x%x\n", codec_index, reg); 188 result = 0xffff; 189 goto end; 190 191 ok2: 192 /* 193 * Read the data returned from the AC97 register. 194 * ACSDA = Status Data Register = 474h 195 */ 196 197 //snd_cs46xx_peekBA0(chip, BA0_ACCAD); 198 result = snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset); 199 end: 200 chip->active_ctrl(chip, -1); 201 return result; 202} 203 204static unsigned short snd_cs46xx_ac97_read(struct snd_ac97 * ac97, 205 unsigned short reg) 206{ 207 struct snd_cs46xx *chip = ac97->private_data; 208 unsigned short val; 209 int codec_index = ac97->num; 210 211 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX && 212 codec_index != CS46XX_SECONDARY_CODEC_INDEX)) 213 return 0xffff; 214 215 val = snd_cs46xx_codec_read(chip, reg, codec_index); 216 217 return val; 218} 219 220 221static void snd_cs46xx_codec_write(struct snd_cs46xx *chip, 222 unsigned short reg, 223 unsigned short val, 224 int codec_index) 225{ 226 int count; 227 228 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX && 229 codec_index != CS46XX_SECONDARY_CODEC_INDEX)) 230 return; 231 232 chip->active_ctrl(chip, 1); 233 234 /* 235 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address 236 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 237 * 3. Write ACCTL = Control Register = 460h for initiating the write 238 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h 239 * 5. if DCV not cleared, break and return error 240 */ 241 242 /* 243 * Setup the AC97 control registers on the CS461x to send the 244 * appropriate command to the AC97 to perform the read. 245 * ACCAD = Command Address Register = 46Ch 246 * ACCDA = Command Data Register = 470h 247 * ACCTL = Control Register = 460h 248 * set DCV - will clear when process completed 249 * reset CRW - Write command 250 * set VFRM - valid frame enabled 251 * set ESYN - ASYNC generation enabled 252 * set RSTN - ARST# inactive, AC97 codec not reset 253 */ 254 snd_cs46xx_pokeBA0(chip, BA0_ACCAD , reg); 255 snd_cs46xx_pokeBA0(chip, BA0_ACCDA , val); 256 snd_cs46xx_peekBA0(chip, BA0_ACCTL); 257 258 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) { 259 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, /* clear ACCTL_DCV */ ACCTL_VFRM | 260 ACCTL_ESYN | ACCTL_RSTN); 261 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | 262 ACCTL_ESYN | ACCTL_RSTN); 263 } else { 264 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC | 265 ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 266 } 267 268 for (count = 0; count < 4000; count++) { 269 /* 270 * First, we want to wait for a short time. 271 */ 272 udelay(10); 273 /* 274 * Now, check to see if the write has completed. 275 * ACCTL = 460h, DCV should be reset by now and 460h = 07h 276 */ 277 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) { 278 goto end; 279 } 280 } 281 snd_printk(KERN_ERR "AC'97 write problem, codec_index = %d, reg = 0x%x, val = 0x%x\n", codec_index, reg, val); 282 end: 283 chip->active_ctrl(chip, -1); 284} 285 286static void snd_cs46xx_ac97_write(struct snd_ac97 *ac97, 287 unsigned short reg, 288 unsigned short val) 289{ 290 struct snd_cs46xx *chip = ac97->private_data; 291 int codec_index = ac97->num; 292 293 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX && 294 codec_index != CS46XX_SECONDARY_CODEC_INDEX)) 295 return; 296 297 snd_cs46xx_codec_write(chip, reg, val, codec_index); 298} 299 300 301/* 302 * Chip initialization 303 */ 304 305int snd_cs46xx_download(struct snd_cs46xx *chip, 306 u32 *src, 307 unsigned long offset, 308 unsigned long len) 309{ 310 void __iomem *dst; 311 unsigned int bank = offset >> 16; 312 offset = offset & 0xffff; 313 314 if (snd_BUG_ON((offset & 3) || (len & 3))) 315 return -EINVAL; 316 dst = chip->region.idx[bank+1].remap_addr + offset; 317 len /= sizeof(u32); 318 319 /* writel already converts 32-bit value to right endianess */ 320 while (len-- > 0) { 321 writel(*src++, dst); 322 dst += sizeof(u32); 323 } 324 return 0; 325} 326 327#ifdef CONFIG_SND_CS46XX_NEW_DSP 328 329#include "imgs/cwc4630.h" 330#include "imgs/cwcasync.h" 331#include "imgs/cwcsnoop.h" 332#include "imgs/cwcbinhack.h" 333#include "imgs/cwcdma.h" 334 335int snd_cs46xx_clear_BA1(struct snd_cs46xx *chip, 336 unsigned long offset, 337 unsigned long len) 338{ 339 void __iomem *dst; 340 unsigned int bank = offset >> 16; 341 offset = offset & 0xffff; 342 343 if (snd_BUG_ON((offset & 3) || (len & 3))) 344 return -EINVAL; 345 dst = chip->region.idx[bank+1].remap_addr + offset; 346 len /= sizeof(u32); 347 348 /* writel already converts 32-bit value to right endianess */ 349 while (len-- > 0) { 350 writel(0, dst); 351 dst += sizeof(u32); 352 } 353 return 0; 354} 355 356#else /* old DSP image */ 357 358#include "cs46xx_image.h" 359 360int snd_cs46xx_download_image(struct snd_cs46xx *chip) 361{ 362 int idx, err; 363 unsigned long offset = 0; 364 365 for (idx = 0; idx < BA1_MEMORY_COUNT; idx++) { 366 if ((err = snd_cs46xx_download(chip, 367 &BA1Struct.map[offset], 368 BA1Struct.memory[idx].offset, 369 BA1Struct.memory[idx].size)) < 0) 370 return err; 371 offset += BA1Struct.memory[idx].size >> 2; 372 } 373 return 0; 374} 375#endif /* CONFIG_SND_CS46XX_NEW_DSP */ 376 377/* 378 * Chip reset 379 */ 380 381static void snd_cs46xx_reset(struct snd_cs46xx *chip) 382{ 383 int idx; 384 385 /* 386 * Write the reset bit of the SP control register. 387 */ 388 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RSTSP); 389 390 /* 391 * Write the control register. 392 */ 393 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_DRQEN); 394 395 /* 396 * Clear the trap registers. 397 */ 398 for (idx = 0; idx < 8; idx++) { 399 snd_cs46xx_poke(chip, BA1_DREG, DREG_REGID_TRAP_SELECT + idx); 400 snd_cs46xx_poke(chip, BA1_TWPR, 0xFFFF); 401 } 402 snd_cs46xx_poke(chip, BA1_DREG, 0); 403 404 /* 405 * Set the frame timer to reflect the number of cycles per frame. 406 */ 407 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf); 408} 409 410static int cs46xx_wait_for_fifo(struct snd_cs46xx * chip,int retry_timeout) 411{ 412 u32 i, status = 0; 413 /* 414 * Make sure the previous FIFO write operation has completed. 415 */ 416 for(i = 0; i < 50; i++){ 417 status = snd_cs46xx_peekBA0(chip, BA0_SERBST); 418 419 if( !(status & SERBST_WBSY) ) 420 break; 421 422 mdelay(retry_timeout); 423 } 424 425 if(status & SERBST_WBSY) { 426 snd_printk(KERN_ERR "cs46xx: failure waiting for " 427 "FIFO command to complete\n"); 428 return -EINVAL; 429 } 430 431 return 0; 432} 433 434static void snd_cs46xx_clear_serial_FIFOs(struct snd_cs46xx *chip) 435{ 436 int idx, powerdown = 0; 437 unsigned int tmp; 438 439 /* 440 * See if the devices are powered down. If so, we must power them up first 441 * or they will not respond. 442 */ 443 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1); 444 if (!(tmp & CLKCR1_SWCE)) { 445 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE); 446 powerdown = 1; 447 } 448 449 /* 450 * We want to clear out the serial port FIFOs so we don't end up playing 451 * whatever random garbage happens to be in them. We fill the sample FIFOS 452 * with zero (silence). 453 */ 454 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0); 455 456 /* 457 * Fill all 256 sample FIFO locations. 458 */ 459 for (idx = 0; idx < 0xFF; idx++) { 460 /* 461 * Make sure the previous FIFO write operation has completed. 462 */ 463 if (cs46xx_wait_for_fifo(chip,1)) { 464 snd_printdd ("failed waiting for FIFO at addr (%02X)\n",idx); 465 466 if (powerdown) 467 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); 468 469 break; 470 } 471 /* 472 * Write the serial port FIFO index. 473 */ 474 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx); 475 /* 476 * Tell the serial port to load the new value into the FIFO location. 477 */ 478 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC); 479 } 480 /* 481 * Now, if we powered up the devices, then power them back down again. 482 * This is kinda ugly, but should never happen. 483 */ 484 if (powerdown) 485 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); 486} 487 488static void snd_cs46xx_proc_start(struct snd_cs46xx *chip) 489{ 490 int cnt; 491 492 /* 493 * Set the frame timer to reflect the number of cycles per frame. 494 */ 495 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf); 496 /* 497 * Turn on the run, run at frame, and DMA enable bits in the local copy of 498 * the SP control register. 499 */ 500 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 501 /* 502 * Wait until the run at frame bit resets itself in the SP control 503 * register. 504 */ 505 for (cnt = 0; cnt < 25; cnt++) { 506 udelay(50); 507 if (!(snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR)) 508 break; 509 } 510 511 if (snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR) 512 snd_printk(KERN_ERR "SPCR_RUNFR never reset\n"); 513} 514 515static void snd_cs46xx_proc_stop(struct snd_cs46xx *chip) 516{ 517 /* 518 * Turn off the run, run at frame, and DMA enable bits in the local copy of 519 * the SP control register. 520 */ 521 snd_cs46xx_poke(chip, BA1_SPCR, 0); 522} 523 524/* 525 * Sample rate routines 526 */ 527 528#define GOF_PER_SEC 200 529 530static void snd_cs46xx_set_play_sample_rate(struct snd_cs46xx *chip, unsigned int rate) 531{ 532 unsigned long flags; 533 unsigned int tmp1, tmp2; 534 unsigned int phiIncr; 535 unsigned int correctionPerGOF, correctionPerSec; 536 537 /* 538 * Compute the values used to drive the actual sample rate conversion. 539 * The following formulas are being computed, using inline assembly 540 * since we need to use 64 bit arithmetic to compute the values: 541 * 542 * phiIncr = floor((Fs,in * 2^26) / Fs,out) 543 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) / 544 * GOF_PER_SEC) 545 * ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M 546 * GOF_PER_SEC * correctionPerGOF 547 * 548 * i.e. 549 * 550 * phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out) 551 * correctionPerGOF:correctionPerSec = 552 * dividend:remainder(ulOther / GOF_PER_SEC) 553 */ 554 tmp1 = rate << 16; 555 phiIncr = tmp1 / 48000; 556 tmp1 -= phiIncr * 48000; 557 tmp1 <<= 10; 558 phiIncr <<= 10; 559 tmp2 = tmp1 / 48000; 560 phiIncr += tmp2; 561 tmp1 -= tmp2 * 48000; 562 correctionPerGOF = tmp1 / GOF_PER_SEC; 563 tmp1 -= correctionPerGOF * GOF_PER_SEC; 564 correctionPerSec = tmp1; 565 566 /* 567 * Fill in the SampleRateConverter control block. 568 */ 569 spin_lock_irqsave(&chip->reg_lock, flags); 570 snd_cs46xx_poke(chip, BA1_PSRC, 571 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF)); 572 snd_cs46xx_poke(chip, BA1_PPI, phiIncr); 573 spin_unlock_irqrestore(&chip->reg_lock, flags); 574} 575 576static void snd_cs46xx_set_capture_sample_rate(struct snd_cs46xx *chip, unsigned int rate) 577{ 578 unsigned long flags; 579 unsigned int phiIncr, coeffIncr, tmp1, tmp2; 580 unsigned int correctionPerGOF, correctionPerSec, initialDelay; 581 unsigned int frameGroupLength, cnt; 582 583 /* 584 * We can only decimate by up to a factor of 1/9th the hardware rate. 585 * Correct the value if an attempt is made to stray outside that limit. 586 */ 587 if ((rate * 9) < 48000) 588 rate = 48000 / 9; 589 590 /* 591 * We can not capture at at rate greater than the Input Rate (48000). 592 * Return an error if an attempt is made to stray outside that limit. 593 */ 594 if (rate > 48000) 595 rate = 48000; 596 597 /* 598 * Compute the values used to drive the actual sample rate conversion. 599 * The following formulas are being computed, using inline assembly 600 * since we need to use 64 bit arithmetic to compute the values: 601 * 602 * coeffIncr = -floor((Fs,out * 2^23) / Fs,in) 603 * phiIncr = floor((Fs,in * 2^26) / Fs,out) 604 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) / 605 * GOF_PER_SEC) 606 * correctionPerSec = Fs,in * 2^26 - Fs,out * phiIncr - 607 * GOF_PER_SEC * correctionPerGOF 608 * initialDelay = ceil((24 * Fs,in) / Fs,out) 609 * 610 * i.e. 611 * 612 * coeffIncr = neg(dividend((Fs,out * 2^23) / Fs,in)) 613 * phiIncr:ulOther = dividend:remainder((Fs,in * 2^26) / Fs,out) 614 * correctionPerGOF:correctionPerSec = 615 * dividend:remainder(ulOther / GOF_PER_SEC) 616 * initialDelay = dividend(((24 * Fs,in) + Fs,out - 1) / Fs,out) 617 */ 618 619 tmp1 = rate << 16; 620 coeffIncr = tmp1 / 48000; 621 tmp1 -= coeffIncr * 48000; 622 tmp1 <<= 7; 623 coeffIncr <<= 7; 624 coeffIncr += tmp1 / 48000; 625 coeffIncr ^= 0xFFFFFFFF; 626 coeffIncr++; 627 tmp1 = 48000 << 16; 628 phiIncr = tmp1 / rate; 629 tmp1 -= phiIncr * rate; 630 tmp1 <<= 10; 631 phiIncr <<= 10; 632 tmp2 = tmp1 / rate; 633 phiIncr += tmp2; 634 tmp1 -= tmp2 * rate; 635 correctionPerGOF = tmp1 / GOF_PER_SEC; 636 tmp1 -= correctionPerGOF * GOF_PER_SEC; 637 correctionPerSec = tmp1; 638 initialDelay = ((48000 * 24) + rate - 1) / rate; 639 640 /* 641 * Fill in the VariDecimate control block. 642 */ 643 spin_lock_irqsave(&chip->reg_lock, flags); 644 snd_cs46xx_poke(chip, BA1_CSRC, 645 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF)); 646 snd_cs46xx_poke(chip, BA1_CCI, coeffIncr); 647 snd_cs46xx_poke(chip, BA1_CD, 648 (((BA1_VARIDEC_BUF_1 + (initialDelay << 2)) << 16) & 0xFFFF0000) | 0x80); 649 snd_cs46xx_poke(chip, BA1_CPI, phiIncr); 650 spin_unlock_irqrestore(&chip->reg_lock, flags); 651 652 /* 653 * Figure out the frame group length for the write back task. Basically, 654 * this is just the factors of 24000 (2^6*3*5^3) that are not present in 655 * the output sample rate. 656 */ 657 frameGroupLength = 1; 658 for (cnt = 2; cnt <= 64; cnt *= 2) { 659 if (((rate / cnt) * cnt) != rate) 660 frameGroupLength *= 2; 661 } 662 if (((rate / 3) * 3) != rate) { 663 frameGroupLength *= 3; 664 } 665 for (cnt = 5; cnt <= 125; cnt *= 5) { 666 if (((rate / cnt) * cnt) != rate) 667 frameGroupLength *= 5; 668 } 669 670 /* 671 * Fill in the WriteBack control block. 672 */ 673 spin_lock_irqsave(&chip->reg_lock, flags); 674 snd_cs46xx_poke(chip, BA1_CFG1, frameGroupLength); 675 snd_cs46xx_poke(chip, BA1_CFG2, (0x00800000 | frameGroupLength)); 676 snd_cs46xx_poke(chip, BA1_CCST, 0x0000FFFF); 677 snd_cs46xx_poke(chip, BA1_CSPB, ((65536 * rate) / 24000)); 678 snd_cs46xx_poke(chip, (BA1_CSPB + 4), 0x0000FFFF); 679 spin_unlock_irqrestore(&chip->reg_lock, flags); 680} 681 682/* 683 * PCM part 684 */ 685 686static void snd_cs46xx_pb_trans_copy(struct snd_pcm_substream *substream, 687 struct snd_pcm_indirect *rec, size_t bytes) 688{ 689 struct snd_pcm_runtime *runtime = substream->runtime; 690 struct snd_cs46xx_pcm * cpcm = runtime->private_data; 691 memcpy(cpcm->hw_buf.area + rec->hw_data, runtime->dma_area + rec->sw_data, bytes); 692} 693 694static int snd_cs46xx_playback_transfer(struct snd_pcm_substream *substream) 695{ 696 struct snd_pcm_runtime *runtime = substream->runtime; 697 struct snd_cs46xx_pcm * cpcm = runtime->private_data; 698 snd_pcm_indirect_playback_transfer(substream, &cpcm->pcm_rec, snd_cs46xx_pb_trans_copy); 699 return 0; 700} 701 702static void snd_cs46xx_cp_trans_copy(struct snd_pcm_substream *substream, 703 struct snd_pcm_indirect *rec, size_t bytes) 704{ 705 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 706 struct snd_pcm_runtime *runtime = substream->runtime; 707 memcpy(runtime->dma_area + rec->sw_data, 708 chip->capt.hw_buf.area + rec->hw_data, bytes); 709} 710 711static int snd_cs46xx_capture_transfer(struct snd_pcm_substream *substream) 712{ 713 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 714 snd_pcm_indirect_capture_transfer(substream, &chip->capt.pcm_rec, snd_cs46xx_cp_trans_copy); 715 return 0; 716} 717 718static snd_pcm_uframes_t snd_cs46xx_playback_direct_pointer(struct snd_pcm_substream *substream) 719{ 720 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 721 size_t ptr; 722 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data; 723 724 if (snd_BUG_ON(!cpcm->pcm_channel)) 725 return -ENXIO; 726 727#ifdef CONFIG_SND_CS46XX_NEW_DSP 728 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2); 729#else 730 ptr = snd_cs46xx_peek(chip, BA1_PBA); 731#endif 732 ptr -= cpcm->hw_buf.addr; 733 return ptr >> cpcm->shift; 734} 735 736static snd_pcm_uframes_t snd_cs46xx_playback_indirect_pointer(struct snd_pcm_substream *substream) 737{ 738 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 739 size_t ptr; 740 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data; 741 742#ifdef CONFIG_SND_CS46XX_NEW_DSP 743 if (snd_BUG_ON(!cpcm->pcm_channel)) 744 return -ENXIO; 745 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2); 746#else 747 ptr = snd_cs46xx_peek(chip, BA1_PBA); 748#endif 749 ptr -= cpcm->hw_buf.addr; 750 return snd_pcm_indirect_playback_pointer(substream, &cpcm->pcm_rec, ptr); 751} 752 753static snd_pcm_uframes_t snd_cs46xx_capture_direct_pointer(struct snd_pcm_substream *substream) 754{ 755 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 756 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr; 757 return ptr >> chip->capt.shift; 758} 759 760static snd_pcm_uframes_t snd_cs46xx_capture_indirect_pointer(struct snd_pcm_substream *substream) 761{ 762 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 763 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr; 764 return snd_pcm_indirect_capture_pointer(substream, &chip->capt.pcm_rec, ptr); 765} 766 767static int snd_cs46xx_playback_trigger(struct snd_pcm_substream *substream, 768 int cmd) 769{ 770 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 771 /*struct snd_pcm_runtime *runtime = substream->runtime;*/ 772 int result = 0; 773 774#ifdef CONFIG_SND_CS46XX_NEW_DSP 775 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data; 776 if (! cpcm->pcm_channel) { 777 return -ENXIO; 778 } 779#endif 780 switch (cmd) { 781 case SNDRV_PCM_TRIGGER_START: 782 case SNDRV_PCM_TRIGGER_RESUME: 783#ifdef CONFIG_SND_CS46XX_NEW_DSP 784 /* magic value to unmute PCM stream playback volume */ 785 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 786 SCBVolumeCtrl) << 2, 0x80008000); 787 788 if (cpcm->pcm_channel->unlinked) 789 cs46xx_dsp_pcm_link(chip,cpcm->pcm_channel); 790 791 if (substream->runtime->periods != CS46XX_FRAGS) 792 snd_cs46xx_playback_transfer(substream); 793#else 794 spin_lock(&chip->reg_lock); 795 if (substream->runtime->periods != CS46XX_FRAGS) 796 snd_cs46xx_playback_transfer(substream); 797 { unsigned int tmp; 798 tmp = snd_cs46xx_peek(chip, BA1_PCTL); 799 tmp &= 0x0000ffff; 800 snd_cs46xx_poke(chip, BA1_PCTL, chip->play_ctl | tmp); 801 } 802 spin_unlock(&chip->reg_lock); 803#endif 804 break; 805 case SNDRV_PCM_TRIGGER_STOP: 806 case SNDRV_PCM_TRIGGER_SUSPEND: 807#ifdef CONFIG_SND_CS46XX_NEW_DSP 808 /* magic mute channel */ 809 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 810 SCBVolumeCtrl) << 2, 0xffffffff); 811 812 if (!cpcm->pcm_channel->unlinked) 813 cs46xx_dsp_pcm_unlink(chip,cpcm->pcm_channel); 814#else 815 spin_lock(&chip->reg_lock); 816 { unsigned int tmp; 817 tmp = snd_cs46xx_peek(chip, BA1_PCTL); 818 tmp &= 0x0000ffff; 819 snd_cs46xx_poke(chip, BA1_PCTL, tmp); 820 } 821 spin_unlock(&chip->reg_lock); 822#endif 823 break; 824 default: 825 result = -EINVAL; 826 break; 827 } 828 829 return result; 830} 831 832static int snd_cs46xx_capture_trigger(struct snd_pcm_substream *substream, 833 int cmd) 834{ 835 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 836 unsigned int tmp; 837 int result = 0; 838 839 spin_lock(&chip->reg_lock); 840 switch (cmd) { 841 case SNDRV_PCM_TRIGGER_START: 842 case SNDRV_PCM_TRIGGER_RESUME: 843 tmp = snd_cs46xx_peek(chip, BA1_CCTL); 844 tmp &= 0xffff0000; 845 snd_cs46xx_poke(chip, BA1_CCTL, chip->capt.ctl | tmp); 846 break; 847 case SNDRV_PCM_TRIGGER_STOP: 848 case SNDRV_PCM_TRIGGER_SUSPEND: 849 tmp = snd_cs46xx_peek(chip, BA1_CCTL); 850 tmp &= 0xffff0000; 851 snd_cs46xx_poke(chip, BA1_CCTL, tmp); 852 break; 853 default: 854 result = -EINVAL; 855 break; 856 } 857 spin_unlock(&chip->reg_lock); 858 859 return result; 860} 861 862#ifdef CONFIG_SND_CS46XX_NEW_DSP 863static int _cs46xx_adjust_sample_rate (struct snd_cs46xx *chip, struct snd_cs46xx_pcm *cpcm, 864 int sample_rate) 865{ 866 867 /* If PCMReaderSCB and SrcTaskSCB not created yet ... */ 868 if ( cpcm->pcm_channel == NULL) { 869 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate, 870 cpcm, cpcm->hw_buf.addr,cpcm->pcm_channel_id); 871 if (cpcm->pcm_channel == NULL) { 872 snd_printk(KERN_ERR "cs46xx: failed to create virtual PCM channel\n"); 873 return -ENOMEM; 874 } 875 cpcm->pcm_channel->sample_rate = sample_rate; 876 } else 877 /* if sample rate is changed */ 878 if ((int)cpcm->pcm_channel->sample_rate != sample_rate) { 879 int unlinked = cpcm->pcm_channel->unlinked; 880 cs46xx_dsp_destroy_pcm_channel (chip,cpcm->pcm_channel); 881 882 if ( (cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate, cpcm, 883 cpcm->hw_buf.addr, 884 cpcm->pcm_channel_id)) == NULL) { 885 snd_printk(KERN_ERR "cs46xx: failed to re-create virtual PCM channel\n"); 886 return -ENOMEM; 887 } 888 889 if (!unlinked) cs46xx_dsp_pcm_link (chip,cpcm->pcm_channel); 890 cpcm->pcm_channel->sample_rate = sample_rate; 891 } 892 893 return 0; 894} 895#endif 896 897 898static int snd_cs46xx_playback_hw_params(struct snd_pcm_substream *substream, 899 struct snd_pcm_hw_params *hw_params) 900{ 901 struct snd_pcm_runtime *runtime = substream->runtime; 902 struct snd_cs46xx_pcm *cpcm; 903 int err; 904#ifdef CONFIG_SND_CS46XX_NEW_DSP 905 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 906 int sample_rate = params_rate(hw_params); 907 int period_size = params_period_bytes(hw_params); 908#endif 909 cpcm = runtime->private_data; 910 911#ifdef CONFIG_SND_CS46XX_NEW_DSP 912 if (snd_BUG_ON(!sample_rate)) 913 return -ENXIO; 914 915 mutex_lock(&chip->spos_mutex); 916 917 if (_cs46xx_adjust_sample_rate (chip,cpcm,sample_rate)) { 918 mutex_unlock(&chip->spos_mutex); 919 return -ENXIO; 920 } 921 922 snd_BUG_ON(!cpcm->pcm_channel); 923 if (!cpcm->pcm_channel) { 924 mutex_unlock(&chip->spos_mutex); 925 return -ENXIO; 926 } 927 928 929 if (cs46xx_dsp_pcm_channel_set_period (chip,cpcm->pcm_channel,period_size)) { 930 mutex_unlock(&chip->spos_mutex); 931 return -EINVAL; 932 } 933 934 snd_printdd ("period_size (%d), periods (%d) buffer_size(%d)\n", 935 period_size, params_periods(hw_params), 936 params_buffer_bytes(hw_params)); 937#endif 938 939 if (params_periods(hw_params) == CS46XX_FRAGS) { 940 if (runtime->dma_area != cpcm->hw_buf.area) 941 snd_pcm_lib_free_pages(substream); 942 runtime->dma_area = cpcm->hw_buf.area; 943 runtime->dma_addr = cpcm->hw_buf.addr; 944 runtime->dma_bytes = cpcm->hw_buf.bytes; 945 946 947#ifdef CONFIG_SND_CS46XX_NEW_DSP 948 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) { 949 substream->ops = &snd_cs46xx_playback_ops; 950 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) { 951 substream->ops = &snd_cs46xx_playback_rear_ops; 952 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) { 953 substream->ops = &snd_cs46xx_playback_clfe_ops; 954 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) { 955 substream->ops = &snd_cs46xx_playback_iec958_ops; 956 } else { 957 snd_BUG(); 958 } 959#else 960 substream->ops = &snd_cs46xx_playback_ops; 961#endif 962 963 } else { 964 if (runtime->dma_area == cpcm->hw_buf.area) { 965 runtime->dma_area = NULL; 966 runtime->dma_addr = 0; 967 runtime->dma_bytes = 0; 968 } 969 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0) { 970#ifdef CONFIG_SND_CS46XX_NEW_DSP 971 mutex_unlock(&chip->spos_mutex); 972#endif 973 return err; 974 } 975 976#ifdef CONFIG_SND_CS46XX_NEW_DSP 977 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) { 978 substream->ops = &snd_cs46xx_playback_indirect_ops; 979 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) { 980 substream->ops = &snd_cs46xx_playback_indirect_rear_ops; 981 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) { 982 substream->ops = &snd_cs46xx_playback_indirect_clfe_ops; 983 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) { 984 substream->ops = &snd_cs46xx_playback_indirect_iec958_ops; 985 } else { 986 snd_BUG(); 987 } 988#else 989 substream->ops = &snd_cs46xx_playback_indirect_ops; 990#endif 991 992 } 993 994#ifdef CONFIG_SND_CS46XX_NEW_DSP 995 mutex_unlock(&chip->spos_mutex); 996#endif 997 998 return 0; 999} 1000 1001static int snd_cs46xx_playback_hw_free(struct snd_pcm_substream *substream) 1002{ 1003 /*struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);*/ 1004 struct snd_pcm_runtime *runtime = substream->runtime; 1005 struct snd_cs46xx_pcm *cpcm; 1006 1007 cpcm = runtime->private_data; 1008 1009 /* if play_back open fails, then this function 1010 is called and cpcm can actually be NULL here */ 1011 if (!cpcm) return -ENXIO; 1012 1013 if (runtime->dma_area != cpcm->hw_buf.area) 1014 snd_pcm_lib_free_pages(substream); 1015 1016 runtime->dma_area = NULL; 1017 runtime->dma_addr = 0; 1018 runtime->dma_bytes = 0; 1019 1020 return 0; 1021} 1022 1023static int snd_cs46xx_playback_prepare(struct snd_pcm_substream *substream) 1024{ 1025 unsigned int tmp; 1026 unsigned int pfie; 1027 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1028 struct snd_pcm_runtime *runtime = substream->runtime; 1029 struct snd_cs46xx_pcm *cpcm; 1030 1031 cpcm = runtime->private_data; 1032 1033#ifdef CONFIG_SND_CS46XX_NEW_DSP 1034 if (snd_BUG_ON(!cpcm->pcm_channel)) 1035 return -ENXIO; 1036 1037 pfie = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2 ); 1038 pfie &= ~0x0000f03f; 1039#else 1040 /* old dsp */ 1041 pfie = snd_cs46xx_peek(chip, BA1_PFIE); 1042 pfie &= ~0x0000f03f; 1043#endif 1044 1045 cpcm->shift = 2; 1046 /* if to convert from stereo to mono */ 1047 if (runtime->channels == 1) { 1048 cpcm->shift--; 1049 pfie |= 0x00002000; 1050 } 1051 /* if to convert from 8 bit to 16 bit */ 1052 if (snd_pcm_format_width(runtime->format) == 8) { 1053 cpcm->shift--; 1054 pfie |= 0x00001000; 1055 } 1056 /* if to convert to unsigned */ 1057 if (snd_pcm_format_unsigned(runtime->format)) 1058 pfie |= 0x00008000; 1059 1060 /* Never convert byte order when sample stream is 8 bit */ 1061 if (snd_pcm_format_width(runtime->format) != 8) { 1062 /* convert from big endian to little endian */ 1063 if (snd_pcm_format_big_endian(runtime->format)) 1064 pfie |= 0x00004000; 1065 } 1066 1067 memset(&cpcm->pcm_rec, 0, sizeof(cpcm->pcm_rec)); 1068 cpcm->pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream); 1069 cpcm->pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << cpcm->shift; 1070 1071#ifdef CONFIG_SND_CS46XX_NEW_DSP 1072 1073 tmp = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2); 1074 tmp &= ~0x000003ff; 1075 tmp |= (4 << cpcm->shift) - 1; 1076 /* playback transaction count register */ 1077 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2, tmp); 1078 1079 /* playback format && interrupt enable */ 1080 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2, pfie | cpcm->pcm_channel->pcm_slot); 1081#else 1082 snd_cs46xx_poke(chip, BA1_PBA, cpcm->hw_buf.addr); 1083 tmp = snd_cs46xx_peek(chip, BA1_PDTC); 1084 tmp &= ~0x000003ff; 1085 tmp |= (4 << cpcm->shift) - 1; 1086 snd_cs46xx_poke(chip, BA1_PDTC, tmp); 1087 snd_cs46xx_poke(chip, BA1_PFIE, pfie); 1088 snd_cs46xx_set_play_sample_rate(chip, runtime->rate); 1089#endif 1090 1091 return 0; 1092} 1093 1094static int snd_cs46xx_capture_hw_params(struct snd_pcm_substream *substream, 1095 struct snd_pcm_hw_params *hw_params) 1096{ 1097 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1098 struct snd_pcm_runtime *runtime = substream->runtime; 1099 int err; 1100 1101#ifdef CONFIG_SND_CS46XX_NEW_DSP 1102 cs46xx_dsp_pcm_ostream_set_period (chip, params_period_bytes(hw_params)); 1103#endif 1104 if (runtime->periods == CS46XX_FRAGS) { 1105 if (runtime->dma_area != chip->capt.hw_buf.area) 1106 snd_pcm_lib_free_pages(substream); 1107 runtime->dma_area = chip->capt.hw_buf.area; 1108 runtime->dma_addr = chip->capt.hw_buf.addr; 1109 runtime->dma_bytes = chip->capt.hw_buf.bytes; 1110 substream->ops = &snd_cs46xx_capture_ops; 1111 } else { 1112 if (runtime->dma_area == chip->capt.hw_buf.area) { 1113 runtime->dma_area = NULL; 1114 runtime->dma_addr = 0; 1115 runtime->dma_bytes = 0; 1116 } 1117 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0) 1118 return err; 1119 substream->ops = &snd_cs46xx_capture_indirect_ops; 1120 } 1121 1122 return 0; 1123} 1124 1125static int snd_cs46xx_capture_hw_free(struct snd_pcm_substream *substream) 1126{ 1127 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1128 struct snd_pcm_runtime *runtime = substream->runtime; 1129 1130 if (runtime->dma_area != chip->capt.hw_buf.area) 1131 snd_pcm_lib_free_pages(substream); 1132 runtime->dma_area = NULL; 1133 runtime->dma_addr = 0; 1134 runtime->dma_bytes = 0; 1135 1136 return 0; 1137} 1138 1139static int snd_cs46xx_capture_prepare(struct snd_pcm_substream *substream) 1140{ 1141 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1142 struct snd_pcm_runtime *runtime = substream->runtime; 1143 1144 snd_cs46xx_poke(chip, BA1_CBA, chip->capt.hw_buf.addr); 1145 chip->capt.shift = 2; 1146 memset(&chip->capt.pcm_rec, 0, sizeof(chip->capt.pcm_rec)); 1147 chip->capt.pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream); 1148 chip->capt.pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << 2; 1149 snd_cs46xx_set_capture_sample_rate(chip, runtime->rate); 1150 1151 return 0; 1152} 1153 1154static irqreturn_t snd_cs46xx_interrupt(int irq, void *dev_id) 1155{ 1156 struct snd_cs46xx *chip = dev_id; 1157 u32 status1; 1158#ifdef CONFIG_SND_CS46XX_NEW_DSP 1159 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 1160 u32 status2; 1161 int i; 1162 struct snd_cs46xx_pcm *cpcm = NULL; 1163#endif 1164 1165 /* 1166 * Read the Interrupt Status Register to clear the interrupt 1167 */ 1168 status1 = snd_cs46xx_peekBA0(chip, BA0_HISR); 1169 if ((status1 & 0x7fffffff) == 0) { 1170 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV); 1171 return IRQ_NONE; 1172 } 1173 1174#ifdef CONFIG_SND_CS46XX_NEW_DSP 1175 status2 = snd_cs46xx_peekBA0(chip, BA0_HSR0); 1176 1177 for (i = 0; i < DSP_MAX_PCM_CHANNELS; ++i) { 1178 if (i <= 15) { 1179 if ( status1 & (1 << i) ) { 1180 if (i == CS46XX_DSP_CAPTURE_CHANNEL) { 1181 if (chip->capt.substream) 1182 snd_pcm_period_elapsed(chip->capt.substream); 1183 } else { 1184 if (ins->pcm_channels[i].active && 1185 ins->pcm_channels[i].private_data && 1186 !ins->pcm_channels[i].unlinked) { 1187 cpcm = ins->pcm_channels[i].private_data; 1188 snd_pcm_period_elapsed(cpcm->substream); 1189 } 1190 } 1191 } 1192 } else { 1193 if ( status2 & (1 << (i - 16))) { 1194 if (ins->pcm_channels[i].active && 1195 ins->pcm_channels[i].private_data && 1196 !ins->pcm_channels[i].unlinked) { 1197 cpcm = ins->pcm_channels[i].private_data; 1198 snd_pcm_period_elapsed(cpcm->substream); 1199 } 1200 } 1201 } 1202 } 1203 1204#else 1205 /* old dsp */ 1206 if ((status1 & HISR_VC0) && chip->playback_pcm) { 1207 if (chip->playback_pcm->substream) 1208 snd_pcm_period_elapsed(chip->playback_pcm->substream); 1209 } 1210 if ((status1 & HISR_VC1) && chip->pcm) { 1211 if (chip->capt.substream) 1212 snd_pcm_period_elapsed(chip->capt.substream); 1213 } 1214#endif 1215 1216 if ((status1 & HISR_MIDI) && chip->rmidi) { 1217 unsigned char c; 1218 1219 spin_lock(&chip->reg_lock); 1220 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_RBE) == 0) { 1221 c = snd_cs46xx_peekBA0(chip, BA0_MIDRP); 1222 if ((chip->midcr & MIDCR_RIE) == 0) 1223 continue; 1224 snd_rawmidi_receive(chip->midi_input, &c, 1); 1225 } 1226 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) { 1227 if ((chip->midcr & MIDCR_TIE) == 0) 1228 break; 1229 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) { 1230 chip->midcr &= ~MIDCR_TIE; 1231 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1232 break; 1233 } 1234 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, c); 1235 } 1236 spin_unlock(&chip->reg_lock); 1237 } 1238 /* 1239 * EOI to the PCI part....reenables interrupts 1240 */ 1241 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV); 1242 1243 return IRQ_HANDLED; 1244} 1245 1246static struct snd_pcm_hardware snd_cs46xx_playback = 1247{ 1248 .info = (SNDRV_PCM_INFO_MMAP | 1249 SNDRV_PCM_INFO_INTERLEAVED | 1250 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/ 1251 /*SNDRV_PCM_INFO_RESUME*/), 1252 .formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 | 1253 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE | 1254 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE), 1255 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1256 .rate_min = 5500, 1257 .rate_max = 48000, 1258 .channels_min = 1, 1259 .channels_max = 2, 1260 .buffer_bytes_max = (256 * 1024), 1261 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE, 1262 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE, 1263 .periods_min = CS46XX_FRAGS, 1264 .periods_max = 1024, 1265 .fifo_size = 0, 1266}; 1267 1268static struct snd_pcm_hardware snd_cs46xx_capture = 1269{ 1270 .info = (SNDRV_PCM_INFO_MMAP | 1271 SNDRV_PCM_INFO_INTERLEAVED | 1272 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/ 1273 /*SNDRV_PCM_INFO_RESUME*/), 1274 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1275 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1276 .rate_min = 5500, 1277 .rate_max = 48000, 1278 .channels_min = 2, 1279 .channels_max = 2, 1280 .buffer_bytes_max = (256 * 1024), 1281 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE, 1282 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE, 1283 .periods_min = CS46XX_FRAGS, 1284 .periods_max = 1024, 1285 .fifo_size = 0, 1286}; 1287 1288#ifdef CONFIG_SND_CS46XX_NEW_DSP 1289 1290static unsigned int period_sizes[] = { 32, 64, 128, 256, 512, 1024, 2048 }; 1291 1292static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes = { 1293 .count = ARRAY_SIZE(period_sizes), 1294 .list = period_sizes, 1295 .mask = 0 1296}; 1297 1298#endif 1299 1300static void snd_cs46xx_pcm_free_substream(struct snd_pcm_runtime *runtime) 1301{ 1302 kfree(runtime->private_data); 1303} 1304 1305static int _cs46xx_playback_open_channel (struct snd_pcm_substream *substream,int pcm_channel_id) 1306{ 1307 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1308 struct snd_cs46xx_pcm * cpcm; 1309 struct snd_pcm_runtime *runtime = substream->runtime; 1310 1311 cpcm = kzalloc(sizeof(*cpcm), GFP_KERNEL); 1312 if (cpcm == NULL) 1313 return -ENOMEM; 1314 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci), 1315 PAGE_SIZE, &cpcm->hw_buf) < 0) { 1316 kfree(cpcm); 1317 return -ENOMEM; 1318 } 1319 1320 runtime->hw = snd_cs46xx_playback; 1321 runtime->private_data = cpcm; 1322 runtime->private_free = snd_cs46xx_pcm_free_substream; 1323 1324 cpcm->substream = substream; 1325#ifdef CONFIG_SND_CS46XX_NEW_DSP 1326 mutex_lock(&chip->spos_mutex); 1327 cpcm->pcm_channel = NULL; 1328 cpcm->pcm_channel_id = pcm_channel_id; 1329 1330 1331 snd_pcm_hw_constraint_list(runtime, 0, 1332 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 1333 &hw_constraints_period_sizes); 1334 1335 mutex_unlock(&chip->spos_mutex); 1336#else 1337 chip->playback_pcm = cpcm; /* HACK */ 1338#endif 1339 1340 if (chip->accept_valid) 1341 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID; 1342 chip->active_ctrl(chip, 1); 1343 1344 return 0; 1345} 1346 1347static int snd_cs46xx_playback_open(struct snd_pcm_substream *substream) 1348{ 1349 snd_printdd("open front channel\n"); 1350 return _cs46xx_playback_open_channel(substream,DSP_PCM_MAIN_CHANNEL); 1351} 1352 1353#ifdef CONFIG_SND_CS46XX_NEW_DSP 1354static int snd_cs46xx_playback_open_rear(struct snd_pcm_substream *substream) 1355{ 1356 snd_printdd("open rear channel\n"); 1357 1358 return _cs46xx_playback_open_channel(substream,DSP_PCM_REAR_CHANNEL); 1359} 1360 1361static int snd_cs46xx_playback_open_clfe(struct snd_pcm_substream *substream) 1362{ 1363 snd_printdd("open center - LFE channel\n"); 1364 1365 return _cs46xx_playback_open_channel(substream,DSP_PCM_CENTER_LFE_CHANNEL); 1366} 1367 1368static int snd_cs46xx_playback_open_iec958(struct snd_pcm_substream *substream) 1369{ 1370 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1371 1372 snd_printdd("open raw iec958 channel\n"); 1373 1374 mutex_lock(&chip->spos_mutex); 1375 cs46xx_iec958_pre_open (chip); 1376 mutex_unlock(&chip->spos_mutex); 1377 1378 return _cs46xx_playback_open_channel(substream,DSP_IEC958_CHANNEL); 1379} 1380 1381static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream); 1382 1383static int snd_cs46xx_playback_close_iec958(struct snd_pcm_substream *substream) 1384{ 1385 int err; 1386 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1387 1388 snd_printdd("close raw iec958 channel\n"); 1389 1390 err = snd_cs46xx_playback_close(substream); 1391 1392 mutex_lock(&chip->spos_mutex); 1393 cs46xx_iec958_post_close (chip); 1394 mutex_unlock(&chip->spos_mutex); 1395 1396 return err; 1397} 1398#endif 1399 1400static int snd_cs46xx_capture_open(struct snd_pcm_substream *substream) 1401{ 1402 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1403 1404 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci), 1405 PAGE_SIZE, &chip->capt.hw_buf) < 0) 1406 return -ENOMEM; 1407 chip->capt.substream = substream; 1408 substream->runtime->hw = snd_cs46xx_capture; 1409 1410 if (chip->accept_valid) 1411 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID; 1412 1413 chip->active_ctrl(chip, 1); 1414 1415#ifdef CONFIG_SND_CS46XX_NEW_DSP 1416 snd_pcm_hw_constraint_list(substream->runtime, 0, 1417 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 1418 &hw_constraints_period_sizes); 1419#endif 1420 return 0; 1421} 1422 1423static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream) 1424{ 1425 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1426 struct snd_pcm_runtime *runtime = substream->runtime; 1427 struct snd_cs46xx_pcm * cpcm; 1428 1429 cpcm = runtime->private_data; 1430 1431 /* when playback_open fails, then cpcm can be NULL */ 1432 if (!cpcm) return -ENXIO; 1433 1434#ifdef CONFIG_SND_CS46XX_NEW_DSP 1435 mutex_lock(&chip->spos_mutex); 1436 if (cpcm->pcm_channel) { 1437 cs46xx_dsp_destroy_pcm_channel(chip,cpcm->pcm_channel); 1438 cpcm->pcm_channel = NULL; 1439 } 1440 mutex_unlock(&chip->spos_mutex); 1441#else 1442 chip->playback_pcm = NULL; 1443#endif 1444 1445 cpcm->substream = NULL; 1446 snd_dma_free_pages(&cpcm->hw_buf); 1447 chip->active_ctrl(chip, -1); 1448 1449 return 0; 1450} 1451 1452static int snd_cs46xx_capture_close(struct snd_pcm_substream *substream) 1453{ 1454 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1455 1456 chip->capt.substream = NULL; 1457 snd_dma_free_pages(&chip->capt.hw_buf); 1458 chip->active_ctrl(chip, -1); 1459 1460 return 0; 1461} 1462 1463#ifdef CONFIG_SND_CS46XX_NEW_DSP 1464static struct snd_pcm_ops snd_cs46xx_playback_rear_ops = { 1465 .open = snd_cs46xx_playback_open_rear, 1466 .close = snd_cs46xx_playback_close, 1467 .ioctl = snd_pcm_lib_ioctl, 1468 .hw_params = snd_cs46xx_playback_hw_params, 1469 .hw_free = snd_cs46xx_playback_hw_free, 1470 .prepare = snd_cs46xx_playback_prepare, 1471 .trigger = snd_cs46xx_playback_trigger, 1472 .pointer = snd_cs46xx_playback_direct_pointer, 1473}; 1474 1475static struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops = { 1476 .open = snd_cs46xx_playback_open_rear, 1477 .close = snd_cs46xx_playback_close, 1478 .ioctl = snd_pcm_lib_ioctl, 1479 .hw_params = snd_cs46xx_playback_hw_params, 1480 .hw_free = snd_cs46xx_playback_hw_free, 1481 .prepare = snd_cs46xx_playback_prepare, 1482 .trigger = snd_cs46xx_playback_trigger, 1483 .pointer = snd_cs46xx_playback_indirect_pointer, 1484 .ack = snd_cs46xx_playback_transfer, 1485}; 1486 1487static struct snd_pcm_ops snd_cs46xx_playback_clfe_ops = { 1488 .open = snd_cs46xx_playback_open_clfe, 1489 .close = snd_cs46xx_playback_close, 1490 .ioctl = snd_pcm_lib_ioctl, 1491 .hw_params = snd_cs46xx_playback_hw_params, 1492 .hw_free = snd_cs46xx_playback_hw_free, 1493 .prepare = snd_cs46xx_playback_prepare, 1494 .trigger = snd_cs46xx_playback_trigger, 1495 .pointer = snd_cs46xx_playback_direct_pointer, 1496}; 1497 1498static struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops = { 1499 .open = snd_cs46xx_playback_open_clfe, 1500 .close = snd_cs46xx_playback_close, 1501 .ioctl = snd_pcm_lib_ioctl, 1502 .hw_params = snd_cs46xx_playback_hw_params, 1503 .hw_free = snd_cs46xx_playback_hw_free, 1504 .prepare = snd_cs46xx_playback_prepare, 1505 .trigger = snd_cs46xx_playback_trigger, 1506 .pointer = snd_cs46xx_playback_indirect_pointer, 1507 .ack = snd_cs46xx_playback_transfer, 1508}; 1509 1510static struct snd_pcm_ops snd_cs46xx_playback_iec958_ops = { 1511 .open = snd_cs46xx_playback_open_iec958, 1512 .close = snd_cs46xx_playback_close_iec958, 1513 .ioctl = snd_pcm_lib_ioctl, 1514 .hw_params = snd_cs46xx_playback_hw_params, 1515 .hw_free = snd_cs46xx_playback_hw_free, 1516 .prepare = snd_cs46xx_playback_prepare, 1517 .trigger = snd_cs46xx_playback_trigger, 1518 .pointer = snd_cs46xx_playback_direct_pointer, 1519}; 1520 1521static struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops = { 1522 .open = snd_cs46xx_playback_open_iec958, 1523 .close = snd_cs46xx_playback_close_iec958, 1524 .ioctl = snd_pcm_lib_ioctl, 1525 .hw_params = snd_cs46xx_playback_hw_params, 1526 .hw_free = snd_cs46xx_playback_hw_free, 1527 .prepare = snd_cs46xx_playback_prepare, 1528 .trigger = snd_cs46xx_playback_trigger, 1529 .pointer = snd_cs46xx_playback_indirect_pointer, 1530 .ack = snd_cs46xx_playback_transfer, 1531}; 1532 1533#endif 1534 1535static struct snd_pcm_ops snd_cs46xx_playback_ops = { 1536 .open = snd_cs46xx_playback_open, 1537 .close = snd_cs46xx_playback_close, 1538 .ioctl = snd_pcm_lib_ioctl, 1539 .hw_params = snd_cs46xx_playback_hw_params, 1540 .hw_free = snd_cs46xx_playback_hw_free, 1541 .prepare = snd_cs46xx_playback_prepare, 1542 .trigger = snd_cs46xx_playback_trigger, 1543 .pointer = snd_cs46xx_playback_direct_pointer, 1544}; 1545 1546static struct snd_pcm_ops snd_cs46xx_playback_indirect_ops = { 1547 .open = snd_cs46xx_playback_open, 1548 .close = snd_cs46xx_playback_close, 1549 .ioctl = snd_pcm_lib_ioctl, 1550 .hw_params = snd_cs46xx_playback_hw_params, 1551 .hw_free = snd_cs46xx_playback_hw_free, 1552 .prepare = snd_cs46xx_playback_prepare, 1553 .trigger = snd_cs46xx_playback_trigger, 1554 .pointer = snd_cs46xx_playback_indirect_pointer, 1555 .ack = snd_cs46xx_playback_transfer, 1556}; 1557 1558static struct snd_pcm_ops snd_cs46xx_capture_ops = { 1559 .open = snd_cs46xx_capture_open, 1560 .close = snd_cs46xx_capture_close, 1561 .ioctl = snd_pcm_lib_ioctl, 1562 .hw_params = snd_cs46xx_capture_hw_params, 1563 .hw_free = snd_cs46xx_capture_hw_free, 1564 .prepare = snd_cs46xx_capture_prepare, 1565 .trigger = snd_cs46xx_capture_trigger, 1566 .pointer = snd_cs46xx_capture_direct_pointer, 1567}; 1568 1569static struct snd_pcm_ops snd_cs46xx_capture_indirect_ops = { 1570 .open = snd_cs46xx_capture_open, 1571 .close = snd_cs46xx_capture_close, 1572 .ioctl = snd_pcm_lib_ioctl, 1573 .hw_params = snd_cs46xx_capture_hw_params, 1574 .hw_free = snd_cs46xx_capture_hw_free, 1575 .prepare = snd_cs46xx_capture_prepare, 1576 .trigger = snd_cs46xx_capture_trigger, 1577 .pointer = snd_cs46xx_capture_indirect_pointer, 1578 .ack = snd_cs46xx_capture_transfer, 1579}; 1580 1581#ifdef CONFIG_SND_CS46XX_NEW_DSP 1582#define MAX_PLAYBACK_CHANNELS (DSP_MAX_PCM_CHANNELS - 1) 1583#else 1584#define MAX_PLAYBACK_CHANNELS 1 1585#endif 1586 1587int __devinit snd_cs46xx_pcm(struct snd_cs46xx *chip, int device, struct snd_pcm ** rpcm) 1588{ 1589 struct snd_pcm *pcm; 1590 int err; 1591 1592 if (rpcm) 1593 *rpcm = NULL; 1594 if ((err = snd_pcm_new(chip->card, "CS46xx", device, MAX_PLAYBACK_CHANNELS, 1, &pcm)) < 0) 1595 return err; 1596 1597 pcm->private_data = chip; 1598 1599 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_ops); 1600 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs46xx_capture_ops); 1601 1602 /* global setup */ 1603 pcm->info_flags = 0; 1604 strcpy(pcm->name, "CS46xx"); 1605 chip->pcm = pcm; 1606 1607 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1608 snd_dma_pci_data(chip->pci), 64*1024, 256*1024); 1609 1610 if (rpcm) 1611 *rpcm = pcm; 1612 1613 return 0; 1614} 1615 1616 1617#ifdef CONFIG_SND_CS46XX_NEW_DSP 1618int __devinit snd_cs46xx_pcm_rear(struct snd_cs46xx *chip, int device, struct snd_pcm ** rpcm) 1619{ 1620 struct snd_pcm *pcm; 1621 int err; 1622 1623 if (rpcm) 1624 *rpcm = NULL; 1625 1626 if ((err = snd_pcm_new(chip->card, "CS46xx - Rear", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0) 1627 return err; 1628 1629 pcm->private_data = chip; 1630 1631 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_rear_ops); 1632 1633 /* global setup */ 1634 pcm->info_flags = 0; 1635 strcpy(pcm->name, "CS46xx - Rear"); 1636 chip->pcm_rear = pcm; 1637 1638 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1639 snd_dma_pci_data(chip->pci), 64*1024, 256*1024); 1640 1641 if (rpcm) 1642 *rpcm = pcm; 1643 1644 return 0; 1645} 1646 1647int __devinit snd_cs46xx_pcm_center_lfe(struct snd_cs46xx *chip, int device, struct snd_pcm ** rpcm) 1648{ 1649 struct snd_pcm *pcm; 1650 int err; 1651 1652 if (rpcm) 1653 *rpcm = NULL; 1654 1655 if ((err = snd_pcm_new(chip->card, "CS46xx - Center LFE", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0) 1656 return err; 1657 1658 pcm->private_data = chip; 1659 1660 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_clfe_ops); 1661 1662 /* global setup */ 1663 pcm->info_flags = 0; 1664 strcpy(pcm->name, "CS46xx - Center LFE"); 1665 chip->pcm_center_lfe = pcm; 1666 1667 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1668 snd_dma_pci_data(chip->pci), 64*1024, 256*1024); 1669 1670 if (rpcm) 1671 *rpcm = pcm; 1672 1673 return 0; 1674} 1675 1676int __devinit snd_cs46xx_pcm_iec958(struct snd_cs46xx *chip, int device, struct snd_pcm ** rpcm) 1677{ 1678 struct snd_pcm *pcm; 1679 int err; 1680 1681 if (rpcm) 1682 *rpcm = NULL; 1683 1684 if ((err = snd_pcm_new(chip->card, "CS46xx - IEC958", device, 1, 0, &pcm)) < 0) 1685 return err; 1686 1687 pcm->private_data = chip; 1688 1689 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_iec958_ops); 1690 1691 /* global setup */ 1692 pcm->info_flags = 0; 1693 strcpy(pcm->name, "CS46xx - IEC958"); 1694 chip->pcm_rear = pcm; 1695 1696 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1697 snd_dma_pci_data(chip->pci), 64*1024, 256*1024); 1698 1699 if (rpcm) 1700 *rpcm = pcm; 1701 1702 return 0; 1703} 1704#endif 1705 1706/* 1707 * Mixer routines 1708 */ 1709static void snd_cs46xx_mixer_free_ac97_bus(struct snd_ac97_bus *bus) 1710{ 1711 struct snd_cs46xx *chip = bus->private_data; 1712 1713 chip->ac97_bus = NULL; 1714} 1715 1716static void snd_cs46xx_mixer_free_ac97(struct snd_ac97 *ac97) 1717{ 1718 struct snd_cs46xx *chip = ac97->private_data; 1719 1720 if (snd_BUG_ON(ac97 != chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] && 1721 ac97 != chip->ac97[CS46XX_SECONDARY_CODEC_INDEX])) 1722 return; 1723 1724 if (ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) { 1725 chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] = NULL; 1726 chip->eapd_switch = NULL; 1727 } 1728 else 1729 chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] = NULL; 1730} 1731 1732static int snd_cs46xx_vol_info(struct snd_kcontrol *kcontrol, 1733 struct snd_ctl_elem_info *uinfo) 1734{ 1735 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1736 uinfo->count = 2; 1737 uinfo->value.integer.min = 0; 1738 uinfo->value.integer.max = 0x7fff; 1739 return 0; 1740} 1741 1742static int snd_cs46xx_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1743{ 1744 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1745 int reg = kcontrol->private_value; 1746 unsigned int val = snd_cs46xx_peek(chip, reg); 1747 ucontrol->value.integer.value[0] = 0xffff - (val >> 16); 1748 ucontrol->value.integer.value[1] = 0xffff - (val & 0xffff); 1749 return 0; 1750} 1751 1752static int snd_cs46xx_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1753{ 1754 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1755 int reg = kcontrol->private_value; 1756 unsigned int val = ((0xffff - ucontrol->value.integer.value[0]) << 16 | 1757 (0xffff - ucontrol->value.integer.value[1])); 1758 unsigned int old = snd_cs46xx_peek(chip, reg); 1759 int change = (old != val); 1760 1761 if (change) { 1762 snd_cs46xx_poke(chip, reg, val); 1763 } 1764 1765 return change; 1766} 1767 1768#ifdef CONFIG_SND_CS46XX_NEW_DSP 1769 1770static int snd_cs46xx_vol_dac_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1771{ 1772 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1773 1774 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->dac_volume_left; 1775 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->dac_volume_right; 1776 1777 return 0; 1778} 1779 1780static int snd_cs46xx_vol_dac_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1781{ 1782 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1783 int change = 0; 1784 1785 if (chip->dsp_spos_instance->dac_volume_right != ucontrol->value.integer.value[0] || 1786 chip->dsp_spos_instance->dac_volume_left != ucontrol->value.integer.value[1]) { 1787 cs46xx_dsp_set_dac_volume(chip, 1788 ucontrol->value.integer.value[0], 1789 ucontrol->value.integer.value[1]); 1790 change = 1; 1791 } 1792 1793 return change; 1794} 1795 1796 1797#define snd_mixer_boolean_info snd_ctl_boolean_mono_info 1798 1799static int snd_cs46xx_iec958_get(struct snd_kcontrol *kcontrol, 1800 struct snd_ctl_elem_value *ucontrol) 1801{ 1802 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1803 int reg = kcontrol->private_value; 1804 1805 if (reg == CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT) 1806 ucontrol->value.integer.value[0] = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED); 1807 else 1808 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_status_in; 1809 1810 return 0; 1811} 1812 1813static int snd_cs46xx_iec958_put(struct snd_kcontrol *kcontrol, 1814 struct snd_ctl_elem_value *ucontrol) 1815{ 1816 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1817 int change, res; 1818 1819 switch (kcontrol->private_value) { 1820 case CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT: 1821 mutex_lock(&chip->spos_mutex); 1822 change = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED); 1823 if (ucontrol->value.integer.value[0] && !change) 1824 cs46xx_dsp_enable_spdif_out(chip); 1825 else if (change && !ucontrol->value.integer.value[0]) 1826 cs46xx_dsp_disable_spdif_out(chip); 1827 1828 res = (change != (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED)); 1829 mutex_unlock(&chip->spos_mutex); 1830 break; 1831 case CS46XX_MIXER_SPDIF_INPUT_ELEMENT: 1832 change = chip->dsp_spos_instance->spdif_status_in; 1833 if (ucontrol->value.integer.value[0] && !change) { 1834 cs46xx_dsp_enable_spdif_in(chip); 1835 /* restore volume */ 1836 } 1837 else if (change && !ucontrol->value.integer.value[0]) 1838 cs46xx_dsp_disable_spdif_in(chip); 1839 1840 res = (change != chip->dsp_spos_instance->spdif_status_in); 1841 break; 1842 default: 1843 res = -EINVAL; 1844 snd_BUG(); /* should never happen ... */ 1845 } 1846 1847 return res; 1848} 1849 1850static int snd_cs46xx_adc_capture_get(struct snd_kcontrol *kcontrol, 1851 struct snd_ctl_elem_value *ucontrol) 1852{ 1853 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1854 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 1855 1856 if (ins->adc_input != NULL) 1857 ucontrol->value.integer.value[0] = 1; 1858 else 1859 ucontrol->value.integer.value[0] = 0; 1860 1861 return 0; 1862} 1863 1864static int snd_cs46xx_adc_capture_put(struct snd_kcontrol *kcontrol, 1865 struct snd_ctl_elem_value *ucontrol) 1866{ 1867 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1868 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 1869 int change = 0; 1870 1871 if (ucontrol->value.integer.value[0] && !ins->adc_input) { 1872 cs46xx_dsp_enable_adc_capture(chip); 1873 change = 1; 1874 } else if (!ucontrol->value.integer.value[0] && ins->adc_input) { 1875 cs46xx_dsp_disable_adc_capture(chip); 1876 change = 1; 1877 } 1878 return change; 1879} 1880 1881static int snd_cs46xx_pcm_capture_get(struct snd_kcontrol *kcontrol, 1882 struct snd_ctl_elem_value *ucontrol) 1883{ 1884 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1885 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 1886 1887 if (ins->pcm_input != NULL) 1888 ucontrol->value.integer.value[0] = 1; 1889 else 1890 ucontrol->value.integer.value[0] = 0; 1891 1892 return 0; 1893} 1894 1895 1896static int snd_cs46xx_pcm_capture_put(struct snd_kcontrol *kcontrol, 1897 struct snd_ctl_elem_value *ucontrol) 1898{ 1899 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1900 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 1901 int change = 0; 1902 1903 if (ucontrol->value.integer.value[0] && !ins->pcm_input) { 1904 cs46xx_dsp_enable_pcm_capture(chip); 1905 change = 1; 1906 } else if (!ucontrol->value.integer.value[0] && ins->pcm_input) { 1907 cs46xx_dsp_disable_pcm_capture(chip); 1908 change = 1; 1909 } 1910 1911 return change; 1912} 1913 1914static int snd_herc_spdif_select_get(struct snd_kcontrol *kcontrol, 1915 struct snd_ctl_elem_value *ucontrol) 1916{ 1917 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1918 1919 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR); 1920 1921 if (val1 & EGPIODR_GPOE0) 1922 ucontrol->value.integer.value[0] = 1; 1923 else 1924 ucontrol->value.integer.value[0] = 0; 1925 1926 return 0; 1927} 1928 1929/* 1930 * Game Theatre XP card - EGPIO[0] is used to select SPDIF input optical or coaxial. 1931 */ 1932static int snd_herc_spdif_select_put(struct snd_kcontrol *kcontrol, 1933 struct snd_ctl_elem_value *ucontrol) 1934{ 1935 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1936 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR); 1937 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR); 1938 1939 if (ucontrol->value.integer.value[0]) { 1940 /* optical is default */ 1941 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, 1942 EGPIODR_GPOE0 | val1); /* enable EGPIO0 output */ 1943 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, 1944 EGPIOPTR_GPPT0 | val2); /* open-drain on output */ 1945 } else { 1946 /* coaxial */ 1947 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE0); /* disable */ 1948 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT0); /* disable */ 1949 } 1950 1951 /* checking diff from the EGPIO direction register 1952 should be enough */ 1953 return (val1 != (int)snd_cs46xx_peekBA0(chip, BA0_EGPIODR)); 1954} 1955 1956 1957static int snd_cs46xx_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1958{ 1959 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1960 uinfo->count = 1; 1961 return 0; 1962} 1963 1964static int snd_cs46xx_spdif_default_get(struct snd_kcontrol *kcontrol, 1965 struct snd_ctl_elem_value *ucontrol) 1966{ 1967 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1968 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 1969 1970 mutex_lock(&chip->spos_mutex); 1971 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_default >> 24) & 0xff); 1972 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_default >> 16) & 0xff); 1973 ucontrol->value.iec958.status[2] = 0; 1974 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_default) & 0xff); 1975 mutex_unlock(&chip->spos_mutex); 1976 1977 return 0; 1978} 1979 1980static int snd_cs46xx_spdif_default_put(struct snd_kcontrol *kcontrol, 1981 struct snd_ctl_elem_value *ucontrol) 1982{ 1983 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol); 1984 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 1985 unsigned int val; 1986 int change; 1987 1988 mutex_lock(&chip->spos_mutex); 1989 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) | 1990 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[2]) << 16) | 1991 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) | 1992 /* left and right validity bit */ 1993 (1 << 13) | (1 << 12); 1994 1995 1996 change = (unsigned int)ins->spdif_csuv_default != val; 1997 ins->spdif_csuv_default = val; 1998 1999 if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) ) 2000 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val); 2001 2002 mutex_unlock(&chip->spos_mutex); 2003 2004 return change; 2005} 2006 2007static int snd_cs46xx_spdif_mask_get(struct snd_kcontrol *kcontrol, 2008 struct snd_ctl_elem_value *ucontrol) 2009{ 2010 ucontrol->value.iec958.status[0] = 0xff; 2011 ucontrol->value.iec958.status[1] = 0xff; 2012 ucontrol->value.iec958.status[2] = 0x00; 2013 ucontrol->value.iec958.status[3] = 0xff; 2014 return 0; 2015} 2016 2017static int snd_cs46xx_spdif_stream_get(struct snd_kcontrol *kcontrol, 2018 struct snd_ctl_elem_value *ucontrol) 2019{ 2020 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2021 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 2022 2023 mutex_lock(&chip->spos_mutex); 2024 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_stream >> 24) & 0xff); 2025 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_stream >> 16) & 0xff); 2026 ucontrol->value.iec958.status[2] = 0; 2027 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_stream) & 0xff); 2028 mutex_unlock(&chip->spos_mutex); 2029 2030 return 0; 2031} 2032 2033static int snd_cs46xx_spdif_stream_put(struct snd_kcontrol *kcontrol, 2034 struct snd_ctl_elem_value *ucontrol) 2035{ 2036 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol); 2037 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 2038 unsigned int val; 2039 int change; 2040 2041 mutex_lock(&chip->spos_mutex); 2042 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) | 2043 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[1]) << 16) | 2044 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) | 2045 /* left and right validity bit */ 2046 (1 << 13) | (1 << 12); 2047 2048 2049 change = ins->spdif_csuv_stream != val; 2050 ins->spdif_csuv_stream = val; 2051 2052 if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN ) 2053 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val); 2054 2055 mutex_unlock(&chip->spos_mutex); 2056 2057 return change; 2058} 2059 2060#endif /* CONFIG_SND_CS46XX_NEW_DSP */ 2061 2062 2063static struct snd_kcontrol_new snd_cs46xx_controls[] __devinitdata = { 2064{ 2065 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2066 .name = "DAC Volume", 2067 .info = snd_cs46xx_vol_info, 2068#ifndef CONFIG_SND_CS46XX_NEW_DSP 2069 .get = snd_cs46xx_vol_get, 2070 .put = snd_cs46xx_vol_put, 2071 .private_value = BA1_PVOL, 2072#else 2073 .get = snd_cs46xx_vol_dac_get, 2074 .put = snd_cs46xx_vol_dac_put, 2075#endif 2076}, 2077 2078{ 2079 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2080 .name = "ADC Volume", 2081 .info = snd_cs46xx_vol_info, 2082 .get = snd_cs46xx_vol_get, 2083 .put = snd_cs46xx_vol_put, 2084#ifndef CONFIG_SND_CS46XX_NEW_DSP 2085 .private_value = BA1_CVOL, 2086#else 2087 .private_value = (VARIDECIMATE_SCB_ADDR + 0xE) << 2, 2088#endif 2089}, 2090#ifdef CONFIG_SND_CS46XX_NEW_DSP 2091{ 2092 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2093 .name = "ADC Capture Switch", 2094 .info = snd_mixer_boolean_info, 2095 .get = snd_cs46xx_adc_capture_get, 2096 .put = snd_cs46xx_adc_capture_put 2097}, 2098{ 2099 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2100 .name = "DAC Capture Switch", 2101 .info = snd_mixer_boolean_info, 2102 .get = snd_cs46xx_pcm_capture_get, 2103 .put = snd_cs46xx_pcm_capture_put 2104}, 2105{ 2106 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2107 .name = SNDRV_CTL_NAME_IEC958("Output ",NONE,SWITCH), 2108 .info = snd_mixer_boolean_info, 2109 .get = snd_cs46xx_iec958_get, 2110 .put = snd_cs46xx_iec958_put, 2111 .private_value = CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT, 2112}, 2113{ 2114 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2115 .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,SWITCH), 2116 .info = snd_mixer_boolean_info, 2117 .get = snd_cs46xx_iec958_get, 2118 .put = snd_cs46xx_iec958_put, 2119 .private_value = CS46XX_MIXER_SPDIF_INPUT_ELEMENT, 2120}, 2121{ 2122 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2123 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), 2124 .info = snd_cs46xx_spdif_info, 2125 .get = snd_cs46xx_spdif_default_get, 2126 .put = snd_cs46xx_spdif_default_put, 2127}, 2128{ 2129 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2130 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK), 2131 .info = snd_cs46xx_spdif_info, 2132 .get = snd_cs46xx_spdif_mask_get, 2133 .access = SNDRV_CTL_ELEM_ACCESS_READ 2134}, 2135{ 2136 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2137 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), 2138 .info = snd_cs46xx_spdif_info, 2139 .get = snd_cs46xx_spdif_stream_get, 2140 .put = snd_cs46xx_spdif_stream_put 2141}, 2142 2143#endif 2144}; 2145 2146#ifdef CONFIG_SND_CS46XX_NEW_DSP 2147/* set primary cs4294 codec into Extended Audio Mode */ 2148static int snd_cs46xx_front_dup_get(struct snd_kcontrol *kcontrol, 2149 struct snd_ctl_elem_value *ucontrol) 2150{ 2151 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2152 unsigned short val; 2153 val = snd_ac97_read(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], AC97_CSR_ACMODE); 2154 ucontrol->value.integer.value[0] = (val & 0x200) ? 0 : 1; 2155 return 0; 2156} 2157 2158static int snd_cs46xx_front_dup_put(struct snd_kcontrol *kcontrol, 2159 struct snd_ctl_elem_value *ucontrol) 2160{ 2161 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2162 return snd_ac97_update_bits(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], 2163 AC97_CSR_ACMODE, 0x200, 2164 ucontrol->value.integer.value[0] ? 0 : 0x200); 2165} 2166 2167static struct snd_kcontrol_new snd_cs46xx_front_dup_ctl = { 2168 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2169 .name = "Duplicate Front", 2170 .info = snd_mixer_boolean_info, 2171 .get = snd_cs46xx_front_dup_get, 2172 .put = snd_cs46xx_front_dup_put, 2173}; 2174#endif 2175 2176#ifdef CONFIG_SND_CS46XX_NEW_DSP 2177/* Only available on the Hercules Game Theater XP soundcard */ 2178static struct snd_kcontrol_new snd_hercules_controls[] = { 2179{ 2180 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2181 .name = "Optical/Coaxial SPDIF Input Switch", 2182 .info = snd_mixer_boolean_info, 2183 .get = snd_herc_spdif_select_get, 2184 .put = snd_herc_spdif_select_put, 2185}, 2186}; 2187 2188 2189static void snd_cs46xx_codec_reset (struct snd_ac97 * ac97) 2190{ 2191 unsigned long end_time; 2192 int err; 2193 2194 /* reset to defaults */ 2195 snd_ac97_write(ac97, AC97_RESET, 0); 2196 2197 /* set the desired CODEC mode */ 2198 if (ac97->num == CS46XX_PRIMARY_CODEC_INDEX) { 2199 snd_printdd("cs46xx: CODEC1 mode %04x\n", 0x0); 2200 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x0); 2201 } else if (ac97->num == CS46XX_SECONDARY_CODEC_INDEX) { 2202 snd_printdd("cs46xx: CODEC2 mode %04x\n", 0x3); 2203 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x3); 2204 } else { 2205 snd_BUG(); /* should never happen ... */ 2206 } 2207 2208 udelay(50); 2209 2210 /* it's necessary to wait awhile until registers are accessible after RESET */ 2211 /* because the PCM or MASTER volume registers can be modified, */ 2212 /* the REC_GAIN register is used for tests */ 2213 end_time = jiffies + HZ; 2214 do { 2215 unsigned short ext_mid; 2216 2217 /* use preliminary reads to settle the communication */ 2218 snd_ac97_read(ac97, AC97_RESET); 2219 snd_ac97_read(ac97, AC97_VENDOR_ID1); 2220 snd_ac97_read(ac97, AC97_VENDOR_ID2); 2221 /* modem? */ 2222 ext_mid = snd_ac97_read(ac97, AC97_EXTENDED_MID); 2223 if (ext_mid != 0xffff && (ext_mid & 1) != 0) 2224 return; 2225 2226 /* test if we can write to the record gain volume register */ 2227 snd_ac97_write(ac97, AC97_REC_GAIN, 0x8a05); 2228 if ((err = snd_ac97_read(ac97, AC97_REC_GAIN)) == 0x8a05) 2229 return; 2230 2231 msleep(10); 2232 } while (time_after_eq(end_time, jiffies)); 2233 2234 snd_printk(KERN_ERR "CS46xx secondary codec doesn't respond!\n"); 2235} 2236#endif 2237 2238static int __devinit cs46xx_detect_codec(struct snd_cs46xx *chip, int codec) 2239{ 2240 int idx, err; 2241 struct snd_ac97_template ac97; 2242 2243 memset(&ac97, 0, sizeof(ac97)); 2244 ac97.private_data = chip; 2245 ac97.private_free = snd_cs46xx_mixer_free_ac97; 2246 ac97.num = codec; 2247 if (chip->amplifier_ctrl == amp_voyetra) 2248 ac97.scaps = AC97_SCAP_INV_EAPD; 2249 2250 if (codec == CS46XX_SECONDARY_CODEC_INDEX) { 2251 snd_cs46xx_codec_write(chip, AC97_RESET, 0, codec); 2252 udelay(10); 2253 if (snd_cs46xx_codec_read(chip, AC97_RESET, codec) & 0x8000) { 2254 snd_printdd("snd_cs46xx: seconadry codec not present\n"); 2255 return -ENXIO; 2256 } 2257 } 2258 2259 snd_cs46xx_codec_write(chip, AC97_MASTER, 0x8000, codec); 2260 for (idx = 0; idx < 100; ++idx) { 2261 if (snd_cs46xx_codec_read(chip, AC97_MASTER, codec) == 0x8000) { 2262 err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97[codec]); 2263 return err; 2264 } 2265 msleep(10); 2266 } 2267 snd_printdd("snd_cs46xx: codec %d detection timeout\n", codec); 2268 return -ENXIO; 2269} 2270 2271int __devinit snd_cs46xx_mixer(struct snd_cs46xx *chip, int spdif_device) 2272{ 2273 struct snd_card *card = chip->card; 2274 struct snd_ctl_elem_id id; 2275 int err; 2276 unsigned int idx; 2277 static struct snd_ac97_bus_ops ops = { 2278#ifdef CONFIG_SND_CS46XX_NEW_DSP 2279 .reset = snd_cs46xx_codec_reset, 2280#endif 2281 .write = snd_cs46xx_ac97_write, 2282 .read = snd_cs46xx_ac97_read, 2283 }; 2284 2285 /* detect primary codec */ 2286 chip->nr_ac97_codecs = 0; 2287 snd_printdd("snd_cs46xx: detecting primary codec\n"); 2288 if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0) 2289 return err; 2290 chip->ac97_bus->private_free = snd_cs46xx_mixer_free_ac97_bus; 2291 2292 if (cs46xx_detect_codec(chip, CS46XX_PRIMARY_CODEC_INDEX) < 0) 2293 return -ENXIO; 2294 chip->nr_ac97_codecs = 1; 2295 2296#ifdef CONFIG_SND_CS46XX_NEW_DSP 2297 snd_printdd("snd_cs46xx: detecting seconadry codec\n"); 2298 /* try detect a secondary codec */ 2299 if (! cs46xx_detect_codec(chip, CS46XX_SECONDARY_CODEC_INDEX)) 2300 chip->nr_ac97_codecs = 2; 2301#endif /* CONFIG_SND_CS46XX_NEW_DSP */ 2302 2303 /* add cs4630 mixer controls */ 2304 for (idx = 0; idx < ARRAY_SIZE(snd_cs46xx_controls); idx++) { 2305 struct snd_kcontrol *kctl; 2306 kctl = snd_ctl_new1(&snd_cs46xx_controls[idx], chip); 2307 if (kctl && kctl->id.iface == SNDRV_CTL_ELEM_IFACE_PCM) 2308 kctl->id.device = spdif_device; 2309 if ((err = snd_ctl_add(card, kctl)) < 0) 2310 return err; 2311 } 2312 2313 /* get EAPD mixer switch (for voyetra hack) */ 2314 memset(&id, 0, sizeof(id)); 2315 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 2316 strcpy(id.name, "External Amplifier"); 2317 chip->eapd_switch = snd_ctl_find_id(chip->card, &id); 2318 2319#ifdef CONFIG_SND_CS46XX_NEW_DSP 2320 if (chip->nr_ac97_codecs == 1) { 2321 unsigned int id2 = chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]->id & 0xffff; 2322 if (id2 == 0x592b || id2 == 0x592d) { 2323 err = snd_ctl_add(card, snd_ctl_new1(&snd_cs46xx_front_dup_ctl, chip)); 2324 if (err < 0) 2325 return err; 2326 snd_ac97_write_cache(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], 2327 AC97_CSR_ACMODE, 0x200); 2328 } 2329 } 2330 /* do soundcard specific mixer setup */ 2331 if (chip->mixer_init) { 2332 snd_printdd ("calling chip->mixer_init(chip);\n"); 2333 chip->mixer_init(chip); 2334 } 2335#endif 2336 2337 /* turn on amplifier */ 2338 chip->amplifier_ctrl(chip, 1); 2339 2340 return 0; 2341} 2342 2343/* 2344 * RawMIDI interface 2345 */ 2346 2347static void snd_cs46xx_midi_reset(struct snd_cs46xx *chip) 2348{ 2349 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, MIDCR_MRST); 2350 udelay(100); 2351 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2352} 2353 2354static int snd_cs46xx_midi_input_open(struct snd_rawmidi_substream *substream) 2355{ 2356 struct snd_cs46xx *chip = substream->rmidi->private_data; 2357 2358 chip->active_ctrl(chip, 1); 2359 spin_lock_irq(&chip->reg_lock); 2360 chip->uartm |= CS46XX_MODE_INPUT; 2361 chip->midcr |= MIDCR_RXE; 2362 chip->midi_input = substream; 2363 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) { 2364 snd_cs46xx_midi_reset(chip); 2365 } else { 2366 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2367 } 2368 spin_unlock_irq(&chip->reg_lock); 2369 return 0; 2370} 2371 2372static int snd_cs46xx_midi_input_close(struct snd_rawmidi_substream *substream) 2373{ 2374 struct snd_cs46xx *chip = substream->rmidi->private_data; 2375 2376 spin_lock_irq(&chip->reg_lock); 2377 chip->midcr &= ~(MIDCR_RXE | MIDCR_RIE); 2378 chip->midi_input = NULL; 2379 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) { 2380 snd_cs46xx_midi_reset(chip); 2381 } else { 2382 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2383 } 2384 chip->uartm &= ~CS46XX_MODE_INPUT; 2385 spin_unlock_irq(&chip->reg_lock); 2386 chip->active_ctrl(chip, -1); 2387 return 0; 2388} 2389 2390static int snd_cs46xx_midi_output_open(struct snd_rawmidi_substream *substream) 2391{ 2392 struct snd_cs46xx *chip = substream->rmidi->private_data; 2393 2394 chip->active_ctrl(chip, 1); 2395 2396 spin_lock_irq(&chip->reg_lock); 2397 chip->uartm |= CS46XX_MODE_OUTPUT; 2398 chip->midcr |= MIDCR_TXE; 2399 chip->midi_output = substream; 2400 if (!(chip->uartm & CS46XX_MODE_INPUT)) { 2401 snd_cs46xx_midi_reset(chip); 2402 } else { 2403 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2404 } 2405 spin_unlock_irq(&chip->reg_lock); 2406 return 0; 2407} 2408 2409static int snd_cs46xx_midi_output_close(struct snd_rawmidi_substream *substream) 2410{ 2411 struct snd_cs46xx *chip = substream->rmidi->private_data; 2412 2413 spin_lock_irq(&chip->reg_lock); 2414 chip->midcr &= ~(MIDCR_TXE | MIDCR_TIE); 2415 chip->midi_output = NULL; 2416 if (!(chip->uartm & CS46XX_MODE_INPUT)) { 2417 snd_cs46xx_midi_reset(chip); 2418 } else { 2419 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2420 } 2421 chip->uartm &= ~CS46XX_MODE_OUTPUT; 2422 spin_unlock_irq(&chip->reg_lock); 2423 chip->active_ctrl(chip, -1); 2424 return 0; 2425} 2426 2427static void snd_cs46xx_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) 2428{ 2429 unsigned long flags; 2430 struct snd_cs46xx *chip = substream->rmidi->private_data; 2431 2432 spin_lock_irqsave(&chip->reg_lock, flags); 2433 if (up) { 2434 if ((chip->midcr & MIDCR_RIE) == 0) { 2435 chip->midcr |= MIDCR_RIE; 2436 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2437 } 2438 } else { 2439 if (chip->midcr & MIDCR_RIE) { 2440 chip->midcr &= ~MIDCR_RIE; 2441 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2442 } 2443 } 2444 spin_unlock_irqrestore(&chip->reg_lock, flags); 2445} 2446 2447static void snd_cs46xx_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) 2448{ 2449 unsigned long flags; 2450 struct snd_cs46xx *chip = substream->rmidi->private_data; 2451 unsigned char byte; 2452 2453 spin_lock_irqsave(&chip->reg_lock, flags); 2454 if (up) { 2455 if ((chip->midcr & MIDCR_TIE) == 0) { 2456 chip->midcr |= MIDCR_TIE; 2457 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */ 2458 while ((chip->midcr & MIDCR_TIE) && 2459 (snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) { 2460 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) { 2461 chip->midcr &= ~MIDCR_TIE; 2462 } else { 2463 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, byte); 2464 } 2465 } 2466 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2467 } 2468 } else { 2469 if (chip->midcr & MIDCR_TIE) { 2470 chip->midcr &= ~MIDCR_TIE; 2471 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2472 } 2473 } 2474 spin_unlock_irqrestore(&chip->reg_lock, flags); 2475} 2476 2477static struct snd_rawmidi_ops snd_cs46xx_midi_output = 2478{ 2479 .open = snd_cs46xx_midi_output_open, 2480 .close = snd_cs46xx_midi_output_close, 2481 .trigger = snd_cs46xx_midi_output_trigger, 2482}; 2483 2484static struct snd_rawmidi_ops snd_cs46xx_midi_input = 2485{ 2486 .open = snd_cs46xx_midi_input_open, 2487 .close = snd_cs46xx_midi_input_close, 2488 .trigger = snd_cs46xx_midi_input_trigger, 2489}; 2490 2491int __devinit snd_cs46xx_midi(struct snd_cs46xx *chip, int device, struct snd_rawmidi **rrawmidi) 2492{ 2493 struct snd_rawmidi *rmidi; 2494 int err; 2495 2496 if (rrawmidi) 2497 *rrawmidi = NULL; 2498 if ((err = snd_rawmidi_new(chip->card, "CS46XX", device, 1, 1, &rmidi)) < 0) 2499 return err; 2500 strcpy(rmidi->name, "CS46XX"); 2501 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs46xx_midi_output); 2502 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs46xx_midi_input); 2503 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX; 2504 rmidi->private_data = chip; 2505 chip->rmidi = rmidi; 2506 if (rrawmidi) 2507 *rrawmidi = NULL; 2508 return 0; 2509} 2510 2511 2512/* 2513 * gameport interface 2514 */ 2515 2516#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE)) 2517 2518static void snd_cs46xx_gameport_trigger(struct gameport *gameport) 2519{ 2520 struct snd_cs46xx *chip = gameport_get_port_data(gameport); 2521 2522 if (snd_BUG_ON(!chip)) 2523 return; 2524 snd_cs46xx_pokeBA0(chip, BA0_JSPT, 0xFF); //outb(gameport->io, 0xFF); 2525} 2526 2527static unsigned char snd_cs46xx_gameport_read(struct gameport *gameport) 2528{ 2529 struct snd_cs46xx *chip = gameport_get_port_data(gameport); 2530 2531 if (snd_BUG_ON(!chip)) 2532 return 0; 2533 return snd_cs46xx_peekBA0(chip, BA0_JSPT); //inb(gameport->io); 2534} 2535 2536static int snd_cs46xx_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons) 2537{ 2538 struct snd_cs46xx *chip = gameport_get_port_data(gameport); 2539 unsigned js1, js2, jst; 2540 2541 if (snd_BUG_ON(!chip)) 2542 return 0; 2543 2544 js1 = snd_cs46xx_peekBA0(chip, BA0_JSC1); 2545 js2 = snd_cs46xx_peekBA0(chip, BA0_JSC2); 2546 jst = snd_cs46xx_peekBA0(chip, BA0_JSPT); 2547 2548 *buttons = (~jst >> 4) & 0x0F; 2549 2550 axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF; 2551 axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF; 2552 axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF; 2553 axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF; 2554 2555 for(jst=0;jst<4;++jst) 2556 if(axes[jst]==0xFFFF) axes[jst] = -1; 2557 return 0; 2558} 2559 2560static int snd_cs46xx_gameport_open(struct gameport *gameport, int mode) 2561{ 2562 switch (mode) { 2563 case GAMEPORT_MODE_COOKED: 2564 return 0; 2565 case GAMEPORT_MODE_RAW: 2566 return 0; 2567 default: 2568 return -1; 2569 } 2570 return 0; 2571} 2572 2573int __devinit snd_cs46xx_gameport(struct snd_cs46xx *chip) 2574{ 2575 struct gameport *gp; 2576 2577 chip->gameport = gp = gameport_allocate_port(); 2578 if (!gp) { 2579 printk(KERN_ERR "cs46xx: cannot allocate memory for gameport\n"); 2580 return -ENOMEM; 2581 } 2582 2583 gameport_set_name(gp, "CS46xx Gameport"); 2584 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci)); 2585 gameport_set_dev_parent(gp, &chip->pci->dev); 2586 gameport_set_port_data(gp, chip); 2587 2588 gp->open = snd_cs46xx_gameport_open; 2589 gp->read = snd_cs46xx_gameport_read; 2590 gp->trigger = snd_cs46xx_gameport_trigger; 2591 gp->cooked_read = snd_cs46xx_gameport_cooked_read; 2592 2593 snd_cs46xx_pokeBA0(chip, BA0_JSIO, 0xFF); // ? 2594 snd_cs46xx_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW); 2595 2596 gameport_register_port(gp); 2597 2598 return 0; 2599} 2600 2601static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip) 2602{ 2603 if (chip->gameport) { 2604 gameport_unregister_port(chip->gameport); 2605 chip->gameport = NULL; 2606 } 2607} 2608#else 2609int __devinit snd_cs46xx_gameport(struct snd_cs46xx *chip) { return -ENOSYS; } 2610static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip) { } 2611#endif /* CONFIG_GAMEPORT */ 2612 2613#ifdef CONFIG_PROC_FS 2614/* 2615 * proc interface 2616 */ 2617 2618static ssize_t snd_cs46xx_io_read(struct snd_info_entry *entry, 2619 void *file_private_data, 2620 struct file *file, char __user *buf, 2621 size_t count, loff_t pos) 2622{ 2623 struct snd_cs46xx_region *region = entry->private_data; 2624 2625 if (copy_to_user_fromio(buf, region->remap_addr + pos, count)) 2626 return -EFAULT; 2627 return count; 2628} 2629 2630static struct snd_info_entry_ops snd_cs46xx_proc_io_ops = { 2631 .read = snd_cs46xx_io_read, 2632}; 2633 2634static int __devinit snd_cs46xx_proc_init(struct snd_card *card, struct snd_cs46xx *chip) 2635{ 2636 struct snd_info_entry *entry; 2637 int idx; 2638 2639 for (idx = 0; idx < 5; idx++) { 2640 struct snd_cs46xx_region *region = &chip->region.idx[idx]; 2641 if (! snd_card_proc_new(card, region->name, &entry)) { 2642 entry->content = SNDRV_INFO_CONTENT_DATA; 2643 entry->private_data = chip; 2644 entry->c.ops = &snd_cs46xx_proc_io_ops; 2645 entry->size = region->size; 2646 entry->mode = S_IFREG | S_IRUSR; 2647 } 2648 } 2649#ifdef CONFIG_SND_CS46XX_NEW_DSP 2650 cs46xx_dsp_proc_init(card, chip); 2651#endif 2652 return 0; 2653} 2654 2655static int snd_cs46xx_proc_done(struct snd_cs46xx *chip) 2656{ 2657#ifdef CONFIG_SND_CS46XX_NEW_DSP 2658 cs46xx_dsp_proc_done(chip); 2659#endif 2660 return 0; 2661} 2662#else /* !CONFIG_PROC_FS */ 2663#define snd_cs46xx_proc_init(card, chip) 2664#define snd_cs46xx_proc_done(chip) 2665#endif 2666 2667/* 2668 * stop the h/w 2669 */ 2670static void snd_cs46xx_hw_stop(struct snd_cs46xx *chip) 2671{ 2672 unsigned int tmp; 2673 2674 tmp = snd_cs46xx_peek(chip, BA1_PFIE); 2675 tmp &= ~0x0000f03f; 2676 tmp |= 0x00000010; 2677 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt disable */ 2678 2679 tmp = snd_cs46xx_peek(chip, BA1_CIE); 2680 tmp &= ~0x0000003f; 2681 tmp |= 0x00000011; 2682 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt disable */ 2683 2684 /* 2685 * Stop playback DMA. 2686 */ 2687 tmp = snd_cs46xx_peek(chip, BA1_PCTL); 2688 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff); 2689 2690 /* 2691 * Stop capture DMA. 2692 */ 2693 tmp = snd_cs46xx_peek(chip, BA1_CCTL); 2694 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000); 2695 2696 /* 2697 * Reset the processor. 2698 */ 2699 snd_cs46xx_reset(chip); 2700 2701 snd_cs46xx_proc_stop(chip); 2702 2703 /* 2704 * Power down the PLL. 2705 */ 2706 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0); 2707 2708 /* 2709 * Turn off the Processor by turning off the software clock enable flag in 2710 * the clock control register. 2711 */ 2712 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; 2713 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); 2714} 2715 2716 2717static int snd_cs46xx_free(struct snd_cs46xx *chip) 2718{ 2719 int idx; 2720 2721 if (snd_BUG_ON(!chip)) 2722 return -EINVAL; 2723 2724 if (chip->active_ctrl) 2725 chip->active_ctrl(chip, 1); 2726 2727 snd_cs46xx_remove_gameport(chip); 2728 2729 if (chip->amplifier_ctrl) 2730 chip->amplifier_ctrl(chip, -chip->amplifier); /* force to off */ 2731 2732 snd_cs46xx_proc_done(chip); 2733 2734 if (chip->region.idx[0].resource) 2735 snd_cs46xx_hw_stop(chip); 2736 2737 if (chip->irq >= 0) 2738 free_irq(chip->irq, chip); 2739 2740 if (chip->active_ctrl) 2741 chip->active_ctrl(chip, -chip->amplifier); 2742 2743 for (idx = 0; idx < 5; idx++) { 2744 struct snd_cs46xx_region *region = &chip->region.idx[idx]; 2745 if (region->remap_addr) 2746 iounmap(region->remap_addr); 2747 release_and_free_resource(region->resource); 2748 } 2749 2750#ifdef CONFIG_SND_CS46XX_NEW_DSP 2751 if (chip->dsp_spos_instance) { 2752 cs46xx_dsp_spos_destroy(chip); 2753 chip->dsp_spos_instance = NULL; 2754 } 2755#endif 2756 2757#ifdef CONFIG_PM 2758 kfree(chip->saved_regs); 2759#endif 2760 2761 pci_disable_device(chip->pci); 2762 kfree(chip); 2763 return 0; 2764} 2765 2766static int snd_cs46xx_dev_free(struct snd_device *device) 2767{ 2768 struct snd_cs46xx *chip = device->device_data; 2769 return snd_cs46xx_free(chip); 2770} 2771 2772/* 2773 * initialize chip 2774 */ 2775static int snd_cs46xx_chip_init(struct snd_cs46xx *chip) 2776{ 2777 int timeout; 2778 2779 /* 2780 * First, blast the clock control register to zero so that the PLL starts 2781 * out in a known state, and blast the master serial port control register 2782 * to zero so that the serial ports also start out in a known state. 2783 */ 2784 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0); 2785 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, 0); 2786 2787 /* 2788 * If we are in AC97 mode, then we must set the part to a host controlled 2789 * AC-link. Otherwise, we won't be able to bring up the link. 2790 */ 2791#ifdef CONFIG_SND_CS46XX_NEW_DSP 2792 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0 | 2793 SERACC_TWO_CODECS); /* 2.00 dual codecs */ 2794 /* snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0); */ /* 2.00 codec */ 2795#else 2796 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_1_03); /* 1.03 codec */ 2797#endif 2798 2799 /* 2800 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97 2801 * spec) and then drive it high. This is done for non AC97 modes since 2802 * there might be logic external to the CS461x that uses the ARST# line 2803 * for a reset. 2804 */ 2805 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, 0); 2806#ifdef CONFIG_SND_CS46XX_NEW_DSP 2807 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, 0); 2808#endif 2809 udelay(50); 2810 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_RSTN); 2811#ifdef CONFIG_SND_CS46XX_NEW_DSP 2812 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_RSTN); 2813#endif 2814 2815 /* 2816 * The first thing we do here is to enable sync generation. As soon 2817 * as we start receiving bit clock, we'll start producing the SYNC 2818 * signal. 2819 */ 2820 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 2821#ifdef CONFIG_SND_CS46XX_NEW_DSP 2822 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_ESYN | ACCTL_RSTN); 2823#endif 2824 2825 /* 2826 * Now wait for a short while to allow the AC97 part to start 2827 * generating bit clock (so we don't try to start the PLL without an 2828 * input clock). 2829 */ 2830 mdelay(10); 2831 2832 /* 2833 * Set the serial port timing configuration, so that 2834 * the clock control circuit gets its clock from the correct place. 2835 */ 2836 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97); 2837 2838 /* 2839 * Write the selected clock control setup to the hardware. Do not turn on 2840 * SWCE yet (if requested), so that the devices clocked by the output of 2841 * PLL are not clocked until the PLL is stable. 2842 */ 2843 snd_cs46xx_pokeBA0(chip, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ); 2844 snd_cs46xx_pokeBA0(chip, BA0_PLLM, 0x3a); 2845 snd_cs46xx_pokeBA0(chip, BA0_CLKCR2, CLKCR2_PDIVS_8); 2846 2847 /* 2848 * Power up the PLL. 2849 */ 2850 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP); 2851 2852 /* 2853 * Wait until the PLL has stabilized. 2854 */ 2855 msleep(100); 2856 2857 /* 2858 * Turn on clocking of the core so that we can setup the serial ports. 2859 */ 2860 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP | CLKCR1_SWCE); 2861 2862 /* 2863 * Enable FIFO Host Bypass 2864 */ 2865 snd_cs46xx_pokeBA0(chip, BA0_SERBCF, SERBCF_HBP); 2866 2867 /* 2868 * Fill the serial port FIFOs with silence. 2869 */ 2870 snd_cs46xx_clear_serial_FIFOs(chip); 2871 2872 /* 2873 * Set the serial port FIFO pointer to the first sample in the FIFO. 2874 */ 2875 /* snd_cs46xx_pokeBA0(chip, BA0_SERBSP, 0); */ 2876 2877 /* 2878 * Write the serial port configuration to the part. The master 2879 * enable bit is not set until all other values have been written. 2880 */ 2881 snd_cs46xx_pokeBA0(chip, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN); 2882 snd_cs46xx_pokeBA0(chip, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN); 2883 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE); 2884 2885 2886#ifdef CONFIG_SND_CS46XX_NEW_DSP 2887 snd_cs46xx_pokeBA0(chip, BA0_SERC7, SERC7_ASDI2EN); 2888 snd_cs46xx_pokeBA0(chip, BA0_SERC3, 0); 2889 snd_cs46xx_pokeBA0(chip, BA0_SERC4, 0); 2890 snd_cs46xx_pokeBA0(chip, BA0_SERC5, 0); 2891 snd_cs46xx_pokeBA0(chip, BA0_SERC6, 1); 2892#endif 2893 2894 mdelay(5); 2895 2896 2897 /* 2898 * Wait for the codec ready signal from the AC97 codec. 2899 */ 2900 timeout = 150; 2901 while (timeout-- > 0) { 2902 /* 2903 * Read the AC97 status register to see if we've seen a CODEC READY 2904 * signal from the AC97 codec. 2905 */ 2906 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY) 2907 goto ok1; 2908 msleep(10); 2909 } 2910 2911 2912 snd_printk(KERN_ERR "create - never read codec ready from AC'97\n"); 2913 snd_printk(KERN_ERR "it is not probably bug, try to use CS4236 driver\n"); 2914 return -EIO; 2915 ok1: 2916#ifdef CONFIG_SND_CS46XX_NEW_DSP 2917 { 2918 int count; 2919 for (count = 0; count < 150; count++) { 2920 /* First, we want to wait for a short time. */ 2921 udelay(25); 2922 2923 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY) 2924 break; 2925 } 2926 2927 /* 2928 * Make sure CODEC is READY. 2929 */ 2930 if (!(snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY)) 2931 snd_printdd("cs46xx: never read card ready from secondary AC'97\n"); 2932 } 2933#endif 2934 2935 /* 2936 * Assert the vaid frame signal so that we can start sending commands 2937 * to the AC97 codec. 2938 */ 2939 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 2940#ifdef CONFIG_SND_CS46XX_NEW_DSP 2941 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 2942#endif 2943 2944 2945 /* 2946 * Wait until we've sampled input slots 3 and 4 as valid, meaning that 2947 * the codec is pumping ADC data across the AC-link. 2948 */ 2949 timeout = 150; 2950 while (timeout-- > 0) { 2951 /* 2952 * Read the input slot valid register and see if input slots 3 and 2953 * 4 are valid yet. 2954 */ 2955 if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4)) 2956 goto ok2; 2957 msleep(10); 2958 } 2959 2960#ifndef CONFIG_SND_CS46XX_NEW_DSP 2961 snd_printk(KERN_ERR "create - never read ISV3 & ISV4 from AC'97\n"); 2962 return -EIO; 2963#else 2964 /* This may happen on a cold boot with a Terratec SiXPack 5.1. 2965 Reloading the driver may help, if there's other soundcards 2966 with the same problem I would like to know. (Benny) */ 2967 2968 snd_printk(KERN_ERR "ERROR: snd-cs46xx: never read ISV3 & ISV4 from AC'97\n"); 2969 snd_printk(KERN_ERR " Try reloading the ALSA driver, if you find something\n"); 2970 snd_printk(KERN_ERR " broken or not working on your soundcard upon\n"); 2971 snd_printk(KERN_ERR " this message please report to alsa-devel@alsa-project.org\n"); 2972 2973 return -EIO; 2974#endif 2975 ok2: 2976 2977 /* 2978 * Now, assert valid frame and the slot 3 and 4 valid bits. This will 2979 * commense the transfer of digital audio data to the AC97 codec. 2980 */ 2981 2982 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 2983 2984 2985 /* 2986 * Power down the DAC and ADC. We will power them up (if) when we need 2987 * them. 2988 */ 2989 /* snd_cs46xx_pokeBA0(chip, BA0_AC97_POWERDOWN, 0x300); */ 2990 2991 /* 2992 * Turn off the Processor by turning off the software clock enable flag in 2993 * the clock control register. 2994 */ 2995 /* tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; */ 2996 /* snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); */ 2997 2998 return 0; 2999} 3000 3001/* 3002 * start and load DSP 3003 */ 3004 3005static void cs46xx_enable_stream_irqs(struct snd_cs46xx *chip) 3006{ 3007 unsigned int tmp; 3008 3009 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_IEV | HICR_CHGM); 3010 3011 tmp = snd_cs46xx_peek(chip, BA1_PFIE); 3012 tmp &= ~0x0000f03f; 3013 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt enable */ 3014 3015 tmp = snd_cs46xx_peek(chip, BA1_CIE); 3016 tmp &= ~0x0000003f; 3017 tmp |= 0x00000001; 3018 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt enable */ 3019} 3020 3021int __devinit snd_cs46xx_start_dsp(struct snd_cs46xx *chip) 3022{ 3023 unsigned int tmp; 3024 /* 3025 * Reset the processor. 3026 */ 3027 snd_cs46xx_reset(chip); 3028 /* 3029 * Download the image to the processor. 3030 */ 3031#ifdef CONFIG_SND_CS46XX_NEW_DSP 3032 3033 if (cs46xx_dsp_load_module(chip, &cwc4630_module) < 0) { 3034 snd_printk(KERN_ERR "image download error [cwc4630]\n"); 3035 return -EIO; 3036 } 3037 3038 if (cs46xx_dsp_load_module(chip, &cwcasync_module) < 0) { 3039 snd_printk(KERN_ERR "image download error [cwcasync]\n"); 3040 return -EIO; 3041 } 3042 3043 if (cs46xx_dsp_load_module(chip, &cwcsnoop_module) < 0) { 3044 snd_printk(KERN_ERR "image download error [cwcsnoop]\n"); 3045 return -EIO; 3046 } 3047 3048 if (cs46xx_dsp_load_module(chip, &cwcbinhack_module) < 0) { 3049 snd_printk(KERN_ERR "image download error [cwcbinhack]\n"); 3050 return -EIO; 3051 } 3052 3053 if (cs46xx_dsp_load_module(chip, &cwcdma_module) < 0) { 3054 snd_printk(KERN_ERR "image download error [cwcdma]\n"); 3055 return -EIO; 3056 } 3057 3058 if (cs46xx_dsp_scb_and_task_init(chip) < 0) 3059 return -EIO; 3060#else 3061 /* old image */ 3062 if (snd_cs46xx_download_image(chip) < 0) { 3063 snd_printk(KERN_ERR "image download error\n"); 3064 return -EIO; 3065 } 3066 3067 /* 3068 * Stop playback DMA. 3069 */ 3070 tmp = snd_cs46xx_peek(chip, BA1_PCTL); 3071 chip->play_ctl = tmp & 0xffff0000; 3072 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff); 3073#endif 3074 3075 /* 3076 * Stop capture DMA. 3077 */ 3078 tmp = snd_cs46xx_peek(chip, BA1_CCTL); 3079 chip->capt.ctl = tmp & 0x0000ffff; 3080 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000); 3081 3082 mdelay(5); 3083 3084 snd_cs46xx_set_play_sample_rate(chip, 8000); 3085 snd_cs46xx_set_capture_sample_rate(chip, 8000); 3086 3087 snd_cs46xx_proc_start(chip); 3088 3089 cs46xx_enable_stream_irqs(chip); 3090 3091#ifndef CONFIG_SND_CS46XX_NEW_DSP 3092 /* set the attenuation to 0dB */ 3093 snd_cs46xx_poke(chip, BA1_PVOL, 0x80008000); 3094 snd_cs46xx_poke(chip, BA1_CVOL, 0x80008000); 3095#endif 3096 3097 return 0; 3098} 3099 3100 3101/* 3102 * AMP control - null AMP 3103 */ 3104 3105static void amp_none(struct snd_cs46xx *chip, int change) 3106{ 3107} 3108 3109#ifdef CONFIG_SND_CS46XX_NEW_DSP 3110static int voyetra_setup_eapd_slot(struct snd_cs46xx *chip) 3111{ 3112 3113 u32 idx, valid_slots,tmp,powerdown = 0; 3114 u16 modem_power,pin_config,logic_type; 3115 3116 snd_printdd ("cs46xx: cs46xx_setup_eapd_slot()+\n"); 3117 3118 /* 3119 * See if the devices are powered down. If so, we must power them up first 3120 * or they will not respond. 3121 */ 3122 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1); 3123 3124 if (!(tmp & CLKCR1_SWCE)) { 3125 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE); 3126 powerdown = 1; 3127 } 3128 3129 /* 3130 * Clear PRA. The Bonzo chip will be used for GPIO not for modem 3131 * stuff. 3132 */ 3133 if(chip->nr_ac97_codecs != 2) { 3134 snd_printk (KERN_ERR "cs46xx: cs46xx_setup_eapd_slot() - no secondary codec configured\n"); 3135 return -EINVAL; 3136 } 3137 3138 modem_power = snd_cs46xx_codec_read (chip, 3139 AC97_EXTENDED_MSTATUS, 3140 CS46XX_SECONDARY_CODEC_INDEX); 3141 modem_power &=0xFEFF; 3142 3143 snd_cs46xx_codec_write(chip, 3144 AC97_EXTENDED_MSTATUS, modem_power, 3145 CS46XX_SECONDARY_CODEC_INDEX); 3146 3147 /* 3148 * Set GPIO pin's 7 and 8 so that they are configured for output. 3149 */ 3150 pin_config = snd_cs46xx_codec_read (chip, 3151 AC97_GPIO_CFG, 3152 CS46XX_SECONDARY_CODEC_INDEX); 3153 pin_config &=0x27F; 3154 3155 snd_cs46xx_codec_write(chip, 3156 AC97_GPIO_CFG, pin_config, 3157 CS46XX_SECONDARY_CODEC_INDEX); 3158 3159 /* 3160 * Set GPIO pin's 7 and 8 so that they are compatible with CMOS logic. 3161 */ 3162 3163 logic_type = snd_cs46xx_codec_read(chip, AC97_GPIO_POLARITY, 3164 CS46XX_SECONDARY_CODEC_INDEX); 3165 logic_type &=0x27F; 3166 3167 snd_cs46xx_codec_write (chip, AC97_GPIO_POLARITY, logic_type, 3168 CS46XX_SECONDARY_CODEC_INDEX); 3169 3170 valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV); 3171 valid_slots |= 0x200; 3172 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots); 3173 3174 if ( cs46xx_wait_for_fifo(chip,1) ) { 3175 snd_printdd("FIFO is busy\n"); 3176 3177 return -EINVAL; 3178 } 3179 3180 /* 3181 * Fill slots 12 with the correct value for the GPIO pins. 3182 */ 3183 for(idx = 0x90; idx <= 0x9F; idx++) { 3184 /* 3185 * Initialize the fifo so that bits 7 and 8 are on. 3186 * 3187 * Remember that the GPIO pins in bonzo are shifted by 4 bits to 3188 * the left. 0x1800 corresponds to bits 7 and 8. 3189 */ 3190 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0x1800); 3191 3192 /* 3193 * Wait for command to complete 3194 */ 3195 if ( cs46xx_wait_for_fifo(chip,200) ) { 3196 snd_printdd("failed waiting for FIFO at addr (%02X)\n",idx); 3197 3198 return -EINVAL; 3199 } 3200 3201 /* 3202 * Write the serial port FIFO index. 3203 */ 3204 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx); 3205 3206 /* 3207 * Tell the serial port to load the new value into the FIFO location. 3208 */ 3209 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC); 3210 } 3211 3212 /* wait for last command to complete */ 3213 cs46xx_wait_for_fifo(chip,200); 3214 3215 /* 3216 * Now, if we powered up the devices, then power them back down again. 3217 * This is kinda ugly, but should never happen. 3218 */ 3219 if (powerdown) 3220 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); 3221 3222 return 0; 3223} 3224#endif 3225 3226/* 3227 * Crystal EAPD mode 3228 */ 3229 3230static void amp_voyetra(struct snd_cs46xx *chip, int change) 3231{ 3232 /* Manage the EAPD bit on the Crystal 4297 3233 and the Analog AD1885 */ 3234 3235#ifdef CONFIG_SND_CS46XX_NEW_DSP 3236 int old = chip->amplifier; 3237#endif 3238 int oval, val; 3239 3240 chip->amplifier += change; 3241 oval = snd_cs46xx_codec_read(chip, AC97_POWERDOWN, 3242 CS46XX_PRIMARY_CODEC_INDEX); 3243 val = oval; 3244 if (chip->amplifier) { 3245 /* Turn the EAPD amp on */ 3246 val |= 0x8000; 3247 } else { 3248 /* Turn the EAPD amp off */ 3249 val &= ~0x8000; 3250 } 3251 if (val != oval) { 3252 snd_cs46xx_codec_write(chip, AC97_POWERDOWN, val, 3253 CS46XX_PRIMARY_CODEC_INDEX); 3254 if (chip->eapd_switch) 3255 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, 3256 &chip->eapd_switch->id); 3257 } 3258 3259#ifdef CONFIG_SND_CS46XX_NEW_DSP 3260 if (chip->amplifier && !old) { 3261 voyetra_setup_eapd_slot(chip); 3262 } 3263#endif 3264} 3265 3266static void hercules_init(struct snd_cs46xx *chip) 3267{ 3268 /* default: AMP off, and SPDIF input optical */ 3269 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0); 3270 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0); 3271} 3272 3273 3274/* 3275 * Game Theatre XP card - EGPIO[2] is used to enable the external amp. 3276 */ 3277static void amp_hercules(struct snd_cs46xx *chip, int change) 3278{ 3279 int old = chip->amplifier; 3280 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR); 3281 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR); 3282 3283 chip->amplifier += change; 3284 if (chip->amplifier && !old) { 3285 snd_printdd ("Hercules amplifier ON\n"); 3286 3287 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, 3288 EGPIODR_GPOE2 | val1); /* enable EGPIO2 output */ 3289 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, 3290 EGPIOPTR_GPPT2 | val2); /* open-drain on output */ 3291 } else if (old && !chip->amplifier) { 3292 snd_printdd ("Hercules amplifier OFF\n"); 3293 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE2); /* disable */ 3294 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT2); /* disable */ 3295 } 3296} 3297 3298static void voyetra_mixer_init (struct snd_cs46xx *chip) 3299{ 3300 snd_printdd ("initializing Voyetra mixer\n"); 3301 3302 /* Enable SPDIF out */ 3303 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0); 3304 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0); 3305} 3306 3307static void hercules_mixer_init (struct snd_cs46xx *chip) 3308{ 3309#ifdef CONFIG_SND_CS46XX_NEW_DSP 3310 unsigned int idx; 3311 int err; 3312 struct snd_card *card = chip->card; 3313#endif 3314 3315 /* set EGPIO to default */ 3316 hercules_init(chip); 3317 3318 snd_printdd ("initializing Hercules mixer\n"); 3319 3320#ifdef CONFIG_SND_CS46XX_NEW_DSP 3321 if (chip->in_suspend) 3322 return; 3323 3324 for (idx = 0 ; idx < ARRAY_SIZE(snd_hercules_controls); idx++) { 3325 struct snd_kcontrol *kctl; 3326 3327 kctl = snd_ctl_new1(&snd_hercules_controls[idx], chip); 3328 if ((err = snd_ctl_add(card, kctl)) < 0) { 3329 printk (KERN_ERR "cs46xx: failed to initialize Hercules mixer (%d)\n",err); 3330 break; 3331 } 3332 } 3333#endif 3334} 3335 3336 3337 3338 3339/* 3340 * Handle the CLKRUN on a thinkpad. We must disable CLKRUN support 3341 * whenever we need to beat on the chip. 3342 * 3343 * The original idea and code for this hack comes from David Kaiser at 3344 * Linuxcare. Perhaps one day Crystal will document their chips well 3345 * enough to make them useful. 3346 */ 3347 3348static void clkrun_hack(struct snd_cs46xx *chip, int change) 3349{ 3350 u16 control, nval; 3351 3352 if (!chip->acpi_port) 3353 return; 3354 3355 chip->amplifier += change; 3356 3357 /* Read ACPI port */ 3358 nval = control = inw(chip->acpi_port + 0x10); 3359 3360 /* Flip CLKRUN off while running */ 3361 if (! chip->amplifier) 3362 nval |= 0x2000; 3363 else 3364 nval &= ~0x2000; 3365 if (nval != control) 3366 outw(nval, chip->acpi_port + 0x10); 3367} 3368 3369 3370/* 3371 * detect intel piix4 3372 */ 3373static void clkrun_init(struct snd_cs46xx *chip) 3374{ 3375 struct pci_dev *pdev; 3376 u8 pp; 3377 3378 chip->acpi_port = 0; 3379 3380 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 3381 PCI_DEVICE_ID_INTEL_82371AB_3, NULL); 3382 if (pdev == NULL) 3383 return; /* Not a thinkpad thats for sure */ 3384 3385 /* Find the control port */ 3386 pci_read_config_byte(pdev, 0x41, &pp); 3387 chip->acpi_port = pp << 8; 3388 pci_dev_put(pdev); 3389} 3390 3391 3392/* 3393 * Card subid table 3394 */ 3395 3396struct cs_card_type 3397{ 3398 u16 vendor; 3399 u16 id; 3400 char *name; 3401 void (*init)(struct snd_cs46xx *); 3402 void (*amp)(struct snd_cs46xx *, int); 3403 void (*active)(struct snd_cs46xx *, int); 3404 void (*mixer_init)(struct snd_cs46xx *); 3405}; 3406 3407static struct cs_card_type __devinitdata cards[] = { 3408 { 3409 .vendor = 0x1489, 3410 .id = 0x7001, 3411 .name = "Genius Soundmaker 128 value", 3412 /* nothing special */ 3413 }, 3414 { 3415 .vendor = 0x5053, 3416 .id = 0x3357, 3417 .name = "Voyetra", 3418 .amp = amp_voyetra, 3419 .mixer_init = voyetra_mixer_init, 3420 }, 3421 { 3422 .vendor = 0x1071, 3423 .id = 0x6003, 3424 .name = "Mitac MI6020/21", 3425 .amp = amp_voyetra, 3426 }, 3427 /* Hercules Game Theatre XP */ 3428 { 3429 .vendor = 0x14af, /* Guillemot Corporation */ 3430 .id = 0x0050, 3431 .name = "Hercules Game Theatre XP", 3432 .amp = amp_hercules, 3433 .mixer_init = hercules_mixer_init, 3434 }, 3435 { 3436 .vendor = 0x1681, 3437 .id = 0x0050, 3438 .name = "Hercules Game Theatre XP", 3439 .amp = amp_hercules, 3440 .mixer_init = hercules_mixer_init, 3441 }, 3442 { 3443 .vendor = 0x1681, 3444 .id = 0x0051, 3445 .name = "Hercules Game Theatre XP", 3446 .amp = amp_hercules, 3447 .mixer_init = hercules_mixer_init, 3448 3449 }, 3450 { 3451 .vendor = 0x1681, 3452 .id = 0x0052, 3453 .name = "Hercules Game Theatre XP", 3454 .amp = amp_hercules, 3455 .mixer_init = hercules_mixer_init, 3456 }, 3457 { 3458 .vendor = 0x1681, 3459 .id = 0x0053, 3460 .name = "Hercules Game Theatre XP", 3461 .amp = amp_hercules, 3462 .mixer_init = hercules_mixer_init, 3463 }, 3464 { 3465 .vendor = 0x1681, 3466 .id = 0x0054, 3467 .name = "Hercules Game Theatre XP", 3468 .amp = amp_hercules, 3469 .mixer_init = hercules_mixer_init, 3470 }, 3471 /* Herculess Fortissimo */ 3472 { 3473 .vendor = 0x1681, 3474 .id = 0xa010, 3475 .name = "Hercules Gamesurround Fortissimo II", 3476 }, 3477 { 3478 .vendor = 0x1681, 3479 .id = 0xa011, 3480 .name = "Hercules Gamesurround Fortissimo III 7.1", 3481 }, 3482 /* Teratec */ 3483 { 3484 .vendor = 0x153b, 3485 .id = 0x112e, 3486 .name = "Terratec DMX XFire 1024", 3487 }, 3488 { 3489 .vendor = 0x153b, 3490 .id = 0x1136, 3491 .name = "Terratec SiXPack 5.1", 3492 }, 3493 /* Not sure if the 570 needs the clkrun hack */ 3494 { 3495 .vendor = PCI_VENDOR_ID_IBM, 3496 .id = 0x0132, 3497 .name = "Thinkpad 570", 3498 .init = clkrun_init, 3499 .active = clkrun_hack, 3500 }, 3501 { 3502 .vendor = PCI_VENDOR_ID_IBM, 3503 .id = 0x0153, 3504 .name = "Thinkpad 600X/A20/T20", 3505 .init = clkrun_init, 3506 .active = clkrun_hack, 3507 }, 3508 { 3509 .vendor = PCI_VENDOR_ID_IBM, 3510 .id = 0x1010, 3511 .name = "Thinkpad 600E (unsupported)", 3512 }, 3513 {} /* terminator */ 3514}; 3515 3516 3517/* 3518 * APM support 3519 */ 3520#ifdef CONFIG_PM 3521static unsigned int saved_regs[] = { 3522 BA0_ACOSV, 3523 /*BA0_ASER_FADDR,*/ 3524 BA0_ASER_MASTER, 3525 BA1_PVOL, 3526 BA1_CVOL, 3527}; 3528 3529int snd_cs46xx_suspend(struct pci_dev *pci, pm_message_t state) 3530{ 3531 struct snd_card *card = pci_get_drvdata(pci); 3532 struct snd_cs46xx *chip = card->private_data; 3533 int i, amp_saved; 3534 3535 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 3536 chip->in_suspend = 1; 3537 snd_pcm_suspend_all(chip->pcm); 3538 // chip->ac97_powerdown = snd_cs46xx_codec_read(chip, AC97_POWER_CONTROL); 3539 // chip->ac97_general_purpose = snd_cs46xx_codec_read(chip, BA0_AC97_GENERAL_PURPOSE); 3540 3541 snd_ac97_suspend(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]); 3542 snd_ac97_suspend(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]); 3543 3544 /* save some registers */ 3545 for (i = 0; i < ARRAY_SIZE(saved_regs); i++) 3546 chip->saved_regs[i] = snd_cs46xx_peekBA0(chip, saved_regs[i]); 3547 3548 amp_saved = chip->amplifier; 3549 /* turn off amp */ 3550 chip->amplifier_ctrl(chip, -chip->amplifier); 3551 snd_cs46xx_hw_stop(chip); 3552 /* disable CLKRUN */ 3553 chip->active_ctrl(chip, -chip->amplifier); 3554 chip->amplifier = amp_saved; /* restore the status */ 3555 3556 pci_disable_device(pci); 3557 pci_save_state(pci); 3558 pci_set_power_state(pci, pci_choose_state(pci, state)); 3559 return 0; 3560} 3561 3562int snd_cs46xx_resume(struct pci_dev *pci) 3563{ 3564 struct snd_card *card = pci_get_drvdata(pci); 3565 struct snd_cs46xx *chip = card->private_data; 3566 int amp_saved; 3567#ifdef CONFIG_SND_CS46XX_NEW_DSP 3568 int i; 3569#endif 3570 unsigned int tmp; 3571 3572 pci_set_power_state(pci, PCI_D0); 3573 pci_restore_state(pci); 3574 if (pci_enable_device(pci) < 0) { 3575 printk(KERN_ERR "cs46xx: pci_enable_device failed, " 3576 "disabling device\n"); 3577 snd_card_disconnect(card); 3578 return -EIO; 3579 } 3580 pci_set_master(pci); 3581 3582 amp_saved = chip->amplifier; 3583 chip->amplifier = 0; 3584 chip->active_ctrl(chip, 1); /* force to on */ 3585 3586 snd_cs46xx_chip_init(chip); 3587 3588 snd_cs46xx_reset(chip); 3589#ifdef CONFIG_SND_CS46XX_NEW_DSP 3590 cs46xx_dsp_resume(chip); 3591 /* restore some registers */ 3592 for (i = 0; i < ARRAY_SIZE(saved_regs); i++) 3593 snd_cs46xx_pokeBA0(chip, saved_regs[i], chip->saved_regs[i]); 3594#else 3595 snd_cs46xx_download_image(chip); 3596#endif 3597 3598 3599 snd_ac97_resume(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]); 3600 snd_ac97_resume(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]); 3601 3602 /* 3603 * Stop capture DMA. 3604 */ 3605 tmp = snd_cs46xx_peek(chip, BA1_CCTL); 3606 chip->capt.ctl = tmp & 0x0000ffff; 3607 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000); 3608 3609 mdelay(5); 3610 3611 /* reset playback/capture */ 3612 snd_cs46xx_set_play_sample_rate(chip, 8000); 3613 snd_cs46xx_set_capture_sample_rate(chip, 8000); 3614 snd_cs46xx_proc_start(chip); 3615 3616 cs46xx_enable_stream_irqs(chip); 3617 3618 if (amp_saved) 3619 chip->amplifier_ctrl(chip, 1); /* turn amp on */ 3620 else 3621 chip->active_ctrl(chip, -1); /* disable CLKRUN */ 3622 chip->amplifier = amp_saved; 3623 chip->in_suspend = 0; 3624 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 3625 return 0; 3626} 3627#endif /* CONFIG_PM */ 3628 3629 3630/* 3631 */ 3632 3633int __devinit snd_cs46xx_create(struct snd_card *card, 3634 struct pci_dev * pci, 3635 int external_amp, int thinkpad, 3636 struct snd_cs46xx ** rchip) 3637{ 3638 struct snd_cs46xx *chip; 3639 int err, idx; 3640 struct snd_cs46xx_region *region; 3641 struct cs_card_type *cp; 3642 u16 ss_card, ss_vendor; 3643 static struct snd_device_ops ops = { 3644 .dev_free = snd_cs46xx_dev_free, 3645 }; 3646 3647 *rchip = NULL; 3648 3649 /* enable PCI device */ 3650 if ((err = pci_enable_device(pci)) < 0) 3651 return err; 3652 3653 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 3654 if (chip == NULL) { 3655 pci_disable_device(pci); 3656 return -ENOMEM; 3657 } 3658 spin_lock_init(&chip->reg_lock); 3659#ifdef CONFIG_SND_CS46XX_NEW_DSP 3660 mutex_init(&chip->spos_mutex); 3661#endif 3662 chip->card = card; 3663 chip->pci = pci; 3664 chip->irq = -1; 3665 chip->ba0_addr = pci_resource_start(pci, 0); 3666 chip->ba1_addr = pci_resource_start(pci, 1); 3667 if (chip->ba0_addr == 0 || chip->ba0_addr == (unsigned long)~0 || 3668 chip->ba1_addr == 0 || chip->ba1_addr == (unsigned long)~0) { 3669 snd_printk(KERN_ERR "wrong address(es) - ba0 = 0x%lx, ba1 = 0x%lx\n", 3670 chip->ba0_addr, chip->ba1_addr); 3671 snd_cs46xx_free(chip); 3672 return -ENOMEM; 3673 } 3674 3675 region = &chip->region.name.ba0; 3676 strcpy(region->name, "CS46xx_BA0"); 3677 region->base = chip->ba0_addr; 3678 region->size = CS46XX_BA0_SIZE; 3679 3680 region = &chip->region.name.data0; 3681 strcpy(region->name, "CS46xx_BA1_data0"); 3682 region->base = chip->ba1_addr + BA1_SP_DMEM0; 3683 region->size = CS46XX_BA1_DATA0_SIZE; 3684 3685 region = &chip->region.name.data1; 3686 strcpy(region->name, "CS46xx_BA1_data1"); 3687 region->base = chip->ba1_addr + BA1_SP_DMEM1; 3688 region->size = CS46XX_BA1_DATA1_SIZE; 3689 3690 region = &chip->region.name.pmem; 3691 strcpy(region->name, "CS46xx_BA1_pmem"); 3692 region->base = chip->ba1_addr + BA1_SP_PMEM; 3693 region->size = CS46XX_BA1_PRG_SIZE; 3694 3695 region = &chip->region.name.reg; 3696 strcpy(region->name, "CS46xx_BA1_reg"); 3697 region->base = chip->ba1_addr + BA1_SP_REG; 3698 region->size = CS46XX_BA1_REG_SIZE; 3699 3700 /* set up amp and clkrun hack */ 3701 pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &ss_vendor); 3702 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &ss_card); 3703 3704 for (cp = &cards[0]; cp->name; cp++) { 3705 if (cp->vendor == ss_vendor && cp->id == ss_card) { 3706 snd_printdd ("hack for %s enabled\n", cp->name); 3707 3708 chip->amplifier_ctrl = cp->amp; 3709 chip->active_ctrl = cp->active; 3710 chip->mixer_init = cp->mixer_init; 3711 3712 if (cp->init) 3713 cp->init(chip); 3714 break; 3715 } 3716 } 3717 3718 if (external_amp) { 3719 snd_printk(KERN_INFO "Crystal EAPD support forced on.\n"); 3720 chip->amplifier_ctrl = amp_voyetra; 3721 } 3722 3723 if (thinkpad) { 3724 snd_printk(KERN_INFO "Activating CLKRUN hack for Thinkpad.\n"); 3725 chip->active_ctrl = clkrun_hack; 3726 clkrun_init(chip); 3727 } 3728 3729 if (chip->amplifier_ctrl == NULL) 3730 chip->amplifier_ctrl = amp_none; 3731 if (chip->active_ctrl == NULL) 3732 chip->active_ctrl = amp_none; 3733 3734 chip->active_ctrl(chip, 1); /* enable CLKRUN */ 3735 3736 pci_set_master(pci); 3737 3738 for (idx = 0; idx < 5; idx++) { 3739 region = &chip->region.idx[idx]; 3740 if ((region->resource = request_mem_region(region->base, region->size, 3741 region->name)) == NULL) { 3742 snd_printk(KERN_ERR "unable to request memory region 0x%lx-0x%lx\n", 3743 region->base, region->base + region->size - 1); 3744 snd_cs46xx_free(chip); 3745 return -EBUSY; 3746 } 3747 region->remap_addr = ioremap_nocache(region->base, region->size); 3748 if (region->remap_addr == NULL) { 3749 snd_printk(KERN_ERR "%s ioremap problem\n", region->name); 3750 snd_cs46xx_free(chip); 3751 return -ENOMEM; 3752 } 3753 } 3754 3755 if (request_irq(pci->irq, snd_cs46xx_interrupt, IRQF_SHARED, 3756 "CS46XX", chip)) { 3757 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); 3758 snd_cs46xx_free(chip); 3759 return -EBUSY; 3760 } 3761 chip->irq = pci->irq; 3762 3763#ifdef CONFIG_SND_CS46XX_NEW_DSP 3764 chip->dsp_spos_instance = cs46xx_dsp_spos_create(chip); 3765 if (chip->dsp_spos_instance == NULL) { 3766 snd_cs46xx_free(chip); 3767 return -ENOMEM; 3768 } 3769#endif 3770 3771 err = snd_cs46xx_chip_init(chip); 3772 if (err < 0) { 3773 snd_cs46xx_free(chip); 3774 return err; 3775 } 3776 3777 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { 3778 snd_cs46xx_free(chip); 3779 return err; 3780 } 3781 3782 snd_cs46xx_proc_init(card, chip); 3783 3784#ifdef CONFIG_PM 3785 chip->saved_regs = kmalloc(sizeof(*chip->saved_regs) * 3786 ARRAY_SIZE(saved_regs), GFP_KERNEL); 3787 if (!chip->saved_regs) { 3788 snd_cs46xx_free(chip); 3789 return -ENOMEM; 3790 } 3791#endif 3792 3793 chip->active_ctrl(chip, -1); /* disable CLKRUN */ 3794 3795 snd_card_set_dev(card, &pci->dev); 3796 3797 *rchip = chip; 3798 return 0; 3799} 3800