1/* 2 * ALSA driver for Xilinx ML403 AC97 Controller Reference 3 * IP: opb_ac97_controller_ref_v1_00_a (EDK 8.1i) 4 * IP: opb_ac97_controller_ref_v1_00_a (EDK 9.1i) 5 * 6 * Copyright (c) by 2007 Joachim Foerster <JOFT@gmx.de> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 * 22 */ 23 24/* Some notes / status of this driver: 25 * 26 * - Don't wonder about some strange implementations of things - especially the 27 * (heavy) shadowing of codec registers, with which I tried to reduce read 28 * accesses to a minimum, because after a variable amount of accesses, the AC97 29 * controller doesn't raise the register access finished bit anymore ... 30 * 31 * - Playback support seems to be pretty stable - no issues here. 32 * - Capture support "works" now, too. Overruns don't happen any longer so often. 33 * But there might still be some ... 34 */ 35 36#include <linux/init.h> 37#include <linux/moduleparam.h> 38 39#include <linux/platform_device.h> 40 41#include <linux/ioport.h> 42#include <linux/slab.h> 43#include <linux/io.h> 44#include <linux/interrupt.h> 45 46/* HZ */ 47#include <linux/param.h> 48/* jiffies, time_*() */ 49#include <linux/jiffies.h> 50/* schedule_timeout*() */ 51#include <linux/sched.h> 52/* spin_lock*() */ 53#include <linux/spinlock.h> 54/* struct mutex, mutex_init(), mutex_*lock() */ 55#include <linux/mutex.h> 56 57/* snd_printk(), snd_printd() */ 58#include <sound/core.h> 59#include <sound/pcm.h> 60#include <sound/pcm_params.h> 61#include <sound/initval.h> 62#include <sound/ac97_codec.h> 63 64#include "pcm-indirect2.h" 65 66 67#define SND_ML403_AC97CR_DRIVER "ml403-ac97cr" 68 69MODULE_AUTHOR("Joachim Foerster <JOFT@gmx.de>"); 70MODULE_DESCRIPTION("Xilinx ML403 AC97 Controller Reference"); 71MODULE_LICENSE("GPL"); 72MODULE_SUPPORTED_DEVICE("{{Xilinx,ML403 AC97 Controller Reference}}"); 73 74static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 75static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 76static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE; 77 78module_param_array(index, int, NULL, 0444); 79MODULE_PARM_DESC(index, "Index value for ML403 AC97 Controller Reference."); 80module_param_array(id, charp, NULL, 0444); 81MODULE_PARM_DESC(id, "ID string for ML403 AC97 Controller Reference."); 82module_param_array(enable, bool, NULL, 0444); 83MODULE_PARM_DESC(enable, "Enable this ML403 AC97 Controller Reference."); 84 85/* Special feature options */ 86/*#define CODEC_WRITE_CHECK_RAF*/ /* don't return after a write to a codec 87 * register, while RAF bit is not set 88 */ 89/* Debug options for code which may be removed completely in a final version */ 90#ifdef CONFIG_SND_DEBUG 91/*#define CODEC_STAT*/ /* turn on some minimal "statistics" 92 * about codec register usage 93 */ 94#define SND_PCM_INDIRECT2_STAT /* turn on some "statistics" about the 95 * process of copying bytes from the 96 * intermediate buffer to the hardware 97 * fifo and the other way round 98 */ 99#endif 100 101/* Definition of a "level/facility dependent" printk(); may be removed 102 * completely in a final version 103 */ 104#undef PDEBUG 105#ifdef CONFIG_SND_DEBUG 106/* "facilities" for PDEBUG */ 107#define UNKNOWN (1<<0) 108#define CODEC_SUCCESS (1<<1) 109#define CODEC_FAKE (1<<2) 110#define INIT_INFO (1<<3) 111#define INIT_FAILURE (1<<4) 112#define WORK_INFO (1<<5) 113#define WORK_FAILURE (1<<6) 114 115#define PDEBUG_FACILITIES (UNKNOWN | INIT_FAILURE | WORK_FAILURE) 116 117#define PDEBUG(fac, fmt, args...) do { \ 118 if (fac & PDEBUG_FACILITIES) \ 119 snd_printd(KERN_DEBUG SND_ML403_AC97CR_DRIVER ": " \ 120 fmt, ##args); \ 121 } while (0) 122#else 123#define PDEBUG(fac, fmt, args...) /* nothing */ 124#endif 125 126 127 128/* Defines for "waits"/timeouts (portions of HZ=250 on arch/ppc by default) */ 129#define CODEC_TIMEOUT_ON_INIT 5 /* timeout for checking for codec 130 * readiness (after insmod) 131 */ 132#ifndef CODEC_WRITE_CHECK_RAF 133#define CODEC_WAIT_AFTER_WRITE 100 /* general, static wait after a write 134 * access to a codec register, may be 135 * 0 to completely remove wait 136 */ 137#else 138#define CODEC_TIMEOUT_AFTER_WRITE 5 /* timeout after a write access to a 139 * codec register, if RAF bit is used 140 */ 141#endif 142#define CODEC_TIMEOUT_AFTER_READ 5 /* timeout after a read access to a 143 * codec register (checking RAF bit) 144 */ 145 146/* Infrastructure for codec register shadowing */ 147#define LM4550_REG_OK (1<<0) /* register exists */ 148#define LM4550_REG_DONEREAD (1<<1) /* read register once, value should be 149 * the same currently in the register 150 */ 151#define LM4550_REG_NOSAVE (1<<2) /* values written to this register will 152 * not be saved in the register 153 */ 154#define LM4550_REG_NOSHADOW (1<<3) /* don't do register shadowing, use plain 155 * hardware access 156 */ 157#define LM4550_REG_READONLY (1<<4) /* register is read only */ 158#define LM4550_REG_FAKEPROBE (1<<5) /* fake write _and_ read actions during 159 * probe() correctly 160 */ 161#define LM4550_REG_FAKEREAD (1<<6) /* fake read access, always return 162 * default value 163 */ 164#define LM4550_REG_ALLFAKE (LM4550_REG_FAKEREAD | LM4550_REG_FAKEPROBE) 165 166struct lm4550_reg { 167 u16 value; 168 u16 flag; 169 u16 wmask; 170 u16 def; 171}; 172 173struct lm4550_reg lm4550_regfile[64] = { 174 [AC97_RESET / 2] = {.flag = LM4550_REG_OK \ 175 | LM4550_REG_NOSAVE \ 176 | LM4550_REG_FAKEREAD, 177 .def = 0x0D50}, 178 [AC97_MASTER / 2] = {.flag = LM4550_REG_OK 179 | LM4550_REG_FAKEPROBE, 180 .wmask = 0x9F1F, 181 .def = 0x8000}, 182 [AC97_HEADPHONE / 2] = {.flag = LM4550_REG_OK \ 183 | LM4550_REG_FAKEPROBE, 184 .wmask = 0x9F1F, 185 .def = 0x8000}, 186 [AC97_MASTER_MONO / 2] = {.flag = LM4550_REG_OK \ 187 | LM4550_REG_FAKEPROBE, 188 .wmask = 0x801F, 189 .def = 0x8000}, 190 [AC97_PC_BEEP / 2] = {.flag = LM4550_REG_OK \ 191 | LM4550_REG_FAKEPROBE, 192 .wmask = 0x801E, 193 .def = 0x0}, 194 [AC97_PHONE / 2] = {.flag = LM4550_REG_OK \ 195 | LM4550_REG_FAKEPROBE, 196 .wmask = 0x801F, 197 .def = 0x8008}, 198 [AC97_MIC / 2] = {.flag = LM4550_REG_OK \ 199 | LM4550_REG_FAKEPROBE, 200 .wmask = 0x805F, 201 .def = 0x8008}, 202 [AC97_LINE / 2] = {.flag = LM4550_REG_OK \ 203 | LM4550_REG_FAKEPROBE, 204 .wmask = 0x9F1F, 205 .def = 0x8808}, 206 [AC97_CD / 2] = {.flag = LM4550_REG_OK \ 207 | LM4550_REG_FAKEPROBE, 208 .wmask = 0x9F1F, 209 .def = 0x8808}, 210 [AC97_VIDEO / 2] = {.flag = LM4550_REG_OK \ 211 | LM4550_REG_FAKEPROBE, 212 .wmask = 0x9F1F, 213 .def = 0x8808}, 214 [AC97_AUX / 2] = {.flag = LM4550_REG_OK \ 215 | LM4550_REG_FAKEPROBE, 216 .wmask = 0x9F1F, 217 .def = 0x8808}, 218 [AC97_PCM / 2] = {.flag = LM4550_REG_OK \ 219 | LM4550_REG_FAKEPROBE, 220 .wmask = 0x9F1F, 221 .def = 0x8008}, 222 [AC97_REC_SEL / 2] = {.flag = LM4550_REG_OK \ 223 | LM4550_REG_FAKEPROBE, 224 .wmask = 0x707, 225 .def = 0x0}, 226 [AC97_REC_GAIN / 2] = {.flag = LM4550_REG_OK \ 227 | LM4550_REG_FAKEPROBE, 228 .wmask = 0x8F0F, 229 .def = 0x8000}, 230 [AC97_GENERAL_PURPOSE / 2] = {.flag = LM4550_REG_OK \ 231 | LM4550_REG_FAKEPROBE, 232 .def = 0x0, 233 .wmask = 0xA380}, 234 [AC97_3D_CONTROL / 2] = {.flag = LM4550_REG_OK \ 235 | LM4550_REG_FAKEREAD \ 236 | LM4550_REG_READONLY, 237 .def = 0x0101}, 238 [AC97_POWERDOWN / 2] = {.flag = LM4550_REG_OK \ 239 | LM4550_REG_NOSHADOW \ 240 | LM4550_REG_NOSAVE, 241 .wmask = 0xFF00}, 242 [AC97_EXTENDED_ID / 2] = {.flag = LM4550_REG_OK \ 243 | LM4550_REG_FAKEREAD \ 244 | LM4550_REG_READONLY, 245 .def = 0x0201}, /* primary codec */ 246 [AC97_EXTENDED_STATUS / 2] = {.flag = LM4550_REG_OK \ 247 | LM4550_REG_NOSHADOW \ 248 | LM4550_REG_NOSAVE, 249 .wmask = 0x1}, 250 [AC97_PCM_FRONT_DAC_RATE / 2] = {.flag = LM4550_REG_OK \ 251 | LM4550_REG_FAKEPROBE, 252 .def = 0xBB80, 253 .wmask = 0xFFFF}, 254 [AC97_PCM_LR_ADC_RATE / 2] = {.flag = LM4550_REG_OK \ 255 | LM4550_REG_FAKEPROBE, 256 .def = 0xBB80, 257 .wmask = 0xFFFF}, 258 [AC97_VENDOR_ID1 / 2] = {.flag = LM4550_REG_OK \ 259 | LM4550_REG_READONLY \ 260 | LM4550_REG_FAKEREAD, 261 .def = 0x4E53}, 262 [AC97_VENDOR_ID2 / 2] = {.flag = LM4550_REG_OK \ 263 | LM4550_REG_READONLY \ 264 | LM4550_REG_FAKEREAD, 265 .def = 0x4350} 266}; 267 268#define LM4550_RF_OK(reg) (lm4550_regfile[reg / 2].flag & LM4550_REG_OK) 269 270static void lm4550_regfile_init(void) 271{ 272 int i; 273 for (i = 0; i < 64; i++) 274 if (lm4550_regfile[i].flag & LM4550_REG_FAKEPROBE) 275 lm4550_regfile[i].value = lm4550_regfile[i].def; 276} 277 278static void lm4550_regfile_write_values_after_init(struct snd_ac97 *ac97) 279{ 280 int i; 281 for (i = 0; i < 64; i++) 282 if ((lm4550_regfile[i].flag & LM4550_REG_FAKEPROBE) && 283 (lm4550_regfile[i].value != lm4550_regfile[i].def)) { 284 PDEBUG(CODEC_FAKE, "lm4550_regfile_write_values_after_" 285 "init(): reg=0x%x value=0x%x / %d is different " 286 "from def=0x%x / %d\n", 287 i, lm4550_regfile[i].value, 288 lm4550_regfile[i].value, lm4550_regfile[i].def, 289 lm4550_regfile[i].def); 290 snd_ac97_write(ac97, i * 2, lm4550_regfile[i].value); 291 lm4550_regfile[i].flag |= LM4550_REG_DONEREAD; 292 } 293} 294 295 296/* direct registers */ 297#define CR_REG(ml403_ac97cr, x) ((ml403_ac97cr)->port + CR_REG_##x) 298 299#define CR_REG_PLAYFIFO 0x00 300#define CR_PLAYDATA(a) ((a) & 0xFFFF) 301 302#define CR_REG_RECFIFO 0x04 303#define CR_RECDATA(a) ((a) & 0xFFFF) 304 305#define CR_REG_STATUS 0x08 306#define CR_RECOVER (1<<7) 307#define CR_PLAYUNDER (1<<6) 308#define CR_CODECREADY (1<<5) 309#define CR_RAF (1<<4) 310#define CR_RECEMPTY (1<<3) 311#define CR_RECFULL (1<<2) 312#define CR_PLAYHALF (1<<1) 313#define CR_PLAYFULL (1<<0) 314 315#define CR_REG_RESETFIFO 0x0C 316#define CR_RECRESET (1<<1) 317#define CR_PLAYRESET (1<<0) 318 319#define CR_REG_CODEC_ADDR 0x10 320/* UG082 says: 321 * #define CR_CODEC_ADDR(a) ((a) << 1) 322 * #define CR_CODEC_READ (1<<0) 323 * #define CR_CODEC_WRITE (0<<0) 324 */ 325/* RefDesign example says: */ 326#define CR_CODEC_ADDR(a) ((a) << 0) 327#define CR_CODEC_READ (1<<7) 328#define CR_CODEC_WRITE (0<<7) 329 330#define CR_REG_CODEC_DATAREAD 0x14 331#define CR_CODEC_DATAREAD(v) ((v) & 0xFFFF) 332 333#define CR_REG_CODEC_DATAWRITE 0x18 334#define CR_CODEC_DATAWRITE(v) ((v) & 0xFFFF) 335 336#define CR_FIFO_SIZE 32 337 338struct snd_ml403_ac97cr { 339 /* lock for access to (controller) registers */ 340 spinlock_t reg_lock; 341 /* mutex for the whole sequence of accesses to (controller) registers 342 * which affect codec registers 343 */ 344 struct mutex cdc_mutex; 345 346 int irq; /* for playback */ 347 int enable_irq; /* for playback */ 348 349 int capture_irq; 350 int enable_capture_irq; 351 352 struct resource *res_port; 353 void *port; 354 355 struct snd_ac97 *ac97; 356 int ac97_fake; 357#ifdef CODEC_STAT 358 int ac97_read; 359 int ac97_write; 360#endif 361 362 struct platform_device *pfdev; 363 struct snd_card *card; 364 struct snd_pcm *pcm; 365 struct snd_pcm_substream *playback_substream; 366 struct snd_pcm_substream *capture_substream; 367 368 struct snd_pcm_indirect2 ind_rec; /* for playback */ 369 struct snd_pcm_indirect2 capture_ind2_rec; 370}; 371 372static struct snd_pcm_hardware snd_ml403_ac97cr_playback = { 373 .info = (SNDRV_PCM_INFO_MMAP | 374 SNDRV_PCM_INFO_INTERLEAVED | 375 SNDRV_PCM_INFO_MMAP_VALID), 376 .formats = SNDRV_PCM_FMTBIT_S16_BE, 377 .rates = (SNDRV_PCM_RATE_CONTINUOUS | 378 SNDRV_PCM_RATE_8000_48000), 379 .rate_min = 4000, 380 .rate_max = 48000, 381 .channels_min = 2, 382 .channels_max = 2, 383 .buffer_bytes_max = (128*1024), 384 .period_bytes_min = CR_FIFO_SIZE/2, 385 .period_bytes_max = (64*1024), 386 .periods_min = 2, 387 .periods_max = (128*1024)/(CR_FIFO_SIZE/2), 388 .fifo_size = 0, 389}; 390 391static struct snd_pcm_hardware snd_ml403_ac97cr_capture = { 392 .info = (SNDRV_PCM_INFO_MMAP | 393 SNDRV_PCM_INFO_INTERLEAVED | 394 SNDRV_PCM_INFO_MMAP_VALID), 395 .formats = SNDRV_PCM_FMTBIT_S16_BE, 396 .rates = (SNDRV_PCM_RATE_CONTINUOUS | 397 SNDRV_PCM_RATE_8000_48000), 398 .rate_min = 4000, 399 .rate_max = 48000, 400 .channels_min = 2, 401 .channels_max = 2, 402 .buffer_bytes_max = (128*1024), 403 .period_bytes_min = CR_FIFO_SIZE/2, 404 .period_bytes_max = (64*1024), 405 .periods_min = 2, 406 .periods_max = (128*1024)/(CR_FIFO_SIZE/2), 407 .fifo_size = 0, 408}; 409 410static size_t 411snd_ml403_ac97cr_playback_ind2_zero(struct snd_pcm_substream *substream, 412 struct snd_pcm_indirect2 *rec) 413{ 414 struct snd_ml403_ac97cr *ml403_ac97cr; 415 int copied_words = 0; 416 u32 full = 0; 417 418 ml403_ac97cr = snd_pcm_substream_chip(substream); 419 420 spin_lock(&ml403_ac97cr->reg_lock); 421 while ((full = (in_be32(CR_REG(ml403_ac97cr, STATUS)) & 422 CR_PLAYFULL)) != CR_PLAYFULL) { 423 out_be32(CR_REG(ml403_ac97cr, PLAYFIFO), 0); 424 copied_words++; 425 } 426 rec->hw_ready = 0; 427 spin_unlock(&ml403_ac97cr->reg_lock); 428 429 return (size_t) (copied_words * 2); 430} 431 432static size_t 433snd_ml403_ac97cr_playback_ind2_copy(struct snd_pcm_substream *substream, 434 struct snd_pcm_indirect2 *rec, 435 size_t bytes) 436{ 437 struct snd_ml403_ac97cr *ml403_ac97cr; 438 u16 *src; 439 int copied_words = 0; 440 u32 full = 0; 441 442 ml403_ac97cr = snd_pcm_substream_chip(substream); 443 src = (u16 *)(substream->runtime->dma_area + rec->sw_data); 444 445 spin_lock(&ml403_ac97cr->reg_lock); 446 while (((full = (in_be32(CR_REG(ml403_ac97cr, STATUS)) & 447 CR_PLAYFULL)) != CR_PLAYFULL) && (bytes > 1)) { 448 out_be32(CR_REG(ml403_ac97cr, PLAYFIFO), 449 CR_PLAYDATA(src[copied_words])); 450 copied_words++; 451 bytes = bytes - 2; 452 } 453 if (full != CR_PLAYFULL) 454 rec->hw_ready = 1; 455 else 456 rec->hw_ready = 0; 457 spin_unlock(&ml403_ac97cr->reg_lock); 458 459 return (size_t) (copied_words * 2); 460} 461 462static size_t 463snd_ml403_ac97cr_capture_ind2_null(struct snd_pcm_substream *substream, 464 struct snd_pcm_indirect2 *rec) 465{ 466 struct snd_ml403_ac97cr *ml403_ac97cr; 467 int copied_words = 0; 468 u32 empty = 0; 469 470 ml403_ac97cr = snd_pcm_substream_chip(substream); 471 472 spin_lock(&ml403_ac97cr->reg_lock); 473 while ((empty = (in_be32(CR_REG(ml403_ac97cr, STATUS)) & 474 CR_RECEMPTY)) != CR_RECEMPTY) { 475 volatile u32 trash; 476 477 trash = CR_RECDATA(in_be32(CR_REG(ml403_ac97cr, RECFIFO))); 478 /* Hmmmm, really necessary? Don't want call to in_be32() 479 * to be optimised away! 480 */ 481 trash++; 482 copied_words++; 483 } 484 rec->hw_ready = 0; 485 spin_unlock(&ml403_ac97cr->reg_lock); 486 487 return (size_t) (copied_words * 2); 488} 489 490static size_t 491snd_ml403_ac97cr_capture_ind2_copy(struct snd_pcm_substream *substream, 492 struct snd_pcm_indirect2 *rec, size_t bytes) 493{ 494 struct snd_ml403_ac97cr *ml403_ac97cr; 495 u16 *dst; 496 int copied_words = 0; 497 u32 empty = 0; 498 499 ml403_ac97cr = snd_pcm_substream_chip(substream); 500 dst = (u16 *)(substream->runtime->dma_area + rec->sw_data); 501 502 spin_lock(&ml403_ac97cr->reg_lock); 503 while (((empty = (in_be32(CR_REG(ml403_ac97cr, STATUS)) & 504 CR_RECEMPTY)) != CR_RECEMPTY) && (bytes > 1)) { 505 dst[copied_words] = CR_RECDATA(in_be32(CR_REG(ml403_ac97cr, 506 RECFIFO))); 507 copied_words++; 508 bytes = bytes - 2; 509 } 510 if (empty != CR_RECEMPTY) 511 rec->hw_ready = 1; 512 else 513 rec->hw_ready = 0; 514 spin_unlock(&ml403_ac97cr->reg_lock); 515 516 return (size_t) (copied_words * 2); 517} 518 519static snd_pcm_uframes_t 520snd_ml403_ac97cr_pcm_pointer(struct snd_pcm_substream *substream) 521{ 522 struct snd_ml403_ac97cr *ml403_ac97cr; 523 struct snd_pcm_indirect2 *ind2_rec = NULL; 524 525 ml403_ac97cr = snd_pcm_substream_chip(substream); 526 527 if (substream == ml403_ac97cr->playback_substream) 528 ind2_rec = &ml403_ac97cr->ind_rec; 529 if (substream == ml403_ac97cr->capture_substream) 530 ind2_rec = &ml403_ac97cr->capture_ind2_rec; 531 532 if (ind2_rec != NULL) 533 return snd_pcm_indirect2_pointer(substream, ind2_rec); 534 return (snd_pcm_uframes_t) 0; 535} 536 537static int 538snd_ml403_ac97cr_pcm_playback_trigger(struct snd_pcm_substream *substream, 539 int cmd) 540{ 541 struct snd_ml403_ac97cr *ml403_ac97cr; 542 int err = 0; 543 544 ml403_ac97cr = snd_pcm_substream_chip(substream); 545 546 switch (cmd) { 547 case SNDRV_PCM_TRIGGER_START: 548 PDEBUG(WORK_INFO, "trigger(playback): START\n"); 549 ml403_ac97cr->ind_rec.hw_ready = 1; 550 551 /* clear play FIFO */ 552 out_be32(CR_REG(ml403_ac97cr, RESETFIFO), CR_PLAYRESET); 553 554 /* enable play irq */ 555 ml403_ac97cr->enable_irq = 1; 556 enable_irq(ml403_ac97cr->irq); 557 break; 558 case SNDRV_PCM_TRIGGER_STOP: 559 PDEBUG(WORK_INFO, "trigger(playback): STOP\n"); 560 ml403_ac97cr->ind_rec.hw_ready = 0; 561#ifdef SND_PCM_INDIRECT2_STAT 562 snd_pcm_indirect2_stat(substream, &ml403_ac97cr->ind_rec); 563#endif 564 /* disable play irq */ 565 disable_irq_nosync(ml403_ac97cr->irq); 566 ml403_ac97cr->enable_irq = 0; 567 break; 568 default: 569 err = -EINVAL; 570 break; 571 } 572 PDEBUG(WORK_INFO, "trigger(playback): (done)\n"); 573 return err; 574} 575 576static int 577snd_ml403_ac97cr_pcm_capture_trigger(struct snd_pcm_substream *substream, 578 int cmd) 579{ 580 struct snd_ml403_ac97cr *ml403_ac97cr; 581 int err = 0; 582 583 ml403_ac97cr = snd_pcm_substream_chip(substream); 584 585 switch (cmd) { 586 case SNDRV_PCM_TRIGGER_START: 587 PDEBUG(WORK_INFO, "trigger(capture): START\n"); 588 ml403_ac97cr->capture_ind2_rec.hw_ready = 0; 589 590 /* clear record FIFO */ 591 out_be32(CR_REG(ml403_ac97cr, RESETFIFO), CR_RECRESET); 592 593 /* enable record irq */ 594 ml403_ac97cr->enable_capture_irq = 1; 595 enable_irq(ml403_ac97cr->capture_irq); 596 break; 597 case SNDRV_PCM_TRIGGER_STOP: 598 PDEBUG(WORK_INFO, "trigger(capture): STOP\n"); 599 ml403_ac97cr->capture_ind2_rec.hw_ready = 0; 600#ifdef SND_PCM_INDIRECT2_STAT 601 snd_pcm_indirect2_stat(substream, 602 &ml403_ac97cr->capture_ind2_rec); 603#endif 604 /* disable capture irq */ 605 disable_irq_nosync(ml403_ac97cr->capture_irq); 606 ml403_ac97cr->enable_capture_irq = 0; 607 break; 608 default: 609 err = -EINVAL; 610 break; 611 } 612 PDEBUG(WORK_INFO, "trigger(capture): (done)\n"); 613 return err; 614} 615 616static int 617snd_ml403_ac97cr_pcm_playback_prepare(struct snd_pcm_substream *substream) 618{ 619 struct snd_ml403_ac97cr *ml403_ac97cr; 620 struct snd_pcm_runtime *runtime; 621 622 ml403_ac97cr = snd_pcm_substream_chip(substream); 623 runtime = substream->runtime; 624 625 PDEBUG(WORK_INFO, 626 "prepare(): period_bytes=%d, minperiod_bytes=%d\n", 627 snd_pcm_lib_period_bytes(substream), CR_FIFO_SIZE / 2); 628 629 /* set sampling rate */ 630 snd_ac97_set_rate(ml403_ac97cr->ac97, AC97_PCM_FRONT_DAC_RATE, 631 runtime->rate); 632 PDEBUG(WORK_INFO, "prepare(): rate=%d\n", runtime->rate); 633 634 /* init struct for intermediate buffer */ 635 memset(&ml403_ac97cr->ind_rec, 0, 636 sizeof(struct snd_pcm_indirect2)); 637 ml403_ac97cr->ind_rec.hw_buffer_size = CR_FIFO_SIZE; 638 ml403_ac97cr->ind_rec.sw_buffer_size = 639 snd_pcm_lib_buffer_bytes(substream); 640 ml403_ac97cr->ind_rec.min_periods = -1; 641 ml403_ac97cr->ind_rec.min_multiple = 642 snd_pcm_lib_period_bytes(substream) / (CR_FIFO_SIZE / 2); 643 PDEBUG(WORK_INFO, "prepare(): hw_buffer_size=%d, " 644 "sw_buffer_size=%d, min_multiple=%d\n", 645 CR_FIFO_SIZE, ml403_ac97cr->ind_rec.sw_buffer_size, 646 ml403_ac97cr->ind_rec.min_multiple); 647 return 0; 648} 649 650static int 651snd_ml403_ac97cr_pcm_capture_prepare(struct snd_pcm_substream *substream) 652{ 653 struct snd_ml403_ac97cr *ml403_ac97cr; 654 struct snd_pcm_runtime *runtime; 655 656 ml403_ac97cr = snd_pcm_substream_chip(substream); 657 runtime = substream->runtime; 658 659 PDEBUG(WORK_INFO, 660 "prepare(capture): period_bytes=%d, minperiod_bytes=%d\n", 661 snd_pcm_lib_period_bytes(substream), CR_FIFO_SIZE / 2); 662 663 /* set sampling rate */ 664 snd_ac97_set_rate(ml403_ac97cr->ac97, AC97_PCM_LR_ADC_RATE, 665 runtime->rate); 666 PDEBUG(WORK_INFO, "prepare(capture): rate=%d\n", runtime->rate); 667 668 /* init struct for intermediate buffer */ 669 memset(&ml403_ac97cr->capture_ind2_rec, 0, 670 sizeof(struct snd_pcm_indirect2)); 671 ml403_ac97cr->capture_ind2_rec.hw_buffer_size = CR_FIFO_SIZE; 672 ml403_ac97cr->capture_ind2_rec.sw_buffer_size = 673 snd_pcm_lib_buffer_bytes(substream); 674 ml403_ac97cr->capture_ind2_rec.min_multiple = 675 snd_pcm_lib_period_bytes(substream) / (CR_FIFO_SIZE / 2); 676 PDEBUG(WORK_INFO, "prepare(capture): hw_buffer_size=%d, " 677 "sw_buffer_size=%d, min_multiple=%d\n", CR_FIFO_SIZE, 678 ml403_ac97cr->capture_ind2_rec.sw_buffer_size, 679 ml403_ac97cr->capture_ind2_rec.min_multiple); 680 return 0; 681} 682 683static int snd_ml403_ac97cr_hw_free(struct snd_pcm_substream *substream) 684{ 685 PDEBUG(WORK_INFO, "hw_free()\n"); 686 return snd_pcm_lib_free_pages(substream); 687} 688 689static int 690snd_ml403_ac97cr_hw_params(struct snd_pcm_substream *substream, 691 struct snd_pcm_hw_params *hw_params) 692{ 693 PDEBUG(WORK_INFO, "hw_params(): desired buffer bytes=%d, desired " 694 "period bytes=%d\n", 695 params_buffer_bytes(hw_params), params_period_bytes(hw_params)); 696 return snd_pcm_lib_malloc_pages(substream, 697 params_buffer_bytes(hw_params)); 698} 699 700static int snd_ml403_ac97cr_playback_open(struct snd_pcm_substream *substream) 701{ 702 struct snd_ml403_ac97cr *ml403_ac97cr; 703 struct snd_pcm_runtime *runtime; 704 705 ml403_ac97cr = snd_pcm_substream_chip(substream); 706 runtime = substream->runtime; 707 708 PDEBUG(WORK_INFO, "open(playback)\n"); 709 ml403_ac97cr->playback_substream = substream; 710 runtime->hw = snd_ml403_ac97cr_playback; 711 712 snd_pcm_hw_constraint_step(runtime, 0, 713 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 714 CR_FIFO_SIZE / 2); 715 return 0; 716} 717 718static int snd_ml403_ac97cr_capture_open(struct snd_pcm_substream *substream) 719{ 720 struct snd_ml403_ac97cr *ml403_ac97cr; 721 struct snd_pcm_runtime *runtime; 722 723 ml403_ac97cr = snd_pcm_substream_chip(substream); 724 runtime = substream->runtime; 725 726 PDEBUG(WORK_INFO, "open(capture)\n"); 727 ml403_ac97cr->capture_substream = substream; 728 runtime->hw = snd_ml403_ac97cr_capture; 729 730 snd_pcm_hw_constraint_step(runtime, 0, 731 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 732 CR_FIFO_SIZE / 2); 733 return 0; 734} 735 736static int snd_ml403_ac97cr_playback_close(struct snd_pcm_substream *substream) 737{ 738 struct snd_ml403_ac97cr *ml403_ac97cr; 739 740 ml403_ac97cr = snd_pcm_substream_chip(substream); 741 742 PDEBUG(WORK_INFO, "close(playback)\n"); 743 ml403_ac97cr->playback_substream = NULL; 744 return 0; 745} 746 747static int snd_ml403_ac97cr_capture_close(struct snd_pcm_substream *substream) 748{ 749 struct snd_ml403_ac97cr *ml403_ac97cr; 750 751 ml403_ac97cr = snd_pcm_substream_chip(substream); 752 753 PDEBUG(WORK_INFO, "close(capture)\n"); 754 ml403_ac97cr->capture_substream = NULL; 755 return 0; 756} 757 758static struct snd_pcm_ops snd_ml403_ac97cr_playback_ops = { 759 .open = snd_ml403_ac97cr_playback_open, 760 .close = snd_ml403_ac97cr_playback_close, 761 .ioctl = snd_pcm_lib_ioctl, 762 .hw_params = snd_ml403_ac97cr_hw_params, 763 .hw_free = snd_ml403_ac97cr_hw_free, 764 .prepare = snd_ml403_ac97cr_pcm_playback_prepare, 765 .trigger = snd_ml403_ac97cr_pcm_playback_trigger, 766 .pointer = snd_ml403_ac97cr_pcm_pointer, 767}; 768 769static struct snd_pcm_ops snd_ml403_ac97cr_capture_ops = { 770 .open = snd_ml403_ac97cr_capture_open, 771 .close = snd_ml403_ac97cr_capture_close, 772 .ioctl = snd_pcm_lib_ioctl, 773 .hw_params = snd_ml403_ac97cr_hw_params, 774 .hw_free = snd_ml403_ac97cr_hw_free, 775 .prepare = snd_ml403_ac97cr_pcm_capture_prepare, 776 .trigger = snd_ml403_ac97cr_pcm_capture_trigger, 777 .pointer = snd_ml403_ac97cr_pcm_pointer, 778}; 779 780static irqreturn_t snd_ml403_ac97cr_irq(int irq, void *dev_id) 781{ 782 struct snd_ml403_ac97cr *ml403_ac97cr; 783 struct platform_device *pfdev; 784 int cmp_irq; 785 786 ml403_ac97cr = (struct snd_ml403_ac97cr *)dev_id; 787 if (ml403_ac97cr == NULL) 788 return IRQ_NONE; 789 790 pfdev = ml403_ac97cr->pfdev; 791 792 /* playback interrupt */ 793 cmp_irq = platform_get_irq(pfdev, 0); 794 if (irq == cmp_irq) { 795 if (ml403_ac97cr->enable_irq) 796 snd_pcm_indirect2_playback_interrupt( 797 ml403_ac97cr->playback_substream, 798 &ml403_ac97cr->ind_rec, 799 snd_ml403_ac97cr_playback_ind2_copy, 800 snd_ml403_ac97cr_playback_ind2_zero); 801 else 802 goto __disable_irq; 803 } else { 804 /* record interrupt */ 805 cmp_irq = platform_get_irq(pfdev, 1); 806 if (irq == cmp_irq) { 807 if (ml403_ac97cr->enable_capture_irq) 808 snd_pcm_indirect2_capture_interrupt( 809 ml403_ac97cr->capture_substream, 810 &ml403_ac97cr->capture_ind2_rec, 811 snd_ml403_ac97cr_capture_ind2_copy, 812 snd_ml403_ac97cr_capture_ind2_null); 813 else 814 goto __disable_irq; 815 } else 816 return IRQ_NONE; 817 } 818 return IRQ_HANDLED; 819 820__disable_irq: 821 PDEBUG(INIT_INFO, "irq(): irq %d is meant to be disabled! So, now try " 822 "to disable it _really_!\n", irq); 823 disable_irq_nosync(irq); 824 return IRQ_HANDLED; 825} 826 827static unsigned short 828snd_ml403_ac97cr_codec_read(struct snd_ac97 *ac97, unsigned short reg) 829{ 830 struct snd_ml403_ac97cr *ml403_ac97cr = ac97->private_data; 831#ifdef CODEC_STAT 832 u32 stat; 833 u32 rafaccess = 0; 834#endif 835 unsigned long end_time; 836 u16 value = 0; 837 838 if (!LM4550_RF_OK(reg)) { 839 snd_printk(KERN_WARNING SND_ML403_AC97CR_DRIVER ": " 840 "access to unknown/unused codec register 0x%x " 841 "ignored!\n", reg); 842 return 0; 843 } 844 /* check if we can fake/answer this access from our shadow register */ 845 if ((lm4550_regfile[reg / 2].flag & 846 (LM4550_REG_DONEREAD | LM4550_REG_ALLFAKE)) && 847 !(lm4550_regfile[reg / 2].flag & LM4550_REG_NOSHADOW)) { 848 if (lm4550_regfile[reg / 2].flag & LM4550_REG_FAKEREAD) { 849 PDEBUG(CODEC_FAKE, "codec_read(): faking read from " 850 "reg=0x%x, val=0x%x / %d\n", 851 reg, lm4550_regfile[reg / 2].def, 852 lm4550_regfile[reg / 2].def); 853 return lm4550_regfile[reg / 2].def; 854 } else if ((lm4550_regfile[reg / 2].flag & 855 LM4550_REG_FAKEPROBE) && 856 ml403_ac97cr->ac97_fake) { 857 PDEBUG(CODEC_FAKE, "codec_read(): faking read from " 858 "reg=0x%x, val=0x%x / %d (probe)\n", 859 reg, lm4550_regfile[reg / 2].value, 860 lm4550_regfile[reg / 2].value); 861 return lm4550_regfile[reg / 2].value; 862 } else { 863#ifdef CODEC_STAT 864 PDEBUG(CODEC_FAKE, "codec_read(): read access " 865 "answered by shadow register 0x%x (value=0x%x " 866 "/ %d) (cw=%d cr=%d)\n", 867 reg, lm4550_regfile[reg / 2].value, 868 lm4550_regfile[reg / 2].value, 869 ml403_ac97cr->ac97_write, 870 ml403_ac97cr->ac97_read); 871#else 872 PDEBUG(CODEC_FAKE, "codec_read(): read access " 873 "answered by shadow register 0x%x (value=0x%x " 874 "/ %d)\n", 875 reg, lm4550_regfile[reg / 2].value, 876 lm4550_regfile[reg / 2].value); 877#endif 878 return lm4550_regfile[reg / 2].value; 879 } 880 } 881 /* if we are here, we _have_ to access the codec really, no faking */ 882 if (mutex_lock_interruptible(&ml403_ac97cr->cdc_mutex) != 0) 883 return 0; 884#ifdef CODEC_STAT 885 ml403_ac97cr->ac97_read++; 886#endif 887 spin_lock(&ml403_ac97cr->reg_lock); 888 out_be32(CR_REG(ml403_ac97cr, CODEC_ADDR), 889 CR_CODEC_ADDR(reg) | CR_CODEC_READ); 890 spin_unlock(&ml403_ac97cr->reg_lock); 891 end_time = jiffies + (HZ / CODEC_TIMEOUT_AFTER_READ); 892 do { 893 spin_lock(&ml403_ac97cr->reg_lock); 894#ifdef CODEC_STAT 895 rafaccess++; 896 stat = in_be32(CR_REG(ml403_ac97cr, STATUS)); 897 if ((stat & CR_RAF) == CR_RAF) { 898 value = CR_CODEC_DATAREAD( 899 in_be32(CR_REG(ml403_ac97cr, CODEC_DATAREAD))); 900 PDEBUG(CODEC_SUCCESS, "codec_read(): (done) reg=0x%x, " 901 "value=0x%x / %d (STATUS=0x%x)\n", 902 reg, value, value, stat); 903#else 904 if ((in_be32(CR_REG(ml403_ac97cr, STATUS)) & 905 CR_RAF) == CR_RAF) { 906 value = CR_CODEC_DATAREAD( 907 in_be32(CR_REG(ml403_ac97cr, CODEC_DATAREAD))); 908 PDEBUG(CODEC_SUCCESS, "codec_read(): (done) " 909 "reg=0x%x, value=0x%x / %d\n", 910 reg, value, value); 911#endif 912 lm4550_regfile[reg / 2].value = value; 913 lm4550_regfile[reg / 2].flag |= LM4550_REG_DONEREAD; 914 spin_unlock(&ml403_ac97cr->reg_lock); 915 mutex_unlock(&ml403_ac97cr->cdc_mutex); 916 return value; 917 } 918 spin_unlock(&ml403_ac97cr->reg_lock); 919 schedule_timeout_uninterruptible(1); 920 } while (time_after(end_time, jiffies)); 921 /* read the DATAREAD register anyway, see comment below */ 922 spin_lock(&ml403_ac97cr->reg_lock); 923 value = 924 CR_CODEC_DATAREAD(in_be32(CR_REG(ml403_ac97cr, CODEC_DATAREAD))); 925 spin_unlock(&ml403_ac97cr->reg_lock); 926#ifdef CODEC_STAT 927 snd_printk(KERN_WARNING SND_ML403_AC97CR_DRIVER ": " 928 "timeout while codec read! " 929 "(reg=0x%x, last STATUS=0x%x, DATAREAD=0x%x / %d, %d) " 930 "(cw=%d, cr=%d)\n", 931 reg, stat, value, value, rafaccess, 932 ml403_ac97cr->ac97_write, ml403_ac97cr->ac97_read); 933#else 934 snd_printk(KERN_WARNING SND_ML403_AC97CR_DRIVER ": " 935 "timeout while codec read! " 936 "(reg=0x%x, DATAREAD=0x%x / %d)\n", 937 reg, value, value); 938#endif 939 /* BUG: This is PURE speculation! But after _most_ read timeouts the 940 * value in the register is ok! 941 */ 942 lm4550_regfile[reg / 2].value = value; 943 lm4550_regfile[reg / 2].flag |= LM4550_REG_DONEREAD; 944 mutex_unlock(&ml403_ac97cr->cdc_mutex); 945 return value; 946} 947 948static void 949snd_ml403_ac97cr_codec_write(struct snd_ac97 *ac97, unsigned short reg, 950 unsigned short val) 951{ 952 struct snd_ml403_ac97cr *ml403_ac97cr = ac97->private_data; 953 954#ifdef CODEC_STAT 955 u32 stat; 956 u32 rafaccess = 0; 957#endif 958#ifdef CODEC_WRITE_CHECK_RAF 959 unsigned long end_time; 960#endif 961 962 if (!LM4550_RF_OK(reg)) { 963 snd_printk(KERN_WARNING SND_ML403_AC97CR_DRIVER ": " 964 "access to unknown/unused codec register 0x%x " 965 "ignored!\n", reg); 966 return; 967 } 968 if (lm4550_regfile[reg / 2].flag & LM4550_REG_READONLY) { 969 snd_printk(KERN_WARNING SND_ML403_AC97CR_DRIVER ": " 970 "write access to read only codec register 0x%x " 971 "ignored!\n", reg); 972 return; 973 } 974 if ((val & lm4550_regfile[reg / 2].wmask) != val) { 975 snd_printk(KERN_WARNING SND_ML403_AC97CR_DRIVER ": " 976 "write access to codec register 0x%x " 977 "with bad value 0x%x / %d!\n", 978 reg, val, val); 979 val = val & lm4550_regfile[reg / 2].wmask; 980 } 981 if (((lm4550_regfile[reg / 2].flag & LM4550_REG_FAKEPROBE) && 982 ml403_ac97cr->ac97_fake) && 983 !(lm4550_regfile[reg / 2].flag & LM4550_REG_NOSHADOW)) { 984 PDEBUG(CODEC_FAKE, "codec_write(): faking write to reg=0x%x, " 985 "val=0x%x / %d\n", reg, val, val); 986 lm4550_regfile[reg / 2].value = (val & 987 lm4550_regfile[reg / 2].wmask); 988 return; 989 } 990 if (mutex_lock_interruptible(&ml403_ac97cr->cdc_mutex) != 0) 991 return; 992#ifdef CODEC_STAT 993 ml403_ac97cr->ac97_write++; 994#endif 995 spin_lock(&ml403_ac97cr->reg_lock); 996 out_be32(CR_REG(ml403_ac97cr, CODEC_DATAWRITE), 997 CR_CODEC_DATAWRITE(val)); 998 out_be32(CR_REG(ml403_ac97cr, CODEC_ADDR), 999 CR_CODEC_ADDR(reg) | CR_CODEC_WRITE); 1000 spin_unlock(&ml403_ac97cr->reg_lock); 1001#ifdef CODEC_WRITE_CHECK_RAF 1002 /* check CR_CODEC_RAF bit to see if write access to register is done; 1003 * loop until bit is set or timeout happens 1004 */ 1005 end_time = jiffies + HZ / CODEC_TIMEOUT_AFTER_WRITE; 1006 do { 1007 spin_lock(&ml403_ac97cr->reg_lock); 1008#ifdef CODEC_STAT 1009 rafaccess++; 1010 stat = in_be32(CR_REG(ml403_ac97cr, STATUS)) 1011 if ((stat & CR_RAF) == CR_RAF) { 1012#else 1013 if ((in_be32(CR_REG(ml403_ac97cr, STATUS)) & 1014 CR_RAF) == CR_RAF) { 1015#endif 1016 PDEBUG(CODEC_SUCCESS, "codec_write(): (done) " 1017 "reg=0x%x, value=%d / 0x%x\n", 1018 reg, val, val); 1019 if (!(lm4550_regfile[reg / 2].flag & 1020 LM4550_REG_NOSHADOW) && 1021 !(lm4550_regfile[reg / 2].flag & 1022 LM4550_REG_NOSAVE)) 1023 lm4550_regfile[reg / 2].value = val; 1024 lm4550_regfile[reg / 2].flag |= LM4550_REG_DONEREAD; 1025 spin_unlock(&ml403_ac97cr->reg_lock); 1026 mutex_unlock(&ml403_ac97cr->cdc_mutex); 1027 return; 1028 } 1029 spin_unlock(&ml403_ac97cr->reg_lock); 1030 schedule_timeout_uninterruptible(1); 1031 } while (time_after(end_time, jiffies)); 1032#ifdef CODEC_STAT 1033 snd_printk(KERN_WARNING SND_ML403_AC97CR_DRIVER ": " 1034 "timeout while codec write " 1035 "(reg=0x%x, val=0x%x / %d, last STATUS=0x%x, %d) " 1036 "(cw=%d, cr=%d)\n", 1037 reg, val, val, stat, rafaccess, ml403_ac97cr->ac97_write, 1038 ml403_ac97cr->ac97_read); 1039#else 1040 snd_printk(KERN_WARNING SND_ML403_AC97CR_DRIVER ": " 1041 "timeout while codec write (reg=0x%x, val=0x%x / %d)\n", 1042 reg, val, val); 1043#endif 1044#else /* CODEC_WRITE_CHECK_RAF */ 1045#if CODEC_WAIT_AFTER_WRITE > 0 1046 /* officially, in AC97 spec there is no possibility for a AC97 1047 * controller to determine, if write access is done or not - so: How 1048 * is Xilinx able to provide a RAF bit for write access? 1049 * => very strange, thus just don't check RAF bit (compare with 1050 * Xilinx's example app in EDK 8.1i) and wait 1051 */ 1052 schedule_timeout_uninterruptible(HZ / CODEC_WAIT_AFTER_WRITE); 1053#endif 1054 PDEBUG(CODEC_SUCCESS, "codec_write(): (done) " 1055 "reg=0x%x, value=%d / 0x%x (no RAF check)\n", 1056 reg, val, val); 1057#endif 1058 mutex_unlock(&ml403_ac97cr->cdc_mutex); 1059 return; 1060} 1061 1062static int __devinit 1063snd_ml403_ac97cr_chip_init(struct snd_ml403_ac97cr *ml403_ac97cr) 1064{ 1065 unsigned long end_time; 1066 PDEBUG(INIT_INFO, "chip_init():\n"); 1067 end_time = jiffies + HZ / CODEC_TIMEOUT_ON_INIT; 1068 do { 1069 if (in_be32(CR_REG(ml403_ac97cr, STATUS)) & CR_CODECREADY) { 1070 /* clear both hardware FIFOs */ 1071 out_be32(CR_REG(ml403_ac97cr, RESETFIFO), 1072 CR_RECRESET | CR_PLAYRESET); 1073 PDEBUG(INIT_INFO, "chip_init(): (done)\n"); 1074 return 0; 1075 } 1076 schedule_timeout_uninterruptible(1); 1077 } while (time_after(end_time, jiffies)); 1078 snd_printk(KERN_ERR SND_ML403_AC97CR_DRIVER ": " 1079 "timeout while waiting for codec, " 1080 "not ready!\n"); 1081 return -EBUSY; 1082} 1083 1084static int snd_ml403_ac97cr_free(struct snd_ml403_ac97cr *ml403_ac97cr) 1085{ 1086 PDEBUG(INIT_INFO, "free():\n"); 1087 /* irq release */ 1088 if (ml403_ac97cr->irq >= 0) 1089 free_irq(ml403_ac97cr->irq, ml403_ac97cr); 1090 if (ml403_ac97cr->capture_irq >= 0) 1091 free_irq(ml403_ac97cr->capture_irq, ml403_ac97cr); 1092 /* give back "port" */ 1093 if (ml403_ac97cr->port != NULL) 1094 iounmap(ml403_ac97cr->port); 1095 kfree(ml403_ac97cr); 1096 PDEBUG(INIT_INFO, "free(): (done)\n"); 1097 return 0; 1098} 1099 1100static int snd_ml403_ac97cr_dev_free(struct snd_device *snddev) 1101{ 1102 struct snd_ml403_ac97cr *ml403_ac97cr = snddev->device_data; 1103 PDEBUG(INIT_INFO, "dev_free():\n"); 1104 return snd_ml403_ac97cr_free(ml403_ac97cr); 1105} 1106 1107static int __devinit 1108snd_ml403_ac97cr_create(struct snd_card *card, struct platform_device *pfdev, 1109 struct snd_ml403_ac97cr **rml403_ac97cr) 1110{ 1111 struct snd_ml403_ac97cr *ml403_ac97cr; 1112 int err; 1113 static struct snd_device_ops ops = { 1114 .dev_free = snd_ml403_ac97cr_dev_free, 1115 }; 1116 struct resource *resource; 1117 int irq; 1118 1119 *rml403_ac97cr = NULL; 1120 ml403_ac97cr = kzalloc(sizeof(*ml403_ac97cr), GFP_KERNEL); 1121 if (ml403_ac97cr == NULL) 1122 return -ENOMEM; 1123 spin_lock_init(&ml403_ac97cr->reg_lock); 1124 mutex_init(&ml403_ac97cr->cdc_mutex); 1125 ml403_ac97cr->card = card; 1126 ml403_ac97cr->pfdev = pfdev; 1127 ml403_ac97cr->irq = -1; 1128 ml403_ac97cr->enable_irq = 0; 1129 ml403_ac97cr->capture_irq = -1; 1130 ml403_ac97cr->enable_capture_irq = 0; 1131 ml403_ac97cr->port = NULL; 1132 ml403_ac97cr->res_port = NULL; 1133 1134 PDEBUG(INIT_INFO, "Trying to reserve resources now ...\n"); 1135 resource = platform_get_resource(pfdev, IORESOURCE_MEM, 0); 1136 /* get "port" */ 1137 ml403_ac97cr->port = ioremap_nocache(resource->start, 1138 (resource->end) - 1139 (resource->start) + 1); 1140 if (ml403_ac97cr->port == NULL) { 1141 snd_printk(KERN_ERR SND_ML403_AC97CR_DRIVER ": " 1142 "unable to remap memory region (%x to %x)\n", 1143 resource->start, resource->end); 1144 snd_ml403_ac97cr_free(ml403_ac97cr); 1145 return -EBUSY; 1146 } 1147 snd_printk(KERN_INFO SND_ML403_AC97CR_DRIVER ": " 1148 "remap controller memory region to " 1149 "0x%x done\n", (unsigned int)ml403_ac97cr->port); 1150 /* get irq */ 1151 irq = platform_get_irq(pfdev, 0); 1152 if (request_irq(irq, snd_ml403_ac97cr_irq, IRQF_DISABLED, 1153 dev_name(&pfdev->dev), (void *)ml403_ac97cr)) { 1154 snd_printk(KERN_ERR SND_ML403_AC97CR_DRIVER ": " 1155 "unable to grab IRQ %d\n", 1156 irq); 1157 snd_ml403_ac97cr_free(ml403_ac97cr); 1158 return -EBUSY; 1159 } 1160 ml403_ac97cr->irq = irq; 1161 snd_printk(KERN_INFO SND_ML403_AC97CR_DRIVER ": " 1162 "request (playback) irq %d done\n", 1163 ml403_ac97cr->irq); 1164 irq = platform_get_irq(pfdev, 1); 1165 if (request_irq(irq, snd_ml403_ac97cr_irq, IRQF_DISABLED, 1166 dev_name(&pfdev->dev), (void *)ml403_ac97cr)) { 1167 snd_printk(KERN_ERR SND_ML403_AC97CR_DRIVER ": " 1168 "unable to grab IRQ %d\n", 1169 irq); 1170 snd_ml403_ac97cr_free(ml403_ac97cr); 1171 return -EBUSY; 1172 } 1173 ml403_ac97cr->capture_irq = irq; 1174 snd_printk(KERN_INFO SND_ML403_AC97CR_DRIVER ": " 1175 "request (capture) irq %d done\n", 1176 ml403_ac97cr->capture_irq); 1177 1178 err = snd_ml403_ac97cr_chip_init(ml403_ac97cr); 1179 if (err < 0) { 1180 snd_ml403_ac97cr_free(ml403_ac97cr); 1181 return err; 1182 } 1183 1184 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ml403_ac97cr, &ops); 1185 if (err < 0) { 1186 PDEBUG(INIT_FAILURE, "probe(): snd_device_new() failed!\n"); 1187 snd_ml403_ac97cr_free(ml403_ac97cr); 1188 return err; 1189 } 1190 1191 *rml403_ac97cr = ml403_ac97cr; 1192 return 0; 1193} 1194 1195static void snd_ml403_ac97cr_mixer_free(struct snd_ac97 *ac97) 1196{ 1197 struct snd_ml403_ac97cr *ml403_ac97cr = ac97->private_data; 1198 PDEBUG(INIT_INFO, "mixer_free():\n"); 1199 ml403_ac97cr->ac97 = NULL; 1200 PDEBUG(INIT_INFO, "mixer_free(): (done)\n"); 1201} 1202 1203static int __devinit 1204snd_ml403_ac97cr_mixer(struct snd_ml403_ac97cr *ml403_ac97cr) 1205{ 1206 struct snd_ac97_bus *bus; 1207 struct snd_ac97_template ac97; 1208 int err; 1209 static struct snd_ac97_bus_ops ops = { 1210 .write = snd_ml403_ac97cr_codec_write, 1211 .read = snd_ml403_ac97cr_codec_read, 1212 }; 1213 PDEBUG(INIT_INFO, "mixer():\n"); 1214 err = snd_ac97_bus(ml403_ac97cr->card, 0, &ops, NULL, &bus); 1215 if (err < 0) 1216 return err; 1217 1218 memset(&ac97, 0, sizeof(ac97)); 1219 ml403_ac97cr->ac97_fake = 1; 1220 lm4550_regfile_init(); 1221#ifdef CODEC_STAT 1222 ml403_ac97cr->ac97_read = 0; 1223 ml403_ac97cr->ac97_write = 0; 1224#endif 1225 ac97.private_data = ml403_ac97cr; 1226 ac97.private_free = snd_ml403_ac97cr_mixer_free; 1227 ac97.scaps = AC97_SCAP_AUDIO | AC97_SCAP_SKIP_MODEM | 1228 AC97_SCAP_NO_SPDIF; 1229 err = snd_ac97_mixer(bus, &ac97, &ml403_ac97cr->ac97); 1230 ml403_ac97cr->ac97_fake = 0; 1231 lm4550_regfile_write_values_after_init(ml403_ac97cr->ac97); 1232 PDEBUG(INIT_INFO, "mixer(): (done) snd_ac97_mixer()=%d\n", err); 1233 return err; 1234} 1235 1236static int __devinit 1237snd_ml403_ac97cr_pcm(struct snd_ml403_ac97cr *ml403_ac97cr, int device, 1238 struct snd_pcm **rpcm) 1239{ 1240 struct snd_pcm *pcm; 1241 int err; 1242 1243 if (rpcm) 1244 *rpcm = NULL; 1245 err = snd_pcm_new(ml403_ac97cr->card, "ML403AC97CR/1", device, 1, 1, 1246 &pcm); 1247 if (err < 0) 1248 return err; 1249 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, 1250 &snd_ml403_ac97cr_playback_ops); 1251 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, 1252 &snd_ml403_ac97cr_capture_ops); 1253 pcm->private_data = ml403_ac97cr; 1254 pcm->info_flags = 0; 1255 strcpy(pcm->name, "ML403AC97CR DAC/ADC"); 1256 ml403_ac97cr->pcm = pcm; 1257 1258 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS, 1259 snd_dma_continuous_data(GFP_KERNEL), 1260 64 * 1024, 1261 128 * 1024); 1262 if (rpcm) 1263 *rpcm = pcm; 1264 return 0; 1265} 1266 1267static int __devinit snd_ml403_ac97cr_probe(struct platform_device *pfdev) 1268{ 1269 struct snd_card *card; 1270 struct snd_ml403_ac97cr *ml403_ac97cr = NULL; 1271 int err; 1272 int dev = pfdev->id; 1273 1274 if (dev >= SNDRV_CARDS) 1275 return -ENODEV; 1276 if (!enable[dev]) 1277 return -ENOENT; 1278 1279 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card); 1280 if (err < 0) 1281 return err; 1282 err = snd_ml403_ac97cr_create(card, pfdev, &ml403_ac97cr); 1283 if (err < 0) { 1284 PDEBUG(INIT_FAILURE, "probe(): create failed!\n"); 1285 snd_card_free(card); 1286 return err; 1287 } 1288 PDEBUG(INIT_INFO, "probe(): create done\n"); 1289 card->private_data = ml403_ac97cr; 1290 err = snd_ml403_ac97cr_mixer(ml403_ac97cr); 1291 if (err < 0) { 1292 snd_card_free(card); 1293 return err; 1294 } 1295 PDEBUG(INIT_INFO, "probe(): mixer done\n"); 1296 err = snd_ml403_ac97cr_pcm(ml403_ac97cr, 0, NULL); 1297 if (err < 0) { 1298 snd_card_free(card); 1299 return err; 1300 } 1301 PDEBUG(INIT_INFO, "probe(): PCM done\n"); 1302 strcpy(card->driver, SND_ML403_AC97CR_DRIVER); 1303 strcpy(card->shortname, "ML403 AC97 Controller Reference"); 1304 sprintf(card->longname, "%s %s at 0x%lx, irq %i & %i, device %i", 1305 card->shortname, card->driver, 1306 (unsigned long)ml403_ac97cr->port, ml403_ac97cr->irq, 1307 ml403_ac97cr->capture_irq, dev + 1); 1308 1309 snd_card_set_dev(card, &pfdev->dev); 1310 1311 err = snd_card_register(card); 1312 if (err < 0) { 1313 snd_card_free(card); 1314 return err; 1315 } 1316 platform_set_drvdata(pfdev, card); 1317 PDEBUG(INIT_INFO, "probe(): (done)\n"); 1318 return 0; 1319} 1320 1321static int snd_ml403_ac97cr_remove(struct platform_device *pfdev) 1322{ 1323 snd_card_free(platform_get_drvdata(pfdev)); 1324 platform_set_drvdata(pfdev, NULL); 1325 return 0; 1326} 1327 1328/* work with hotplug and coldplug */ 1329MODULE_ALIAS("platform:" SND_ML403_AC97CR_DRIVER); 1330 1331static struct platform_driver snd_ml403_ac97cr_driver = { 1332 .probe = snd_ml403_ac97cr_probe, 1333 .remove = snd_ml403_ac97cr_remove, 1334 .driver = { 1335 .name = SND_ML403_AC97CR_DRIVER, 1336 .owner = THIS_MODULE, 1337 }, 1338}; 1339 1340static int __init alsa_card_ml403_ac97cr_init(void) 1341{ 1342 return platform_driver_register(&snd_ml403_ac97cr_driver); 1343} 1344 1345static void __exit alsa_card_ml403_ac97cr_exit(void) 1346{ 1347 platform_driver_unregister(&snd_ml403_ac97cr_driver); 1348} 1349 1350module_init(alsa_card_ml403_ac97cr_init) 1351module_exit(alsa_card_ml403_ac97cr_exit) 1352