1#ifndef __SAA7146__ 2#define __SAA7146__ 3 4#include <linux/module.h> /* for module-version */ 5#include <linux/delay.h> /* for delay-stuff */ 6#include <linux/slab.h> /* for kmalloc/kfree */ 7#include <linux/pci.h> /* for pci-config-stuff, vendor ids etc. */ 8#include <linux/init.h> /* for "__init" */ 9#include <linux/interrupt.h> /* for IMMEDIATE_BH */ 10#include <linux/kmod.h> /* for kernel module loader */ 11#include <linux/i2c.h> /* for i2c subsystem */ 12#include <asm/io.h> /* for accessing devices */ 13#include <linux/stringify.h> 14#include <linux/mutex.h> 15#include <linux/scatterlist.h> 16#include <media/v4l2-device.h> 17 18#include <linux/vmalloc.h> /* for vmalloc() */ 19#include <linux/mm.h> /* for vmalloc_to_page() */ 20 21#define SAA7146_VERSION_CODE 0x000600 /* 0.6.0 */ 22 23#define saa7146_write(sxy,adr,dat) writel((dat),(sxy->mem+(adr))) 24#define saa7146_read(sxy,adr) readl(sxy->mem+(adr)) 25 26extern unsigned int saa7146_debug; 27 28//#define DEBUG_PROLOG printk("(0x%08x)(0x%08x) %s: %s(): ",(dev==0?-1:(dev->mem==0?-1:saa7146_read(dev,RPS_ADDR0))),(dev==0?-1:(dev->mem==0?-1:saa7146_read(dev,IER))),KBUILD_MODNAME,__func__) 29 30#ifndef DEBUG_VARIABLE 31 #define DEBUG_VARIABLE saa7146_debug 32#endif 33 34#define DEBUG_PROLOG printk("%s: %s(): ",KBUILD_MODNAME, __func__) 35#define INFO(x) { printk("%s: ",KBUILD_MODNAME); printk x; } 36 37#define ERR(x) { DEBUG_PROLOG; printk x; } 38 39#define DEB_S(x) if (0!=(DEBUG_VARIABLE&0x01)) { DEBUG_PROLOG; printk x; } /* simple debug messages */ 40#define DEB_D(x) if (0!=(DEBUG_VARIABLE&0x02)) { DEBUG_PROLOG; printk x; } /* more detailed debug messages */ 41#define DEB_EE(x) if (0!=(DEBUG_VARIABLE&0x04)) { DEBUG_PROLOG; printk x; } /* print enter and exit of functions */ 42#define DEB_I2C(x) if (0!=(DEBUG_VARIABLE&0x08)) { DEBUG_PROLOG; printk x; } /* i2c debug messages */ 43#define DEB_VBI(x) if (0!=(DEBUG_VARIABLE&0x10)) { DEBUG_PROLOG; printk x; } /* vbi debug messages */ 44#define DEB_INT(x) if (0!=(DEBUG_VARIABLE&0x20)) { DEBUG_PROLOG; printk x; } /* interrupt debug messages */ 45#define DEB_CAP(x) if (0!=(DEBUG_VARIABLE&0x40)) { DEBUG_PROLOG; printk x; } /* capture debug messages */ 46 47#define SAA7146_ISR_CLEAR(x,y) \ 48 saa7146_write(x, ISR, (y)); 49 50struct saa7146_dev; 51struct saa7146_extension; 52struct saa7146_vv; 53 54/* saa7146 page table */ 55struct saa7146_pgtable { 56 unsigned int size; 57 __le32 *cpu; 58 dma_addr_t dma; 59 /* used for offsets for u,v planes for planar capture modes */ 60 unsigned long offset; 61 /* used for custom pagetables (used for example by budget dvb cards) */ 62 struct scatterlist *slist; 63 int nents; 64}; 65 66struct saa7146_pci_extension_data { 67 struct saa7146_extension *ext; 68 void *ext_priv; /* most likely a name string */ 69}; 70 71#define MAKE_EXTENSION_PCI(x_var, x_vendor, x_device) \ 72 { \ 73 .vendor = PCI_VENDOR_ID_PHILIPS, \ 74 .device = PCI_DEVICE_ID_PHILIPS_SAA7146, \ 75 .subvendor = x_vendor, \ 76 .subdevice = x_device, \ 77 .driver_data = (unsigned long)& x_var, \ 78 } 79 80struct saa7146_extension 81{ 82 char name[32]; /* name of the device */ 83#define SAA7146_USE_I2C_IRQ 0x1 84#define SAA7146_I2C_SHORT_DELAY 0x2 85 int flags; 86 87 /* pairs of subvendor and subdevice ids for 88 supported devices, last entry 0xffff, 0xfff */ 89 struct module *module; 90 struct pci_driver driver; 91 struct pci_device_id *pci_tbl; 92 93 /* extension functions */ 94 int (*probe)(struct saa7146_dev *); 95 int (*attach)(struct saa7146_dev *, struct saa7146_pci_extension_data *); 96 int (*detach)(struct saa7146_dev*); 97 98 u32 irq_mask; /* mask to indicate, which irq-events are handled by the extension */ 99 void (*irq_func)(struct saa7146_dev*, u32* irq_mask); 100}; 101 102struct saa7146_dma 103{ 104 dma_addr_t dma_handle; 105 __le32 *cpu_addr; 106}; 107 108struct saa7146_dev 109{ 110 struct module *module; 111 112 struct list_head item; 113 114 struct v4l2_device v4l2_dev; 115 116 /* different device locks */ 117 spinlock_t slock; 118 struct mutex lock; 119 120 unsigned char __iomem *mem; /* pointer to mapped IO memory */ 121 u32 revision; /* chip revision; needed for bug-workarounds*/ 122 123 /* pci-device & irq stuff*/ 124 char name[32]; 125 struct pci_dev *pci; 126 u32 int_todo; 127 spinlock_t int_slock; 128 129 /* extension handling */ 130 struct saa7146_extension *ext; /* indicates if handled by extension */ 131 void *ext_priv; /* pointer for extension private use (most likely some private data) */ 132 struct saa7146_ext_vv *ext_vv_data; 133 134 /* per device video/vbi informations (if available) */ 135 struct saa7146_vv *vv_data; 136 void (*vv_callback)(struct saa7146_dev *dev, unsigned long status); 137 138 /* i2c-stuff */ 139 struct mutex i2c_lock; 140 141 u32 i2c_bitrate; 142 struct saa7146_dma d_i2c; /* pointer to i2c memory */ 143 wait_queue_head_t i2c_wq; 144 int i2c_op; 145 146 /* memories */ 147 struct saa7146_dma d_rps0; 148 struct saa7146_dma d_rps1; 149}; 150 151static inline struct saa7146_dev *to_saa7146_dev(struct v4l2_device *v4l2_dev) 152{ 153 return container_of(v4l2_dev, struct saa7146_dev, v4l2_dev); 154} 155 156/* from saa7146_i2c.c */ 157int saa7146_i2c_adapter_prepare(struct saa7146_dev *dev, struct i2c_adapter *i2c_adapter, u32 bitrate); 158 159/* from saa7146_core.c */ 160extern struct list_head saa7146_devices; 161extern struct mutex saa7146_devices_lock; 162int saa7146_register_extension(struct saa7146_extension*); 163int saa7146_unregister_extension(struct saa7146_extension*); 164struct saa7146_format* saa7146_format_by_fourcc(struct saa7146_dev *dev, int fourcc); 165int saa7146_pgtable_alloc(struct pci_dev *pci, struct saa7146_pgtable *pt); 166void saa7146_pgtable_free(struct pci_dev *pci, struct saa7146_pgtable *pt); 167int saa7146_pgtable_build_single(struct pci_dev *pci, struct saa7146_pgtable *pt, struct scatterlist *list, int length ); 168void *saa7146_vmalloc_build_pgtable(struct pci_dev *pci, long length, struct saa7146_pgtable *pt); 169void saa7146_vfree_destroy_pgtable(struct pci_dev *pci, void *mem, struct saa7146_pgtable *pt); 170void saa7146_setgpio(struct saa7146_dev *dev, int port, u32 data); 171int saa7146_wait_for_debi_done(struct saa7146_dev *dev, int nobusyloop); 172 173/* some memory sizes */ 174#define SAA7146_I2C_MEM ( 1*PAGE_SIZE) 175#define SAA7146_RPS_MEM ( 1*PAGE_SIZE) 176 177/* some i2c constants */ 178#define SAA7146_I2C_TIMEOUT 100 /* i2c-timeout-value in ms */ 179#define SAA7146_I2C_RETRIES 3 /* how many times shall we retry an i2c-operation? */ 180#define SAA7146_I2C_DELAY 5 /* time we wait after certain i2c-operations */ 181 182/* unsorted defines */ 183#define ME1 0x0000000800 184#define PV1 0x0000000008 185 186/* gpio defines */ 187#define SAA7146_GPIO_INPUT 0x00 188#define SAA7146_GPIO_IRQHI 0x10 189#define SAA7146_GPIO_IRQLO 0x20 190#define SAA7146_GPIO_IRQHL 0x30 191#define SAA7146_GPIO_OUTLO 0x40 192#define SAA7146_GPIO_OUTHI 0x50 193 194/* debi defines */ 195#define DEBINOSWAP 0x000e0000 196 197/* define for the register programming sequencer (rps) */ 198#define CMD_NOP 0x00000000 /* No operation */ 199#define CMD_CLR_EVENT 0x00000000 /* Clear event */ 200#define CMD_SET_EVENT 0x10000000 /* Set signal event */ 201#define CMD_PAUSE 0x20000000 /* Pause */ 202#define CMD_CHECK_LATE 0x30000000 /* Check late */ 203#define CMD_UPLOAD 0x40000000 /* Upload */ 204#define CMD_STOP 0x50000000 /* Stop */ 205#define CMD_INTERRUPT 0x60000000 /* Interrupt */ 206#define CMD_JUMP 0x80000000 /* Jump */ 207#define CMD_WR_REG 0x90000000 /* Write (load) register */ 208#define CMD_RD_REG 0xa0000000 /* Read (store) register */ 209#define CMD_WR_REG_MASK 0xc0000000 /* Write register with mask */ 210 211#define CMD_OAN MASK_27 212#define CMD_INV MASK_26 213#define CMD_SIG4 MASK_25 214#define CMD_SIG3 MASK_24 215#define CMD_SIG2 MASK_23 216#define CMD_SIG1 MASK_22 217#define CMD_SIG0 MASK_21 218#define CMD_O_FID_B MASK_14 219#define CMD_E_FID_B MASK_13 220#define CMD_O_FID_A MASK_12 221#define CMD_E_FID_A MASK_11 222 223/* some events and command modifiers for rps1 squarewave generator */ 224#define EVT_HS (1<<15) // Source Line Threshold reached 225#define EVT_VBI_B (1<<9) // VSYNC Event 226#define RPS_OAN (1<<27) // 1: OR events, 0: AND events 227#define RPS_INV (1<<26) // Invert (compound) event 228#define GPIO3_MSK 0xFF000000 // GPIO #3 control bits 229 230/* Bit mask constants */ 231#define MASK_00 0x00000001 /* Mask value for bit 0 */ 232#define MASK_01 0x00000002 /* Mask value for bit 1 */ 233#define MASK_02 0x00000004 /* Mask value for bit 2 */ 234#define MASK_03 0x00000008 /* Mask value for bit 3 */ 235#define MASK_04 0x00000010 /* Mask value for bit 4 */ 236#define MASK_05 0x00000020 /* Mask value for bit 5 */ 237#define MASK_06 0x00000040 /* Mask value for bit 6 */ 238#define MASK_07 0x00000080 /* Mask value for bit 7 */ 239#define MASK_08 0x00000100 /* Mask value for bit 8 */ 240#define MASK_09 0x00000200 /* Mask value for bit 9 */ 241#define MASK_10 0x00000400 /* Mask value for bit 10 */ 242#define MASK_11 0x00000800 /* Mask value for bit 11 */ 243#define MASK_12 0x00001000 /* Mask value for bit 12 */ 244#define MASK_13 0x00002000 /* Mask value for bit 13 */ 245#define MASK_14 0x00004000 /* Mask value for bit 14 */ 246#define MASK_15 0x00008000 /* Mask value for bit 15 */ 247#define MASK_16 0x00010000 /* Mask value for bit 16 */ 248#define MASK_17 0x00020000 /* Mask value for bit 17 */ 249#define MASK_18 0x00040000 /* Mask value for bit 18 */ 250#define MASK_19 0x00080000 /* Mask value for bit 19 */ 251#define MASK_20 0x00100000 /* Mask value for bit 20 */ 252#define MASK_21 0x00200000 /* Mask value for bit 21 */ 253#define MASK_22 0x00400000 /* Mask value for bit 22 */ 254#define MASK_23 0x00800000 /* Mask value for bit 23 */ 255#define MASK_24 0x01000000 /* Mask value for bit 24 */ 256#define MASK_25 0x02000000 /* Mask value for bit 25 */ 257#define MASK_26 0x04000000 /* Mask value for bit 26 */ 258#define MASK_27 0x08000000 /* Mask value for bit 27 */ 259#define MASK_28 0x10000000 /* Mask value for bit 28 */ 260#define MASK_29 0x20000000 /* Mask value for bit 29 */ 261#define MASK_30 0x40000000 /* Mask value for bit 30 */ 262#define MASK_31 0x80000000 /* Mask value for bit 31 */ 263 264#define MASK_B0 0x000000ff /* Mask value for byte 0 */ 265#define MASK_B1 0x0000ff00 /* Mask value for byte 1 */ 266#define MASK_B2 0x00ff0000 /* Mask value for byte 2 */ 267#define MASK_B3 0xff000000 /* Mask value for byte 3 */ 268 269#define MASK_W0 0x0000ffff /* Mask value for word 0 */ 270#define MASK_W1 0xffff0000 /* Mask value for word 1 */ 271 272#define MASK_PA 0xfffffffc /* Mask value for physical address */ 273#define MASK_PR 0xfffffffe /* Mask value for protection register */ 274#define MASK_ER 0xffffffff /* Mask value for the entire register */ 275 276#define MASK_NONE 0x00000000 /* No mask */ 277 278/* register aliases */ 279#define BASE_ODD1 0x00 /* Video DMA 1 registers */ 280#define BASE_EVEN1 0x04 281#define PROT_ADDR1 0x08 282#define PITCH1 0x0C 283#define BASE_PAGE1 0x10 /* Video DMA 1 base page */ 284#define NUM_LINE_BYTE1 0x14 285 286#define BASE_ODD2 0x18 /* Video DMA 2 registers */ 287#define BASE_EVEN2 0x1C 288#define PROT_ADDR2 0x20 289#define PITCH2 0x24 290#define BASE_PAGE2 0x28 /* Video DMA 2 base page */ 291#define NUM_LINE_BYTE2 0x2C 292 293#define BASE_ODD3 0x30 /* Video DMA 3 registers */ 294#define BASE_EVEN3 0x34 295#define PROT_ADDR3 0x38 296#define PITCH3 0x3C 297#define BASE_PAGE3 0x40 /* Video DMA 3 base page */ 298#define NUM_LINE_BYTE3 0x44 299 300#define PCI_BT_V1 0x48 /* Video/FIFO 1 */ 301#define PCI_BT_V2 0x49 /* Video/FIFO 2 */ 302#define PCI_BT_V3 0x4A /* Video/FIFO 3 */ 303#define PCI_BT_DEBI 0x4B /* DEBI */ 304#define PCI_BT_A 0x4C /* Audio */ 305 306#define DD1_INIT 0x50 /* Init setting of DD1 interface */ 307 308#define DD1_STREAM_B 0x54 /* DD1 B video data stream handling */ 309#define DD1_STREAM_A 0x56 /* DD1 A video data stream handling */ 310 311#define BRS_CTRL 0x58 /* BRS control register */ 312#define HPS_CTRL 0x5C /* HPS control register */ 313#define HPS_V_SCALE 0x60 /* HPS vertical scale */ 314#define HPS_V_GAIN 0x64 /* HPS vertical ACL and gain */ 315#define HPS_H_PRESCALE 0x68 /* HPS horizontal prescale */ 316#define HPS_H_SCALE 0x6C /* HPS horizontal scale */ 317#define BCS_CTRL 0x70 /* BCS control */ 318#define CHROMA_KEY_RANGE 0x74 319#define CLIP_FORMAT_CTRL 0x78 /* HPS outputs formats & clipping */ 320 321#define DEBI_CONFIG 0x7C 322#define DEBI_COMMAND 0x80 323#define DEBI_PAGE 0x84 324#define DEBI_AD 0x88 325 326#define I2C_TRANSFER 0x8C 327#define I2C_STATUS 0x90 328 329#define BASE_A1_IN 0x94 /* Audio 1 input DMA */ 330#define PROT_A1_IN 0x98 331#define PAGE_A1_IN 0x9C 332 333#define BASE_A1_OUT 0xA0 /* Audio 1 output DMA */ 334#define PROT_A1_OUT 0xA4 335#define PAGE_A1_OUT 0xA8 336 337#define BASE_A2_IN 0xAC /* Audio 2 input DMA */ 338#define PROT_A2_IN 0xB0 339#define PAGE_A2_IN 0xB4 340 341#define BASE_A2_OUT 0xB8 /* Audio 2 output DMA */ 342#define PROT_A2_OUT 0xBC 343#define PAGE_A2_OUT 0xC0 344 345#define RPS_PAGE0 0xC4 /* RPS task 0 page register */ 346#define RPS_PAGE1 0xC8 /* RPS task 1 page register */ 347 348#define RPS_THRESH0 0xCC /* HBI threshold for task 0 */ 349#define RPS_THRESH1 0xD0 /* HBI threshold for task 1 */ 350 351#define RPS_TOV0 0xD4 /* RPS timeout for task 0 */ 352#define RPS_TOV1 0xD8 /* RPS timeout for task 1 */ 353 354#define IER 0xDC /* Interrupt enable register */ 355 356#define GPIO_CTRL 0xE0 /* GPIO 0-3 register */ 357 358#define EC1SSR 0xE4 /* Event cnt set 1 source select */ 359#define EC2SSR 0xE8 /* Event cnt set 2 source select */ 360#define ECT1R 0xEC /* Event cnt set 1 thresholds */ 361#define ECT2R 0xF0 /* Event cnt set 2 thresholds */ 362 363#define ACON1 0xF4 364#define ACON2 0xF8 365 366#define MC1 0xFC /* Main control register 1 */ 367#define MC2 0x100 /* Main control register 2 */ 368 369#define RPS_ADDR0 0x104 /* RPS task 0 address register */ 370#define RPS_ADDR1 0x108 /* RPS task 1 address register */ 371 372#define ISR 0x10C /* Interrupt status register */ 373#define PSR 0x110 /* Primary status register */ 374#define SSR 0x114 /* Secondary status register */ 375 376#define EC1R 0x118 /* Event counter set 1 register */ 377#define EC2R 0x11C /* Event counter set 2 register */ 378 379#define PCI_VDP1 0x120 /* Video DMA pointer of FIFO 1 */ 380#define PCI_VDP2 0x124 /* Video DMA pointer of FIFO 2 */ 381#define PCI_VDP3 0x128 /* Video DMA pointer of FIFO 3 */ 382#define PCI_ADP1 0x12C /* Audio DMA pointer of audio out 1 */ 383#define PCI_ADP2 0x130 /* Audio DMA pointer of audio in 1 */ 384#define PCI_ADP3 0x134 /* Audio DMA pointer of audio out 2 */ 385#define PCI_ADP4 0x138 /* Audio DMA pointer of audio in 2 */ 386#define PCI_DMA_DDP 0x13C /* DEBI DMA pointer */ 387 388#define LEVEL_REP 0x140, 389#define A_TIME_SLOT1 0x180, /* from 180 - 1BC */ 390#define A_TIME_SLOT2 0x1C0, /* from 1C0 - 1FC */ 391 392/* isr masks */ 393#define SPCI_PPEF 0x80000000 /* PCI parity error */ 394#define SPCI_PABO 0x40000000 /* PCI access error (target or master abort) */ 395#define SPCI_PPED 0x20000000 /* PCI parity error on 'real time data' */ 396#define SPCI_RPS_I1 0x10000000 /* Interrupt issued by RPS1 */ 397#define SPCI_RPS_I0 0x08000000 /* Interrupt issued by RPS0 */ 398#define SPCI_RPS_LATE1 0x04000000 /* RPS task 1 is late */ 399#define SPCI_RPS_LATE0 0x02000000 /* RPS task 0 is late */ 400#define SPCI_RPS_E1 0x01000000 /* RPS error from task 1 */ 401#define SPCI_RPS_E0 0x00800000 /* RPS error from task 0 */ 402#define SPCI_RPS_TO1 0x00400000 /* RPS timeout task 1 */ 403#define SPCI_RPS_TO0 0x00200000 /* RPS timeout task 0 */ 404#define SPCI_UPLD 0x00100000 /* RPS in upload */ 405#define SPCI_DEBI_S 0x00080000 /* DEBI status */ 406#define SPCI_DEBI_E 0x00040000 /* DEBI error */ 407#define SPCI_IIC_S 0x00020000 /* I2C status */ 408#define SPCI_IIC_E 0x00010000 /* I2C error */ 409#define SPCI_A2_IN 0x00008000 /* Audio 2 input DMA protection / limit */ 410#define SPCI_A2_OUT 0x00004000 /* Audio 2 output DMA protection / limit */ 411#define SPCI_A1_IN 0x00002000 /* Audio 1 input DMA protection / limit */ 412#define SPCI_A1_OUT 0x00001000 /* Audio 1 output DMA protection / limit */ 413#define SPCI_AFOU 0x00000800 /* Audio FIFO over- / underflow */ 414#define SPCI_V_PE 0x00000400 /* Video protection address */ 415#define SPCI_VFOU 0x00000200 /* Video FIFO over- / underflow */ 416#define SPCI_FIDA 0x00000100 /* Field ID video port A */ 417#define SPCI_FIDB 0x00000080 /* Field ID video port B */ 418#define SPCI_PIN3 0x00000040 /* GPIO pin 3 */ 419#define SPCI_PIN2 0x00000020 /* GPIO pin 2 */ 420#define SPCI_PIN1 0x00000010 /* GPIO pin 1 */ 421#define SPCI_PIN0 0x00000008 /* GPIO pin 0 */ 422#define SPCI_ECS 0x00000004 /* Event counter 1, 2, 4, 5 */ 423#define SPCI_EC3S 0x00000002 /* Event counter 3 */ 424#define SPCI_EC0S 0x00000001 /* Event counter 0 */ 425 426/* i2c */ 427#define SAA7146_I2C_ABORT (1<<7) 428#define SAA7146_I2C_SPERR (1<<6) 429#define SAA7146_I2C_APERR (1<<5) 430#define SAA7146_I2C_DTERR (1<<4) 431#define SAA7146_I2C_DRERR (1<<3) 432#define SAA7146_I2C_AL (1<<2) 433#define SAA7146_I2C_ERR (1<<1) 434#define SAA7146_I2C_BUSY (1<<0) 435 436#define SAA7146_I2C_START (0x3) 437#define SAA7146_I2C_CONT (0x2) 438#define SAA7146_I2C_STOP (0x1) 439#define SAA7146_I2C_NOP (0x0) 440 441#define SAA7146_I2C_BUS_BIT_RATE_6400 (0x500) 442#define SAA7146_I2C_BUS_BIT_RATE_3200 (0x100) 443#define SAA7146_I2C_BUS_BIT_RATE_480 (0x400) 444#define SAA7146_I2C_BUS_BIT_RATE_320 (0x600) 445#define SAA7146_I2C_BUS_BIT_RATE_240 (0x700) 446#define SAA7146_I2C_BUS_BIT_RATE_120 (0x000) 447#define SAA7146_I2C_BUS_BIT_RATE_80 (0x200) 448#define SAA7146_I2C_BUS_BIT_RATE_60 (0x300) 449 450static inline void SAA7146_IER_DISABLE(struct saa7146_dev *x, unsigned y) 451{ 452 unsigned long flags; 453 spin_lock_irqsave(&x->int_slock, flags); 454 saa7146_write(x, IER, saa7146_read(x, IER) & ~y); 455 spin_unlock_irqrestore(&x->int_slock, flags); 456} 457 458static inline void SAA7146_IER_ENABLE(struct saa7146_dev *x, unsigned y) 459{ 460 unsigned long flags; 461 spin_lock_irqsave(&x->int_slock, flags); 462 saa7146_write(x, IER, saa7146_read(x, IER) | y); 463 spin_unlock_irqrestore(&x->int_slock, flags); 464} 465 466#endif 467